Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the following steps: forming a conductive structure; the conductive structure is provided with a first surface and a second surface which are oppositely arranged along a first direction, and the conductive structure at least comprises a metal semiconductor compound layer extending along the first direction; forming a semiconductor body; the semiconductor body is located on the first surface of the conductive structure and connected with the metal semiconductor compound layer; forming a storage structure; the storage structure is located on the second surface of the conductive structure and connected with the metal semiconductor compound layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), are one of the most important access components in electronic systems, and usually adopt a transistor and a capacitor to form a 1T1C structure as a memory cell. The 1T1C structure makes the DRAM have a high integration and a low cost, and has an irreplaceable position in computer access devices. With the rapid development of semiconductor technology, the DRAM is rapidly developing towards high density and high quality. SUMMARY

[0003] According to an aspect of the present disclosure, a semiconductor device is provided, comprising: a conductive structure having a first surface and a second surface oppositely arranged along a first direction; the conductive structure at least comprising a metal semiconductor compound layer extending along the first direction; a semiconductor body located at the first surface of the conductive structure and connected with the metal semiconductor compound layer; a storage structure located at the second surface of the conductive structure and connected with the metal semiconductor compound layer.

[0004] In some embodiments, the conductive structure is entirely the metal semiconductor compound layer.

[0005] In some embodiments, the conductive structure further comprises a semiconductor layer, the semiconductor layer being in contact with the semiconductor body and surrounded by the metal semiconductor compound layer.

[0006] In some embodiments, the metal element in the metal semiconductor compound layer comprises nickel, cobalt or titanium; and the material of the semiconductor layer comprises a single crystal material.

[0007] In some embodiments, the conductive structure at least comprises a first part, a side surface of the first part being aligned with a side surface of the semiconductor body along the first direction.

[0008] In some embodiments, the conductive structure further comprises a second part surrounding the first part, and a sum of sizes of the first part and the second part in a cross section perpendicular to the first direction is greater than a size of the semiconductor body in the cross section perpendicular to the first direction.

[0009] In some embodiments, the conductive structure and the semiconductor body form a step structure at a junction of the two, the step structure comprising a side surface extending along the first direction and a step surface extending along a second direction, the second direction being perpendicular to the first direction.

[0010] In some embodiments, the step structure has a same dimension along the second direction in the first direction, and the step structure has a same dimension along the first direction in the second direction.

[0011] In some embodiments, there is no interface between the semiconductor layer in the conductive structure and the semiconductor body.

[0012] In some embodiments, the semiconductor body extends along a first direction; the conductive structure has a type of doping ion, the type of the doping ion being the same as a type of doping ion in the semiconductor body at opposite ends along the first direction.

[0013] In some embodiments, the semiconductor body and the conductive structure each include a plurality of semiconductor bodies and a plurality of conductive structures, the semiconductor device further comprising: a first dielectric layer between the plurality of conductive structures; a second dielectric layer between the plurality of semiconductor bodies; the first dielectric layer and the second dielectric layer being the same or different in material; the first dielectric layer and the second dielectric layer each comprising an oxide; or, the first dielectric layer comprising a nitride and the second dielectric layer comprising an oxide.

[0014] In some embodiments, the semiconductor body, the conductive structure, and the storage structure each include a plurality of semiconductor bodies, the plurality of semiconductor bodies being arranged in an array; the semiconductor device further comprising: a plurality of word lines, the word lines being coupled to at least one side surface of each semiconductor body in a row of the semiconductor bodies; a plurality of bit lines, the bit lines being coupled to a surface of each semiconductor body in a column of the semiconductor bodies, the surface being distal to the conductive structure along the first direction.

[0015] In some embodiments, the word line is located at one side surface of the semiconductor body; or, the word line is located at two opposite side surfaces of the semiconductor body; or, the word line encircles a side surface of the semiconductor body.

[0016] In some embodiments, two adjacent semiconductor bodies form a semiconductor body group, the two semiconductor bodies in a semiconductor body group being separated by a first isolation structure; two adjacent semiconductor body groups are separated by a second isolation structure; the two word lines are located at two side surfaces of the corresponding semiconductor bodies in the semiconductor body group, the two side surfaces being distal to the first isolation structure.

[0017] In some embodiments, a dimension of a cross-section of the storage structure near one end of the conductive structure perpendicular to the first direction is greater than a dimension of a cross-section of the storage structure away from the other end of the conductive structure perpendicular to the first direction.

[0018] In some embodiments, the storage structure comprises a capacitor; the capacitor comprises a cup-shaped capacitor, a cylinder-shaped capacitor, or a pillar-shaped capacitor.

[0019] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a conductive structure; the conductive structure has a first surface and a second surface oppositely arranged along a first direction, and the conductive structure comprises at least a metal semiconductor compound layer extending along the first direction; forming a semiconductor body; the semiconductor body is located at the first surface of the conductive structure and connected to the metal semiconductor compound layer; forming a storage structure; the storage structure is located at the second surface of the conductive structure and connected to the metal semiconductor compound layer.

[0020] In some embodiments, the semiconductor body and the conductive structure are formed by: forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer; removing part of the initial dielectric layer along the first direction to expose part of the initial semiconductor bodies; the remaining initial semiconductor bodies form the semiconductor body; at least part of the exposed initial semiconductor bodies are subjected to a metallization process to form the metal semiconductor compound layer; and the exposed initial semiconductor bodies subjected to the metallization process form the conductive structure.

[0021] In some embodiments, the method further comprises: before at least part of the exposed initial semiconductor bodies are subjected to the metallization process, forming a semiconductor thickening layer around the exposed initial semiconductor bodies by an epitaxy process; at least part of the exposed initial semiconductor bodies and the semiconductor thickening layer are subjected to the metallization process to form the metal semiconductor compound layer; and the exposed initial semiconductor bodies and the semiconductor thickening layer subjected to the metallization process form the conductive structure.

[0022] In some embodiments, the method further comprises: after forming a plurality of the conductive structures, filling a first dielectric layer between the plurality of conductive structures; the remaining initial dielectric layer forms a second dielectric layer; and the material of the first dielectric layer is different from the material of the second dielectric layer.

[0023] In some embodiments, forming the semiconductor body and the conductive structure comprises: forming an initial semiconductor body extending along the first direction; a plurality of initial semiconductor bodies are separated by an initial dielectric layer; one of two surfaces of the initial semiconductor body oppositely arranged along the first direction is exposed; performing a metallization process on part of the initial semiconductor body using the exposed surface to form a metal semiconductor compound layer; the metal semiconductor compound layer is used as the conductive structure, and the remaining part of the initial semiconductor body that is not metallized forms the semiconductor body.

[0024] In some embodiments, the initial semiconductor body comprises a plurality, and the conductive structure and the semiconductor body formed comprise a plurality; the material of the first dielectric layer between the plurality of conductive structures is the same as the material of the second dielectric layer between the plurality of semiconductor bodies.

[0025] In some embodiments, forming the semiconductor body and the conductive structure comprises: forming a plurality of initial semiconductor bodies extending along the first direction; a plurality of initial semiconductor bodies are separated by an initial dielectric layer; removing part of the initial semiconductor body to form a second trench in the initial dielectric layer; the remaining initial semiconductor body forms the semiconductor body; performing a widening process on the second trench to form a first trench; the size of the first trench along a second direction is greater than the size of the second trench along the second direction, and the second direction is perpendicular to the first direction; forming the conductive structure in the first trench.

[0026] In some embodiments, forming the conductive structure in the first trench comprises: forming an initial semiconductor layer in the first trench; performing a metallization process on the initial semiconductor layer to form a metal semiconductor compound layer.

[0027] In some embodiments, forming the semiconductor layer in the first trench comprises: forming the initial semiconductor layer in the first trench by a deposition process, and the material of the initial semiconductor layer comprises a polycrystalline material.

[0028] In some embodiments, forming the semiconductor layer in the first trench comprises: forming the initial semiconductor layer in the first trench by an epitaxy process, and the material of the initial semiconductor layer comprises a single crystal material.

[0029] In some embodiments, forming the metal semiconductor compound layer comprises: forming an initial metal layer covering the exposed surface of the structure to be metallized; performing an annealing process on the structure to be metallized with the initial metal layer to form the metal semiconductor compound layer.

[0030] In some embodiments, the method further comprises: forming a word line on at least one side of the semiconductor body; and forming a bit line on a surface of the semiconductor body distal from the conductive structure among two surfaces of the semiconductor body oppositely arranged along the first direction.

[0031] In some embodiments, forming a word line on at least one side of the semiconductor body comprises: forming the word line on one side of the semiconductor body; forming the word line on two oppositely arranged sides of the semiconductor body; or forming a word line surrounding the side of the semiconductor body.

[0032] In some embodiments, two semiconductor bodies adjacent to each other form a semiconductor body group, two semiconductor bodies in one semiconductor body group are spaced apart by a first isolation structure, two semiconductor body groups adjacent to each other are spaced apart by a second isolation structure, and forming a word line on at least one side of the semiconductor body comprises: forming the word line on one side of the semiconductor body distal from the first isolation structure among two sides of the corresponding semiconductor body in the semiconductor body group, respectively.

[0033] In some embodiments, the storage structure comprises a capacitor, and forming the storage structure comprises: forming a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor.

[0034] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises: forming a conductive structure having a first surface and a second surface oppositely arranged along a first direction, and the conductive structure at least comprises a metal-semiconductor compound layer extending along the first direction; forming a semiconductor body on the first surface and connected with the metal-semiconductor compound layer; and forming a storage structure on the second surface and connected with the metal-semiconductor compound layer. In the embodiments of the present disclosure, by forming the conductive structure at least comprising the metal-semiconductor compound layer extending along the first direction, self-alignment of the conductive structure and the semiconductor body can be achieved, which on one hand can increase the alignment accuracy of the conductive structure and the semiconductor body, reduce the alignment difficulty of the two, improve the reliability of the semiconductor device, save the manufacturing time and cost, and improve the process speed and efficiency; on the other hand, the metal-semiconductor compound layer as the material of the conductive structure between the semiconductor body and the storage structure has a lower resistivity, which can achieve better electrical connection between the semiconductor body and the storage structure, and improve the reliability of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A structure diagram of a dynamic random access memory provided by an embodiment of the present disclosure Figure 1 ;

[0036] Figures 2a-2d A structure diagram of a conductive structure in a manufacturing process provided by an embodiment of the present disclosure

[0037] Figure 3 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is provided.

[0038] Figures 4a-4d A cross-sectional view of a process for forming an initial semiconductor body according to an embodiment of the present disclosure is provided.

[0039] Figures 5a-5d A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided Figure 1 .

[0040] Figures 6a-6c A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided Figure 1 .

[0041] Figures 7a-7e A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided

[0042] Figures 8a-8d A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided Figure 3 .

[0043] Figures 9a-9e A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided

[0044] Figures 10a-10i A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided

[0045] Figures 11a-11c A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided

[0046] Figures 12a-12d A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided

[0047] Figure 13 A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided

[0048] Figure 14 A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided Figure 3 .

[0049] In the drawings, which are not necessarily drawn to scale, like numerals describe similar components throughout the several views. Like numerals having different letter suffixes can represent different instances of the components. The drawings illustrate generally, by way of example, various embodiments discussed herein. DETAILED DESCRIPTION

[0050] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are described herein, the present disclosure can be embodied in various forms without being limited to specific described embodiments. Rather, these embodiments are provided as examples of implementing the present disclosure, with the understanding that the scope of the disclosure is to be given the broadest interpretation in accordance with the appended claims.

[0051] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known structures and techniques have not been described in order to avoid obscuring the understanding of this description. In the following description, numerous specific details are presented to provide a thorough understanding of the present disclosure. One skilled in the relevant art, however, will recognize that the present disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. Some features have not been described in detail because they can be apparent to one skilled in the art, or can not be necessary for an understanding of the present disclosure.

[0052] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0053] It is to be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described herein is turned over, then a relative prefi x term such as "below" can be interpreted as "above" or "up". The spatially relative terms can be interpreted differently depending on the particular orientation of the device. Thus, the examples described herein should be understood not to be limited to the following described orientations, but are to be interpreted as a broader description of the application, in suitable form. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0056] The semiconductor device related to the embodiments of the present disclosure is at least a part of a final device structure to be used in subsequent processes. Here, the final device can include a memory, which includes but is not limited to a dynamic random access memory, and only the dynamic random access memory will be described below. However, it should be noted that the description of the dynamic random access memory in the following embodiments is only used to illustrate the present disclosure, and does not limit the scope of the present disclosure.

[0057] The semiconductor device related to the embodiments of the present disclosure is at least a part of a final device structure to be used in subsequent processes. Here, the final device can include a memory, which includes but is not limited to a dynamic random access memory, and only the dynamic random access memory will be described below. However, it should be noted that the description of the dynamic random access memory in the following embodiments is only used to illustrate the present disclosure, and does not limit the scope of the present disclosure.

[0058] With the development of dynamic random access memory technology, the size of the memory cell is getting smaller and smaller, and the array architecture is from 8F 2 to 6F 2 to 4F 2 In addition, based on the requirements of dynamic random access memory for ion and leakage current, the architecture of the memory is from planar array transistor to recess gate array transistor, from recess gate array transistor to buried channel array transistor, and from buried channel array transistor to vertical channel array transistor.

[0059] In some embodiments of the present disclosure, whether it is a planar transistor or a buried transistor, the dynamic random access memory is composed of a plurality of memory cells, each memory cell is composed of a transistor and a capacitor controlled by the transistor, that is, the dynamic random access memory includes a 1 transistor (T) and 1 capacitor (C) (1T1C) architecture; Its main principle of action is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0060] The following will be described in detail Figure 1 One kind of architecture of dynamic random access memory is described in detail. Before introducing Figure 1 The semiconductor device is shown, each direction that can be used in the following description is defined. The extension direction of the semiconductor body is defined as the first direction (that is, the Z direction). In the plane perpendicular to the Z direction, the intersecting second direction (that is, the X direction) and the third direction (that is, the Y direction) are defined. In some embodiments, the X direction, the Y direction and the Z direction can be perpendicular to each other.

[0061] A cross-sectional view of a three-dimensional (3D) dynamic random access memory 100 including vertical transistors is provided in embodiments of the present disclosure; as Figure 1 shown, the dynamic random access memory 100 includes a first device 102 and a second device 104 stacked on the first device 102 along the Z-axis direction, and the first device 102 and the second device 104 are connected through a bonding interface 106; The first device 102 and the second device 104 can be connected by hybrid bonding or the like. In some embodiments, the second device 104 can be bonded on the top of the first device 102 in a face-to-face manner at the bonding interface 106. The first device 102 can include a first substrate 1010, a peripheral circuit 1012 located on one side of the first substrate 1010, and a first interconnection layer 1016 located on the side of the peripheral circuit 1012 away from the first substrate 1010, the first interconnection layer 1016 is used to transmit the electrical signal of the peripheral circuit 1012. The peripheral circuit 1012 can include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation STI) and doped regions (such as the well, source and drain of the transistor 1014) can also be formed on or in the first substrate 1010.

[0062] The first device 102 can also include a first bonding layer 1018 at the bonding interface 106 and on a side of the first interconnect layer 1016 distal to the peripheral circuit 1012. The first bonding layer 1018 can include a plurality of first bonding contacts 1019 and a dielectric electrically isolating the first bonding contacts 1019. The first bonding contacts 1019 and surrounding dielectric in the first bonding layer 1018 can be used for hybrid bonding. In contrast, the second device 104 can also include a second bonding layer 1020 at the bonding interface 106 and on a side of the first bonding layer 1018 distal to the first interconnect layer 1016. The second bonding layer 1020 can include a plurality of second bonding contacts 1021 and a dielectric electrically isolating the second bonding contacts 1021. The second bonding contacts 1021 and surrounding dielectric in the second bonding layer 1020 can be used for hybrid bonding. Here, the second bonding contacts 1021 contact the first bonding contacts 1019 at the bonding interface 106.

[0063] In some embodiments, the peripheral circuit 1012 can also include coupling to word lines (WL) and word line drivers / row decoders in the second interconnect layer 1022 through the second bonding contacts 1021 in the second bonding layer 1020 and the first bonding contacts 1019 in the first bonding layer 1018 and the first interconnect layer 1016. In other embodiments, the peripheral circuit 1012 can also include coupling to bit lines 1023 (BL) and bit line drivers / column decoders in the second interconnect layer 1022 through the second bonding contacts 1021 in the second bonding layer 1020 and the first bonding contacts 1019 in the first bonding layer 1018 and the first interconnect layer 1016, where the second interconnect layer 1022 includes the bit lines 1023 above the second bonding layer 1020, the bit lines 1023 used to transmit electrical signals. In other embodiments, the first device 102 and the second device 104 can not be connected through bonding, but instead integrated on the same substrate (only the first substrate, not the second substrate) and connected directly through one or more interconnect layers between the first device 102 and the second device 104. In this case, the first bonding layer 1018 and the first bonding contacts 1019 are not present in the first device 102; the second bonding layer 1020 and the second bonding contacts 1019 are not present in the second device 104; and the bonding interface 106 between the first device 102 and the second device 104 is also not present.

[0064] Reference Figure 1 The second device 104 also includes an array of memory cells on the second interconnect layer 1022, which can include a plurality of memory cells 1024, a second substrate 1048 on the memory cells 1024, and a third interconnect layer 1050 on the second substrate 1048. Figure 1A cross-section of a dynamic random access memory 100 in the middle can be taken along the bit line direction (X-axis direction), and a bit line 1023 in a second interconnect layer 1022 extending laterally in the X-axis direction can be coupled to a column of memory cells 1024.

[0065] Here, each memory cell 1024 can include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting one side of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure can also fully surround the semiconductor body, half- surround the semiconductor body, be located at two opposite sides of the semiconductor body, etc., which are not elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 abuts one side of the semiconductor body 1030, and the gate electrode 1034 abuts the gate dielectric 1032.

[0066] In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (e.g., the lower end in the middle) extends beyond the gate dielectric 1032 into an interlayer dielectric (ILD) layer in the vertical direction (Z-axis direction), and the other end (e.g., the upper end in the middle) of the semiconductor body 1030 is flush with a corresponding end of the gate dielectric 1032. In other embodiments, both ends (the upper end and the lower end) of the semiconductor body 1030 extend beyond the gate electrode 1034 into the ILD layer in the vertical direction (Z-axis direction). Figure 1 Figure 1 In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (e.g., the lower end in the middle) extends beyond the gate dielectric 1032 into an interlayer dielectric (ILD) layer in the vertical direction (Z-axis direction), and the other end (e.g., the upper end in the middle) of the semiconductor body 1030 is flush with a corresponding end of the gate dielectric 1032. In other embodiments, both ends (the upper end and the lower end) of the semiconductor body 1030 extend beyond the gate electrode 1034 into the ILD layer in the vertical direction (Z-axis direction).

[0067] ​The vertical transistor 1026 can also include a source 1038 and a drain 1040 disposed at two end portions (upper end portion and lower end portion) of the semiconductor body 1030 in the vertical direction (Z-axis direction), respectively (the positions of the source and the drain can be exchanged, and hereinafter, the upper end portion is taken as the source 1038 and the lower end portion is taken as the drain 1040 as an example). In some embodiments, the source 1038 is coupled to the capacitor 1028, and the drain 1040 is coupled to the bit line 1023.

[0068] Since the gate electrode can be part of or extend in the word line direction as a word line, the second device 104 of the dynamic random access memory 100 can also include a plurality of word lines each extending in the word line direction (Y-axis direction). Here, each word line 1034 can be coupled to a row of the memory cell 1024.

[0069] The vertical transistor 1026 extends vertically through and contacts the word line 1034, and the drain 1040 of the vertical transistor 1026 at its lower end portion contacts the bit line 1023. Therefore, due to the vertical arrangement of the vertical transistor 1026, the word line 1034 and the bit line 1023 can be disposed in different planes in the vertical direction, which simplifies the wiring of the word line 1034 and the bit line 1023. Here, the vertical transistor 1026 can be arranged in a mirror-symmetrical manner to increase the density of the memory cell 1024 in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetrical to each other with respect to the trench isolation 1060, that is, the second device 104 can include a plurality of trench isolations 1060 each extending in the word line direction (Y-axis direction) parallel to the word line 1034 and disposed between two adjacent rows of the semiconductor body 1030 of the vertical transistor 1026. In some embodiments, the rows of the vertical transistor 1026 separated by the trench isolation 1060 are mirror-symmetrical to each other with respect to the trench isolation 1060. It should be understood that the trench isolation 1060 can include air gaps each disposed laterally between adjacent semiconductor bodies 1030. The second device 104 also includes a plurality of gate isolations 1062 each extending in the word line direction (Y-axis direction) parallel to the word line 1034 and disposed between two adjacent rows of the word line 1034 of the vertical transistor 1026. It should be understood that the dimensions of the gate isolation 1062 and the word line 1034 in the bit line direction (X-axis direction) can be the same as or different from the dimensions of the trench isolation 1060 in the bit line direction (X-axis direction); when the dimensions of the gate isolation 1062 and the word line 1034 in the bit line direction (X-axis direction) are different, the spacing between the plurality of semiconductor bodies 1030 arranged in the bit line direction (X-axis direction) is different, that is, the plurality of semiconductor bodies 1030 arranged in the bit line direction (X-axis direction) are non-uniformly arranged.

[0070] AsFigure 1 As shown, the capacitor structure 1028 is positioned above and in contact with a source 1038 of the vertical transistor 1026 (i.e., an upper end portion of the semiconductor body 1030), the capacitor structure 1028 can be a vertical capacitor.

[0071] In some embodiments, a conductive structure 1064 is formed between the capacitor structure 1028 and the vertical transistor 1026 to reduce contact resistance. As shown, the conductive structure 1064 can include a semiconductor layer, a metal-semiconductor compound layer, and a metal layer that are sequentially stacked from bottom to top. Figure 1

[0072] As shown, the second device 104 can also include a capacitor contact 1047 that contacts the common plate of the vertical transistor 1026 for coupling the second electrode 1046 of the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer that forms the capacitor structure 1028 has the same dielectric material, e.g., silicon oxide, as the two ILD layers into which the semiconductor body 1030 extends. The configuration of the capacitor structure 1028 can include any suitable structure and configuration, e.g., a planar capacitor, a stacked capacitor, a multi-finned capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. Figure 1

[0073] As shown, the vertical transistor 1026 extends vertically through and contacts the word line 1034, the drain 1040 of the vertical transistor 1026 at its lower end portion contacts the bit line 1023, and the source 1038 of the vertical transistor 1026 at its upper end portion contacts the capacitor structure 1028. That is, due to the vertical arrangement of the vertical transistor 1026, the bit line 1023 and the capacitor structure 1028 can be disposed in different planes in the vertical direction and coupled to opposite end portions of the vertical transistor 1026 of the memory cell 1024 in the vertical direction. In some embodiments, the bit line 1023 and the capacitor structure 1028 are disposed on opposite sides of the vertical transistor 1026 in the vertical direction, which simplifies the routing of the bit line 1023 and reduces the coupling capacitance between the bit line 1023 and the capacitor structure 1028 compared to conventional memory cells in which the bit line and the capacitor structure are disposed on the same side of the planar transistor. Figure 1

[0074] ​​​In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuit 1012 of the first device 102 and the bonding interface 106 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect routing distance and complexity.

[0075] In some embodiments, the second device 104 further includes a second substrate 1048 disposed above the memory cell 1024, and a pad-out third interconnect layer 1050 above the memory cell 1024. The pad-out third interconnect layer 1050 may include interconnects in one or more ILD layers, such as contact pads 1054.

[0076] In some embodiments, the second device 104 further includes one or more contacts 1052, which extend through a portion of the pad-out third interconnect layer 1050 and the second substrate 1048 to couple the pad-out third interconnect layer 1050 to the memory cell 1024 and the second interconnect layer 1022. In this manner, the peripheral circuit 1012 can be coupled to the memory cell 1024 through the first interconnect layer 1016 and the second interconnect layer 1022 and the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuit 1012 and the memory cell 1024 can be coupled to an external circuit through the contacts 1052 and the pad-out third interconnect layer 1050.

[0077] As mentioned above, in order to reduce the contact resistance between the capacitor structure 1028 and the vertical transistor 1026, a conductive structure 1064 is provided between the capacitor structure 1028 and the vertical transistor 1026. The present disclosure provides a method for manufacturing the conductive structure 1064, referring to FIG. Figures 2a-2d .

[0078] like Figure 2a As shown, a mask layer 2020 is formed on a semiconductor body 1030 (which is subsequently used to form the aforementioned vertical transistor 1026 ).

[0079] like Figure 2b As shown, a conductive hole 2030 is formed in the mask layer 2020 using a self-alignment technique to expose a surface of the semiconductor body 1030 close to the mask layer 2020 .

[0080] like Figure 2cAs shown, a semiconductor material (such as polysilicon) is deposited in the conductive hole 2030, and the semiconductor material is optionally doped and etched back (EB) to form a semiconductor layer 6010; then, a metal semiconductor compound layer 5010, such as cobalt silicide (CoSi), is formed on the semiconductor layer.

[0081] like Figure 2d As shown, a metal material is deposited in the conductive hole 2030 and chemical mechanical polishing (CMP) is performed to form a metal layer 1130 such as titanium nitride TiN or tungsten W on the metal semiconductor compound layer 5010. The semiconductor layer 6010, the metal semiconductor compound layer 5010, and the metal layer 1130 form a conductive structure 1064.

[0082] In the above embodiment, the alignment accuracy between the semiconductor body 1030 and the conductive structure is highly dependent on the pattern accuracy of the mask layer, and the corresponding photolithography process of the mask layer has high requirements. At the same time, the depth difference between the semiconductor body and the word line in the Z-axis direction, the technical defects in the process of forming the metal silicide layer, etc., make the alignment between the conductive structure 1064 and the semiconductor body 1030 more difficult. In addition, the cost of the mask layer and other issues also increase the production cost.

[0083] Based on this, in order to solve one or more of the above problems, the present disclosure also provides a method for manufacturing a semiconductor device. Figure 3 , Figure 3 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure; the method comprises:

[0084] Step S301: forming a conductive structure; the conductive structure has a first surface and a second surface disposed opposite to each other along a first direction, and the conductive structure at least includes a metal semiconductor compound layer extending along the first direction;

[0085] Step S302: forming a semiconductor body; the semiconductor body is located on the first surface of the conductive structure and connected to the metal-semiconductor compound layer;

[0086] Step S303: forming a storage structure; the storage structure is located on the second surface of the conductive structure and connected to the metal-semiconductor compound layer.

[0087] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 3The steps shown in the method can be adjusted in sequence according to actual needs. It should be noted that the semiconductor device can include one conductive structure, one semiconductor body and one storage structure, or multiple conductive structures, multiple semiconductor bodies and multiple storage structures. Here and hereinafter, the semiconductor device is taken as an example including multiple conductive structures, multiple semiconductor bodies and multiple storage structures.

[0088] As mentioned above, there can be various different relative positions between the gate structure and the semiconductor body in the semiconductor device, and different relative positions correspond to different specific manufacturing methods. In the embodiment of the present disclosure, two gate structures corresponding to two adjacent semiconductor bodies are taken as examples for description, and the two gate structures are respectively arranged back-to-back (as shown in the method). Figure 1 The semiconductor device can include multiple conductive structures, multiple semiconductor bodies and multiple storage structures arranged in an array along the X-axis direction and the Y-axis direction. It should be understood that the following formation method of the semiconductor structure is only used to illustrate the present disclosure, and is not used to limit the scope of the present disclosure.

[0089] The method for forming the conductive structure and the semiconductor body includes various methods. In the embodiment of the present disclosure, several methods are exemplarily shown, and the formation process of the multiple conductive structures and the multiple semiconductor bodies is described in detail below in combination with the drawings.

[0090] In some embodiments, after performing the step S301 and the step S302, the method specifically includes:

[0091] It should be understood that Figure 3 The steps shown in the method are not exclusive, and other steps can be performed before, after or between any steps shown in the method; Figure 3 The steps shown in the method can be adjusted in sequence according to actual needs. It should be noted that the semiconductor device can include one conductive structure, one semiconductor body and one storage structure, or multiple conductive structures, multiple semiconductor bodies and multiple storage structures. Here and hereinafter, the semiconductor device is taken as an example including multiple conductive structures, multiple semiconductor bodies and multiple storage structures.

[0092] As mentioned above, there can be various different relative positions between the gate structure and the semiconductor body in the semiconductor device, and different relative positions correspond to different specific manufacturing methods. In the embodiment of the present disclosure, two gate structures corresponding to two adjacent semiconductor bodies are taken as examples for description, and the two gate structures are respectively arranged back-to-back (as shown in the method). Figure 1 The semiconductor device can include multiple conductive structures, multiple semiconductor bodies and multiple storage structures arranged in an array along the X-axis direction and the Y-axis direction. It should be understood that the following formation method of the semiconductor structure is only used to illustrate the present disclosure, and is not used to limit the scope of the present disclosure.

[0093] There are many methods for forming conductive structures and semiconductor bodies. Several of them are exemplarily shown in the embodiments of the present disclosure. The formation process of multiple conductive structures and multiple semiconductor bodies is described in detail below with reference to the accompanying drawings.

[0094] In the process of executing step S301 to step S303 , the formation process of the conductive structure and the semiconductor body is first introduced.

[0095] In some embodiments, forming a conductive structure and a semiconductor body includes:

[0096] forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies being separated by an initial dielectric layer;

[0097] removing a portion of the initial dielectric layer along the first direction to expose a portion of the initial semiconductor body; the remaining initial semiconductor body forms the semiconductor body;

[0098] At least a portion of the exposed initial semiconductor body is metallized to form a metal-semiconductor compound layer; and the exposed initial semiconductor body that has been metallized serves as the conductive structure.

[0099] Figures 4a-4d This is a cross-sectional diagram of a process for forming an initial semiconductor body provided by an embodiment of the present disclosure. It should be noted that: Figure 4c for Figure 4b The cross-sectional view along the AA' direction is shown in FIG. ; the formation process of the multiple initial semiconductor bodies will be described in detail below in conjunction with the accompanying drawings.

[0100] refer to Figure 4a , providing a substrate 4000, the material of the substrate 4000 may be a semiconductor material, such as silicon, more specifically, the material of the substrate 4000 may be single crystal silicon.

[0101] refer to Figure 4b 、 Figure 4c , a plurality of initial semiconductor bodies 4010 arranged in an array are formed in the substrate 4000. In some embodiments, the method of forming the initial semiconductor bodies 4010 may include: first forming a plurality of trenches extending along the X-axis direction in the substrate 4000, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the Y-axis direction in the substrate 4000, wherein the trenches extending along the Y-axis direction are adjusted according to the relative position between the gate structure and the semiconductor body. Figure 4b What is shown in the figure is that when two gate structures corresponding to two adjacent semiconductor bodies are arranged back to back, the grooves extending along the Y-axis direction include alternating grooves of different sizes. The remaining insulating material previously filled in the grooves is removed, and the initial semiconductor column bodies 4010 arranged in an array are formed.

[0102] It should be noted that Figure 4c The shape of the cross section of the initial semiconductor body along the X-axis and the Y-axis shown in the figure is a square. This shape is only used for example and is not used to limit the shape of the initial semiconductor body and the subsequent semiconductor body formed by the initial semiconductor body in this cross section. The shape of the initial semiconductor body and the semiconductor body in this cross section can also include rectangle, circle, ellipse, and approximate shapes of these shapes, etc.

[0103] In other embodiments, the method of forming the initial semiconductor body 4010 may also include: first forming a plurality of grooves extending along the Y-axis direction in the substrate 4000, filling the grooves with insulating material (such as silicon oxide), and then forming a plurality of grooves extending along the X-axis direction in the substrate 4000.

[0104] In some specific embodiments, a groove along the X-axis direction and / or the Y-axis direction can be formed by a photolithography process (hereinafter referred to as photolithography-etching (LE)). Methods for filling the groove with an insulating material include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0105] Next, refer to Figure 4d According to the requirements of subsequent semiconductor device manufacturing processes, a first isolation structure 4020 and a second isolation structure 4030 are formed in the trench extending along the Y-axis direction. It can be understood that the first isolation structure 4020 is similar to Figure 1 The role of the trench isolation 1060 is similar to the second isolation structure 4030. Figure 1 The function of the middle gate isolation 1062.

[0106] In some embodiments, as Figure 4d The first isolation structure 4020 may include an air gap 4021 and a capping layer 4022, wherein the air gap 4021 may include air; the material of the capping layer 4022 includes but is not limited to silicon oxide. In other embodiments, the first isolation structure 4020 may also include a conductive material layer and a protective layer ( Figure 4d (not shown), the conductive material layer can provide a good electrostatic shielding effect. However, it should be noted that when the first isolation structure 4020 includes a conductive material layer, the protective layer must surround the conductive material layer to prevent the conductive material layer from contacting the semiconductor pillar. In some specific embodiments, the method for forming the first isolation structure 4020 includes, but is not limited to, PVD, CVD, ALD, and other processes.

[0107] In some embodiments, as Figure 4d , the second isolation structure 4030 can include gate structures 4031, gate separation layers 4032 between the gate structures 4031, and an initial dielectric layer 4033 on the gate structures 4031, wherein the gate structures 4031 can include a gate electrode and a gate dielectric, and optionally, the gate structures 4031 can further include a barrier layer between the gate electrode and the gate dielectric. The material of the gate electrode can include but is not limited to tungsten, the material of the gate dielectric can include but is not limited to silicon oxide, and the material of the barrier layer can include but is not limited to titanium nitride. The material of the gate separation layers 4032 and the material of the initial dielectric layer 4033 can be the same or different. Exemplarily, the material of the gate separation layers 4032 and the material of the initial dielectric layer 4033 are both silicon oxide. In some specific embodiments, the method of forming the gate structures 4031 in the second isolation structure 4030 includes but is not limited to deposition, etching, and the like; the method of forming the gate separation layers 4022 in the second isolation structure 4030 includes but is not limited to deposition, etching, and the like; and the method of forming the initial dielectric layer 4033 in the second isolation structure 4030 includes but is not limited to deposition, CMP, and the like.

[0108] It should be noted that the cross-sectional views of the manufacturing process shown in the drawings from Figure 2a to the following are intermediate stages of manufacturing, and some of the structure topographies shown in the drawings can not be the final product form of the semiconductor device. For example, the lower end portions (the end portions close to the substrate) of the word lines (gate electrodes) shown in the drawings are connected together, and the lower end portions of the word lines (gate electrodes) in the final product of the semiconductor device are disconnected, forming back-to-back.

[0109] Figures 5a-5d A cross-sectional view of a process of forming a conductive structure and a semiconductor body provided in an embodiment of the present disclosure Figure 1 . In an embodiment of the present disclosure, the surface of the upper end portion of the initial semiconductor body is metallized. Specifically:

[0110] Referring to Figure 5a , a plurality of initial semiconductor bodies 4010 extending along the Z-axis direction are formed; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. Wherein, the specific formation manner of the initial semiconductor body 4010 can refer to the examples given in the foregoing Figures 4a-4d .

[0111] Referring to Figure 5bPart of the initial dielectric layer 4033 is removed along the Z-axis direction from the top of the initial dielectric layer, exposing part of the initial semiconductor body, at this time, the initial semiconductor body 4010 includes exposed initial semiconductor body 4011 and unexposed initial semiconductor body 4012. In some embodiments, after part of the initial dielectric layer is removed, the top surface of the remaining initial dielectric layer is higher than the top surface of the gate electrode, that is, there is a height difference h between the remaining initial dielectric layer and the gate electrode, so that the corresponding part of the initial semiconductor body of the height difference can be used to form the drain or source of the vertical transistor. In some specific embodiments, the method of removing part of the initial dielectric layer 4033 includes but is not limited to dry etching.

[0112] Reference Figure 5c At least part of the exposed initial semiconductor body 4011 is subjected to a metallization process to form a metal semiconductor compound layer 5010. In some specific embodiments, the metal elements in the metal semiconductor compound layer 5010 include but are not limited to nickel, cobalt, or titanium, etc.

[0113] In some specific embodiments, forming the metal semiconductor compound layer 5010 specifically includes: forming an initial metal layer (not shown in the figure) covering the exposed surface of the structure to be subjected to the metallization process (including the top surface and the side surface of the exposed initial semiconductor body 4011); and performing an annealing process on the structure to be subjected to the metallization process formed with the initial metal layer to form the metal semiconductor compound layer. Figure 5b Figure 5c In some specific embodiments, forming the metal semiconductor compound layer 5010 specifically includes: forming an initial metal layer (not shown in the figure) covering the exposed surface of the structure to be subjected to the metallization process (including the top surface and the side surface of the exposed initial semiconductor body 4011); and performing an annealing process on the structure to be subjected to the metallization process formed with the initial metal layer to form the metal semiconductor compound layer.

[0114] It should be noted that the metallization process is mainly carried out in the semiconductor material covering the initial metal layer, and is not carried out in the non-semiconductor material covering the initial metal layer, such as oxide or nitride material. Therefore, after forming the metal semiconductor compound layer, it is generally necessary to remove the excess initial metal layer covering the non-semiconductor material.

[0115] Figures 6a-6c The cross-sectional schematic diagrams of the metal semiconductor compound layer in different proportions in the semiconductor material in several metallization processes provided by the embodiments of the present disclosure Figure 1 It should be noted that, Figures 6a-6c corresponding to several possible metallization cases. Figure 5c

[0116] In some specific embodiments, as shown in Figure 6a , during the metallization process, the exposed initial semiconductor body 4011 is fully metallized, and based on this, the conductive structure 1064 formed is all the metal semiconductor compound layer, and the unexposed initial semiconductor body 4012 forms the semiconductor body 1030.

[0117] In some specific embodiments, as shown in Figure 6b ​​As shown, during the metallization process, the exposed initial semiconductor body 4011 is fully metallized, and the metal-semiconductor compound layer 5010 further extends into the unexposed initial semiconductor body 4012. It should be noted that the metal-semiconductor compound layer 5010 extending into the unexposed initial semiconductor body 4012 is not necessarily the same as the metal-semiconductor compound layer 5010 on the exposed initial semiconductor body 4011.

[0118] In some embodiments, as shown in FIG. 1C, the exposed initial semiconductor body 4011 is partially metallized during the metallization process, and the metal-semiconductor compound layer 5010 does not extend into the unexposed initial semiconductor body 4012. Figure 6c As shown, during the metallization process, the exposed initial semiconductor body 4011 is fully metallized, and the metal-semiconductor compound layer 5010 further extends into the unexposed initial semiconductor body 4012. It should be noted that the metal-semiconductor compound layer 5010 extending into the unexposed initial semiconductor body 4012 is not necessarily the same as the metal-semiconductor compound layer 5010 on the exposed initial semiconductor body 4011. Figure 6c As shown, the regular shape in FIG. 1B can have a middle bottom lower than the edge bottom. Based on this, the formed conductive structure 1064 overlaps with the unexposed initial semiconductor body 4012, and at this time, the formed conductive structure 1064 is entirely a metal-semiconductor compound layer, and the unmetallized part of the unexposed initial semiconductor body 4012 forms a semiconductor body 1030.

[0119] It can be understood that in the foregoing embodiments, a part of the initial semiconductor body 4010 is directly used to form the conductive structure 1064, and another part of the initial semiconductor body 4010 is used to form the semiconductor body 1030. Because the initial semiconductor body 4010 is once formed from bottom to top, and the conductive structure 1064 and the semiconductor body 1030 share the same initial semiconductor body 4010, the conductive structure 1064 and the semiconductor body 1030 can be directly self-aligned, and the use of a mask layer is omitted. In this way, the alignment accuracy between the conductive structure and the semiconductor body in the embodiments of the present application is high, the process difficulty is low, and the mask layer can be omitted, thereby saving the manufacturing process and reducing the manufacturing cost of the semiconductor device.

[0120] Here, the self-alignment can be understood as the geometric center of the conductive structure 1064 and the semiconductor body 1030 being aligned; or the side surface of the conductive structure 1064 being aligned with the side surface of the semiconductor body along the Z-axis direction; or the conductive structure and the semiconductor body 1030 being overlapped in the normal projection of the section perpendicular to the first direction. It should be noted that there can be a slight deviation in the geometric center of the two due to manufacturing errors and the like, or a slight size change (overall thickening or thinning) of the exposed initial semiconductor body 4011 before and after the metallization process, which is within the scope of protection of the present application.

[0121] In some embodiments, referring to Figure 5d After forming the plurality of conductive structures 1064, the first dielectric layer 5020 is filled between the plurality of conductive structures 1064, the top surface of the first dielectric layer 5020 is not lower than the top surface of the conductive structure 1064; the remaining initial dielectric layer forms the second dielectric layer 5030; the material of the first dielectric layer 5020 is the same as or different from the material of the second dielectric layer 5030. In some specific embodiments, the material of the first dielectric layer 5020 is the same as the material of the second dielectric layer 5030, for example, both are silicon oxide. In other specific embodiments, the material of the first dielectric layer 5020 is different from the material of the second dielectric layer 5030, for example, the material of the first dielectric layer 5020 is silicon nitride or silicon nitride boron, and the material of the second dielectric layer 5030 is silicon oxide. In some specific embodiments, the method of filling the first dielectric layer 5020 includes but is not limited to PVD, CVD and the like.

[0122] It should be noted that the material selection of the first dielectric layer 5020 is mainly considered for the formation of the storage structure in the subsequent process. Specifically, the storage structure includes a capacitor, and when the capacitor is formed, the capacitor is generally long in the Z-axis direction, so multiple support layers are formed, and the insulating layer filled in the support layer is hollowed out, and the material of the insulating layer can include silicon oxide. In order to prevent the second dielectric layer 5030 from being affected by the wet etching of the insulating layer between the support layers, the first dielectric layer 5020 needs to be set as a material with a different etching selectivity ratio from the insulating layer to play a blocking role. Therefore, when the material of the first dielectric layer 5020 is silicon nitride or silicon nitride boron, it can directly play a blocking role, and when the material of the first dielectric layer 5020 is silicon oxide, a layer of material with a different etching selectivity ratio from the insulating layer needs to be formed on the first dielectric layer 5020 before the capacitor is formed.

[0123] It should be noted that in the scenario of the back-to-back gate structure, the arrangement of the plurality of semiconductor bodies along the X axis is not uniform, and the self-alignment of the conductive structure and the semiconductor body also presents an uneven arrangement along the X axis, while the storage structure connected with the conductive structure presents a uniform arrangement along the X axis. At this time, in order to improve the connection window between the conductive structure and the storage structure, the size of the bottom of the storage structure can be expanded. In some embodiments, the size of the end of the storage structure close to the conductive structure in the cross section perpendicular to the Z axis is greater than the size of the end of the storage structure away from the conductive structure in the cross section perpendicular to the Z axis.

[0124] In some embodiments, the method further comprises:

[0125] forming a semiconductor thickening layer on the periphery of the exposed initial semiconductor body by an epitaxy process before at least the partially exposed initial semiconductor body is subjected to the metallization process;

[0126] subjecting at least the exposed initial semiconductor body and the semiconductor thickening layer to at least the metallization process to form the metal semiconductor compound layer; and using the exposed initial semiconductor body and the semiconductor thickening layer subjected to the metallization process as the conductive structure.

[0127] Figures 7a-7e A cross-sectional view of a process for forming a conductive structure and a semiconductor body is provided in an embodiment of the present disclosure. In the embodiment of the present disclosure, the surface of the upper end of the initial semiconductor body is thickened before being subjected to the metallization process. Specifically:

[0128] Reference Figure 7a a plurality of initial semiconductor bodies 4010 extending along the Z axis are formed; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. The initial semiconductor body 4010 can be formed in the manner described above with reference to the examples given in the foregoing Figures 4a-4d .

[0129] Reference Figure 7b part of the initial dielectric layer 4033 is removed along the Z axis from the top of the initial dielectric layer, exposing part of the initial semiconductor body. At this time, the initial semiconductor body 4010 includes an exposed initial semiconductor body 4011 and an unexposed initial semiconductor body 4012. The removal of part of the initial dielectric layer can be performed in the manner described above with reference to the description in the foregoing Figure 5b .

[0130] Reference Figure 7csemiconductor thickening layer 7010 is formed on the exposed side surface of the exposed initial semiconductor body 4011 by an epitaxial process. Here, the semiconductor thickening layer is formed uniformly based on each exposed surface of the exposed initial semiconductor body 4011. That is, the semiconductor thickening layer has a uniform variation in size along the Z-axis direction, and also has a uniform variation in size along a direction perpendicular to the Z-axis direction. A cross-sectional shape of the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 together along a plane formed by the intersection of the X-axis and the Y-axis is the same as a cross-sectional shape of the exposed initial semiconductor body 4011 along the plane. In some embodiments, the material of the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 is monocrystalline silicon. In some embodiments, the thickness (1 / 2 of the size along the X-axis direction) of the semiconductor thickening layer 7010 can be adjusted according to actual processes, and for example, the thickness of the semiconductor thickening layer 7010 ranges from 1 nm to 5 nm.

[0131] In some embodiments, the semiconductor thickening layer 7010 can also be located on the top of the exposed initial semiconductor body 4011 (not shown in the figure). Figure 7c

[0132] Reference is made to Figure 7d At least part of the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 is at least subjected to a metallization process to form a metal semiconductor compound layer 5010. In some embodiments, the metal element in the metal semiconductor compound layer 5010 includes but is not limited to nickel, cobalt, titanium, or the like.

[0133] In some embodiments, forming the metal semiconductor compound layer 5010 includes: forming an initial metal layer covering the exposed surface of the structure to be subjected to the metallization process (including the top surface of the exposed initial semiconductor body 4011 and the side surface of the semiconductor thickening layer 7010 in the figure); and performing an annealing process on the structure to be subjected to the metallization process on which the initial metal layer is formed to form the metal semiconductor compound layer. Figure 7c

[0134] It should be noted that in the metallization process, the metal semiconductor compound layer can have different proportions in the semiconductor material with different degrees of metallization. In some embodiments, in the metallization process, the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 are fully metallized together, based on which the formed conductive structure 1064 is entirely the metal semiconductor compound layer, and the unexposed initial semiconductor body 4012 forms the semiconductor body 1030, which can be referred to in the figure. Figure 7d

[0135] ​​​In some embodiments, during the metallization process, the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 are partially metallized, the interior of the exposed initial semiconductor body 4011 is still the semiconductor layer 6010, based on which, the formed conductive structure 1064 includes the semiconductor layer 6010 and the metal semiconductor compound layer 5010 surrounding the semiconductor layer 6010, and the unexposed initial semiconductor body 4012 forms the semiconductor body 1030. It can be understood that, since the semiconductor layer 6010 is actually a part of the exposed initial semiconductor body 4011, it is consistent with the material of the entire initial semiconductor body, such as monocrystalline silicon, and there is no interface between it and the unexposed initial semiconductor body 4012. For a detailed understanding, please refer to Figure 6b

[0136] In some embodiments, during the metallization process, the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 are fully metallized, and the metal semiconductor compound layer 5010 further extends into the unexposed initial semiconductor body 4012. It should be noted that at this time, the metal semiconductor compound extending into the unexposed initial semiconductor body 4012 may not necessarily be a regular shape, such as the middle bottom being lower than the edge bottom. Based on this, the formed conductive structure 1064 overlaps with the unexposed initial semiconductor body 4012, at this time, the formed conductive structure 1064 is entirely the metal semiconductor compound layer, and the unexposed initial semiconductor body 4012 forms the semiconductor body 1030. For a detailed understanding, please refer to Figure 6c

[0137] It can be understood that, in the foregoing embodiments, a part of the initial semiconductor body 4010 is used to form the conductive structure 1064 after thickening and metallization, and another part of the initial semiconductor body 4010 is used to form the semiconductor body 1030. Because the initial semiconductor body 4010 is once-formed from bottom to top, and the conductive structure 1064 and the semiconductor body 1030 share the same initial semiconductor body 4010, the conductive structure 1064 and the semiconductor body 1030 can be directly self-aligned, and the semiconductor thickening layer makes the structure to be metallized thicker than the semiconductor body, which can obtain a larger conductive structure, thereby improving the connection window between the conductive structure and the storage structure, and also achieving the effect of further reducing the contact resistance.

[0138] In some embodiments, please refer to Figure 7d ​​After forming the plurality of conductive structures 1064, a first dielectric layer 5020 is filled between the plurality of conductive structures 1064; the remaining initial dielectric layer forms a second dielectric layer 5030; the material of the first dielectric layer 5020 is the same as or different from the material of the second dielectric layer 5030. In some embodiments, the material of the first dielectric layer 5020 is the same as the material of the second dielectric layer 5030, for example, both are silicon oxide. In some other embodiments, the material of the first dielectric layer 5020 is different from the material of the second dielectric layer 5030, for example, the material of the first dielectric layer 5020 is silicon nitride or silicon nitride boron, and the material of the second dielectric layer 5030 is silicon oxide.

[0139] In some embodiments, the semiconductor body and the conductive structure are formed by:

[0140] forming an initial semiconductor body extending along the first direction; a plurality of initial semiconductor bodies are separated by an initial dielectric layer; one surface of the initial semiconductor body exposed relative to the other surface of the initial semiconductor body along the first direction;

[0141] forming a metal semiconductor compound layer by performing a metallization process on part of the initial semiconductor body using the exposed surface; the metal semiconductor compound layer is used as the conductive structure, and the remaining part of the initial semiconductor body that is not metallized forms the semiconductor body.

[0142] Figures 8a-8d a cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure Figure 3 In the embodiments of the present disclosure, the upper end of the initial semiconductor body is metallized directly using the top surface of the initial semiconductor body exposed. Specifically:

[0143] Reference is made to Figure 8a forming a plurality of initial semiconductor bodies 4010 extending along the Z-axis direction; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. The specific formation of the initial semiconductor body 4010 can refer to the examples given in the foregoing Figures 4a-4d .

[0144] Reference is made to Figure 8b forming an initial metal layer 8010 covering the top surface of the initial semiconductor body 4010; at this time, the initial metal layer 8010 covers the top surface of the initial semiconductor body 4010 and the top surface of the initial dielectric layer 4033; the structure to be metallized with the initial metal layer is subjected to an annealing process. As described above, the metallization process is mainly performed in the semiconductor material covered by the initial metal layer 8010.

[0145] Based on this, reference is made to Figure 8cThe exposed top portion of the initial semiconductor body 4011 is subjected to a metallization process to form a metal semiconductor compound layer 5010. In some embodiments, the metal element in the metal semiconductor compound layer 5010 includes, but is not limited to, nickel, cobalt, titanium, or the like. The remaining metal layer 8011 covering the top surface of the initial dielectric layer 4033 remains. The metal semiconductor compound layer is the conductive structure 1064, and the remaining portion of the initial semiconductor body that is not subjected to the metallization process forms the semiconductor body 1030.

[0146] The metallization process does not occur in the non-semiconductor material, such as oxide or nitride, that covers the initial metal layer. Based on this, referring to Figure 8d After the metal semiconductor compound layer is formed, the remaining metal layer 8011 covering the non-semiconductor material is removed.

[0147] It can be appreciated that in the foregoing embodiments, the conductive structure 1064 is formed by directly metallizing the exposed top portion of the initial semiconductor body 4010, and the semiconductor body 1030 is formed by another portion of the initial semiconductor body 4010. Because the initial semiconductor body 4010 is monolithically formed from bottom to top, and the conductive structure 1064 and the semiconductor body 1030 share the same initial semiconductor body 4010, the conductive structure 1064 and the semiconductor body 1030 can be directly self-aligned, and this scheme is relatively Figures 5a-5d The illustrated scheme further reduces the process of removing the initial dielectric layer, and the scheme is simple and further saves the fabrication process.

[0148] It should be noted that the material of the first dielectric layer between the plurality of conductive structures is the same as the material of the second dielectric layer between the plurality of semiconductor bodies. In some embodiments, both are silicon oxide. As previously described, if the insulating material used in the subsequent process to form the storage structure includes silicon oxide, a barrier layer that is different from the silicon oxide in etching selectivity needs to be formed on the second dielectric layer before the storage structure is formed.

[0149] It should be noted that in the foregoing embodiments, because the conductive structure shares the same semiconductor pillar with the semiconductor body used to form the vertical transistor, whether the source and drain doping of the vertical transistor is performed before or after the metallization process, the doping ions will remain in the conductive structure. Based on this, the semiconductor body extends in the first direction; the conductive structure has doping ions, and the type of the doping ions is the same as the doping type of the doping ions in the opposite ends of the semiconductor body along the first direction.

[0150] In some embodiments, forming the semiconductor pillar semiconductor body and the interconnection structure conductive structure includes:

[0151] forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer;

[0152] removing part of the initial semiconductor bodies to form second trenches in the initial dielectric layer; the remaining initial semiconductor bodies form the semiconductor bodies;

[0153] widening the second trenches to form first trenches; the first trenches have a dimension along a second direction that is greater than a dimension of the second trenches along the second direction, the second direction being perpendicular to the first direction;

[0154] forming the conductive structures in the first trenches.

[0155] Figures 9a-9e A cross-sectional view of a process of forming a conductive structure and a semiconductor body is provided in the embodiments of the present disclosure. In the embodiments of the present disclosure, after removing the upper end of the initial semiconductor body, the removed position is widened, and the semiconductor material formed in the widened position is metallized. Specifically:

[0156] Reference Figure 9a forming a plurality of initial semiconductor bodies 4010 extending along the Z-axis direction; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. The specific forming method of the initial semiconductor body 4010 can refer to the examples given in the foregoing Figures 4a-4d .

[0157] Reference Figure 9b from the top of the initial dielectric layer, part of the initial semiconductor bodies 4010 are removed along the Z-axis direction to form second trenches 9010 in the initial dielectric layer 4033. In some embodiments, after part of the initial semiconductor bodies 4010 are removed, the top surface of the remaining initial semiconductor bodies is higher than the top surface of the gate electrode, and the remaining initial semiconductor bodies form the semiconductor bodies. In some specific embodiments, the method of forming the second trenches 9010 can include but is not limited to dry etching.

[0158] It can be understood that after part of the initial semiconductor bodies 4010 are removed, the dimension of the second trenches 9010 along the second direction, i.e., the X-axis direction, is the same as the dimension of the initial semiconductor bodies 4010 along the second direction, i.e., the X-axis direction, and the dimension of the second trenches 9010 along the third direction, i.e., the Y-axis direction, is the same as the dimension of the initial semiconductor bodies 4010 along the third direction, i.e., the Y-axis direction.

[0159] In some embodiments, reference Figure 9cThe second trench 9010 is widened by removing part of the initial dielectric layer 4033 on the side of the second trench 9010, and a first trench 9020 is formed. In some embodiments, the method of removing part of the initial dielectric layer 4033 on the side of the second trench 9010 can include, but is not limited to, dry etching.

[0160] It can be understood that the size L1 of the first trench 9020 along the second direction (i.e., the X-axis direction) is greater than the size L2 of the second trench 9010 along the second direction (i.e., the X-axis direction), and / or the size of the first trench 9020 along the third direction (i.e., the Y-axis direction) is greater than the size of the second trench 9010 along the third direction (i.e., the Y-axis direction).

[0161] Reference is made to FIG. 9B, which is a schematic view of a structure obtained after the second trench 9010 is widened, according to some embodiments of the present disclosure. Figure 9d The conductive structure 1064 is formed in the first trench 9020. In some embodiments, forming the conductive structure in the first trench 9020 can specifically include forming an initial semiconductor layer 9030 in the first trench 9020. In some embodiments, the initial semiconductor layer 9030 is formed in the first trench 9020 by a deposition process, and the material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon. In other embodiments, the initial semiconductor layer 9030 is formed in the first trench 9020 by an epitaxy process, and the material of the initial semiconductor layer includes a single-crystal material, such as single-crystal silicon.

[0162] Reference is made to FIG. 9C, which is a schematic view of a structure obtained after the initial semiconductor layer 9030 is formed in the first trench 9020, according to some embodiments of the present disclosure. Figure 9e The initial semiconductor layer 9030 is subjected to a metallization process to form a metal semiconductor compound layer 5010, which is used as the conductive structure 1064. The process of the metallization process can be understood with reference to the foregoing metallization process.

[0163] It should be noted that in some embodiments of the present disclosure, the second trench 9010 is not widened, and the metal semiconductor compound layer 5010 is directly formed in the second trench 9010 to obtain the conductive structure 1064.

[0164] In some embodiments, forming the semiconductor body and the conductive structure includes:

[0165] A plurality of initial semiconductor bodies extending along the first direction are formed, and the plurality of initial semiconductor bodies are separated by an initial dielectric layer.

[0166] Part of the initial dielectric layer is removed along the first direction to expose part of the initial semiconductor bodies.

[0167] A liner layer covering the exposed side of the initial semiconductor body is formed.

[0168] filling a first dielectric layer between the liner layers;

[0169] removing part of the initial semiconductor body; the remaining initial semiconductor body forms the semiconductor body; the remaining initial dielectric layer forms the second dielectric layer;

[0170] removing part of the liner layer covering the side surface of the first dielectric layer to form a plurality of first grooves; the remaining liner layer forms a third dielectric layer;

[0171] forming the conductive structure in the first grooves.

[0172] Figures 10a-10i A cross-sectional schematic diagram of a process for forming a conductive structure and a semiconductor body is provided in the embodiments of the present disclosure. In the embodiments of the present disclosure, a liner layer is formed around the exposed upper end of an initial semiconductor body to subsequently form a semiconductor material larger in size than the initial semiconductor body, and the semiconductor material is metallized. Specifically:

[0173] Reference Figure 10a A plurality of initial semiconductor bodies 4010 extending along the Z-axis direction are formed; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. The specific formation method of the initial semiconductor body 4010 can refer to the examples given in the foregoing Figures 4a-4d .

[0174] Reference Figure 10b Part of the initial dielectric layer 4033 is removed along the Z-axis direction from the top of the initial dielectric layer 4033 to expose part of the initial semiconductor body, at this time, the initial semiconductor body 4010 includes exposed initial semiconductor body 4011 and unexposed initial semiconductor body 4012. The remaining initial dielectric layer forms a second dielectric layer 5030; the specific formation method of removing part of the initial dielectric layer can refer to the description in the foregoing Figure 5b .

[0175] Reference Figure 10cA liner layer 1110 is formed on the top surface and the side surface of the exposed initial semiconductor body 4011. Here, the liner layer 1110 is formed uniformly based on each exposed surface of the exposed initial semiconductor body 4011, that is, the size of the liner layer along the Z-axis direction varies uniformly, and the size of the liner layer along the direction perpendicular to the Z-axis direction also varies uniformly. The cross-sectional shape of the exposed initial semiconductor body 4011 and the liner layer 1110 together along the plane formed by the intersection of the X-axis and the Y-axis is the same as the cross-sectional shape of the exposed initial semiconductor body 4011 along the plane. In some embodiments, the method of forming the liner layer 1110 includes but is not limited to PVD, CVD, ALD, etc. In some embodiments, the thickness of the liner layer 1110 (1 / 2 of the size along the X-axis direction) can be adjusted according to the actual process. For example, the thickness of the liner layer 1110 ranges from 1 nm to 5 nm.

[0176] Referring to Figure 10d The first dielectric layer 5020 is filled between the liner layers 1110. In some embodiments, the etching selectivity ratio of the liner layer 1110 and the first dielectric layer is different. For example, the material of the first dielectric layer 5020 can include an oxide such as silicon oxide; the material of the liner layer 1110 can include a nitride such as silicon nitride, silicon oxynitride, or one or more of high dielectric materials. In some embodiments, the method of forming the first dielectric layer 5020 includes depositing a first dielectric material layer between the liner layers 1110 by PVD, CVD, etc., and removing part of the first dielectric material layer by CMP, etc., wherein part of the liner layer 1110 located on the top of the exposed initial semiconductor body 4011 is removed at the same time as part of the first dielectric material layer is removed to expose the top of the initial semiconductor body 4011.

[0177] Referring to Figure 10e Part of the initial semiconductor body 4011 is removed along the Z-axis direction from the top of the exposed initial semiconductor body 4011, and the surface S1 of the remaining initial semiconductor body is higher than the surface S2 of the third dielectric layer 1120 close to the first dielectric layer 5020. In some embodiments, the method of removing part of the initial semiconductor body 4011 includes but is not limited to a dry etching process.

[0178] Referring to Figure 10f Part of the liner layer 1110 covering the side surface of the first dielectric layer 5020 is removed to form a plurality of first grooves 9020, the remaining liner layer 1110 forms the third dielectric layer 1120, and the surface S1 of the remaining initial semiconductor body is higher than the surface S2 of the third dielectric layer close to the first dielectric layer. In some embodiments, the method of removing part of the liner layer 1110 covering the side surface of the first dielectric layer 5020 includes but is not limited to a wet etching process.

[0179] In some embodiments, the third dielectric layer 1120 can include at least a first sub-dielectric layer, and the third dielectric layer 1120 can include a first sub-dielectric layer 1121 and a second sub-dielectric layer 1122; wherein the first sub-dielectric layer 1121 extends along the second direction, i.e., the X-axis direction, and covers the second dielectric layer 5030, and the second sub-dielectric layer 1122 extends along the first direction, i.e., the Z-axis direction, and covers part of the side surface of the initial semiconductor body 4010.

[0180] In some embodiments, the remaining initial semiconductor body extends to the first trench 9020 from the end of the two ends of the remaining initial semiconductor body that are oppositely arranged along the first direction and that are close to the first trench 9020; and the surface S1 of the remaining initial semiconductor body close to the first trench 9020 is higher than the surface S3 of the second sub-dielectric layer 1122 close to the first trench 9020.

[0181] In some embodiments, the sum of the size of the second sub-dielectric layer 1122 and the size of the remaining initial semiconductor body in the second direction, i.e., the Y-axis direction, is the same as the size of the first trench 9020 in the second direction, i.e., the Y-axis direction.

[0182] It can be understood that the size of the first trench 9020 along the second direction, i.e., the X-axis direction, is greater than the size of the initial semiconductor body 4010 along the second direction, i.e., the X-axis direction, and the size of the first trench 9020 along the third direction, i.e., the Y-axis direction, is greater than the size of the initial semiconductor body 4010 along the third direction, i.e., the Y-axis direction. That is, the size of the pad layer after being removed and then used to form the conductive structure is greater than the size of the initial semiconductor body, so that the effect of thickening the conductive structure is achieved, and the thickness of the pad layer is the thickness by which the conductive structure is thickened compared with the initial semiconductor body 4010.

[0183] In addition, due to the large area of the second dielectric layer 5030, there may be defects such as cavities during filling. Here, S1 is higher than S2, which can protect the second dielectric layer 5030 from being exposed, thereby avoiding the etching liquid from entering the cavity and causing adverse consequences when the pad layer 1110 on the side of the first dielectric layer 5020 is removed by wet etching.

[0184] Next, referring to Figure 10g , Figure 10h and Figure 10i , the conductive structure 1064 is formed in the first trench 9020. In some embodiments, forming the conductive structure in the first trench includes: forming an initial semiconductor layer 9030 in the first trench; and performing a metallization process on the initial semiconductor layer 9030 to form a metal semiconductor compound layer 5010.

[0185] In some specific embodiments, referring to Figure 10gIn some embodiments, the initial semiconductor layer is formed in the first trench by a deposition process, and a material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon.

[0186] Figures 10a-10f In some embodiments, the initial semiconductor layer is formed in the first trench by an epitaxy process, and a material of the initial semiconductor layer includes a single-crystal material, such as single-crystalline silicon. Figure 11a Figure 11b In some embodiments, the initial semiconductor layer is formed in the first trench by a deposition process, and a material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon. Figure 11c In some embodiments, the initial semiconductor layer is formed in the first trench by an epitaxy process, and a material of the initial semiconductor layer includes a single-crystal material, such as single-crystalline silicon.

[0187] Figure 11a In some embodiments, the initial semiconductor layer is formed in the first trench by a deposition process, and a material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon.

[0188] In some embodiments, the initial semiconductor layer is formed in the first trench by an epitaxy process, and a material of the initial semiconductor layer includes a single-crystal material, such as single-crystalline silicon. Figure 10h Figure 11b In some embodiments, the initial semiconductor layer is formed in the first trench by a deposition process, and a material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon.

[0189] In some embodiments, the initial semiconductor layer is formed in the first trench by an epitaxy process, and a material of the initial semiconductor layer includes a single-crystal material, such as single-crystalline silicon.

[0190] In some embodiments, the initial semiconductor layer is formed in the first trench by a deposition process, and a material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon. Figure 10i Figure 11c In some embodiments, the initial semiconductor layer is formed in the first trench by an epitaxy process, and a material of the initial semiconductor layer includes a single-crystal material, such as single-crystalline silicon.

[0191] In some embodiments, the initial semiconductor layer is formed in the first trench by a deposition process, and a material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon. Figures 12a-12d In some embodiments, the initial semiconductor layer is formed in the first trench by an epitaxy process, and a material of the initial semiconductor layer includes a single-crystal material, such as single-crystalline silicon.

[0192] ​​​​In some specific embodiments, Figure 12a As shown, during the metallization process, the initial semiconductor layer 9030 is partially metallized, the top of the initial semiconductor layer 9030 is metallized, and the rest of the initial semiconductor layer 9030 is not metallized. Furthermore, a metal layer 1130 is formed on top of the initial semiconductor layer 9030. Consequently, the conductive structure 1064 is formed to include the semiconductor layer 6010, the metal-semiconductor compound layer 5010, and the metal layer 1130 stacked in sequence.

[0193] In some specific embodiments, Figure 12b As shown, during the metallization process, a portion of the initial semiconductor layer 9030 is metallized, the top portion of the initial semiconductor layer 9030 is metallized, and the remaining portion of the initial semiconductor layer 9030 is not metallized. Furthermore, no metal layer is formed on top of the initial semiconductor layer 9030. Consequently, the resulting conductive structure 1064 includes a semiconductor layer 6010 and a metal-semiconductor compound layer 5010 stacked sequentially.

[0194] In some specific embodiments, Figure 12c As shown, during the metallization process, the initial semiconductor layer 9030 is completely metallized, and no metal layer is formed on top of the initial semiconductor layer 9030. Based on this, the formed conductive structure 1064 is entirely a metal-semiconductor compound layer.

[0195] In some specific embodiments, Figure 12d As shown, during the metallization process, the initial semiconductor layer 9030 is completely metallized, while the metal-semiconductor compound layer 5010 extends further into the initial semiconductor body 4010 below the third dielectric layer. Furthermore, no metal layer is formed on top of the initial semiconductor layer 9030. Consequently, there is a certain overlap between the formed conductive structure 1064 and the initial semiconductor body 4010 below the third dielectric layer. In this case, the formed conductive structure 1064 is entirely a metal-semiconductor compound layer, while the unmetallized portion of the initial semiconductor body 4010 below the third dielectric layer forms the semiconductor body 1030.

[0196] It can be understood that in the foregoing embodiments, the conductive structure 1064 is formed by thickening and metallizing part of the initial semiconductor body 4010, and the semiconductor body 1030 is formed by the other part of the initial semiconductor body 4010. Because the initial semiconductor body 4010 is once formed from bottom to top, and the conductive structure 1064 and the semiconductor body 1030 share the same initial semiconductor body 4010, the conductive structure 1064 and the semiconductor body 1030 can be directly self-aligned, and the initial semiconductor body 4010 can be thickened by the liner layer to obtain a larger conductive structure, thereby improving the connection window between the conductive structure and the storage structure, and also achieving the effect of further reducing the contact resistance.

[0197] Meanwhile, the initial semiconductor body 4010 is thickened by the liner layer, and the liner layer can be conformally formed on the surface of the initial semiconductor body, and the process controllability is good; in addition, the initial semiconductor body 4010 is thickened by the liner layer, and no additional mask layer is needed, which is conducive to reducing the manufacturing cost.

[0198] Here, the fabrication of the conductive structure and the semiconductor body is completed, and the fabrication of other structures of the semiconductor device will be introduced next.

[0199] In some embodiments, step S303 is performed to form a storage structure connected to the metal semiconductor compound layer on the second surface of the conductive structure; the formation method of the storage structure is relatively mature, and will not be described here.

[0200] In some specific embodiments, the storage structure includes a capacitor; the formation of the storage structure includes forming a cup-shaped capacitor CUP, a cylindrical capacitor CYL, or a pillar-shaped capacitor PIL. The shape of the capacitor can be selected and set according to actual needs, and the present disclosure is not limited.

[0201] In some embodiments, the method further includes: forming a word line on at least one side of the semiconductor body; and forming a bit line on the surface of the semiconductor body that is away from the conductive structure among the two surfaces of the semiconductor body that are oppositely arranged along the first direction.

[0202] Here, the word line can extend along a third direction, and the bit line can extend along a second direction.

[0203] In some embodiments, forming a word line on at least one side of the semiconductor body includes: forming the word line on one side of the semiconductor body; forming the word line on two oppositely arranged sides of the semiconductor body; and forming a word line that surrounds the side of the semiconductor body.

[0204] It is understood that the conductive structure in the embodiments of the present disclosure can be applied to different word line (gate structure) scenarios. For example, the conductive structure in the embodiments of the present disclosure can be applied to a scenario where two word line structures corresponding to two adjacent semiconductor bodies are arranged back-to-back. The figures in the embodiments of the present disclosure use the back-to-back arrangement as an example.

[0205] In some specific embodiments, two adjacent semiconductor bodies form a semiconductor body group, and the two semiconductor bodies in a semiconductor body group are separated by a first isolation structure (ie, Figure 4d The first isolation structure 4020 is separated; the two adjacent semiconductor body groups are separated by the second isolation structure (ie Figure 4d The final form corresponding to the second isolation structure 4030 in the semiconductor body, the lower end of the gate electrode is disconnected); forming a word line on at least one side of the semiconductor body, including: forming the word line on one side away from the first isolation structure in the two side surfaces of the corresponding semiconductor body in the semiconductor body group.

[0206] In the embodiment of the present disclosure, self-alignment of the conductive structure and the semiconductor body can be achieved through clever use of the initial semiconductor body, which can increase the alignment accuracy of the conductive structure and the semiconductor body, reduce the difficulty of alignment between the two, improve the reliability of the semiconductor device, save production time and cost, and improve process speed and efficiency; on the other hand, the metal semiconductor compound layer, as the material of the conductive structure between the semiconductor body and the storage structure, has a low resistivity, which can achieve better electrical connection between the semiconductor body and the storage structure, thereby improving the reliability of the semiconductor device.

[0207] An embodiment of the present disclosure also provides a semiconductor device, comprising: a conductive structure having a first surface and a second surface arranged opposite to each other along a first direction; the conductive structure at least comprising a metal semiconductor compound layer extending along the first direction; a semiconductor body located on the first surface of the conductive structure and connected to the metal semiconductor compound layer; and a storage structure located on the second surface of the conductive structure and connected to the metal semiconductor compound layer.

[0208] In some embodiments, the conductive structure is entirely the metal-semiconductor compound layer.

[0209] In some embodiments, the conductive structure further includes a semiconductor layer, wherein the semiconductor layer is in contact with the semiconductor body and is surrounded by the metal-semiconductor compound layer.

[0210] In some embodiments, the metal element in the metal semiconductor compound layer includes nickel, cobalt, or titanium; and the material of the semiconductor layer includes a single crystal material.

[0211] In some embodiments, the conductive structure comprises at least a first portion, a side of the first portion is aligned with a side of the semiconductor body along the first direction.

[0212] In some embodiments, the conductive structure further comprises a second portion surrounding the first portion, a sum of dimensions of the first portion and the second portion in a cross section perpendicular to the first direction is greater than a dimension of the semiconductor body in a cross section perpendicular to the first direction.

[0213] Here, the first portion can be understood as a portion overlapping with a projection of the semiconductor body on a cross section perpendicular to the first direction, and the second portion can be understood as a portion thickened or enlarged in various manners.

[0214] In some embodiments, the conductive structure and the semiconductor body form a step structure at a connection therebetween, the step structure comprises a side extending along the first direction and a step surface extending along a second direction perpendicular to the first direction.

[0215] In some embodiments, dimensions of the step structure along the second direction are all same in the first direction, and dimensions of the step structure along the first direction are all same in the second direction.

[0216] In some embodiments, there is no interface between the semiconductor layer in the conductive structure and the semiconductor body.

[0217] In some embodiments, the semiconductor body extends along a first direction; the conductive structure comprises a type of doping ion, and the type of the doping ion is same as a doping type of doping ions in opposite ends of the semiconductor body along the first direction.

[0218] In some embodiments, the semiconductor body and the conductive structure both comprise a plurality of semiconductor bodies and a plurality of conductive structures; the semiconductor device further comprises: a first dielectric layer between the plurality of conductive structures; a second dielectric layer between the plurality of semiconductor bodies; the first dielectric layer and the second dielectric layer are same or different in material; the first dielectric layer and the second dielectric layer both comprise an oxide; or, the first dielectric layer comprises a nitride, and the second dielectric layer comprises an oxide.

[0219] In some embodiments, the semiconductor body, the conductive structure and the storage structure both comprise a plurality of semiconductor bodies, a plurality of conductive structures and a plurality of storage structures; the plurality of semiconductor bodies are arranged in an array.

[0220] The semiconductor device further includes a plurality of word lines coupled with at least one side surface of each semiconductor body in a row of the semiconductor bodies; and a plurality of bit lines coupled with a surface of each semiconductor body in a column of the semiconductor bodies, which is distal to the conductive structure and opposite to the other surface of the semiconductor body along the first direction.

[0221] In some embodiments, the word line is located at one side surface of the semiconductor body; or the word line is located at two opposite side surfaces of the semiconductor body; or the word line encircles the side surface of the semiconductor body.

[0222] In some embodiments, two adjacent semiconductor bodies form a semiconductor body group, and the two semiconductor bodies in the semiconductor body group are spaced apart by a first isolation structure; two adjacent semiconductor body groups are spaced apart by a second isolation structure; and the two word lines are respectively located at two side surfaces of the corresponding semiconductor bodies in the semiconductor body group, which are distal to the first isolation structure.

[0223] In some embodiments, a dimension of the storage structure at a cross section perpendicular to the first direction, which is proximal to the conductive structure, is greater than a dimension of the storage structure at a cross section perpendicular to the first direction, which is distal to the conductive structure.

[0224] In some embodiments, the storage structure includes a capacitor; and the capacitor includes a cup-shaped capacitor, a cylinder-shaped capacitor, or a pillar-shaped capacitor.

[0225] It should be noted that the features of each structure in the semiconductor device described above can be understood with reference to the features of each structure described in the method of manufacturing the semiconductor device.

[0226] In some embodiments, the semiconductor device includes a memory device, and the memory device includes a DRAM.

[0227] Figure 13 A structure diagram of a dynamic random access memory according to an embodiment of the present disclosure is shown in FIG. 2. Figure 13As shown, the semiconductor device 100 comprises: a conductive structure having a first surface and a second surface oppositely arranged along a first direction; the conductive structure comprises at least a metal semiconductor compound layer extending along the first direction; a semiconductor body located at the first surface of the conductive structure and connected with the metal semiconductor compound layer; a storage structure located at the second surface of the conductive structure and connected with the metal semiconductor compound layer. The conductive structure 1064 is arranged in alignment with the geometric center of the semiconductor body 1030, and it should be understood that the alignment here needs to exclude slight deviations caused by manufacturing errors and the like. The conductive structure 1064 has the same size along a second direction (for example, the X-axis) as the semiconductor body 1030 along the second direction (for example, the X-axis), and it should be understood that the same here needs to exclude slight size deviations caused by metallization processing and the like. The conductive structure 1064 comprises a metal semiconductor compound layer extending along the first direction. Figure 13 Other structures shown in the foregoing embodiments can be understood with reference to Figure 1 .

[0228] Figure 14 A structure of a dynamic random access memory provided by the embodiments of the present disclosure Figure 3 ; and Figure 13 the difference is that the conductive structure 1064 has a size along a second direction (for example, the X-axis) greater than the size of the semiconductor body 1030 along the second direction (for example, the X-axis), and the excess size on both sides of the conductive structure 1064 relative to the semiconductor body 1030 is the same.

[0229] It should be noted that Figure 13 and Figure 14 shown are only application examples of the conductive structure and the semiconductor body in the dynamic random access memory in the foregoing embodiments of the present disclosure, and it can be understood that other conductive structures and semiconductor bodies in the foregoing embodiments of the present disclosure can also be similarly applied to the dynamic random access memory.

[0230] It should be noted that Figure 13 and Figure 14 shown are similar Figure 1 only show examples under the condition that the first device 102 and the second device 104 are connected by bonding, and it can be understood that other conductive structures and semiconductor bodies in the foregoing embodiments of the present disclosure can also be similarly applied to the case where the foregoing first device 102 and the second device 104 are directly stacked on the same substrate.

[0231] It should be noted that Figure 13 and Figure 14 shown are similar Figure 1Only the example that two adjacent semiconductor bodies correspond to two gate structures respectively arranged back to back is shown, and it can be understood that other conductive structures in the foregoing embodiments of the present disclosure can also be applied to the various different cases that the foregoing gate structures are located on the same side of the semiconductor body, the gate structures are located on the opposite sides of the semiconductor body, and the gate structures surround the semiconductor body.

[0232] The embodiment of the present disclosure further provides a storage system, comprising: the semiconductor device as described in the foregoing embodiments of the present disclosure; and a memory controller connected with the semiconductor device and used for controlling the semiconductor device.

[0233] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0234] The specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this, any person skilled in the art in the technical range disclosed by the present disclosure, can easily think of changes or replacement, should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a conductive structure having a first surface and a second surface oppositely arranged along a first direction; the conductive structure comprises at least a metal-semiconductor compound layer extending along the first direction; a semiconductor body located on the first surface of the conductive structure and connected to the metal-semiconductor compound layer; a storage structure located on the second surface of the conductive structure and connected to the metal-semiconductor compound layer.

2. The semiconductor device according to claim 1, wherein The conductive structure is entirely the metal-semiconductor compound layer.

3. The semiconductor device of claim 1, wherein The conductive structure further comprises a semiconductor layer, which is in contact with the semiconductor body and surrounded by the metal-semiconductor compound layer.

4. The semiconductor device according to claim 3, wherein The metal element in the metal-semiconductor compound layer comprises nickel, cobalt or titanium; and the material of the semiconductor layer comprises a single crystal material.

5. The semiconductor device according to claim 2 or 3, wherein The conductive structure comprises at least a first part, the side surface of which is aligned with the side surface of the semiconductor body along the first direction.

6. The semiconductor device of claim 5, wherein, The conductive structure further comprises a second part surrounding the first part, and the sum of the sizes of the first part and the second part in a cross section perpendicular to the first direction is greater than the size of the semiconductor body in a cross section perpendicular to the first direction.

7. The semiconductor device of claim 6, wherein The conductive structure and the semiconductor body form a step structure at the connection therebetween, which comprises a side surface extending along the first direction and a step surface extending along a second direction perpendicular to the first direction.

8. The semiconductor device of claim 7, wherein, The sizes of the step structure along the second direction are all the same in the first direction, and the sizes of the step structure along the first direction are all the same in the second direction.

9. The semiconductor device according to claim 2 or 3, wherein There is no interface between the semiconductor layer in the conductive structure and the semiconductor body.

10. The semiconductor device of claim 1, wherein The semiconductor body extends along the first direction. The conductive structure has doping ions, and the type of the doping ions is the same as the doping type of the doping ions in the opposite ends of the semiconductor body along the first direction.

11. The semiconductor device of claim 1, wherein The semiconductor body and the conductive structure both comprise a plurality of semiconductor bodies and conductive structures, and the semiconductor device further comprises: a first dielectric layer between the plurality of conductive structures; a second dielectric layer between the plurality of semiconductor bodies; the materials of the first dielectric layer and the second dielectric layer are the same or different; the materials of the first dielectric layer and the second dielectric layer both comprise an oxide; or the material of the first dielectric layer comprises a nitride, and the material of the second dielectric layer comprises an oxide.

12. The semiconductor device of claim 1, wherein The semiconductor body, the conductive structure and the storage structure both comprise a plurality of semiconductor bodies, semiconductor structures and storage structures, and the plurality of semiconductor bodies are arranged in an array; The semiconductor device further comprises: a plurality of word lines, each of which is coupled to at least one side surface of each semiconductor body in a row of semiconductor bodies; a plurality of bit lines, each of which is coupled to a surface of each semiconductor body in a column of semiconductor bodies, which is oppositely arranged to the surface of the semiconductor body facing the conductive structure along the first direction.

13. The semiconductor device of claim 12, wherein, The word line is located on one side surface of the semiconductor body. Alternatively, the word line is located on two oppositely arranged side surfaces of the semiconductor body. Alternatively, the word line surrounds the side surface of the semiconductor body.

14. The semiconductor device of claim 13, wherein, Two semiconductor bodies adjacent to each other form a semiconductor body group, two semiconductor bodies in a semiconductor body group are separated by a first isolation structure; two semiconductor body groups adjacent to each other are separated by a second isolation structure. Two word lines are respectively located at one side of two sides of a corresponding semiconductor body in the semiconductor body group, which is far away from the first isolation structure.

15. The semiconductor device of claim 14, wherein, The size of a cross section of the storage structure near one end of the conductive structure in a direction perpendicular to the first direction is greater than the size of a cross section of the storage structure far away from the conductive structure in the direction perpendicular to the first direction.

16. The semiconductor device of claim 1, wherein The storage structure comprises a capacitor; the capacitor comprises a cup-shaped capacitor, a cylindrical capacitor or a pillar-shaped capacitor.

17. A method of fabricating a semiconductor device, comprising: Comprising: forming a conductive structure; The conductive structure has a first surface and a second surface arranged oppositely along a first direction, and the conductive structure at least comprises a metal semiconductor compound layer extending along the first direction; forming a semiconductor body; The semiconductor body is located at the first surface of the conductive structure and connected with the metal semiconductor compound layer; forming a storage structure; The storage structure is located at the second surface of the conductive structure and connected with the metal semiconductor compound layer.

18. The method of fabricating a semiconductor device according to Claim 17, wherein forming the semiconductor body and the conductive structure, comprising: forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer; removing part of the initial dielectric layer along the first direction to expose part of the initial semiconductor bodies; the remaining initial semiconductor bodies form the semiconductor body; at least part of the exposed initial semiconductor bodies is subjected to a metallization process to form a metal semiconductor compound layer; the exposed initial semiconductor bodies subjected to the metallization process serve as the conductive structure.

19. The method of fabricating a semiconductor device according to Claim 18, wherein The method further comprises: forming a semiconductor thickening layer around the exposed initial semiconductor bodies by an epitaxy process before at least part of the exposed initial semiconductor bodies is subjected to the metallization process; at least part of the exposed initial semiconductor bodies and the semiconductor thickening layer is subjected to the metallization process to form the metal semiconductor compound layer; the exposed initial semiconductor bodies and the semiconductor thickening layer subjected to the metallization process serve as the conductive structure.

20. The method of fabricating a semiconductor device according to Claim 18, wherein The method further comprises: after forming a plurality of the conductive structures, filling a first dielectric layer between the plurality of conductive structures; the remaining initial dielectric layer forms a second dielectric layer; the material of the first dielectric layer is different from the material of the second dielectric layer.

21. The method of fabricating a semiconductor device according to Claim 17, wherein forming the semiconductor body and the conductive structure, comprising: forming an initial semiconductor body extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer; one surface of the initial semiconductor body arranged oppositely along the first direction is exposed; part of the initial semiconductor body is subjected to a metallization process by using the exposed surface to form a metal semiconductor compound layer; the metal semiconductor compound layer serves as the conductive structure, and the remaining part of the initial semiconductor body which is not subjected to the metallization process forms the semiconductor body.

22. The method of fabricating a semiconductor device according to Claim 21, wherein The initial semiconductor bodies comprise a plurality, and the conductive structures and the semiconductor bodies comprise a plurality; the material of the first dielectric layer between the plurality of conductive structures is the same as the material of the second dielectric layer between the plurality of semiconductor bodies.

23. The method of fabricating a semiconductor device according to Claim 17, wherein The semiconductor bodies and the conductive structures are formed by: forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer; removing part of the initial semiconductor bodies to form second grooves in the initial dielectric layer; the remaining initial semiconductor bodies form the semiconductor bodies; widening the second grooves to form first grooves; the size of the first grooves along a second direction is greater than the size of the second grooves along the second direction, and the second direction is perpendicular to the first direction; forming the conductive structures in the first grooves.

24. The method of fabricating a semiconductor device according to Claim 23, wherein, The semiconductor bodies and the conductive structures are formed by: forming an initial semiconductor layer in the first grooves; forming a metal semiconductor compound layer by metallizing the initial semiconductor layer.

25. The method of fabricating a semiconductor device according to Claim 24, wherein The semiconductor layer is formed in the first grooves by: forming the initial semiconductor layer in the first grooves by a deposition process, and the material of the initial semiconductor layer comprises a polycrystalline material.

26. The method of fabricating a semiconductor device according to Claim 24, wherein The semiconductor layer is formed in the first grooves by: forming the initial semiconductor layer in the first grooves by an epitaxy process, and the material of the initial semiconductor layer comprises a single crystal material.

27. The method of fabricating a semiconductor device according to claim 18 or 24, wherein The metal semiconductor compound layer is formed by: forming an initial metal layer covering the exposed surface of the structure to be metallized; annealing the structure to be metallized with the initial metal layer to form the metal semiconductor compound layer.

28. The method of fabricating a semiconductor device of claim 17, wherein, The method further comprises: forming word lines on at least one side of the semiconductor bodies; forming bit lines on the surface of the semiconductor bodies away from the conductive structures among the two surfaces of the semiconductor bodies arranged opposite along the first direction.

29. The method of fabricating a semiconductor device according to Claim 28, wherein, The word lines are formed on at least one side of the semiconductor bodies by: forming the word lines on one side of the semiconductor bodies; forming the word lines on both sides of the semiconductor bodies arranged opposite; forming the word lines surrounding the side of the semiconductor bodies.

30. The method of fabricating a semiconductor device according to Claim 29, wherein Two semiconductor bodies adjacent form a semiconductor body group, and the two semiconductor bodies in a semiconductor body group are separated by a first isolation structure; two semiconductor body groups adjacent are separated by a second isolation structure; The word lines are formed on at least one side of the semiconductor bodies by: forming the word lines on one side of the semiconductor bodies away from the first isolation structure among the two sides of the corresponding semiconductor bodies in the semiconductor body group, respectively.

31. The method of fabricating a semiconductor device of claim 17, wherein, The storage structure comprises a capacitor; the storage structure is formed by: forming a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor.

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