Manufacturing method of memory device and memory device
By forming multiple grooves in the storage device and adjusting the channel length, the problem of limited storage density improvement is solved, achieving higher storage density and lower costs.
Patent Information
- Application Number
- CN202410451138.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-15
- Publication Date
- 2025-10-24
AI Technical Summary
In the prior art, the gate length of a memory device limits the shrinking space of the memory cell, resulting in limited storage density improvement and increased processing costs.
By forming multiple first grooves and second grooves in the storage device, a gate stack structure and source/drain regions are formed in the array area respectively, and the vertical channel length is adjusted by adjusting the depth of the grooves, thereby improving storage density and reducing costs.
The storage density of the memory device is effectively improved, the manufacturing cost is reduced, and the problem that the gate length limits the storage density improvement is solved.
Smart Images
Figure CN120835554A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a manufacturing method of a memory device and the memory device. BACKGROUND
[0002] In the past few decades, scaling of integrated circuit features has been the driving force behind the ever-growing semiconductor industry, with smaller and smaller features enabling greater densities of functional units on the active area of a semiconductor chip. For example, shrinking the size of transistors allows for incorporating a greater number of memory devices or logic devices on a chip.
[0003] The present application inventors have found that current semiconductor devices, such as floating gate devices, employ a traditional ETOX (Electron Tunneling Oxide) structure, which generally scales device features by reducing the channel length. However, when the channel length is reduced to a certain extent, short channel effects occur, so the gate length needs to be set within a certain range, which limits the space for scaling the memory cell and prevents further improvement of the memory density. SUMMARY
[0004] The present application mainly solves the technical problem of providing a manufacturing method of a memory device and the memory device, which can effectively improve the memory density of the memory device and reduce the cost.
[0005] To solve the above technical problem, one technical solution adopted by the present application is to provide a manufacturing method of a memory device, comprising: providing a semiconductor base, the semiconductor base comprising a substrate and a mask layer arranged on the substrate; opening a plurality of first grooves in the semiconductor base, a part of the plurality of first grooves being located in an array region in a memory region; forming a gate stack structure in the plurality of first grooves in the array region; opening a plurality of second grooves on both sides of the gate stack structure and forming source / drain regions in the substrate at the bottom of the second grooves, wherein the highest point of the source / drain regions is lower than the surface of the substrate.
[0006] In an embodiment of the present application, the semiconductor base is provided by: providing a substrate, forming a first dielectric layer and a second dielectric layer on the substrate; opening a plurality of third grooves from the second dielectric layer towards the substrate, wherein the plurality of third grooves are sequentially and spaced apart along a first direction and extend along a second direction; forming a shallow trench isolation structure in the plurality of third grooves and removing the second dielectric layer; forming a semiconductor layer and a third dielectric layer on the first dielectric layer to form the semiconductor base, wherein the third dielectric layer covers the semiconductor layer and the shallow trench isolation structure, and the third dielectric layer, the semiconductor layer and the first dielectric layer serve as the mask layer.
[0007] In an embodiment of the present application, the forming the gate stack structure in the plurality of first recesses in the array region comprises: forming a gate insulating layer and a floating gate in the first recesses; forming an inter-gate dielectric layer and a control gate on the gate insulating layer and the floating gate; taking the gate insulating layer, the floating gate, the inter-gate dielectric layer and the control gate as the gate stack structure.
[0008] In an embodiment of the present application, the forming the inter-gate dielectric layer and the control gate comprises: forming the inter-gate dielectric layer on the floating gate, and covering the inter-gate dielectric layer with a second gate material; removing part of the second gate material in the first recesses of the array region, so that the second gate material remaining in the first recesses serves as the control gate of the storage unit.
[0009] In an embodiment of the present application, the storage region further comprises a lead-out region, another part of the plurality of first recesses is located in the lead-out region; the gate insulating layer, the floating gate, the inter-gate dielectric layer and the second gate material are formed in the first recesses in the lead-out region, the second gate material in the first recesses in the lead-out region serves as a lead-out end of the storage unit, and the lead-out end is connected to the control gates of a plurality of the storage units in the same row.
[0010] In an embodiment of the present application, the semiconductor substrate further comprises a peripheral region; after the forming the gate stack structure, the method further comprises: removing the mask layer in the peripheral region; and forming MOS tubes in the peripheral region.
[0011] In an embodiment of the present application, the forming the plurality of second recesses in the array region and forming source / drain regions in the substrate at the bottom of the second recesses comprises: forming a plurality of second recesses in the array region between the gate stack structures, wherein the depth of the second recesses is less than the depth of the first recesses; and performing ion implantation in the substrate at the bottom of the plurality of second recesses to form spaced-apart source regions and drain regions, respectively.
[0012] In an embodiment of the present application, the lowest point of the source region and / or the drain region is higher than the lowest point of the first recess.
[0013] In an embodiment of the present application, the depths of the source region and the drain region are the same or different.
[0014] To solve the above technical problems, another technical solution adopted by the present application is to provide a memory device, comprising: a substrate, a gate stack structure, a source region and a drain region; wherein a base recess is formed in the substrate; the gate stack structure is formed in the base recess; the source region and the drain region are formed in the substrate on both sides of the gate stack structure; wherein the highest point of the source region and the drain region is lower than the surface of the substrate.
[0015] In an embodiment of the present application, the gate stack structure comprises: a gate insulating layer, a floating gate, an inter-gate dielectric layer and a control gate; the gate insulating layer is formed on the inner wall of the base recess; the floating gate is formed in the base recess, and the floating gate is isolated from the substrate by the gate insulating layer; the inter-gate dielectric layer is formed in the base recess and covers the floating gate; the control gate is formed on the inter-gate dielectric layer, and the control gate is isolated from the floating gate by the inter-gate dielectric layer; wherein each storage unit of the memory device corresponds to a control gate.
[0016] In an embodiment of the present application, the memory device comprises a storage area; the base recess is located in the storage area, and the storage area comprises an array area and a lead-out area, and the gate stack structure is located in the array area; a lead-out end of a storage unit is formed in the base recess of the lead-out area, and the lead-out end is connected to the control gate of a plurality of the storage units in the same row, wherein the top of the lead-out end is higher than the base recess.
[0017] In an embodiment of the present application, further comprising: a peripheral area and MOS tubes, the peripheral area is isolated from the storage area by a shallow trench isolation structure in the substrate; a plurality of MOS tubes are formed on the substrate of the peripheral area.
[0018] In an embodiment of the present application, further comprising: the depth of the source region and the drain region is the same or different.
[0019] In an embodiment of the present application, the shallow trench isolation structure of the storage area comprises a first isolation part and a second isolation part, the first isolation part and the second isolation part are arranged at intervals in the second direction, and the highest point of the first isolation part is lower than the highest point of the floating gate, and the highest point of the second isolation part is not lower than the highest point of the floating gate.
[0020] In an embodiment of the present application, the lowest point of the source region and / or the drain region is higher than the lowest point of the base recess.
[0021] Different from the prior art, the manufacturing method of the memory device provided in the application comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a mask layer arranged on the substrate; opening a plurality of first grooves in the semiconductor substrate, and part of the plurality of first grooves is located in an array region in a storage region; forming a gate insulating layer and a gate stack structure in the plurality of first grooves in the array region; opening a plurality of second grooves on both sides of the gate stack structure, and forming a source / drain region in the substrate at the bottom of the second grooves, wherein the highest point of the source / drain region is lower than the surface of the substrate; that is, in the application, the channel length in the vertical direction is adjusted by the depth of the first grooves and the second grooves, so that the storage density of the memory device can be effectively improved, and the cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings. Among them:
[0023] Figure 1 is a flowchart of an embodiment of the manufacturing method of the memory device in the application;
[0024] Figure 2a is a first direction structure diagram of an embodiment of forming a first dielectric layer and a second dielectric layer on the substrate in the application, Figure 2b is a second direction structure diagram of an embodiment of forming a first dielectric layer and a second dielectric layer on the substrate in the application;
[0025] Figure 3a is a first direction structure diagram of an embodiment of opening a third groove to the substrate in the application, Figure 3b is a second direction structure diagram of an embodiment of opening a third groove to the substrate in the application;
[0026] Figure 4a is a first direction structure diagram of an embodiment of forming a shallow trench isolation structure in the application, Figure 4b is a second direction structure diagram of an embodiment of forming a shallow trench isolation structure in the application;
[0027] Figure 5a is a first direction structure diagram of an embodiment of removing the second dielectric layer in the application, Figure 5b is a second direction structure diagram of an embodiment of removing the second dielectric layer in the application;
[0028] Figure 6a is a first direction structure diagram of an embodiment of forming a semiconductor layer and a third dielectric layer in the application, Figure 6bis a second direction structural schematic diagram of an embodiment of forming a semiconductor layer and a third dielectric layer in the present application;
[0029] Figure 7a is a first direction structural schematic diagram of an embodiment of forming a first recess in the present application, Figure 7b is a second direction structural schematic diagram of an embodiment of forming a first recess in the present application;
[0030] Figure 8a is a structural schematic diagram of an embodiment of forming a gate insulating layer and a first gate material in the present application, Figure 8b is a structural schematic diagram of an embodiment of forming a gate insulating layer and a first gate material in the present application;
[0031] Figure 9a is a first direction structural schematic diagram of an embodiment of forming a floating gate in the present application, Figure 9b is a second direction structural schematic diagram of an embodiment of forming a floating gate in the present application;
[0032] Figure 10a is a first direction structural schematic diagram of an embodiment of lowering a shallow trench isolation structure in the present application, Figure 10b is a second direction structural schematic diagram of an embodiment of lowering a shallow trench isolation structure in the present application;
[0033] Figure 11a is a first direction structural schematic diagram of an embodiment of forming an inter-gate dielectric layer and a second gate material in the present application, Figure 11b is a second direction structural schematic diagram of an embodiment of forming an inter-gate dielectric layer and a second gate material in the present application;
[0034] Figure 12a is a first direction structural schematic diagram of an embodiment of removing part of a second gate material in the present application, Figure 12b is a second direction structural schematic diagram of an embodiment of removing a second gate material in the present application;
[0035] Figure 13a is a first direction structural schematic diagram of an embodiment of filling a first oxide layer in the present application, Figure 13b is a second direction structural schematic diagram of an embodiment of filling a first oxide layer in the present application;
[0036] Figure 14a is a first direction structural schematic diagram of an embodiment of forming a MOS transistor in the present application, Figure 14b is a second direction structural schematic diagram of an embodiment of forming a MOS transistor in the present application;
[0037] Figure 15a is a first direction structural schematic diagram of an embodiment of forming a second recess in the present application, Figure 15b is a second direction structural schematic diagram of an embodiment of forming a second recess in the present application;
[0038] Figure 16a is a first direction structure schematic diagram of one embodiment of forming source / drain region in the application, Figure 16b is a second direction structure schematic diagram of one embodiment of forming source / drain region in the application;
[0039] Figure 17 is a top view of one embodiment of memory device in the application.
[0040] In the drawings, semiconductor substrate 100, substrate 110, first dielectric layer 120, second dielectric layer 130, semiconductor layer 140, third dielectric layer 150, fourth dielectric layer 151, fifth dielectric layer 152, source / drain region 160, third recess 101, shallow trench isolation structure 102, first recess 103, second recess 104, gate insulating layer 210, floating gate 220, inter-gate dielectric layer 230, control gate 240, first gate material 201, second gate material 202, spare area 203, first oxide layer 300, MOS tube 400, second oxide layer 500, peripheral region P, storage region C, array region A, lead-out region B. DETAILED DESCRIPTION
[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0042] In the current memory device manufacturing process, especially in the manufacturing of memory device, in the existing ETOX structure, the setting of the gate length is usually >100 nm, thereby limiting the micro-space of the storage unit. With the improvement of storage density, the technical difficulty and cost of device processing are greatly improved, which affects the storage density of the memory device.
[0043] Therefore, a manufacturing method of memory device is provided, which forms a first recess, sets a gate stack structure in the first recess, forms a second recess, and forms source / drain regions in the substrate at the bottom of the second recess, and adjusts the channel length in the vertical direction with the depth of the first recess and the second recess, which can effectively improve the storage density of the memory device and reduce the cost.
[0044] Please refer to Figure 1 , Figure 1 is a flowchart of one embodiment of the manufacturing method of memory device in the application.
[0045] As Figure 1 shown, the manufacturing method of memory device in the application comprises:
[0046] S10, providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a mask layer disposed on the substrate.
[0047] Specifically, a substrate is provided, and a mask layer is disposed on the substrate.
[0048] S20, a plurality of first grooves are formed in the semiconductor substrate, and a part of the plurality of first grooves are located in an array region in a storage region.
[0049] The plurality of first grooves are spaced apart in the semiconductor substrate, and are used for subsequently disposing a gate stack structure.
[0050] Specifically, the semiconductor substrate comprises a storage region, the storage region comprising an array region and a lead-out region, a plurality of first grooves are formed in the semiconductor substrate, and a part of the plurality of first grooves are located in the array region and another part are located in the lead-out region.
[0051] S30, forming a gate stack structure in the plurality of first grooves in the array region.
[0052] The gate stack structure comprises a gate insulating layer, a floating gate, an inter-gate dielectric layer and a control gate.
[0053] Specifically, after the plurality of first grooves are formed, the gate insulating layer, the floating gate, the inter-gate dielectric layer and the control gate are sequentially formed in the first grooves, so that the gate insulating layer covers the first grooves, the floating gate is disposed on the gate insulating layer, and the gate insulating layer isolates the floating gate from the substrate; the inter-gate dielectric layer covers the floating gate, and the control gate is disposed on the inter-gate dielectric layer, and the inter-gate dielectric layer isolates the control gate from the floating gate.
[0054] S40, forming a second groove on both sides of the gate stack structure, and forming a source / drain region in the substrate at the bottom of the second groove, wherein the highest point of the source / drain region is lower than the surface of the substrate.
[0055] The plurality of second grooves and the first grooves are both disposed in the array region, and the plurality of second grooves are isolated by the first grooves.
[0056] Specifically, after the gate stack structure is formed in the first grooves, a plurality of second grooves are formed between the first grooves in the array region, and a source / drain region is formed in the substrate at the bottom of the second groove, wherein the highest point of the source / drain region is lower than the surface of the substrate, that is, the lowest point of the second groove is lower than the surface of the substrate and higher than the lowest point of the first groove.
[0057] The source / drain region refers to a source region or a drain region, and the lowest point of the source region and / or the drain region is higher than the lowest point of the first groove.
[0058] In some embodiments, the lowest point of the source region is higher than the lowest point of the first recess, and the lowest point of the drain region is also higher than the lowest point of the first recess; in other embodiments, the lowest point of one of the source / drain regions is higher than the lowest point of the first recess, and the lowest point of the other one can be lower than the lowest point of the first recess, so that the channel length of the device can be adjusted.
[0059] In the present embodiment, by forming the first recess and the second recess in the array region, and forming the source / drain region in the second recess respectively after forming the gate stack structure in the first recess, the channel of the device becomes an arc-shaped channel, the width of the gate stack structure in the horizontal direction is reduced, and the channel length can be adjusted by the depth of the first recess and the second recess, which can effectively improve the storage density of the memory device and reduce the cost.
[0060] The operation flow of one embodiment of step S10 is as follows:
[0061] A substrate 110 is provided, and a first dielectric layer 120 and a second dielectric layer 130 are formed on the substrate 110.
[0062] The substrate can be any suitable substrate known in the art, for example, can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, also including multi-layer structures composed of these semiconductors, etc., or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).
[0063] Please refer to Figure 2a and Figure 2b , Figure 2a is a first direction structure schematic diagram of one embodiment of the present application for forming a first dielectric layer and a second dielectric layer on a substrate, Figure 2b is a second direction structure schematic diagram of one embodiment of the present application for forming a first dielectric layer and a second dielectric layer on a substrate.
[0064] The first direction is the word line (WL) extension direction, the first direction is the X direction, the second direction is the bit line (BL) extension direction, and the second direction is the Y direction, i.e., the first direction and the second direction are perpendicular in the same horizontal plane.
[0065] Specifically, as Figure 2a and Figure 2bAs shown, a substrate 110 is provided, and a first dielectric layer 120 and a second dielectric layer 130 are sequentially formed on the substrate 110.
[0066] In some embodiments, the first dielectric layer 120 can be an oxide layer, such as a silicon oxide layer; and the second dielectric layer 130 can be a nitride layer, such as a silicon nitride layer.
[0067] Next, a plurality of third recesses 101 are formed from the second dielectric layer 130 towards the substrate, wherein the plurality of third recesses 101 are sequentially and spacedly arranged along a first direction and extend along a second direction.
[0068] Referring to Figure 3a and Figure 3b , Figure 3a is a first direction structural schematic diagram of an embodiment of the present application for forming the third recesses towards the substrate, Figure 3b is a second direction structural schematic diagram of an embodiment of the present application for forming the third recesses towards the substrate.
[0069] As shown in Figure 3a and 3b , a plurality of third recesses 101 are formed from the second dielectric layer 130 towards the substrate 110 to define a plurality of active areas (AA) in the substrate 110; Figure 3a is a first direction cross-sectional view, Figure 3b is a second direction cross-sectional view of the active area.
[0070] In some embodiments, the plurality of third recesses 101 are sequentially and spacedly arranged along the first direction (X direction), and the bottom of the third recess 101 is higher than the bottom of the substrate 110 and lower than the top of the substrate 110, i.e., the third recess 101 extends to a portion of the substrate 110.
[0071] In some embodiments, the semiconductor substrate includes a storage region and a peripheral region, and the storage region includes an array region and a lead-out region; wherein the third recess 101 of the storage region can be formed first to form the AA region (CAA) of the storage region, and then the third recess of the peripheral region is formed to form the AA region (PAA) of the peripheral region; in another embodiment, the third recess of the storage region and the peripheral region can be formed simultaneously to form the AA region of the storage region and the AA region of the peripheral region. Furthermore, a wider third recess can be formed on the boundary between the storage region and the peripheral region to divide the storage region and the peripheral region.
[0072] Then, a shallow trench isolation structure 102 is formed in the plurality of third recesses 101.
[0073] Referring to Figure 4a and Figure 4b , Figure 4a is a first direction structural schematic diagram of an embodiment of forming a shallow trench isolation structure in the present application, Figure 4b is a second direction structural schematic diagram of an embodiment of forming a shallow trench isolation structure in the present application.
[0074] As shown in Figure 4a and 4b , the isolation material is filled in the third recess 101 to form the shallow trench isolation structure 102, and the surface exposed by the shallow trench isolation structure 102 is subjected to chemical mechanical polishing so as to be flat; Figure 4a is a first direction cross-sectional view, Figure 4b is a second direction cross-sectional view of the active area of the storage region in the right side of the dotted line in Figure 4b is a second direction cross-sectional view of the active area of the peripheral region in the left side of the dotted line in Figure 4a and Figure 4b are continued to be manufactured.
[0075] In some embodiments, part of the shallow trench isolation structure 102 is arranged in the substrate 110, and part of the shallow trench isolation structure 102 protrudes from the substrate 110 to define a plurality of active areas (AA) including the active area of the storage region and the active area of the peripheral region, the shallow trench isolation structure 102 extends along the second direction and is arranged at intervals in the first direction.
[0076] In some embodiments, before forming the shallow trench isolation structure 102, the substrate 110 of the storage region can also be subjected to ion implantation to form a first well region 111 in the substrate 110, such as ion implantation to the substrate 110 based on the third recess 101, thereby forming the first well region 111 in the substrate 110 of the storage region, and forming the shallow trench isolation structure 102 in the third recess 101 after forming the first well region 111.
[0077] After forming the shallow trench isolation structure 102, the second dielectric layer 130 is removed.
[0078] Referring to Figure 5a and Figure 5b , Figure 5a is a first direction structural schematic diagram of an embodiment of removing the second dielectric layer in the present application, Figure 5b is a second direction structural schematic diagram of an embodiment of removing the second dielectric layer in the present application.
[0079] As shown in Figure 5a and 5b , the second dielectric layer 130 is removed so that part of the sidewall of the shallow trench isolation structure 102 is exposed, and the first dielectric layer 120 is exposed.
[0080] In some embodiments, the substrate 110 of the storage region can be ion implanted with the first dielectric layer 120 as a barrier layer to form a second well region 112 in the substrate; wherein the second well region 112 is closer to the first dielectric layer 120 than the first well region 111, and the second well region 112 is above the first well region 111 in the height direction; and the shallow trench isolation structure penetrates the second well region 112 and extends into the first well region 111.
[0081] The first well region 111 and the second well region 112 are of different doping types, i.e. the doping types of the first well region and the second well region are opposite; for example, the first well region is N-type doped, and the second well region is P-type doped; conversely, the first well region is P-type doped, and the second well region is N-type doped.
[0082] Then, the semiconductor layer 140 and the third dielectric layer 150 are formed on the first dielectric layer 120 to form the semiconductor base 100, wherein the third dielectric layer 150 covers the semiconductor layer 140 and the shallow trench isolation structure 102.
[0083] Referring to Figure 6a and Figure 6b , Figure 6a is a first direction structural schematic diagram of an embodiment of forming the semiconductor layer and the third dielectric layer in the present application, Figure 6b is a second direction structural schematic diagram of an embodiment of forming the semiconductor layer and the third dielectric layer in the present application.
[0084] As shown in Figure 6a and 6b , the semiconductor layer 140 and the third dielectric layer 150 are sequentially formed on the exposed first dielectric layer 120, so that the semiconductor layer 140 covers the first dielectric layer 120, and the semiconductor layer 140 is chemically mechanically polished to make the surface of the semiconductor layer 140 flat and flush with the shallow trench isolation structure 102, while the third dielectric layer 150 covers the semiconductor layer 140 and the shallow trench isolation structure 102.
[0085] In some embodiments, the semiconductor layer 140 can be a polycrystalline material, such as polysilicon; in one of the embodiments, the third dielectric layer 150 can include multiple sub-dielectric layers, such as the third dielectric layer 150 including a fourth dielectric layer 151 and a fifth dielectric layer 152, the fourth dielectric layer 151 can be a nitrided layer, and the fifth dielectric layer 152 can be an oxidized layer, the nitrided layer can be a silicon nitride layer, and the oxidized layer can be a silicon oxide layer; taking the first dielectric layer 120, the semiconductor layer 140 and the third dielectric layer 150 as mask layers.
[0086] At this point, the semiconductor base 100 is formed, i.e. the semiconductor base 100 includes a substrate and a mask layer arranged on the substrate.
[0087] Then, the operation of step S20 is performed.
[0088] A plurality of first recesses are formed in the semiconductor substrate, and a portion of the plurality of first recesses is located in the array region in the memory region.
[0089] The operation flow of one embodiment of step S20 is as follows.
[0090] Referring to Figure 7a and Figure 7b , Figure 7a is a first direction structural schematic diagram of one embodiment of forming the first recess in the present application, Figure 7b is a second direction structural schematic diagram of one embodiment of forming the first recess in the present application.
[0091] As shown in Figure 7a and 7b , a plurality of first recesses 103 are formed in the memory region, and the first recesses 103 extend along the first direction.
[0092] Then, the operation of step S30 is performed.
[0093] A gate stack structure is formed in the plurality of first recesses, and the gate stack structure includes a gate insulating layer, a floating gate, a gate medium layer, and a control gate.
[0094] Step S30 can include the following steps:
[0095] The portion of the first recess 103 in the substrate is defined as a substrate recess, and in some embodiments, the depth of the substrate recess is 1000A-2000A, A is the unit length, that is, angstrom, 1 nm is 10A, such as 1200A, 1500A, etc.
[0096] The gate insulating layer 210 and the floating gate 220 are formed in the first recess.
[0097] Specifically, the gate insulating layer 210 is formed on the inner wall of the first recess, and the first gate material 201 is filled in the first recess 103, so that the first gate material 201 covers the first recess 103.
[0098] Referring to Figure 8a and Figure 8b , Figure 8a is a first direction structural schematic diagram of one embodiment of forming the gate insulating layer and the first gate material in the present application, Figure 8b is a second direction structural schematic diagram of one embodiment of forming the gate insulating layer and the first gate material in the present application.
[0099] As shown in Figure 8a and 8bAs shown, in the memory region, a gate insulating layer 210 is formed on the inner wall of the first recess, and then the first gate material 201 is filled in the first recess 103, so that the first gate material 201 covers the gate insulating layer 210, i.e. the first gate material 201 covers the first recess 103, and the first gate material 201 is subjected to chemical mechanical polishing, so that the surface of the first gate material 201 is flat and flush with the mask layer.
[0100] Referring to Figure 9a and Figure 9b , Figure 9a is a first direction structural schematic diagram of an embodiment of forming a floating gate in the present application, Figure 10b is a second direction structural schematic diagram of an embodiment of forming a floating gate in the present application.
[0101] As shown in Figure 9a and 9b , the height of the first gate material 201 and the gate insulating layer 210 in the first recess 103 is reduced, and at the same time, the fifth dielectric layer 152 and part of the shallow trench isolation structure 102 are removed, and the remaining first gate material 201 in the first recess serves as a floating gate 220, which is not higher than the top of the substrate 110, i.e. the floating gate 220 is in the substrate 110.
[0102] In one embodiment, the height of the shallow trench isolation structure 102 can be further reduced.
[0103] Referring to Figure 10a and Figure 10b , Figure 10a is a first direction structural schematic diagram of an embodiment of reducing the shallow trench isolation structure in the present application, Figure 10b is a second direction structural schematic diagram of an embodiment of reducing the shallow trench isolation structure in the present application.
[0104] As shown in Figure 10a and 10b , based on Figure 9a and 9b , the height of the shallow trench isolation structure 102 in the memory region is reduced, so that the shallow trench isolation structure 102 in the memory region is lower than the floating gate 220.
[0105] Further, a gate-to-gate dielectric layer and a second gate material are formed in the plurality of first recesses, and the second gate material is isolated from the floating gate by the gate-to-gate dielectric layer.
[0106] In which, the gate-to-gate dielectric layer 230 is formed in the memory region first, and then the second gate material 202 covers the gate-to-gate dielectric layer 230.
[0107] Referring to Figure 11a and Figure 11b , Figure 11ais a first direction structural schematic diagram of an embodiment of forming the intergate dielectric layer and the second gate material in the present application, Figure 11b is a second direction structural schematic diagram of an embodiment of forming the intergate dielectric layer and the second gate material in the present application.
[0108] As shown in Figure 11a and 11b , the intergate dielectric layer 230 is formed in the plurality of first grooves 103 of the storage region, so that the intergate dielectric layer 230 covers the floating gate 220, the shallow trench isolation structure 102 and the gate insulating layer 210 of the storage region, forms a dentiform structure, and the second gate material 202 is formed on the intergate dielectric layer 230, the dentiform structure increases the coupling area of the subsequently formed control gate 240 and the floating gate 220, and improves the coupling rate.
[0109] In some embodiments, the intergate dielectric layer 230 can be an ON (Oxide-Nitride) structure, that is, the intergate dielectric layer 230 can contain an oxide layer and a nitride layer, such as a silicon oxide layer and a silicon nitride layer, forming an ON structure; the second gate material can be a polycrystalline material, such as polysilicon or the like.
[0110] Further, because the storage region is divided into an array region and a lead-out region, it is necessary to remove part of the second gate material in the first groove of the array region.
[0111] Referring to Figure 12a and Figure 12b , Figure 12a is a first direction structural schematic diagram of an embodiment of removing part of the second gate material in the present application, Figure 12b is a second direction structural schematic diagram of an embodiment of removing part of the second gate material in the present application.
[0112] As shown in Figure 12a and 12b , on the basis of Figure 11a and 11b , part of the second gate material 202 in the array region is removed to form a spare area 203, and the second gate material 202 remaining in the array region serves as the control gate 240 of the storage unit, and the plurality of control gates 240 are connected together.
[0113] Because the storage region also includes a lead-out region, the gate insulating layer, the floating gate, the intergate dielectric layer and the second gate material are also formed in the first groove of the lead-out region, and the second gate material in the first groove of the lead-out region serves as the lead-out end of the storage unit, and the lead-out end is connected with the second gate material 202 in the array region, that is, the lead-out end is used to connect the control gates 240 of the plurality of storage units in the same row in the first direction.
[0114] In some embodiments, a photoresist layer can be formed in the lead-out region, and then the storage region is etched so that part of the second gate material 202 in the array region is etched, while the second gate material 202 in the lead-out region is reserved.
[0115] Further, the first oxide layer is filled in the empty region.
[0116] Referring to Figure 13a and Figure 13b , Figure 13a is a first direction structural schematic diagram of an embodiment of filling the first oxide layer in the present application, Figure 13b is a second direction structural schematic diagram of an embodiment of filling the first oxide layer in the present application.
[0117] As shown in Figure 13a and 13b , on the basis of Figure 12a and 12b , the first oxide layer 300 is filled in the empty region 203 so that the first oxide layer 300 covers the control gate 240 in the array region, and the first oxide layer 300 is subjected to chemical mechanical polishing.
[0118] Further, the mask layer in the peripheral region is removed, and the MOS tube is formed in the peripheral region.
[0119] Referring to Figure 14a and Figure 14b , Figure 14a is a first direction structural schematic diagram of an embodiment of forming the MOS tube in the present application, Figure 14b is a second direction structural schematic diagram of an embodiment of forming the MOS tube in the present application.
[0120] As shown in Figure 14a and Figure 14b , after the gate stack structure is formed, the mask layer in the peripheral region is removed, and then the MOS tube 400 is formed in the active area PAA in the peripheral region.
[0121] In some embodiments, when the gate oxide layer (i.e., the second oxide layer 500) of the MOS tube is formed, the second oxide layer 500 is also formed on the lead-out end.
[0122] Then, the operation of step S40 is performed.
[0123] The operation flow of an embodiment of step S40 is as follows:
[0124] A plurality of second grooves are opened on both sides of the gate stack structure in the array region, and a source / drain region is formed in the substrate at the bottom of the second grooves.
[0125] First, a plurality of second grooves are opened in the array region.
[0126] Referring to Figure 15a and Figure 15b , Figure 15a is a first direction structural schematic diagram of one embodiment of the application in which the second recesses are formed, Figure 15b is a second direction structural schematic diagram of one embodiment of the application in which the second recesses are formed.
[0127] As shown in Figure 15a and 15b , a plurality of second recesses 104 are formed in the array region of the memory region, wherein the second recesses 104 are separated by the gate stack structure in the first recess 103, the second recesses 104 extend into the substrate, and the depth of the second recesses 104 is less than the depth of the first recess 103.
[0128] In some embodiments, the depths of the second recesses 104 can be the same, and the depths of the second recesses 104 are all less than the depth of the first recess 103.
[0129] In other embodiments, the depths of different second recesses 104 can be different, but the depths of the second recesses 104 are all less than the depth of the first recess 103, for example, the depth of one second recess 104 can be greater than the depth of another second recess 104, or the depth of one second recess 104 can be less than the depth of another second recess 104, which can be set according to actual requirements. In some embodiments in which the depths of different second recesses are different, multi-step etching can be used to form second recesses with different depths.
[0130] Further, ion implantation is performed in the substrate at the bottom of the plurality of second recesses 104 to form spaced source / drain regions, which are source regions or drain regions; for example, a source region is formed in the substrate at the bottom of one second recess 104, and a drain region is formed in the substrate at the bottom of an adjacent second recess 104.
[0131] Referring to Figure 16a and Figure 16b , Figure 16a is a first direction structural schematic diagram of one embodiment of the application in which the source / drain regions are formed, Figure 16b is a second direction structural schematic diagram of one embodiment of the application in which the source / drain regions are formed.
[0132] As shown in Figure 16a and 16b , ion implantation is performed in the substrate at the bottom of the second recess 104 to form source / drain regions 160, wherein the source / drain regions 160 are source regions or drain regions and are spaced apart and arranged in the substrate at the bottom of different second recesses 104.
[0133] An arc-shaped channel is formed from the source region to the drain region, and the channel length of the device is adjusted by adjusting the depth of the first groove 103 , the depth of the source region, and the depth of the drain region to meet the channel length condition, that is, the memory cell is miniaturized in the horizontal direction.
[0134] In some embodiments, the source region, drain region and gate structure of the MOS tube in the peripheral area, as well as the source / drain region and lead-out terminal in the storage area need to be covered with a metal silicon compound layer to reduce contact resistance.
[0135] In some embodiments, in order to more clearly illustrate the memory device, a corresponding top view is provided.
[0136] See Figure 17 , Figure 17 1 is a top view of an embodiment of a memory device in this application.
[0137] like Figure 17 As shown, the memory device can be divided into a peripheral area P and a storage area C, and the storage area C can be further divided into an array area A and a lead-out area B. In addition, in the first direction, it can be divided into two types of areas, a first-direction first-type area X1 and a first-direction second-type area X2. As shown in the aforementioned Figure Xa, Figure 2a 、 Figure 3a 、 Figure 4a The cross-sectional views of the first type area X1 in the first direction are shown, and the cross-sectional view of the second type area X2 in the first direction is not shown. In the second direction, the area can be divided into three types: the first type area Y1 in the second direction, the second type area Y2 in the second direction, and the third type area Y3 in the second direction. The left side of the dotted line on the left side of the aforementioned Figure Xb is the peripheral area, which is the cross-sectional view of the first type area Y1 in the second direction, as shown in FIG. Figure 14b 、 Figure 16b The portion between the left dotted line and the right dotted line of the aforementioned Figure Xb is the array area, that is, the cross-sectional view of the second type area Y2 in the second direction, and the right side of the right dotted line is the lead-out area, that is, the cross-sectional view of the third type area Y3 in the second direction, as shown in FIG. Figure 14b 、 Figure 16b wait.
[0138] It can be understood that the shallow trench isolation structure in the array area can be divided into a first isolation part and a second isolation part. The first isolation part is the shallow trench isolation structure that appears in the cross-sectional view of the first type region X1 in the first direction, and the second isolation part is located in the second type region X2 in the second direction, that is, the first isolation part (not marked in the figure) and the second isolation part (not marked in the figure) are spaced apart in the second direction.
[0139] In the embodiment, a plurality of first grooves are formed in the array region, a gate stack structure is formed in the first grooves, a plurality of second grooves are formed in the region between the first grooves, and a source / drain region is formed in the substrate at the bottom of the second grooves, so that the source region to the drain region forms an arc-shaped channel, the width of the gate stack structure in the horizontal direction is reduced, and the channel length of the device is adjusted by the depth of the first grooves and the depth of the source region and the drain region, so that the storage density of the memory device can be effectively improved and the cost can be reduced.
[0140] In the application, a memory device is also included, which is described with reference to Figure 16a 、 Figure 16b and Figure 17 .
[0141] Specifically, the memory device 10 includes a substrate 110, a gate stack structure 200, a source region and a drain region; wherein a base groove is formed in the substrate 110; the gate stack structure 200 is formed in the base groove; the source region and the drain region are formed in the substrate 110 on both sides of the gate stack structure 200; the highest point of the source region and the drain region is lower than the surface of the substrate 110, and the lowest point of the source region and the drain region is higher than the lowest point of the base groove.
[0142] In some embodiments, the gate stack structure 200 includes a gate insulating layer 210, a floating gate 220, an inter-gate dielectric layer 230, and a control gate 240; the gate insulating layer 210 is formed on the inner wall of the base groove; the floating gate 220 is formed in the base groove, and the floating gate 220 is isolated from the substrate 110 by the gate insulating layer 210; the inter-gate dielectric layer 230 is formed in the base groove and covers the floating gate 220; the control gate 240 is formed on the inter-gate dielectric layer 230, and the control gate 240 is isolated from the floating gate 220 by the inter-gate dielectric layer 230; wherein each storage unit of the memory device corresponds to one control gate 240.
[0143] In some embodiments, the memory device includes a storage region C, the base groove is located in the storage region C, the storage region C includes an array region A and a lead-out region B, and the gate stack structure is located in the array region A; that is, a part of the base groove is located in the array region A, and another part of the base groove is located in the lead-out region B; a lead-out end of a storage unit is formed in the base groove of the lead-out region B, and the lead-out end is connected to the control gates 240 of a plurality of storage units in the same row, wherein the top of the lead-out end is higher than the base groove.
[0144] In some embodiments, the memory device further includes a peripheral region, and the peripheral region is formed with MOS tubes 400; wherein the peripheral region and the storage region are isolated by a shallow trench isolation structure 102 in the substrate 110; an active region PAA on the substrate of the peripheral region is formed with a plurality of MOS tubes.
[0145] In some embodiments, the source region and the drain region can have the same depth, and the depth of the source region and the drain region can be less than the depth of the substrate recess. In other embodiments, the source region and the drain region can have different depths, but the depths of the source region and the drain region are both less than the depth of the substrate recess; that is, the lowest point of the source region and the drain region is higher than the lowest point of the substrate recess, and the highest point of the source region and the drain region is lower than the highest point of the floating gate.
[0146] In some embodiments, the shallow trench isolation structure 102 is further included; that is, the shallow trench isolation structure 102 is formed in the substrate 110, the shallow trench isolation structure 102 is spaced apart along the first direction and extends along the second direction; for example, the shallow trench isolation structure 102 in the storage region includes a first isolation part and a second isolation part, wherein, in the first direction, the first type region X1, the first isolation part and the second isolation part are spaced apart from each other in the second direction, and the highest point of the first isolation part is lower than the highest point of the floating gate, forming a tooth-shaped structure, in the first direction, the second type region X2, the highest point of the second isolation part is not lower than the highest point of the floating gate; that is, the highest point of the second isolation part can be flush with the highest point of the floating gate, or higher than the highest point of the floating gate.
[0147] It can be understood that the shallow trench isolation structure in the substrate 110 is spaced apart along the first direction and extends along the second direction, and the shallow trench isolation structure in the substrate 110 is connected in the second direction, and only the second isolation part of the shallow trench isolation structure of the second type region X2 is reserved on the substrate 110, and the second isolation part is spaced apart from the active area (AA) in the second direction.
[0148] In some embodiments, the shallow trench isolation structure 102 of the array region is lower than the floating gate 220 to form a tooth-shaped structure to improve the coupling area of the control gate 240 and the floating gate 220.
[0149] In the embodiment, the manufacturing method of the memory device includes: providing a semiconductor substrate including a substrate and a mask layer disposed on the substrate; opening a plurality of first recesses in the semiconductor substrate, a part of the plurality of first recesses being located in an array region in a storage region; forming a gate stack structure in the plurality of first recesses; opening a second recess on both sides of the gate stack structure and forming a source-drain region in the substrate at the bottom of the second recess, wherein the highest point of the source-drain region is lower than the surface of the substrate. The channel of the device in the present application becomes an arc-shaped channel, the width of the gate structure in the horizontal direction is reduced, and the channel length can be adjusted by the depth of the first recess and the second recess, which can effectively improve the storage density of the memory device and reduce the cost.
[0150] The above merely describes the embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation made by using the content of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A manufacturing method of a memory device, characterized by, Comprising: providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a mask layer disposed on the substrate; opening a plurality of first recesses in the semiconductor substrate, a portion of the plurality of first recesses being located in an array region in a memory region; forming a gate stack structure in the plurality of first recesses in the array region; opening a second recess on both sides of the gate stack structure and forming a source / drain region in the substrate at the bottom of the second recess, wherein the highest point of the source / drain region is lower than the surface of the substrate.
2. The method of claim 1, wherein the semiconductor substrate is provided by: providing a substrate, forming a first dielectric layer and a second dielectric layer on the substrate; opening a plurality of third recesses from the second dielectric layer towards the substrate, wherein the plurality of third recesses are sequentially and spaced apart along a first direction and extend along a second direction; forming a shallow trench isolation structure in the plurality of third recesses and removing the second dielectric layer; forming a semiconductor layer and a third dielectric layer on the first dielectric layer to form the semiconductor substrate, wherein the third dielectric layer covers the semiconductor layer and the shallow trench isolation structure, and the third dielectric layer, the semiconductor layer and the first dielectric layer serve as the mask layer.
3. The method of claim 1, wherein the gate stack structure is formed in the plurality of first recesses in the array region by: forming a gate insulating layer and a floating gate in the first recess; forming an inter-gate dielectric layer and a control gate on the gate insulating layer and the floating gate; and taking the gate insulating layer, the floating gate, the inter-gate dielectric layer and the control gate as the gate stack structure.
4. The method of claim 3, wherein the inter-gate dielectric layer and the control gate are formed by: forming the inter-gate dielectric layer on the floating gate and covering the inter-gate dielectric layer with a second gate material; removing part of the second gate material in the first recess of the array region, so that the second gate material remaining in the first recess serves as the control gate of a memory cell.
5. The method of claim 4, wherein the memory region further comprises a lead-out region, and another portion of the plurality of first recesses is located in the lead-out region; forming the gate insulating layer, the floating gate, the inter-gate dielectric layer and the second gate material in the first recess of the lead-out region, wherein the second gate material in the first recess of the lead-out region serves as a lead-out end of the memory cell, and the lead-out end is connected to the control gates of a plurality of memory cells in the same row.
6. The method of claim 1, wherein the semiconductor substrate further comprises a peripheral region; after forming the gate stack structure, further comprising: removing the mask layer in the peripheral region; and forming a MOS tube in the peripheral region.
7. The method of claim 1, wherein the plurality of second recesses are opened in the array region and the source / drain region is formed in the substrate at the bottom of the second recess by: a plurality of second grooves are opened towards the substrate between the gate stack structures in the array region, wherein the depth of the second grooves is less than the depth of the first grooves; ion implantation is performed in the substrate at the bottom of the plurality of second grooves to form spaced-apart source regions and drain regions, respectively.
8. The method of claim 7, wherein the lowest point of the source regions and / or the drain regions is higher than the lowest point of the first grooves.
9. The method of claim 7, wherein the depth of the source regions and the drain regions is the same or different.
10. A memory device, comprising: comprising: a substrate having a base groove formed therein; a gate stack structure formed in the base groove; source regions and drain regions formed in the substrate on both sides of the gate stack structure; wherein the highest point of the source regions and the drain regions is lower than the surface of the substrate.
11. The memory device of claim 10, wherein the gate stack structure comprises: a gate insulating layer formed on the inner wall of the base groove; a floating gate formed in the base groove, the floating gate being separated from the substrate by the gate insulating layer; an inter-gate dielectric layer formed in the base groove, covering the floating gate; a control gate formed on the inter-gate dielectric layer, the control gate being separated from the floating gate by the inter-gate dielectric layer; wherein each memory cell of the memory device corresponds to one control gate.
12. The memory device of claim 11, wherein the memory device comprises a memory region; the base groove is located in the memory region, the memory region comprising an array region and a lead-out region, the gate stack structure being located in the array region; a lead-out end of a memory cell is formed in the base groove of the lead-out region, the lead-out end connecting the control gates of a plurality of the memory cells in the same row, wherein the top of the lead-out end is higher than the base groove.
13. The memory device of claim 12, wherein, further comprising: a peripheral region separated from the memory region by a shallow trench isolation structure in the substrate; a plurality of MOS transistors formed on the substrate of the peripheral region.
14. The memory device of claim 10, wherein, further comprising: the depth of the source regions and the drain regions is the same or different.
15. The memory device of claim 12, wherein the shallow trench isolation structure of the memory region comprises a first isolation portion and a second isolation portion, the first isolation portion and the second isolation portion being spaced apart in a second direction, and the highest point of the first isolation portion is lower than the highest point of the floating gate, and the highest point of the second isolation portion is not lower than the highest point of the floating gate.
16. The memory device of any one of claims 10-15, wherein the lowest point of the source regions and / or the drain regions is higher than the lowest point of the base groove.