Semiconductor device, preparation method and memory system

Abstract

The invention provides a semiconductor device, a preparation method and a memory system. The semiconductor device comprises a laminated structure, a grid line isolation structure, a first spacing structure and a second spacing structure. The laminated structure comprises gate layers and first dielectric layers which are alternately stacked in the first direction. The grid line isolation structure extends in the laminated structure along a second direction intersected with the first direction, and comprises a first branch and a second branch which are distributed at an interval in the second direction. The first spacing structure and the second spacing structure are both located between the first branch and the second branch, and the second spacing structure is arranged around the first spacing structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a semiconductor device, a method for manufacturing the semiconductor device, and a memory system. BACKGROUND

[0002] Memory is one of the important storage components in electronic systems. Taking a three-dimensional memory as an example, a semiconductor device can include a stack structure and a gate line isolation structure, wherein the stack structure is formed by alternately stacking gate layers and dielectric layers, and the gate line isolation structure extends in the stack structure along a direction intersecting the stacking direction of the stack structure.

[0003] With the rapid development of semiconductor technology, how to simplify the manufacturing process of semiconductor devices, reduce the manufacturing cost of semiconductor devices, and optimize the overall performance of semiconductor devices is one of the important research directions in the industry. SUMMARY

[0004] The present application provides a semiconductor device, a manufacturing method, and a memory system, which can at least partially solve the above problems or other problems in the art.

[0005] In one aspect, the present application provides a semiconductor device, which includes a stack structure including gate layers and first dielectric layers alternately stacked along a first direction; and a gate line isolation structure extending in the stack structure along a second direction intersecting the first direction and including first and second subparts spaced apart in the second direction, wherein the semiconductor device further includes first and second spacer structures, the first and second spacer structures are both located between the first and second subparts, and the second spacer structure is arranged around the first spacer structure.

[0006] In one embodiment of the present application, the semiconductor device further includes a channel structure extending in the stack structure along the first direction, wherein the channel structure includes a functional layer and a channel layer located on a surface of the functional layer; and the first spacer structure and the channel structure include the same layer structure.

[0007] In one embodiment of the present application, the second spacer structure includes a plurality of isolation layers, wherein the isolation layers and the first dielectric layers are alternately stacked along the first direction and are arranged in the same layer as the gate layers.

[0008] In one embodiment of the present application, the second spacer structure further includes an isolation column, wherein the isolation column extends along the first direction and includes the same insulating dielectric material as the isolation layers.

[0009] In an embodiment of the present disclosure, the first spacing structure includes a first separation structure and a second separation structure, wherein the first separation structure is closer to the first sub-portion than the second separation structure along the second direction; and the second separation structure is closer to the second sub-portion than the first separation structure along the second direction.

[0010] In an embodiment of the present disclosure, the first spacing structure has a dimension along the second direction that is greater than a dimension of the first spacing structure along a third direction, wherein the third direction intersects the first direction and the second direction.

[0011] In an embodiment of the present disclosure, the first spacing structure includes a plurality of columnar structures spaced apart from each other along the second direction.

[0012] In an embodiment of the present disclosure, at least one surface of the gate line isolation structure includes a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

[0013] In an embodiment of the present disclosure, the stack structure includes an array region and a connection region arranged along the second direction; and the gate layer includes a first portion located in the array region and a second portion located in the connection region, wherein a surface of the first portion facing the connection region includes a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

[0014] In an embodiment of the present disclosure, the stack structure further includes a second dielectric layer disposed in the same layer as the second portion, wherein the first dielectric layer and the second dielectric layer include different insulating dielectric materials.

[0015] In an embodiment of the present disclosure, a dimension of the first sub-portion or the second sub-portion along a third direction is less than or equal to a dimension of the first spacing structure along the third direction, wherein the third direction intersects the first direction and the second direction.

[0016] In an embodiment of the present disclosure, an extension dimension D of the second spacing structure along a direction intersecting the first direction satisfies: 400nm≤D≤1500nm.

[0017] In an embodiment of the present disclosure, the stack structure includes an array region and a connection region arranged along the second direction, wherein the first spacing structure and the second spacing structure are both located in a first sub-region of the array region close to the connection region.

[0018] Another aspect of the present application provides a semiconductor device, comprising: a stack structure comprising gate layers and first dielectric layers alternately stacked along a first direction; a first channel structure and a second channel structure each extending in the stack structure along the first direction; a gate line isolation structure extending in the stack structure along a second direction intersecting the first direction and comprising a first portion and a second portion spaced apart from each other; an isolation structure between the first portion and the second portion, wherein the isolation structure and a plurality of the second channel structures are distributed along a third direction intersecting the first direction and the second direction; and in a direction intersecting the first direction, a size of the second channel structure is greater than a size of the first channel structure.

[0019] In an embodiment of the present application, a portion of the plurality of the second channel structures is located on one side of the isolation structure along the third direction, and another portion of the plurality of the second channel structures is located in the isolation structure.

[0020] In an embodiment of the present application, an extension size D of the isolation structure in a direction intersecting the first direction satisfies: 400nm≤D≤1500nm.

[0021] In an embodiment of the present application, the isolation structure comprises a plurality of isolation layers, wherein the isolation layers and the first dielectric layers are alternately stacked along the first direction and are arranged in the same layer as the gate layers.

[0022] In an embodiment of the present application, the isolation structure further comprises an isolation column, wherein the isolation column extends along the first direction and comprises the same insulating dielectric material as the isolation layers.

[0023] In an embodiment of the present application, in a direction intersecting the first direction, a size d1 of the first channel structure and a size d2 of the second channel satisfy: 1.1d1≤d2.

[0024] In an embodiment of the present application, in a direction intersecting the first direction, the size d2 of the second channel satisfies: 110nm

[0025] In an embodiment of the present application, a size of the first portion in a third direction is less than or equal to a size of the second portion in the third direction, wherein the third direction intersects the first direction and the second direction.

[0026] In an embodiment of the present application, a size b1 of the first portion in the third direction and a size b2 of the second portion in the third direction satisfy: 1.1b1≤b2.

[0027] In an embodiment of the present application, the size b2 of the second sub-section in the third direction satisfies: 300nm < b2≤900nm.

[0028] In an embodiment of the present application, the stack structure includes an array region and a connection region distributed along a second direction intersecting the first direction; and the gate layer includes a first portion located in the array region and a second portion located in the connection region, wherein a surface of the first portion facing the connection region includes a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

[0029] In an embodiment of the present application, the stack structure further includes a second dielectric layer disposed in the same layer as the second gate layer, wherein the first dielectric layer and the second dielectric layer include different insulating dielectric materials.

[0030] In an embodiment of the present application, the spacer structure includes a first spacer structure and a second spacer structure disposed around the first spacer structure.

[0031] In an embodiment of the present application, the first spacer structure includes a first separation structure and a second separation structure, wherein the first separation structure is closer to the first sub-section than the second separation structure along the second direction; and the second separation structure is closer to the second sub-section than the first separation structure along the second direction.

[0032] In an embodiment of the present application, the size of the first spacer structure along the second direction is greater than the size of the first spacer structure along a third direction, wherein the third direction intersects the first direction and the second direction.

[0033] In an embodiment of the present application, the first channel structure and the second channel structure each include a functional layer and a channel layer located on a surface of the functional layer; and the first spacer structure and the channel structure include the same layer structure.

[0034] In an embodiment of the present application, at least one surface of the gate line isolation structure includes a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

[0035] In another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: alternately stacking gate sacrificial layers and first dielectric layers in a first direction to form a stack structure; forming a first gap and a second gap spaced apart from each other in the stack structure, the first gap and the second gap each extending in a second direction intersecting the first direction; forming a first spacer structure between the first gap and the second gap and a second spacer structure disposed around the first spacer structure; and removing portions of the gate sacrificial layers via the first gap and the second gap to form gate layers.

[0036] In one embodiment of the present disclosure, forming the second spacer structure includes: forming a first opening and a second opening between the first gap and the second gap, wherein the first opening and the second opening are spaced apart in the second direction; removing portions of the gate sacrificial layers via the second opening to form an isolation gap; and filling the second opening and the isolation gap with an insulating dielectric material to form the second spacer structure.

[0037] In one embodiment of the present disclosure, the semiconductor device further includes a channel structure, and the method further includes: forming a channel hole extending in the first direction in the stack structure and the first opening; and forming a functional layer in the channel hole and the first opening, and a channel layer on a surface of the functional layer, wherein the functional layer and the channel layer fill portions of the first opening to form the first spacer structure.

[0038] In one embodiment of the present disclosure, the first opening includes at least one of a hole extending in the first direction and a slot extending in the second direction.

[0039] In one embodiment of the present disclosure, forming the first gap and the second gap includes: forming first holes extending through the stack structure in the first direction, wherein a plurality of the first holes are spaced apart in the second direction; and removing at least portions of the stack structure between first holes adjacent in the second direction to form the first gap and the second gap.

[0040] In one embodiment of the present disclosure, the semiconductor device further includes a channel structure, and forming the channel structure includes: forming a channel hole extending in the first direction in the stack structure; and forming a functional layer in the channel hole, and a channel layer on a surface of the functional layer, wherein the channel hole is formed in a process of forming the first hole.

[0041] In one embodiment of the present application, removing part of the gate sacrificial layer via the first gap and the second gap to form a gate layer comprises: filling the second gap with a first sacrificial layer; removing part of the gate sacrificial layer via the first gap to form a first void; filling the first void and the first gap with a second sacrificial layer; removing the first sacrificial layer and removing part of the gate sacrificial layer via the second gap to form a second void in communication with the first void; and removing the second sacrificial layer and forming the gate layer in the first void and the second void.

[0042] In another aspect of the present application, a method for manufacturing a semiconductor device is provided, the method comprising: alternately stacking gate sacrificial layers and first dielectric layers in a first direction to form a stack structure; forming a first channel structure and a second channel structure extending in the stack structure in the first direction, wherein a size of the second channel structure is greater than a size of the first channel structure in a direction intersecting the first direction; forming a first gap and a second gap spaced apart from each other in the stack structure, the first gap and the second gap each extending in a second direction intersecting the first direction; forming a spacer structure between the first gap and the second gap, wherein a plurality of the second channel structures are located on one side of the spacer structure in a third direction, the spacer structure and the plurality of the second channel structures being distributed in the third direction, the third direction intersecting the first direction and the second direction; and removing part of the gate sacrificial layer via the first gap and the second gap to form a gate layer.

[0043] In one embodiment of the present application, forming the first channel structure and the second channel structure comprises: forming a first channel hole and a second channel hole, wherein the first channel hole and the second channel hole each extend in the stack structure in the first direction, and a size of the second channel hole is greater than a size of the first channel hole in a direction intersecting the first direction; and forming a functional layer in the first channel hole and the second channel hole, respectively, and forming a channel layer on a surface of the functional layer.

[0044] In one embodiment of the present application, forming the first gap and the second gap comprises: forming first holes passing through the stack structure in the first direction, wherein a plurality of the first holes are arranged spaced apart in the second direction; and removing at least a portion of the stack structure between first holes adjacent in the second direction to form the first gap and the second gap.

[0045] In one embodiment of the present application, a size of the second channel hole is equal to a size of the first hole in a direction intersecting the first direction.

[0046] In one embodiment of the present application, the first trench hole and the second trench hole are formed in a process of forming the first hole.

[0047] In one embodiment of the present application, the forming of the spacing structure comprises: forming a second opening between the first gap and the second gap; removing part of the gate sacrificial layer via the second opening to form an isolation gap; and filling the second opening and the isolation gap with an insulating dielectric material to form the spacing structure.

[0048] In one embodiment of the present application, the forming of the second opening comprises: forming a second hole passing through the stack structure along a first direction, wherein a plurality of the second holes are arranged at intervals along a second direction; and removing at least part of the stack structure between second holes adjacent in the second direction to form the second opening.

[0049] In yet another aspect of the present application, a memory system is provided, comprising: a controller and the semiconductor device of any one of the aspects or the other aspects of the present application, the controller being coupled to the semiconductor device and configured to control the semiconductor device to store data.

[0050] In one embodiment, the semiconductor device comprises at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0051] In one aspect, the semiconductor device and the method of manufacturing the same, and the memory system according to at least one embodiment of the present application, the semiconductor device comprises a stack structure, a gate line isolation structure, a first spacing structure and a second spacing structure, wherein the first spacing structure and the second spacing structure divide the gate line isolation structure into a first part and a second part which are arranged at intervals in an extension direction of the gate line isolation structure. The gate electrode layer of the stack structure can be manufactured by a gate-last process, for example, a gate sacrificial layer is formed in advance, and in the process of removing the gate sacrificial layer by a process such as wet etching, the etchant and the chemical precursor are brought into contact with the gate sacrificial layer by the gate line gap, for example, the first gate line gap and the second gate line gap, generated when the gate line isolation structure is formed, and then part of the gate sacrificial layer is removed to form the gate electrode layer. The first spacing structure and the second spacing structure divide the gate line isolation structure into the first part and the second part; similarly, in the process of manufacturing the semiconductor device, the first spacing structure and the second spacing structure divide the first gap and the second gap, which can reduce the situation that the excess etchant flows into other structures which have been formed in the semiconductor intermediate body via the gate line gap in the process of removing the gate sacrificial layer by the gate-last process in the process of manufacturing the semiconductor device, thereby improving the overall performance of the semiconductor device.

[0052] In addition, the semiconductor device further comprises a channel structure, and the second spacing structure is arranged around the first spacing structure, so as to improve the stress of the stack structure at the part where the first spacing structure and the second spacing structure are located, reduce the morphology deviation of the plurality of channel structures corresponding to the first spacing structure and the second spacing structure, and further improve the uniformity of the plurality of channel structures and the comprehensive performance of the semiconductor device.

[0053] In another aspect, the semiconductor device and the preparation method thereof and the memory system provided by at least one embodiment of the present application comprise a stack structure, a gate line isolation structure, a channel structure, and a spacing structure, wherein the channel structure comprises a first channel structure and a second channel structure, and the spacing structure divides the gate line isolation structure into a first part and a second part which are spaced apart in the extension direction of the gate line isolation structure. This can reduce the case that the excess etching liquid flows into the other structures which have been formed in the semiconductor intermediate body through the gate line gap in the process of removing the gate sacrificial layer by using the gate-last process in the preparation of the semiconductor device, and further improve the comprehensive performance of the semiconductor device.

[0054] In addition, the spacing structure and the plurality of second channel structures are distributed in a direction intersecting the stacking direction of the stack structure and the extension direction of the gate line isolation structure, and the size of the second channel structure is set to be greater than the size of the first channel structure in the direction intersecting the stacking direction, which can improve the stress of the stack structure at the part where the spacing structure is located, reduce the morphology deviation of the channel structure, and further improve the uniformity of the plurality of channel structures and the comprehensive performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0055] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-restrictive embodiments, made with reference to the attached drawings. In the drawings:

[0056] FIG. 1 is a top view of a semiconductor device according to an embodiment of the present application;

[0057] FIG. 2 is a top view of a semiconductor device according to another embodiment of the present application;

[0058] FIG. 3 is FIG. 1 is a sectional view of the semiconductor device shown along line A-A';

[0059] FIG. 4 is a sectional view of a semiconductor device according to an embodiment of the present application;

[0060] FIG. 5 is a top view of a gate line isolation structure according to an embodiment of the present application;

[0061] FIG. 6 is a top view schematic diagram of a semiconductor device according to one embodiment of the present application;

[0062] FIG. 7 is a top view schematic diagram of a semiconductor device according to yet another embodiment of the present application;

[0063] FIG. 8 is FIG. 7 is a cross-sectional view schematic diagram of the semiconductor device taken along line B-B';

[0064] FIG. 9 is a cross-sectional view schematic diagram of a semiconductor device according to yet another embodiment of the present application;

[0065] FIG. 10 is a top view schematic diagram of a semiconductor device according to yet another embodiment of the present application;

[0066] FIG. 11 is FIG. 10 is a cross-sectional view schematic diagram of the semiconductor device taken along line C-C';

[0067] FIG. 12 is FIG. 10 is a cross-sectional view schematic diagram of the semiconductor device taken along line E-E';

[0068] FIG. 13 is a cross-sectional view schematic diagram of a semiconductor device according to yet another embodiment of the present application;

[0069] FIG. 14 is a flowchart of a method of manufacturing a semiconductor device according to one embodiment of the present application;

[0070] FIG. 15 to FIG. 31 are process schematic diagrams of a method of manufacturing a semiconductor device according to one embodiment of the present application, respectively;

[0071] FIG. 32 is a flowchart of a method of manufacturing a semiconductor device according to another embodiment of the present application;

[0072] FIG. 33 to FIG. 41 are process schematic diagrams of a method of manufacturing a semiconductor device according to another embodiment of the present application, respectively; and

[0073] FIG. 42 is a schematic diagram of a memory system structure according to one embodiment of the present application.

[0074] DETAILED DESCRIPTION

[0075] The present application will be described in detail below with reference to the attached drawings. The exemplary embodiments described herein are merely meant to explain the present application and not meant to limit the scope of the present application. Throughout the specification, like reference numerals refer to like elements.

[0076] In the drawings, the thicknesses of parts, sizes, and shapes are slightly adjusted for the convenience of explanation. The drawings are merely examples and are not strictly drawn to scale. As used in this document, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring device or measuring methodology which would be recognized by those of ordinary skill in the art.

[0077] It should also be understood that the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprise", "comprising", "containing", "containing", "have", "having", and / or "including" are to be construed open-ended, in that they mean "including, but not limited to", unless otherwise noted. Additionally, when combinations are recited, such as "at least one of A and B", it is intended that the scope of the application includes each of the following alternatives: A alone, B alone, and both A and B. Also, the use of "may" indicates "one or more implementations of the application". Also, the term "exemplary" is intended to refer to an example or illustration.

[0078] In addition, in the present application, when expressions such as "connected", "covered", and / or "formed on" are used, it can mean direct contact or indirect contact between the respective components, unless there is a clear other limitation or it can be derived from the context.

[0079] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Also, unless otherwise specifically defined, terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and are not to be interpreted in an idealized or overly formal sense unless specifically so defined in the application.

[0080] Note that the embodiments and features in the embodiments in the present application can be combined with each other as long as there is no conflict. Also, unless specifically limited or contradicted by the context, the specific steps in the methods described in the present application are not necessarily limited to the order described and can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0081] FIG. 1 is a top view schematic diagram of a semiconductor device 1000 according to one embodiment of the present application. FIG. 2 is a top view schematic diagram of a semiconductor device 1000 according to another embodiment of the present application. FIG. 3 is FIG. 1A cross-sectional view of the semiconductor device 1000 taken along the line A-A' is shown. FIG. 4 A cross-sectional view of the semiconductor device 1000 according to an embodiment of the present application is shown.

[0082] As shown in FIG. 1 to FIG. 4 , one aspect of the present application provides a semiconductor device 1000, which can include a stack structure 200, a gate line isolation structure 400, a first spacer structure 431 and a second spacer structure 432. The stack structure 200 includes first dielectric layers 210 and gate layers 220 alternately stacked along a first direction (e.g., the z direction). The gate line isolation structure 400 extends in the stack structure 200 along a second direction (e.g., the x direction) intersecting the z direction, and includes first portions 410 and second portions 420 spaced apart in the x direction. The first spacer structure 431 and the second spacer structure 432 are both located between the first portions 410 and the second portions 420, and the second spacer structure 432 is disposed around the first spacer structure 431.

[0083] It should be noted that, in order to facilitate observation of the shape and position of the rest of the structures in the semiconductor device 1000 except for the gate layers 220, FIG. 1 , FIG. 2 The shape profile of the gate layers 220 is shown only by black lines, and is not filled in.

[0084] The gate layers of the stack structure provided by the embodiments of the present application can be prepared by a back gate process, for example, a gate sacrificial layer is formed in advance, and in the process of removing the gate sacrificial layer by using a process such as wet etching, the etchant and the chemical precursor are brought into contact with the gate sacrificial layer by means of the gate line gaps, such as the first gate line gap and the second gate line gap, generated when the gate line isolation structure is formed, and then part of the gate sacrificial layer is removed to form the gate layers. The first spacer structure and the second spacer structure divide the gate line isolation structure into the first portion and the second portion; similarly, in the process of preparing the semiconductor device, the first spacer structure and the second spacer structure divide the first gap from the second gap, which can reduce the situation that the excess etchant flows into the other structures formed in the semiconductor intermediate body through the gate line gap in the process of removing the gate sacrificial layer by using the back gate process in the preparation of the semiconductor device, and thus improve the overall performance of the semiconductor device.

[0085] In addition, the semiconductor device further includes a channel structure, and the second spacer structure is disposed around the first spacer structure, which can improve the stress of the stack structure at the part where the first spacer structure and the second spacer structure are located, reduce the situation of the morphology deviation of the plurality of channel structures corresponding to the first spacer structure and the second spacer structure, and thus improve the uniformity of the plurality of channel structures and the overall performance of the semiconductor device.

[0086] Specifically, as shown in FIG. 4As shown, the stack structure 200 can be disposed on one side of the substrate 100. The substrate 100 can include a layer of semiconductor material, wherein the semiconductor material can include, but is not limited to, elemental semiconductor material (e.g., silicon, germanium), group III-V compound semiconductor material, group II- VI compound semiconductor material, organic semiconductor material, or other semiconductor material known in the art. Exemplarily, the substrate 100 can include a silicon substrate. In addition, the substrate 100 can be a composite structure, for example, the composite structure can include a layer structure connected with the channel structure 300, which will be described in detail below in connection with the drawings.

[0087] Optionally, as shown in FIG. 2B, the stack structure 200 can include a plurality of first dielectric layers 210 and a plurality of composite layers, wherein the composite layers can include a gate layer 220 and a second dielectric layer 240 disposed in the same layer. For example, the gate layer 220 and the second dielectric layer 240 can be connected and distributed with each other in an x-y plane intersecting the z direction, the gate layer 220 extends along the x direction from the array region 01 to the connection region 02 of the stack structure 200, and is connected with the second dielectric layer 240 disposed in the same layer, wherein the second dielectric layer 240 is located in the connection region 02. FIG. 1 and FIG. 4 As shown, the stack structure 200 includes an array region 01 and a connection region 02 distributed adjacent to each other in the x direction, wherein the array region 01 can include a first sub-region 011 and a second sub-region 012 distributed adjacent to each other in the x direction, the first sub-region 011 is closer to the connection region 02 than the second sub-region 012. The connection region 02 can include a contact structure (not shown) connected with each gate layer 220, so that the gate layer is connected with an external circuit (not shown) through the contact structure.

[0088] As an option, the gate layer 220 can include a conductive material, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The first dielectric layer 210 can be used as an isolation stack, including but not limited to a layer of insulating dielectric material such as a silicon oxide layer.

[0089] In addition, the stack structure 200 further includes a plurality of second dielectric layers 240, the second dielectric layers 240 and the first dielectric layers 210 are two different layers of insulating dielectric material, for example, the second dielectric layers 240 can include but are not limited to a layer of insulating dielectric material such as a silicon nitride layer. In addition, the plurality of second dielectric layers 240 and the plurality of gate layers 220 can have the same stack height. Optionally, the number of layers of the stack structure 200 is not limited to the number of layers shown in the figure, and can be additionally provided as needed, for example, 32 layers, 64 layers, 128 layers, etc.

[0090] In other words, the stack structure 200 can include alternately stacked first dielectric layers 210 and composite layers, wherein the composite layers can include gate layers 220 and second dielectric layers 240 disposed in the same layer. For example, the gate layer 220 and the second dielectric layer 240 can be connected and distributed with each other in an x-y plane intersecting the z direction, the gate layer 220 extends along the x direction from the array region 01 to the connection region 02 of the stack structure 200, and is connected with the second dielectric layer 240 disposed in the same layer, wherein the second dielectric layer 240 is located in the connection region 02.

[0091] Optionally, the gate layer 220 can include a first portion 221 located in the array region 01 and a second portion 222 located in the connection region 02, and the first portion 221 and the second portion 222 are connected to each other. In addition, a surface 2212 of the first portion 221 facing the connection region 02 includes a curved surface, and the curved surface includes at least one of a concave surface and a convex surface. This can release local stress of the semiconductor device and increase stability of the semiconductor device.

[0092] In addition, as shown in FIG. 3 and FIG. 4 , the laminated structure 200 can further include a dielectric cover layer 250, which can be made of the same material as the first dielectric layer 210. Optionally, the dielectric cover layer 250 can have a dimension along the z direction that is greater than the dimension of the first dielectric layer 210 or the gate layer 220 along the z direction.

[0093] In addition, with reference to FIG. 1 , FIG. 3 and FIG. 4 , in some embodiments of the present application, the semiconductor device 1000 further includes a channel structure 300 extending in the laminated structure 200 along the z direction, wherein the channel structure 300 includes a functional layer 301 and a channel layer 302 located on a surface of the functional layer 301. For example, the channel structure 300 can include the functional layer 301 located on the inner wall of a first channel hole (not shown) and the channel layer 302 located on the surface of the functional layer 301. The functional layer 301 can include a blocking layer, a charge trapping layer and a tunneling layer arranged in sequence on the inner wall of the channel hole. In some embodiments, the functional layer 301 can include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 301 can have a structure different from the ONO configuration. The channel layer 302 can be located on the surface of the tunneling layer and can be used to transport the required charges (electrons or holes). The channel layer 302 can be made of a semiconductor material such as polysilicon or monocrystalline silicon, and can have conductive impurities. In addition, the channel structure 300 can further include a channel filling dielectric layer filled in the remaining space of the channel hole after the functional layer 301 and the channel layer 302 have been formed. The channel filling dielectric layer includes a layer of insulating dielectric material such as a silicon oxide layer.

[0094] Optionally, the first spacer structure 431 can comprise the same layer structure as the channel structure 300. In other words, the first spacer structure 431 can comprise a first layer 401 and a second layer 402 on the surface of the first layer 401. For example, the first layer 401 can have the same layer structure as the functional layer 301, and the first layer 401 can comprise an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the first layer 401 can also have a structure different from the ONO configuration. The second layer 402 can have the same layer structure as the channel layer 302. The second layer 402 can be made of a semiconductor material such as polysilicon or monocrystalline silicon, and can have conductive impurities. In addition, the first spacer structure 431 can further comprise a third layer having the same layer structure as the channel fill medium layer. The third layer comprises an insulating medium material layer such as a silicon oxide layer.

[0095] In addition, the first spacer structure 431 can be formed in the same process as the channel structure 300 to simplify the preparation process of the semiconductor device and reduce the preparation cost of the semiconductor device.

[0096] Optionally, the channel structure 300 comprises a first channel structure 310, a second channel structure 320, and a third channel structure.

[0097] Specifically, the stack structure 200 comprises an array region 01 and a connection region 02 adjacently distributed in the x direction, wherein the array region 01 comprises a first sub-region 011 and a second sub-region 012 adjacently distributed in the x direction, and the first sub-region 011 is closer to the connection region 02 than the second sub-region 012. A plurality of first channel structures 310 can be located in the second sub-region 012 of the array region 01. A plurality of second channel structures 320 can be located in the first sub-region 011 of the array region 01. A plurality of third channel structures can be located in the connection region 02.

[0098] The plurality of second channel structures and the plurality of third channel structures can play a supporting role in the above-mentioned process of removing the gate sacrificial layer to reduce the possibility of deformation and collapse of the semiconductor intermediate. Alternatively, the layout of the second channel structure and the third channel structure in the x-y plane and the number of the two can be selected according to different semiconductor device architectures, while playing a supporting role, reducing the overall size of the second channel structure and the third channel structure in the finally formed semiconductor device, and increasing the storage density of the semiconductor device.

[0099] Optionally, the radial size of at least one of the second channel structure 320 and the third channel structure can be greater than or equal to the radial size of the first channel structure 310, wherein the radial size can be understood as the size of the structure in the plane intersecting the z direction (for example, the x-y plane).

[0100] Optionally, the second channel structure 320 and the third channel structure can comprise the same layer structure as the first channel structure 310. For example, the second channel structure 320 and the third channel structure can also comprise the functional layer 301 and the channel layer 302 on the surface of the functional layer 301.

[0101] Alternatively, considering that the second channel structure 320 and the third channel structure only play a supporting role, the second channel structure 320 and the third channel structure can also comprise a different layer structure from the first channel structure 310.

[0102] FIG. 5 is a top view schematic diagram of a gate line isolation structure 400 according to an embodiment of the present application.

[0103] Reference is made to FIG. 1 and FIG. 5 In some embodiments of the present application, at least one surface 4111 (which can be understood as a surface of a sidewall of the gate line isolation structure 400, hereinafter referred to as sidewall 4111) of the gate line isolation structure 400 comprises a curved surface, which comprises at least one of a concave surface and a convex surface. In addition, the gate line isolation structure 400 extends in a wavy shape in the x direction.

[0104] Specifically, the gate line isolation structure 400 comprises a sidewall 4111 in contact with the stack structure 200, wherein the sidewall 4111 is a curved surface, which comprises at least one of a concave surface and a convex surface. Optionally, the sidewall 4111 of the gate line isolation structure 400 has a wavy shape on both sides in the x direction. Optionally, the sidewall 4111 of the first portion 410 comprises a curved surface, which comprises at least one of a concave surface and a convex surface. In addition, the sidewall 4111 of the first portion 410 has a wavy shape on both sides in the x direction. Optionally, the sidewall 4111 of the second portion 420 comprises a curved surface, which comprises at least one of a concave surface and a convex surface. In addition, the sidewall 4111 of the second portion 420 has a wavy shape on both sides in the x direction.

[0105] In other words, in this embodiment, the gate line isolation structure 400 can be formed by first forming a gate line gap, for example, a first gap and a second gap, in a stack structure (not shown) comprising a gate sacrificial layer, and then filling the gate line gap. Alternatively, the gate line gap accommodating the gate line isolation structure 400 can be formed by first forming a first hole (not shown), and then removing at least the portion of the stack structure between adjacent first holes. Thus, the surface of the sidewall of the stack structure in contact with the gate line gap is a curved surface, and the sidewall 4111 of the gate line isolation structure 400 formed in the gate line gap also comprises a curved surface.

[0106] In this embodiment, the gate line gap accommodating the gate line isolation structure 400 is formed in steps. The first holes formed can be formed together with "deep holes" for other structures in the semiconductor device 1000, and then the first holes are connected to form the gate line gap, such as the first gap and the second gap, by a "hole expansion" process. By forming the various holes for different structures in the semiconductor device 1000, such as the first channel hole, the second channel hole, and the first hole, in the same process, the number of etching processes for forming high aspect ratio structures can be effectively reduced, thereby reducing the difficulty of manufacturing the semiconductor device 1000 and reducing the cost of manufacturing the semiconductor device 1000.

[0107] In addition, the various holes for different structures in the semiconductor device 1000 are formed in the same process, and can also be prepared using the same photolithography mask, which can improve the overlay accuracy of the etching process, reduce the overlay error, and enable the semiconductor device 1000 to have relatively high overall performance.

[0108] Alternatively, referring to FIG. 4 , the gate line isolation structure 400, such as the first portion 410 or the second portion 420, can include the gate line isolation layer 112 and the gate line filling layer 111 on the surface of the gate line isolation layer 112. Alternatively, the material of the gate line isolation layer 112 can include at least one of a high dielectric constant dielectric layer and an insulating dielectric material layer such as a silicon oxide layer. In addition, the material of the gate line filling layer 111 can include at least one of a semiconductor material such as polysilicon and an insulating dielectric material layer such as silicon oxide, silicon nitride, and silicon oxynitride. Alternatively, the material of the gate line filling layer 111 can also include a conductive material layer. The present application does not limit the internal filling material of the gate line isolation structure 400.

[0109] Again referring to FIG. 1 , FIG. 3 and FIG. 4 , the second spacing structure 432 includes a plurality of isolation layers 4321, wherein the isolation layers 4321 can be alternately stacked along the z direction with the first dielectric layer 210 and disposed in the same layer as the gate layer 220. Alternatively, the material of the isolation layer 4321 can include any suitable insulating dielectric material. For example, the isolation layer 4321 includes an insulating dielectric material layer such as a silicon oxide layer. Alternatively, the isolation layer 4321 can include the same insulating dielectric material layer as the first dielectric layer 210, in which case there is still a boundary between the isolation layer 4321 and the first dielectric layer 210 due to the different formation processes of the isolation layer 4321 and the first dielectric layer 210.

[0110] In addition, the second spacing structure 432 also includes an isolation column 4322 extending along the z direction and including the same insulating dielectric material as the isolation layer 4321.

[0111] Referring to FIG. 1and FIG. 3 The first isolation structure 431 is surrounded by the second isolation structure 432 and extends in the z direction through a plurality of isolation layers 4321.

[0112] Optionally, the first and second isolation structures 431 and 432 are both located in a first sub-region 011 of the array region 01 close to the connection region 02. In this embodiment, the first section 410 extends in the x direction and is located in a second sub-region 012 of the array region 01 away from the connection region 02; the second section 420 extends in the x direction and extends from the first sub-region 011 of the array region 01 into the connection region 02.

[0113] FIG. 6 is a top view schematic diagram of a semiconductor device 1 according to an embodiment.

[0114] As shown in FIG. 6 , in this embodiment, the semiconductor device 1 includes a stack structure 200, a gate line isolation structure 400, and a second isolation structure 432. The second isolation structure 432 divides the gate line isolation structure 400 into a first section 410 and a second section 420 spaced apart in the x direction. Similarly, in the process of preparing the semiconductor device 1, the second isolation structure 432 can divide the first gap and the second gap, and the gate sacrificial layer can be removed through the first gap and the second gap, respectively. However, in this process, since the remaining part of the semiconductor intermediate body includes "deep holes" (not shown) formed by the etching process, such as the first channel hole, the second channel hole, etc., and the area where the second isolation structure 432 is located does not have "deep holes" because it needs to divide the first gap and the second gap. This will cause the stress to be uneven throughout the semiconductor intermediate body, and the "deep holes" adjacent to the area where the second isolation structure 432 is located will be affected by the above-mentioned uneven stress, causing topography deviation, and ultimately resulting in poor uniformity of the plurality of channel structures in the semiconductor device.

[0115] In combination FIG. 1 and FIG. 6 , the second isolation structure 432 is arranged around the first isolation structure 431, or at least one first isolation structure 431 is arranged in the second isolation structure 432. By forming the "deep hole" when the first isolation structure 431 is formed, the stress in the area where the second isolation structure is located can be improved, the topography deviation of the plurality of channel structures corresponding to the area can be reduced, and the uniformity of the plurality of channel structures can be improved, thereby improving the stability and conductivity of the semiconductor device.

[0116] Optionally, referring to FIG. 1To optimize the above effect, in some embodiments of the present application, the first spacing structure 431 can include a first separation structure 4311 and a second separation structure 4312, wherein the first separation structure 4311 can be closer to the first part 410 relative to the second separation structure 4312 along the x direction, and the second separation structure 4312 can be closer to the second part 420 relative to the first separation structure 4311 along the x direction. In other words, the first part 410, the first separation structure 4311, the second separation structure 4312, and the second part 420 can be sequentially arranged along the x direction. By improving the positional relationship between the first separation structure or the second separation structure and the gate line isolation structure, the distribution of the local stress in the region of the semiconductor intermediate body where the second spacing structure is located can be improved.

[0117] Optionally, as shown in FIG. 2 To optimize the above effect and improve the stress of the region of the semiconductor intermediate body where the second spacing structure is located in a particular direction, the size c2 of the first spacing structure 431 along the x direction can be greater than the size c1 of the first spacing structure along the third direction (y direction), wherein the y direction intersects the x direction and the z direction. In other words, in the process of preparing the semiconductor device, the "deep hole" containing the first spacing structure 431 can be a "slot" with a high aspect ratio structure, wherein the "deep hole" can be understood as a two-dimensional figure with a circular cross section perpendicular to its extension direction, and the "slot" can be understood as a two-dimensional figure with an elliptical or rectangular cross section perpendicular to its extension direction.

[0118] Optionally, as shown in FIG. 1 and FIG. 3 To optimize the above effect, the number of "deep holes" generated when forming the first spacing structure 431 can be increased, and the first spacing structure 431 can include a plurality of columnar structures spaced along the x direction. For example, the first separation structure 4311 can include a plurality of columnar structures spaced along the x direction; and the second separation structure 4312 can include a plurality of columnar structures spaced along the x direction.

[0119] In addition, to optimize the above effect, the radial size of the "deep hole" generated when forming the first spacing structure 431 can be increased, and the size of the first part 410 or the second part 420 in the y direction can be less than or equal to the size of the first spacing structure 431 in the y direction.

[0120] Optionally, the extension size D of the second spacing structure 432 in the direction intersecting the z direction (for example, the x direction or the y direction) can satisfy: 400nm≤D≤1500nm. By reasonably controlling the extension length of the second spacing structure, the length of the effective storage area of the semiconductor device including a plurality of first channels 310 can be relatively increased, and the storage capacity of the semiconductor device can be improved.

[0121] Therefore, according to at least one embodiment of the present application, a semiconductor device is provided, which comprises a stack structure, a gate line isolation structure, a first spacer structure and a second spacer structure, wherein the first spacer structure and the second spacer structure divide the gate line isolation structure into a first part and a second part which are spaced apart in the extension direction of the gate line isolation structure. The gate electrode layer of the stack structure can be prepared by a gate-last process, for example, a gate electrode sacrificial layer is formed in advance, and in the process of removing the gate electrode sacrificial layer by using a process such as wet etching, the etchant and chemical precursors are allowed to contact the gate electrode sacrificial layer by means of the gate line gap, for example, the first gate line gap and the second gate line gap, generated when the gate line isolation structure is formed, and then part of the gate electrode sacrificial layer is removed to form the gate electrode layer. The first spacer structure and the second spacer structure divide the gate line isolation structure into the first part and the second part; similarly, in the process of preparing the semiconductor device, the first spacer structure and the second spacer structure divide the first gap and the second gap, which can reduce the situation that the excess etchant flows into the other structures which have been formed in the semiconductor intermediate body through the gate line gap in the process of removing the gate electrode sacrificial layer by using the gate-last process in the preparation of the semiconductor device, and thus the overall performance of the semiconductor device is improved.

[0122] In addition, the semiconductor device further comprises a channel structure, and the second spacer structure is arranged around the first spacer structure, which can improve the stress of the stack structure in the part where the first spacer structure and the second spacer structure are located, reduce the situation of the morphology deviation of the plurality of channel structures corresponding to the first spacer structure and the second spacer structure, and thus improve the uniformity of the plurality of channel structures and the overall performance of the semiconductor device.

[0123] FIG. 7 is a top view schematic diagram of a semiconductor device 1000 according to another embodiment of the present application.

[0124] FIG. 8 is FIG. 7 The semiconductor device 1000 shown is a cross-sectional schematic diagram taken along the line B-B'.

[0125] FIG. 9 is a cross-sectional schematic diagram of a semiconductor device 1000 according to another embodiment of the present application.

[0126] As FIG. 7 to FIG. 9As shown, another aspect of the present application provides a semiconductor device 1000, which can include a stack structure 200, a gate line isolation structure 400, a first channel structure 310, a second channel structure 320, and a spacer structure 430. The stack structure 200 includes first dielectric layers 210 and gate layers 220 alternately stacked along a first direction (e.g., the z direction). The gate line isolation structure 400 extends in the stack structure 200 along a second direction (e.g., the x direction) intersecting the z direction, and includes first portions 410 and second portions 420 distributed in the x direction with a spacing. The spacer structure 430 is located between the first portions 410 and the second portions 420. The first channel structure 310 and the second channel structure 320 both extend in the stack structure 200 along the z direction, wherein a plurality of the second channel structures 320 are located on one side of the spacer structure 430 along a third direction (the y direction) intersecting the x direction and the z direction, and a size d2 of the second channel structure 320 is greater than a size d1 of the first channel structure 310 in a direction (e.g., the x direction or the y direction) intersecting the z direction.

[0127] It should be noted that, in order to facilitate observation of the shape and position of the rest of the structures in the semiconductor device 1000 except for the gate layers 220, FIG. 7 The shape of the gate layers 220 shown by only black lines.

[0128] The gate layers of the stack structure provided by the embodiments of the present application can be prepared by a back gate process, for example, a gate sacrificial layer is formed in advance, and in the process of removing the gate sacrificial layer by using a process such as wet etching, the etchant and the chemical precursor are brought into contact with the gate sacrificial layer by means of the gate line gap, for example, the first gate line gap and the second gate line gap, generated when the gate line isolation structure is formed, and then part of the gate sacrificial layer is removed to form the gate layer. The spacer structure divides the gate line isolation structure into the first portion and the second portion; similarly, in the process of preparing the semiconductor device, the spacer structure divides the first gap from the second gap, which can reduce the case that the excess etchant flows into the other structures formed in the semiconductor intermediate body through the gate line gap in the process of removing the gate sacrificial layer by using the back gate process in the preparation of the semiconductor device, and thus improve the overall performance of the semiconductor device.

[0129] In addition, the spacer structure and the plurality of second channel structures are distributed along a direction intersecting both the stacking direction of the stack structure and the extending direction of the gate line isolation structure, and the size of the second channel structure is set to be greater than the size of the first channel structure in the direction intersecting the stacking direction, which can improve the stress of the stack structure at the part where the spacer structure is located, reduce the case of morphology deviation of the second channel structure, and thus improve the uniformity of the plurality of channel structures and the overall performance of the semiconductor device.

[0130] Specifically, as FIG. 9As shown, the stacked structure 200 may be disposed on one side of the substrate 100. The substrate 100 may include a semiconductor material layer, wherein the semiconductor material may include, but is not limited to, a single element semiconductor material (e.g., silicon, germanium), a Group III-V compound semiconductor material, a Group II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. For example, the substrate 100 may include a silicon substrate. Alternatively, the substrate 100 may be a composite structure, for example, a composite structure including a layer structure connected to a channel structure 300, wherein the channel structure 300 will be described in detail below in conjunction with the accompanying drawings.

[0131] like FIG. 7 and FIG. 9 As shown, the stacked structure 200 may include an array region 01 and a connection region 02 adjacently distributed in the x-direction, wherein the array region 01 may include a first sub-region 011 and a second sub-region 012 adjacently distributed in the x-direction, and the first sub-region 011 is closer to the connection region 02 than the second sub-region 012.

[0132] Alternatively, the gate layer 220 may include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The first dielectric layer 210 may serve as an isolation stack layer, including but not limited to an insulating dielectric material layer such as a silicon oxide layer.

[0133] In addition, the stacked structure 200 further includes a plurality of second dielectric layers 240. The second dielectric layers 240 and the first dielectric layer 210 are made of two different insulating dielectric materials. For example, the second dielectric layers 240 may include, but are not limited to, insulating dielectric materials such as silicon nitride layers. Furthermore, the plurality of second dielectric layers 240 and the plurality of gate layers 220 may have the same stack height. Optionally, the number of layers in the stacked structure 200 is not limited to that shown in the figure and may be further configured as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0134] In other words, the stacked structure 200 may include alternating first dielectric layers 210 and composite layers, wherein the composite layer may include a gate layer 220 and a second dielectric layer 240 disposed in the same layer. For example, the gate layer 220 and the second dielectric layer 240 may be connected and distributed in an xy plane intersecting the z-direction. The gate layer 220 extends from the array region 01 of the stacked structure 200 along the x-direction to the connection region 02 and is connected to the second dielectric layer 240 disposed in the same layer, wherein the second dielectric layer 240 is located in the connection region 02.

[0135] Alternatively, as FIG. 7As shown, the gate layer 220 can include a first portion 221 located in the array region 01 and a second portion 222 located in the connection region 02, and the first portion 221 and the second portion 222 are connected to each other. In addition, a surface 2212 of the first portion 221 facing the connection region 02 includes a curved surface, and the curved surface includes at least one of a concave surface and a convex surface. This can release local stress of the semiconductor device and increase stability of the semiconductor device.

[0136] In addition, as FIG. 9 As shown, the stack structure 200 can further include a dielectric cover layer 250, which can be made of the same material as the first dielectric layer 210. Alternatively, the dielectric cover layer 250 can have a dimension along the z direction greater than that of the first dielectric layer 210 or the gate layer 220 along the z direction.

[0137] In addition, as FIG. 7 and FIG. 9 As shown, in some embodiments of the present application, the semiconductor device 1000 further includes a channel structure 300 extending in the stack structure 200 along the z direction, wherein the channel structure 300 can include a first channel structure 310 and a second channel structure 320, and a dimension d2 of the second channel structure 320 is greater than a dimension d1 of the first channel structure 310 in a direction (e.g., the x direction or the y direction) intersecting the z direction.

[0138] For example, in the direction (e.g., the x direction or the y direction) intersecting the z direction, the dimension d1 of the first channel structure 310 and the dimension d2 of the second channel structure 320 can satisfy: 1.1d1≤d2.

[0139] Alternatively, in the direction (e.g., the x direction or the y direction) intersecting the z direction, the dimension d2 of the second channel structure 320 can satisfy: 110nm<d2≤150nm.

[0140] Alternatively, the first channel structure 310 can be located in a second sub-region 012 of the array region 01, and the second channel structure 320 can be located in a first sub-region 011 of the array region 01 and distributed along the y direction with the spacing structure 430.

[0141] For example, a part of the plurality of second channel structures 320 can be located on one side of the spacing structure 430 along the y direction, and another part of the plurality of second channel structures 320 can be located in the spacing structure 430.

[0142] In addition, the channel structure 300 can further include a third channel structure, which can be located in the second sub-region. The plurality of second channel structures and the plurality of third channel structures can function as supports for the semiconductor intermediate during the process of removing the gate sacrificial layer, so as to reduce the possibility of deformation and collapse of the semiconductor intermediate. Alternatively, the layout of the second channel structure and the third channel structure in the x-y plane and the number of the second channel structure and the third channel structure can be selected according to different settings of the semiconductor device architecture, so as to reduce the overall size of the second channel structure and the third channel structure in the semiconductor device formed finally, and increase the storage density of the semiconductor device.

[0143] Alternatively, the size of the third channel structure in the direction intersecting the z direction (for example, the x direction or the y direction) can be greater than or equal to the size d1 of the first channel structure 310. Alternatively, the size of the third channel structure in the direction intersecting the z direction (for example, the x direction or the y direction) can be greater than or equal to the size d2 of the second channel structure 320.

[0144] The first channel structure 310 includes a functional layer 301 and a channel layer 302 located on the surface of the functional layer 301. The functional layer 301 can include, in sequence, a blocking layer, a charge trapping layer and a tunneling layer arranged on the inner wall of the first channel hole (not shown). In some embodiments, the functional layer 301 can include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 301 can have a structure different from the ONO configuration. The channel layer 302 can be located on the surface of the tunneling layer and can be used to transport the required charges (electrons or holes). The channel layer 302 can be made of a semiconductor material such as polysilicon or monocrystalline silicon, and can have conductive impurities. In addition, the channel structure 300 can further include a channel filling medium layer filled in the remaining space of the channel hole after the functional layer 301 and the channel layer 302 have been formed. The channel filling medium layer includes an insulating medium material layer such as a silicon oxide layer.

[0145] The second channel structure 320 and the third channel structure can function as supports during the process of removing the gate sacrificial layer, so as to reduce the possibility of deformation and collapse of the semiconductor intermediate. Thus, the layout of the second channel structure and the third channel structure in the x-y plane and the number of the second channel structure and the third channel structure can be selected according to different settings of the semiconductor device architecture, so as to reduce the overall size of the second channel structure and the third channel structure in the semiconductor device formed finally, and increase the storage density of the semiconductor device.

[0146] Alternatively, the second channel structure 320 and the third channel structure may include the same layer structure as the first channel structure 310. For example, the second channel structure 320 and the third channel structure may also include a functional layer 301 and a channel layer 302 located on a surface of the functional layer 301.

[0147] As another option, considering that the second channel structure 320 and the third channel structure only play a supporting role, the second channel structure 320 and the third channel structure may also include a different layer structure from the first channel structure 310 .

[0148] like FIG. 9 As shown, the gate line isolation structure 400 such as the first division 410 or the second division 420 may include a gate line isolation layer 112 and a gate line filling layer 111 located on the surface of the gate line isolation layer 112. Optionally, the material of the gate line isolation layer 112 may include at least one of a high dielectric constant dielectric layer and an insulating dielectric material layer such as a silicon oxide layer. In addition, the material of the gate line filling layer 111 may include a semiconductor material such as polysilicon and at least one of an insulating dielectric material layer such as silicon oxide, silicon nitride, and silicon oxynitride. Optionally, the material of the gate line filling layer 111 may also include a conductive material layer. The present application does not limit the internal filling material of the gate line isolation structure 400. In other words, at least one of the first division 410 and the second division 420 may include a gate line isolation layer 112 and a gate line filling layer 111 located on the surface of the gate line isolation layer 112.

[0149] In addition, reference FIG. 7 In some embodiments of the present application, at least one surface 4111 of the gate line isolation structure 400 (which can be understood as the surface of a sidewall of the gate line isolation structure 400, hereinafter referred to as the sidewall 4111) includes a curved surface, which includes at least one of a concave surface and a convex surface. Furthermore, the gate line isolation structure 400 extends in a wavy shape in the x-direction.

[0150] Specifically, the gate line isolation structure 400 includes the stacked structure 200 (eg FIG. 9 The sidewall 4111 of the first subsection 410 is in contact with the sidewall 4111 of the second subsection 420, wherein the sidewall 4111 is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface. For example, the sidewall 4111 of the first subsection 410 is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface, and the sidewall 4111 of the second subsection 420 is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

[0151] Optionally, the sidewalls 411 of the gate line isolation structure 400 have a wavy shape on both sides along the x-direction. For example, the sidewalls 4111 of the first subsection 410 have a wavy shape on both sides along the x-direction, and the sidewalls 4111 of the second subsection 420 have a wavy shape on both sides along the x-direction.

[0152] In other words, in this embodiment, the gate line isolation structure 400 can be formed by first forming the gate line gaps, such as the first gap and the second gap, in a stack structure (not shown) including the gate sacrificial layer, and then filling the gate line gaps. Alternatively, the gate line gaps accommodating the gate line isolation structure 400 can be formed by first forming the first holes (not shown), and then removing at least the portions of the stack structure between the adjacent first holes. Thus, the surface of the sidewall of the gate line gap in contact with the stack structure is curved, and the sidewall 4111 of the gate line isolation structure 400 formed in the gate line gap also includes a curved surface.

[0153] In this embodiment, the gate line gaps accommodating the gate line isolation structure 400 are formed in steps. The first holes formed first can be formed together with the “deep holes” for forming other structures in the semiconductor device 1000, and then the first holes are connected to form the gate line gaps, such as the first gap and the second gap, by a “hole expansion” process. By forming the various holes for different structures in the semiconductor device 1000, such as the first channel hole, the second channel hole, and the first hole, in the same process, the number of etching processes for forming high aspect ratio structures can be effectively reduced, and thus the difficulty of manufacturing the semiconductor device 1000 is reduced, and the cost of manufacturing the semiconductor device 1000 is reduced.

[0154] In addition, the various holes for different structures in the semiconductor device 1000 are formed in the same process, and thus the same photolithography mask can be used to manufacture the various holes, which can improve the overlay accuracy of the etching process, reduce the overlay error, and make the finally formed semiconductor device 1000 have relatively high overall performance.

[0155] Alternatively, the first part 410 of the gate line isolation structure 400 extends along the x direction and is located in the second sub-region 012 of the array region 01 away from the connection region 02; and the second part 420 extends along the x direction and extends from the first sub-region 011 of the array region 01 into the connection region 02.

[0156] Alternatively, the size b1 of the first part 410 in the y direction is less than or equal to the size b2 of the second part 420 in the y direction. For example, the size b1 of the first part 410 in the y direction and the size b2 of the second part 420 in the y direction can satisfy: 1.1b1≤b2. In addition, the size b2 of the second part 420 in the y direction can satisfy: 300nm<b2≤900nm.

[0157] As described above, the first gap for accommodating the first subsection 410 and the second gap for accommodating the second subsection 420 can be prepared by first forming a first hole and then performing a "hole expansion" process. Thus, the multiple first holes used to form the first gap and the multiple first holes used to form the second gap can have the same size in the xy plane, simplifying the etching process used to form high-aspect-ratio structures. The "hole expansion" process can then be used to specifically change the local size of the first gap or the second gap in the xy plane to meet the requirements of different semiconductor devices, where the xy plane can be understood as a plane intersecting the z direction.

[0158] like FIG. 6 As shown, the semiconductor device 1 includes a stacked structure 200, a gate line isolation structure 400, and a second spacer structure 432. The second spacer structure 432 divides the gate line isolation structure 400 into a first subsection 410 and a second subsection 420 spaced apart in the x-direction. In this embodiment, since the region where the second spacer structure 432 is located is required to generate the first and second gaps when the first and second subsections 410 and 420 are divided during the preparation of the semiconductor device 1, there are no "deep holes" of a high aspect ratio structure. However, a large number of "deep holes" exist in the remaining regions of the semiconductor intermediate body, which will result in uneven stress in various parts of the semiconductor intermediate body. The "deep holes" adjacent to the region where the second spacer structure 432 is located will be affected by the uneven stress and will experience morphological deviation, thereby deteriorating the uniformity of multiple channel structures in the ultimately formed semiconductor device.

[0159] In at least one embodiment of the present application, a semiconductor device 1000 may include a stacked structure 200, a gate line isolation structure 400, a first channel structure 310, a second channel structure 320, and a spacer structure 430. The spacer structure 430 is located between the first subdivision 410 and the second subdivision 420 of the gate line isolation structure 400. The plurality of second channel structures 320 and the spacer structure 430 are distributed along the y-direction, wherein in a direction intersecting the z-direction (e.g., the x-direction or the y-direction), a dimension d2 of the second channel structure 320 may be greater than a dimension d1 of the first channel structure 310. Therefore, in the process of preparing the semiconductor device 1000, a portion of the second channel hole for accommodating the second channel structure 320 may be adjacent to the area where the spacing structure 430 is located, and the other portion may be located in the spacing structure 430, and the size of the second channel hole in the direction intersecting with its own extension direction is larger than the size of the "deep hole" in the remaining areas of the semiconductor intermediate in the direction intersecting with its own extension direction. This can improve the stress in the area where the spacing structure is located, reduce the morphological deviation of multiple channel structures corresponding to the area, thereby improving the uniformity of multiple channel structures and improving the stability and conductivity of the semiconductor device.

[0160] Optionally, the extension dimension D of the spacer structure 430 in a direction intersecting the z-direction (e.g., the x-direction or the y-direction) may satisfy the following condition: 400 nm ≤ D ≤ 1500 nm. By properly controlling the extension length of the spacer structure, the length of the effective storage area including the plurality of first channels 310 in the semiconductor device can be relatively increased, thereby improving the storage capacity of the semiconductor device.

[0161] Alternatively, as FIG. 7 to FIG. 9 As shown, the spacer structure 430 includes a plurality of isolation layers 4321. The isolation layers 4321 may be alternately stacked with the first dielectric layer 210 along the z-direction and disposed in the same layer as the gate layer 220. Alternatively, the isolation layers 4321 may be made of any suitable insulating dielectric material. For example, the isolation layers 4321 may include an insulating dielectric material layer such as a silicon oxide layer. Alternatively, the isolation layers 4321 may include the same insulating dielectric material layer as the first dielectric layer 210. In this case, since the isolation layers 4321 and the first dielectric layer 210 are formed through different processes, a boundary still exists between the isolation layers 4321 and the first dielectric layer 210.

[0162] In addition, the spacing structure 430 further includes an isolation column 4322, which extends along the z-direction and comprises the same insulating dielectric material as the isolation layer 4321. Optionally, the isolation column 4322 is located on one side of the second channel structure 320 in the y-direction.

[0163] FIG. 10 FIG. 1 is a schematic top view of a semiconductor device 1000 according to another embodiment of the present application. FIG. 11 yes FIG. 10 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line CC′. FIG. 12 yes FIG. 10 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line EE′. FIG. 13 A schematic cross-sectional view of a semiconductor device 1000 according to yet another embodiment of the present application.

[0164] like FIG. 10 to FIG. 13As shown, in another aspect, the present application provides a semiconductor device 1000, which can include a stack structure 200, a gate line isolation structure 400, a first channel structure 310, a second channel structure 320, and a spacer structure 430, wherein the spacer structure 430 includes a first spacer structure 431 and a second spacer structure 432 surrounding the first spacer structure 431. The stack structure 200 includes first dielectric layers 210 and gate layers 220 alternately stacked along a first direction (e.g., the z direction). The gate line isolation structure 400 extends in the stack structure 200 along a second direction (e.g., the x direction) intersecting the z direction, and includes first portions 410 and second portions 420 spaced apart in the x direction. The spacer structure 430 is located between the first portions 410 and the second portions 420. The first channel structure 310 and the second channel structure 320 both extend in the stack structure 200 along the z direction, wherein a plurality of the second channel structures 320 and the spacer structure 430 are distributed along a third direction (the y direction) intersecting both the x direction and the z direction. In the direction intersecting the z direction (e.g., the x direction or the y direction), the size d2 of the second channel structure 320 can be greater than the size d1 of the first channel structure 310, and in addition, the second spacer structure 432 can be arranged around the first spacer structure 431.

[0165] It should be noted that, in order to facilitate observation of the shape and position of the rest of the structures in the semiconductor device 1000 except for the gate layers 220, FIG. 10 The shape of the gate layers 220 shown by only black lines.

[0166] The gate layers of the stack structure provided by the embodiments of the present application can be prepared by a back gate process, for example, a gate sacrificial layer is formed in advance, and in the process of removing the gate sacrificial layer by using a process such as wet etching, the etchant and the chemical precursor are brought into contact with the gate sacrificial layer by means of the gate line gap, for example, the first gate line gap and the second gate line gap, generated when the gate line isolation structure is formed, and then part of the gate sacrificial layer is removed to form the gate layers. The first spacer structure and the second spacer structure divide the gate line isolation structure into the first portion and the second portion; similarly, in the process of preparing the semiconductor device, the first spacer structure and the second spacer structure divide the first gap from the second gap, which can reduce the situation that the excess etchant flows into the other structures already formed in the semiconductor intermediate body through the gate line gap in the process of removing the gate sacrificial layer by using the back gate process in the preparation of the semiconductor device, thereby improving the overall performance of the semiconductor device.

[0167] In addition, the second spacer structure is arranged around the first spacer structure, and the plurality of second channel structures are distributed with the spacer structure along a third direction, and in a direction intersecting the stacking direction of the stack structure, the size of the second channel structure is greater than the size of the first channel structure, which can improve the stress of the stack structure in the part where the spacer structure is located, reduce the case of morphology deviation of the plurality of channel structures corresponding to the spacer structure, and further improve the uniformity of the plurality of channel structures, and improve the overall performance of the semiconductor device.

[0168] Specifically, as shown in the drawings, FIG. 10 In some embodiments of the present application, the first spacer structure 431 can include a first separation structure 4311 and a second separation structure 4312, wherein the first separation structure 4311 can be closer to the first part 410 relative to the second separation structure 4312 along the x direction, and the second separation structure 4312 can be closer to the second part 420 relative to the first separation structure 4311 along the x direction. In other words, the first part 410, the first separation structure 4311, the second separation structure 4312 and the second part 420 are sequentially arranged along the x direction. By improving the positional relationship between the first separation structure or the second separation structure and the gate line isolation structure, the distribution of the local stress in the area of the semiconductor intermediate body where the second spacer structure is located can be improved.

[0169] In addition, in some embodiments of the present application, in order to optimize the above-mentioned effect, the number of "deep holes" generated when the first spacer structure 431 is formed can be increased. In other words, the first spacer structure 431 can include a plurality of columnar structures distributed along the x direction. Specifically, the first separation structure 4311 can include a plurality of columnar structures distributed along the x direction; the second separation structure 4312 can include a plurality of columnar structures distributed along the x direction.

[0170] As shown in the drawings, FIG. 11 and FIG. 12As shown, in some embodiments of the present application, the first spacer structure 431 may have the same layer structure as the channel structure 300. In other words, taking the second channel structure 320 as an example, the channel structure 300 may include a functional layer 301 and a channel layer 302 located on the surface of the functional layer 301. The first spacer structure 431 may include a first layer 401 and a second layer 402 located on the surface of the first layer 401. The first layer 401 may have the same layer structure as the functional layer 301 and may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the first layer 401 may have a structure other than an ONO configuration. The second layer 402 may have the same layer structure as the channel layer 302. The second layer 402 may be made of a semiconductor material such as polycrystalline silicon or single crystal silicon and may contain conductive impurities. In addition, the first spacer structure 431 may also include a third layer having the same layer structure as the trench fill dielectric layer of the channel structure. The third layer may include an insulating dielectric material layer such as a silicon oxide layer.

[0171] In addition, the first spacer structure 431 and the channel structure 300 can also be formed in the same process to simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device.

[0172] like FIG. 10 As shown, in some embodiments of the present application, to optimize the aforementioned effects and reduce stress in a specific direction in the region where the spacer structure is located, the dimension c2 of the first spacer structure 431 along the x-direction may be greater than the dimension c1 of the first spacer structure along the y-direction. In other words, during the semiconductor device fabrication process, the "deep hole" that accommodates the first spacer structure 431 may be a "groove" with a high aspect ratio. A "deep hole" may be understood as a symmetrical two-dimensional shape, such as a circle, with a cross-section perpendicular to its own extension direction, while a "groove" may be understood as an asymmetrical two-dimensional shape, such as an ellipse or rectangle, with a cross-section perpendicular to its own extension direction.

[0173] In addition, reference FIG. 10 and FIG. 13 In some embodiments of the present application, at least one surface 4111 of the gate line isolation structure 400 (which can be understood as the surface of a sidewall of the gate line isolation structure 400, hereinafter referred to as the sidewall 4111) includes a curved surface, which includes at least one of a concave surface and a convex surface. Furthermore, the gate line isolation structure 400 extends in a wavy shape in the x-direction.

[0174] The side wall 4111 of the gate line isolation structure 400 in contact with the stack structure 200 comprises a curved surface, which comprises at least one of a concave surface and a convex surface. Alternatively, the side wall 4111 of the gate line isolation structure 400 has a wavy shape along both sides in the x direction. Alternatively, the side wall 4111 of the first portion 410 comprises a curved surface, which comprises at least one of a concave surface and a convex surface. In addition, the side wall 4111 of the first portion 410 has a wavy shape along both sides in the x direction. Alternatively, the side wall 4111 of the second portion 420 comprises a curved surface, which comprises at least one of a concave surface and a convex surface. In addition, the side wall 4111 of the second portion 420 has a wavy shape along both sides in the x direction.

[0175] In other words, in this embodiment, the gate line isolation structure 400 can be formed by first forming gate line gaps, such as the first gap and the second gap, in the stack structure comprising the gate sacrificial layer, and then filling the gate line gaps. Alternatively, the gate line gaps accommodating the gate line isolation structure 400 can be formed by first forming the first holes, and then removing at least the portions of the stack structure between adjacent first holes. Thus, the surface of the side wall of the stack structure in contact with the gate line gap is a curved surface, and the side wall 4111 of the gate line isolation structure 400 formed in the gate line gap also comprises a curved surface.

[0176] In this embodiment, the gate line gap accommodating the gate line isolation structure 400 is formed in steps. The first holes formed first can be formed together with the "deep holes" for other structures in the semiconductor device 1000, and then the first holes are connected to form the gate line gaps, such as the first gap and the second gap, by a "hole expansion" process. By forming various holes for different structures of the semiconductor device 1000, such as the first channel hole, the second channel hole and the first hole, in the same process, the number of etching processes for forming high aspect ratio structures can be effectively reduced, thereby reducing the difficulty of manufacturing the semiconductor device 1000 and reducing the cost of manufacturing the semiconductor device 1000.

[0177] In addition, the various holes for different structures of the semiconductor device 1000 are formed in the same process, and can also be prepared using the same photolithography mask, which can improve the overlay accuracy of the etching process, reduce the overlay error, and make the finally formed semiconductor device 1000 have relatively high overall performance.

[0178] Therefore, according to at least one embodiment of the present application, a semiconductor device is provided, which comprises a stack structure, a gate line isolation structure, a channel structure, and a spacing structure, wherein the channel structure comprises a first channel structure and a second channel structure, and the spacing structure divides the gate line isolation structure into a first part and a second part which are spaced apart in an extension direction of the gate line isolation structure. This can reduce the case that the excess etching liquid flows into other structures which have been formed in the semiconductor intermediate body through the gate line gap in the process of removing the gate sacrificial layer by using the gate-last process in the preparation of the semiconductor device, thereby improving the overall performance of the semiconductor device.

[0179] In addition, the spacing structure and the plurality of second channel structures are distributed in a direction which intersects both the stacking direction of the stack structure and the extension direction of the gate line isolation structure, and the size of the second channel structure is set to be greater than the size of the first channel structure in the direction intersecting the stacking direction, which can improve the stress of the stack structure in the part where the spacing structure is located, reduce the case of morphology deviation of the channel structure, thereby improving the uniformity of the plurality of channel structures and the overall performance of the semiconductor device.

[0180] FIG. 14 is a flowchart of a preparation method 2000 of a semiconductor device according to an embodiment of the present application. FIG. 15 to FIG. 31 are process schematic diagrams of the preparation method 2000 of the semiconductor device according to an embodiment of the present application, respectively.

[0181] As shown in FIG. 14 , the preparation method 2000 of the semiconductor device can comprise:

[0182] S11, alternately stacking a gate sacrificial layer and a first dielectric layer in a first direction to form a stack structure.

[0183] S12, forming a first gap and a second gap which are spaced apart from each other in the stack structure, and the first gap and the second gap both extend in a second direction intersecting the first direction.

[0184] S13, forming a first spacing structure between the first gap and the second gap and a second spacing structure arranged around the first spacing structure.

[0185] S14, removing part of the gate sacrificial layer through the first gap and the second gap to form a gate layer.

[0186] The specific processes of each step of the above preparation method 2000 in the embodiments of the present application will be described in detail below. FIG. 15 to FIG. 31

[0187] Step S11

[0188] FIG. 15 ​is a top view schematic diagram of a structure after forming the first hole 101 according to an embodiment of the present application. FIG. 16 is a cross-sectional view schematic diagram of a structure after forming the first hole 101 according to an embodiment of the present application. FIG. 17 is a cross-sectional view schematic diagram of a structure after forming the first hole 101 according to an embodiment of the present application.

[0189] As shown in FIG. 14 to FIG. 17 forming the stack structure 200’ can include, for example, providing the substrate 100’; and alternately stacking the first dielectric layer 210 and the gate sacrificial layer 230 to form the stack structure 200’.

[0190] In particular, in an embodiment of the present application, the material of the substrate 100’ can be selected from any suitable semiconductor material, such as monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or group III-V compound such as gallium arsenide, etc. Further, the substrate 100’ can be selected as monocrystalline silicon.

[0191] In an embodiment of the present application, the substrate 100’ can be, for example, a composite substrate for supporting the device structure thereon. The substrate 100’ can be formed by sequentially disposing a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0192] The substrate 100’ can include a substrate sacrificial layer (not shown) for subsequent formation of a semiconductor connecting layer (e.g., a second semiconductor layer, etc. formed in a subsequent step). The substrate sacrificial layer can include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer can include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer can be a high dielectric constant dielectric layer, or as another option, the substrate sacrificial layer can include a first dielectric layer (not shown), a sacrificial layer (not shown), and a second dielectric layer (not shown) sequentially disposed, wherein the first and second dielectric layers can be silicon nitride layers and the sacrificial layer can be a silicon oxide layer. Alternatively, the sacrificial layer can also be monocrystalline silicon or polycrystalline silicon, and in particular, in an embodiment of the present application, the exemplary material forming the sacrificial layer can be polycrystalline silicon. As another option, the substrate sacrificial layer can include any one or more of a dielectric material, a semiconductor material, and a conductive material.

[0193] The portion of the substrate 100' can also form a well region doped by N-type or P-type dopants via an ion implantation or diffusion process. The dopants can include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present disclosure, the well regions can be made of the same dopants or different dopants, and further, the well regions can have the same doping concentration or different doping concentrations, which are not limited in the present disclosure.

[0194] After the substrate 100' is formed, a stack structure 200' can be formed on one side of the substrate 100' by one or more thin film deposition processes, which can include, but are not limited to, a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), or any combination thereof, which are not limited in the present disclosure.

[0195] The stack structure 200' can include a plurality of pairs of the first dielectric layer 210 and the gate sacrificial layer 230 stacked alternately with each other. For example, the stack structure 200' can include 64 pairs, 128 pairs, or more than 128 pairs of the first dielectric layer 210 and the gate sacrificial layer 230.

[0196] In other words, the first dielectric layer 210 and the gate sacrificial layer 230 can be stacked along a first direction (z direction) to form the stack structure 200'. In some embodiments, the first dielectric layer 210 and the gate sacrificial layer 230 can include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the first dielectric layer 210 and the gate sacrificial layer 230 can include silicon oxide and silicon nitride, respectively. The silicon oxide layer can be used as an isolation stack layer, and the silicon nitride layer can be used as a sacrificial stack layer. Subsequently, a portion of the sacrificial stack layer can be etched away, and the etched-away portion of the sacrificial stack layer can be replaced with a conductor layer including a conductive material to form a gate conductive layer of a three-dimensional memory.

[0197] The preparation method of the single dielectric stack structure is described above. In fact, as the demand for the storage capacity of semiconductor devices such as three-dimensional memory increases, the storage stack gradually increases. In order to break through the limit of process, a double stack technology or a multi-stack technology can also be used to form a dielectric stack structure by sequentially stacking a plurality of sub-dielectric stack structures in the stacking direction of the dielectric stack structure, wherein each sub-dielectric stack structure can include a plurality of first dielectric layers and gate sacrificial layers alternately stacked. The number of layers of each sub-dielectric stack structure can be the same or different. Since the content and structure involved in the preparation process of the single dielectric stack structure described above can be fully or partially applicable to the technical effects of the dielectric stack structure formed by the plurality of sub-dielectric stack structures described herein, the related or similar content is not described again. However, those skilled in the art can understand that the subsequent preparation process can be based on the multi-dielectric stack structure or the single-dielectric stack structure.

[0198] As shown in FIG. 15 The stack structure 200' can include an array region 01 and a connection region 02 adjacent to each other in the x direction, wherein the array region 01 can include a first sub-region 011 and a second sub-region 012 adjacent to each other in the x direction, and the first sub-region 011 is closer to the connection region 02 than the second sub-region 012. The array region 01 can be used to form a first channel structure with a storage function in the subsequent process, and the connection region 02 can be used to form a contact structure in the subsequent process, which can be connected with the gate layer formed in the subsequent process, and the gate layer is connected with the external circuit through the contact structure.

[0199] Step S12

[0200] FIG. 18 is a cross-sectional schematic view of a structure after filling the first channel hole 104 according to an embodiment of the present application. FIG. 19 is a cross-sectional schematic view of a structure after filling the second channel hole 105 according to an embodiment of the present application. FIG. 20 is a cross-sectional schematic view of a structure after forming the first hole 101 according to an embodiment of the present application. FIG. 21 is a cross-sectional schematic view of a structure after forming the first gap 113 according to an embodiment of the present application. FIG. 22 is a cross-sectional schematic view of a structure after forming the first gap 113 according to an embodiment of the present application.

[0201] As shown in FIG. 15 to FIG. 22As shown, the step S12 of forming the first gap and the second gap spaced from each other in the stack structure, both of which extend along a second direction intersecting the first direction, can for example include: forming the first holes 101 through the stack structure 200' along the first direction, wherein the plurality of first holes 101 are arranged spaced along the second direction (x direction); and removing at least portions of the stack structure 200' between the first holes 101 adjacent in the x direction, to form the first gap 113 and the second gap 114.

[0202] In particular, with reference to FIG. 15 to FIG. 17 In some embodiments of the present application, the method 2000 of fabricating the semiconductor device further includes: in the process of forming the first holes 101, forming channel holes, wherein the channel holes include the first channel hole 104 and the second channel hole 105.

[0203] The finally formed semiconductor device can include a first channel structure and a second channel structure, wherein the first channel hole 104 can be used to form the first channel structure, and the second channel hole 105 can be used to form the second channel structure.

[0204] In addition, the finally formed semiconductor device can further include a third channel structure. Thus, as an option, the third channel hole 106 used to form the third channel structure can also be formed in the process of forming the first holes 101.

[0205] In addition, in some embodiments of the present application, the finally formed semiconductor device can include a first spacing structure and a second spacing structure. Thus, the first opening 102 used to form the first spacing structure and the second opening 103 used to form the second spacing structure can also be formed in the process of forming the first holes 101.

[0206] In other words, in some embodiments of the present application, the gate line gap accommodating the gate line isolation structure, such as the first gap 113 and the second gap 114, is formed in steps. The first holes 101 formed first can be formed together with the "deep holes" required for fabricating other structures of the semiconductor device, and then the plurality of first holes 101 are connected to form the first gap 113 and the second gap 114 through a "bore expansion" process. By forming a plurality of holes for different structures of the semiconductor device, such as the first channel hole, the second channel hole, and the first hole, in the same process, the number of etching processes for forming high aspect ratio structures can be effectively reduced, thereby reducing the difficulty of fabricating the semiconductor device and reducing the cost of fabricating the semiconductor device.

[0207] In addition, the plurality of holes for different structures of the semiconductor device are formed in the same process, and can also be prepared using the same photolithography mask, which can improve the overlay accuracy of the etching process, reduce the overlay error, and enable the finally formed semiconductor device to have relatively high overall performance.

[0208] Optionally, the plurality of "deep holes" in the stack structure 200' can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., can also be performed to form the plurality of "deep holes" in the stack structure 200', such as the first hole 101, the first opening 102, the second opening 103, the first trench hole 104, the second trench hole 105, and the third trench hole 106.

[0209] Optionally, the plurality of "deep holes" in the stack structure 200' can have the same depth in the z direction, which can simplify the difficulty of the etching process used to form the high aspect ratio structure.

[0210] In addition, referring to FIG. 15 In the direction intersecting the z direction (for example, the x direction or the y direction), the size of the third trench hole 106 can be greater than or equal to the size of the first trench hole 104. Optionally, in the direction intersecting the z direction, the size of the third trench hole 106 can be greater than or equal to the size of the second trench hole 105. Optionally, in the direction intersecting the z direction, the size of the first hole 101 can be greater than or equal to the size of the first trench hole 104. Optionally, in the direction intersecting the z direction, the size of the first hole 101 can be equal to the size of the first opening 102 or the second opening 103.

[0211] In addition, the first opening 102 can include at least one of a "hole" extending in the z direction and a "slot" extending in the x direction.

[0212] In other words, in the finally formed semiconductor device, the second spacing structure is arranged around the first spacing structure, which can improve the stress of the stack structure in the part where the spacing structure is located, reduce the case of morphology deviation of the plurality of trench structures corresponding to the spacing structure, and further improve the uniformity of the plurality of trench structures, and improve the overall performance of the semiconductor device. In order to optimize the above-mentioned effect and improve the stress in a certain direction of the region where the spacing structure is located, the size of the first spacing structure in the x direction can be greater than the size of the first spacing structure in the y direction. Thus, in the process of preparing the semiconductor device, the first opening 102 containing the first spacing structure can be a "hole" or a "slot" with a high aspect ratio structure, wherein the "hole extending in the z direction" can be understood as a two-dimensional figure with a circular cross section perpendicular to the extension direction, and the "slot extending in the x direction" can be understood as a two-dimensional figure with an elliptical or rectangular cross section perpendicular to the extension direction.

[0213] Optionally, any of the above-mentioned "deep holes" can select a suitable shape, size, and position of the "hole" or "slot" according to the architecture of the finally formed semiconductor device. For example, FIG. 15 The cross-sectional shape of the "hole" or "slot" shown in the x-y plane is rectangular.

[0214] Optionally, the first openings 102 and the second openings 103 can be distributed along the x direction in the first sub-region 011 of the stack structure 200'. In addition, the plurality of second via holes 105 can be located in the first sub-region 011 of the stack structure 200'. The plurality of first via holes 104 can be located in the second sub-region 012 of the stack structure 200'. The plurality of third via holes 106 can be located in the connection region 02 of the stack structure 200'.

[0215] Reference is made to FIG. 18 to FIG. 22 After the first holes 101 are formed, at least portions of the stack structure 200' between the first holes 101 adjacent in the x direction can be removed to form the first gap 113 and the second gap 114.

[0216] Specifically, the via hole sacrificial layer can be filled in the first openings 102, the first via holes 104, the second via holes 105, and the third via holes 106 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The via hole sacrificial layer can include a carbon-containing material layer. The via hole sacrificial layer can be formed of a material having a high deposition rate to facilitate fast filling of the above-mentioned "deep holes", and should be any material having a high dry etching selectivity with respect to the first dielectric layer 210 and the gate sacrificial layer 230 to facilitate removal in subsequent steps.

[0217] Afterwards, the first holes 101 can be "enlarged" to make the plurality of first holes 101 communicate with each other to form the first gap 113 and the second gap 114 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. can also be performed.

[0218] Alternatively, the first holes 101 can be stepwise enlarged or extended in multiple directions to form the first gap 113 and the second gap 114.

[0219] Reference is made to FIG. 20 and FIG. 21 Taking the formation of the first gap 113 as an example, portions of the stack structure 200' can be removed along the radial direction of the first holes 101 to enlarge the size of the aperture of the portion of the first holes 101 in the stack structure 200' in the x direction from L1 to L2; afterwards, portions of the substrate 100' can be continuously removed along the radial direction of the first holes 101 to also enlarge the size of the aperture of the portion of the first holes 101 in the substrate 100' in the x direction from L1 to L2, thereby forming the first gap 113, wherein the size of the first gap 113 in the x direction can be L1.

[0220] In addition, the portion of the stack structure 200' along the radial direction of the first hole 101 can also be removed, so that the size of the hole diameter of the portion of the first hole 101 in the stack structure 200' in the x direction is expanded from L1 to L2. This can omit the step of "removing the portion of the substrate 100' along the radial direction of the first hole 101". Considering the role of the first gap 113 and the second gap 114 in the removal of the portion of the gate sacrificial layer 230 (as shown in FIG. 19 , the first gap 113 and the second gap 114 can both extend through the stack structure 200' in the z direction without extending into the substrate 100'.

[0221] In addition, referring to FIG. 15 and FIG. 22 , as an option, the second openings 103 can be "enlarged" in the process of forming the first gap 113 and the second gap 114 by "hole expansion", so that the plurality of second openings 103 spaced apart in the x direction are connected to form a connected second opening 115.

[0222] It should be noted that FIG. 15 and FIG. 22 In order to facilitate the observation of the shape and position of the "deep hole", other layer structures of the stack structure 200' (refer to FIG. 19 , such as the gate sacrificial layer 230 (refer to FIG. 19 ), are omitted.

[0223] In addition, as shown in FIG. 22 , after the formation of the first gap 113 and the second gap 114, other manufacturing processes can be performed to remove the hole groove sacrificial layer in the first opening 102, the first channel hole 104, the second channel hole 105, and the third channel hole 106, such as dry etching process or combination of dry and wet etching process; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to facilitate the formation of subsequent steps.

[0224] Step S13

[0225] FIG. 23 is a top view schematic diagram of the structure after the formation of the first spacing structure 431 according to an embodiment of the present application. FIG. 24 is a cross-sectional view schematic diagram of the first spacing structure 431 according to an embodiment of the present application. FIG. 25 is a top view schematic diagram of the structure after the formation of the isolation gap 116 according to an embodiment of the present application. FIG. 26 is a cross-sectional view schematic diagram of the structure after the formation of the second spacing structure 432 according to an embodiment of the present application. FIG. 27 is a top view schematic diagram of the structure after the formation of the second spacing structure 432 according to an embodiment of the present application.

[0226] like FIG. 22 to FIG. 27 As shown, step S13 of forming a first spacing structure between the first gap and the second gap and a second spacing structure disposed around the first spacing structure may for example include: forming the first spacing structure between the first gap and the second gap; and forming the second spacing structure.

[0227] Specifically, if FIG. 22 to FIG. 24 As shown, in some embodiments of the present application, after forming the channel hole and the first opening 102, wherein the channel hole includes the first channel hole 104, the second channel hole 105 and the third channel hole 106, forming the first spacing structure 431 may include: forming a functional layer 301 in the channel hole and the first opening 102, and forming a channel layer 302 on the surface of the functional layer 301, wherein the functional layer 301 and the channel layer 302 fill the portion in the first opening 102 to form a first spacing structure 431.

[0228] In other words, in order to simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device, the first spacer structure 431 can be formed in the same process as the first channel structure 310, the second channel structure 320 and the third channel structure (hereinafter referred to as the first channel structure 310, the second channel structure 320 and the third channel structure). Specifically, the functional layer 301 of the channel structure and the first layer 401 of the first spacer structure 431 can be prepared using the same material, and the functional layer 301 and the first layer 401 can both include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 301 and the first layer 401 can also have a structure different from the ONO configuration. In addition, the channel layer 302 and the second layer 402 can both be prepared from semiconductor materials such as polycrystalline silicon or single crystal silicon, and can have conductive impurities. In addition, the trench structure may further include a trench filling dielectric layer 303 , and the first spacer structure 431 may further include a third layer 403 . The trench filling dielectric layer 303 and the third layer 403 may include insulating dielectric material layers such as a silicon oxide layer.

[0229] like FIG. 23 、 FIG. 25 to FIG. 27 As shown, after forming the connected second opening 115, in some embodiments of the present application, forming the second spacing structure 432 may include: removing part of the gate sacrificial layer 230 through the connected second opening 115 to form an isolation gap 116; and filling the connected second opening 115 and the isolation gap 116 with an insulating dielectric material to form a second spacing structure 432.

[0230] In the subsequent process of forming the gate layer by using the later gate process, part of the gate sacrificial layer 230 can be removed by using a process such as wet etching, wherein the etchant and chemical precursor can be in contact with the gate sacrificial layer 230 through the first gate line gap 113 and the second gate line gap 114, and then part of the gate sacrificial layer 230 is removed to form the gate layer. In this process, the first spacer structure 431 and the second spacer structure 432 can separate the first gap 113 from the second gap 114, so that part of the gate sacrificial layer 230 can be removed by using the first gap 113 and the second gap 114 respectively. For example, when part of the gate sacrificial layer 230 is removed by using the first gap 113, the etchant in the first gap 113 cannot flow into the second gap 114 or other structures formed in the semiconductor intermediate body through the second gap 114, because the first gap 113 and the second gap 114 are separated by the first spacer structure 431 and the second spacer structure 432. Similarly, when part of the gate sacrificial layer 230 is removed by using the second gap 114, the etchant in the second gap 114 cannot flow into the first gap 113 or other structures formed in the semiconductor intermediate body through the first gap 113, because the first gap 113 and the second gap 114 are separated by the first spacer structure 431 and the second spacer structure 432. This realizes the step-by-step removal of part of the gate sacrificial layer 230 by using the first gap 113 and the second gap 114, reduces the damage to other structures formed in the semiconductor intermediate body, and improves the overall performance of the semiconductor device finally formed.

[0231] In addition, the extension size D of the second spacer structure 431 in the direction intersecting the z direction can satisfy: 400nm≤D≤1500nm. By reasonably controlling the extension length of the second spacer structure, the length of the effective storage area in the semiconductor device finally formed can be relatively improved, and the storage capacity of the semiconductor device can be improved.

[0232] Specifically, as shown in FIG. 23 and FIG. 25 , part of the gate sacrificial layer 230 adjacent to the connected second opening 115 can be removed by using a process such as dry etching or a combination of dry etching and wet etching, and other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. to form the isolation gap 116.

[0233] Then, as shown in FIG. 25 to FIG. 27 , the insulating medium material can be filled in the connected second opening 115 and the isolation gap 116 by using one or more thin film deposition processes to form the second spacer structure 432.

[0234] The second spacer structure 432 includes a plurality of spacer layers 4321, where the spacer layers 4321 can be alternatively stacked along the z direction with the first dielectric layers 210 and co-located with the gate sacrificial layers 230. Optionally, the spacer layers 4321 can include any suitable insulating dielectric material. For example, the spacer layers 4321 include layers of insulating dielectric material such as silicon oxide layers. Alternatively, the spacer layers 4321 can include the same layers of insulating dielectric material as the first dielectric layers 210, in which case, since the spacer layers 4321 are formed from the insulating dielectric material filling the isolation voids 116, which is different from the formation process of the first dielectric layers 210, there can still be a boundary between the spacer layers 4321 and the first dielectric layers 210. Further, the second spacer structure 432 also includes spacer columns 4322 extending along the z direction and including the same insulating dielectric material as the spacer layers 4321.

[0235] Step S14

[0236] FIG. 28 is a top-down schematic view of a structure after forming the first sacrificial layers 117 according to an embodiment of the application. FIG. 29 is a top-down schematic view of a structure after forming the second sacrificial layers 118 according to an embodiment of the application. FIG. 30 is a top-down schematic view of a structure after exposing the second gaps 114 according to an embodiment of the application. FIG. 31 is a top-down schematic view of a structure after forming the second voids 1181 according to an embodiment of the application.

[0237] Referring to FIG. 1 , FIG. 27 to FIG. 31 The step S14 of removing portions of the gate sacrificial layers 230 via the first gaps 113 and the second gaps 114 to form the gate layers 220 can include, for example: filling the second gaps 114 with the first sacrificial layers 117, removing portions of the gate sacrificial layers 230 via the first gaps 113 to form the first voids 1171; filling the first voids 1171 and the first gaps 113 with the second sacrificial layers 118; removing the first sacrificial layers 117 and removing portions of the gate sacrificial layers 230 via the second gaps 114 to form the second voids 1181 in communication with the first voids 1171; and removing the second sacrificial layers 118 and forming the gate layers 220 in the first voids 1171 and the second voids 1181.

[0238] In particular, as FIG. 27 to FIG. 28As shown, the first sacrificial layer 117 can be filled in the second gap 114 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Optionally, the first sacrificial layer 117 may include a semiconductor material layer such as polysilicon, or a carbon-containing material layer. The first sacrificial layer 117 can be formed of a material with a high deposition rate to facilitate rapid filling of the aforementioned multiple "deep holes", and the hole groove sacrificial layer should be relatively thin relative to the first dielectric layer 210 (such as FIG. 26 As shown) and the gate sacrificial layer 230 have any material with high dry etching selectivity to facilitate removal in subsequent steps.

[0239] After forming the first sacrificial layer 117, a process such as wet etching can be used to remove a portion of the gate sacrificial layer 230 to form a first gap 1171. The gate sacrificial layer 230 may include a portion located in the array region 01 of the stacked structure 200' and a portion located in the connection region 02 of the stacked structure 200'. Optionally, the portion of the gate sacrificial layer 230 located in the array region 01 of the stacked structure 200' can be removed via the first gap 113. In addition, due to the influence of the first spacing structure 431 and the second spacing structure 432 located between the first gap 113 and the second gap 114, the gap wall of the first gap 1171 facing the connection region 02 of the stacked structure 200' includes a curved surface, wherein the curved surface includes at least one of a concave surface and a convex surface.

[0240] like FIG. 28 to FIG. 29 As shown, after forming the first void 1171, a second sacrificial layer 118 may be filled in the first void 1171 and the first gap 113 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Optionally, the second sacrificial layer 118 may include a semiconductor material layer such as polysilicon, or a carbon-containing material layer. The second sacrificial layer 118 may be formed of a material with a high deposition rate to facilitate rapid filling of the aforementioned multiple "deep holes", and the hole groove sacrificial layer should be relatively thin relative to the first dielectric layer 210 (such as FIG. 26 As shown in FIG, the second sacrificial layer 118 and the gate sacrificial layer 230 may be made of any material having a high dry etching selectivity to facilitate removal in subsequent steps.

[0241] like FIG. 29 to FIG. 30 As shown, the first sacrificial layer 117 can be removed to expose the second gap 114 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0242] like FIG. 30 to FIG. 31As shown, a portion of the gate sacrificial layer 230 can be removed by a process such as wet etching to form a second void 1181 in communication with the first void 1171. Alternatively, a portion of the gate sacrificial layer 230 located at the connection region 02 of the stack structure 200' can be removed by the second gap 114. In addition, since the surfaces of the sidewalls of the stack structure 200' in contact with the first gap 113 and the second gap 114 each include a curved surface, a portion of the void wall of the first void 1171 and the second void 1181 each includes a curved surface, wherein the curved surface includes at least one of a concave surface and a convex surface.

[0243] As shown in FIG. 1C, after the first void 1171 and the second void 1181 are formed, a gate layer 220 can be formed in the first void 1171 and the second void 1181 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate layer 220 can include a conductive material such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. FIG. 1 FIG. 31 As shown in FIG. 1C, after the first void 1171 and the second void 1181 are formed, a gate layer 220 can be formed in the first void 1171 and the second void 1181 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate layer 220 can include a conductive material such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

[0244] In addition, the method 2000 of fabricating a semiconductor device according to an embodiment of the present application further includes forming an isolation dielectric layer (not shown) on the inner walls of the first void 1171 and the second void 1181 and on the inner sidewalls of the first gap 113 and the second gap 114 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Alternatively, the isolation dielectric layer can be a high dielectric constant dielectric layer. In addition, an adhesion layer (not shown) can be formed between the first dielectric layer 210 and the gate layer 220 or between the isolation dielectric layer and the gate layer 220 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, the adhesion layer can be a titanium nitride (TiN) layer.

[0245] In addition, in combination with FIG. 1 , FIG. 4 and FIG. 31 ​In some embodiments of the present application, after the gate layer 220 is formed, the gate line isolation structure 400 can also be formed by filling the first gap 113 and the second gap 114. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to sequentially fill the gate line isolation layer 112 and the gate line filling layer 111 in the first gap 113 and the second gap 114, respectively, to form the gate line isolation structure 400. The gate line filling layer 111 can be made of an insulating medium material such as silicon oxide, silicon nitride, and silicon oxynitride, or a semiconductor material such as polysilicon, without limitation. After the gate line isolation structure 400 and the gate layer 220 are formed in the stack structure 200', the stack structure 200' is formed into a layered structure 200.

[0246] In addition, it should be noted that FIG. 1 The cross-sectional shape of the gate layer 220 in the x-y plane is not the same as that of the gate line isolation structure 400. FIG. 31 The cross-sectional shape of the first gap 1171 and the second gap 1181 in the x-y plane is not the same, where the x-y plane is a plane intersecting the z direction. In other words, the gate layer formed by the first gap 1171 and the second gap 1181 is not the same as that of the gate line isolation structure 400. FIG. 1 The cross-sectional shape of the gate layer 220 in the x-y plane is not the same. As an option, the cross-sectional shape of the first gap 1171 and the second gap 1181 in the x-y plane can be selected according to different settings of the architecture of the semiconductor device to be finally formed, so as to effectively reduce the extension size of the gate layer, reduce the bulk resistance of the gate layer, and improve the integration of the semiconductor device while achieving the control of the channel structure 300 by the external circuit.

[0247] Thus, the method for manufacturing a semiconductor device according to at least one embodiment of the present application provides a semiconductor device including a stack structure, a gate line isolation structure, a first spacer structure, and a second spacer structure, wherein the first spacer structure and the second spacer structure divide the gate line isolation structure into a first part and a second part which are spaced apart in an extension direction of the gate line isolation structure. The gate electrode layer of the stack structure can be manufactured by a gate-last process, for example, by pre-forming a gate electrode sacrificial layer, and in the process of removing the gate electrode sacrificial layer by using a process such as wet etching, the etchant and chemical precursors are allowed to contact the gate electrode sacrificial layer by means of the gate line gaps, for example, the first gate line gap and the second gate line gap, generated when the gate line isolation structure is formed, and thus part of the gate electrode sacrificial layer is removed to form the gate electrode layer. The first spacer structure and the second spacer structure divide the gate line isolation structure into the first part and the second part; likewise, the first spacer structure and the second spacer structure divide the first gap and the second gap in the process of manufacturing the semiconductor device, which can reduce the situation that the excess etchant flows into other structures which have been formed in the semiconductor intermediate body through the gate line gaps in the process of removing the gate electrode sacrificial layer by using the gate-last process in the process of manufacturing the semiconductor device, and thus the overall performance of the semiconductor device is improved.

[0248] In addition, the semiconductor device further includes a channel structure, and the second spacer structure is arranged around the first spacer structure, which can improve the stress of the stack structure in the part where the first spacer structure and the second spacer structure are located, reduce the situation that the morphology of the plurality of channel structures corresponding to the first spacer structure and the second spacer structure deviates, and thus the uniformity of the plurality of channel structures is improved, and the overall performance of the semiconductor device is improved.

[0249] FIG. 32 The flow chart of the method 2000 for manufacturing a semiconductor device according to another embodiment of the present application is shown. FIG. 33 to FIG. 41 The process schematic diagrams of the method 2000 for manufacturing a semiconductor device according to another embodiment of the present application are shown.

[0250] As shown in FIG. 32 the method 2000 for manufacturing a semiconductor device can include:

[0251] S21, alternately stacking a gate electrode sacrificial layer and a first dielectric layer in a first direction to form a stack structure.

[0252] S22, forming a first channel structure and a second channel structure which extend in the stack structure in the first direction, wherein the size of the second channel structure is greater than the size of the first channel structure in a direction intersecting the first direction.

[0253] S23, forming a first gap and a second gap which are spaced apart in the stack structure, wherein the first gap and the second gap both extend in a second direction intersecting the first direction.

[0254] S24, forming a spacer structure between the first gap and the second gap, wherein the spacer structure and the plurality of second trench structures are distributed along a third direction, the third direction being perpendicular to the first direction and the second direction.

[0255] S25, removing part of the gate sacrificial layer via the first gap and the second gap to form a gate layer.

[0256] Since the content involved in the semiconductor device preparation method 2000 described in the above embodiment of one aspect of the present application can be completely or partially applicable to the semiconductor device preparation method described in the embodiment of another aspect of the present application, the related or similar content will not be repeated. However, it is understood by those skilled in the art that the semiconductor device 1000 (as shown in FIG. 1 to FIG. 6 ) can be formed according to the semiconductor device preparation method 2000 described in the embodiment of one aspect of the present application, and the semiconductor device 1000 (as shown in FIG. 7 to FIG. 13 ) can also be formed according to the semiconductor device preparation method 2000 described in the embodiment of another aspect of the present application. Based on this, the semiconductor device preparation method 2000 described in the embodiment of one aspect of the present application and the semiconductor device preparation method 2000 described in the embodiment of another aspect of the present application both have the same beneficial effects as the semiconductor structure 1000, which will not be repeated here.

[0257] The following will combine FIG. 33 to FIG. 41 to specifically explain the specific process of each step of the above preparation method 2000 in the embodiments of the present application.

[0258] Step S22

[0259] FIG. 33 is a top view schematic diagram of the structure after forming the first channel hole 104 according to an embodiment of the present application. FIG. 34 is a cross-sectional view schematic diagram of the structure after forming the first channel hole 104 according to an embodiment of the present application. FIG. 35 is a cross-sectional view schematic diagram of the first channel structure 310 and the second channel structure 320 according to an embodiment of the present application.

[0260] As FIG. 33 to FIG. 35As shown, the forming, S22, of the first and second trench structures extending in the first direction in the stack structure, wherein the size of the second trench structure is greater than the size of the first trench structure in a direction intersecting the first direction, can comprise: forming the first and second trench holes 104, 105, wherein the first and second trench holes 104, 105 each extend in the z direction in the stack structure 200', and the size m2 of the second trench hole 105 is greater than the size ml of the first trench hole 104 in a direction intersecting the z direction (e.g., the x direction, the y direction); and forming the functional layer 301 in the first and second trench holes 104, 105, respectively, and forming the trench layer 302 on the surface of the functional layer 301.

[0261] Alternatively, the method 2000 of fabricating the semiconductor device can comprise forming the gate line gap in steps. For example, the first holes 101 can be formed first, and then the plurality of first holes 101 can be connected to form the gate line gap by a "hole expansion" process. The gate line gap can accommodate a gate line isolation structure in the semiconductor device.

[0262] Optionally, the first holes 101 can be formed together with "deep holes" for fabricating other structures in the semiconductor device 1000. For example, the first holes 101 can be formed in the same process as the first and second trench holes 104, 105.

[0263] Specifically, the first holes 101, the first and second trench holes 104, 105 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; and further, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., can be performed to remove portions of the stack structure 200' to form the first holes 101, the first and second trench holes 104, 105.

[0264] The plurality of first holes 101 can extend through the stack structure 200' in the z direction, wherein the plurality of first holes 101 can be spaced apart in the second direction (x direction). The plurality of first trench holes 104 can extend through the stack structure 200' in the z direction, wherein the plurality of first trench holes 104 can be spaced apart in the second direction (x direction) and can be spaced apart in the third direction (y direction). The plurality of second trench holes 105 can extend through the stack structure 200' in the z direction, wherein the plurality of second trench holes 105 can be spaced apart in the second direction (x direction) and can be spaced apart in the third direction (y direction).

[0265] Further, the semiconductor device can further comprise a third trench structure, and thus the first holes 101 can be formed in the same process as the first, second, and third trench holes 104, 105, 106, wherein the third trench structure is formed in the third trench hole 106.

[0266] Optionally, the size m2 of the second trench hole 105 in the direction intersecting the z direction (e.g., x direction, y direction) can be equal to the size of the first hole 101. Optionally, the size of the third trench hole 106 in the direction intersecting the z direction (e.g., x direction, y direction) can be greater than or equal to the size m2 of the second trench hole 105.

[0267] Optionally, the stacked structure 200' can include an array region 01 and a connection region 02 adjacently distributed in the x direction, wherein the array region 01 can include a first sub-region 011 and a second sub-region 012 adjacently distributed in the x direction, the first sub-region 011 being closer to the connection region 02 than the second sub-region 012. The plurality of first trench holes 104 can be located in the second sub-region 012; the plurality of second trench holes 105 can be located in the first sub-region 011; and the plurality of third trench holes 106 can be located in the connection region 02.

[0268] Optionally, the first hole 101, the first trench hole 104 and the second trench hole 105 can have the same extension size in the z direction, so as to simplify the process difficulty in preparing the plurality of "deep holes".

[0269] By forming the plurality of holes for different structures of the semiconductor device, such as the first trench hole, the second trench hole and the first hole, in the same process, the number of etching processes used to form the high aspect ratio structure can be effectively reduced, thereby reducing the difficulty in preparing the semiconductor device and reducing the cost of preparing the semiconductor device.

[0270] In addition, the plurality of holes for different structures of the semiconductor device are formed in the same process, and can also be prepared using the same photolithography mask, which can improve the overlay accuracy of the etching process, reduce the overlay error, and enable the finally formed semiconductor device to have relatively high overall performance.

[0271] Step S23

[0272] FIG. 36 is a top view schematic diagram of a structure after forming the first gap 113 and the second gap 114 according to an embodiment of the present application.

[0273] As shown in FIG. 33 , FIG. 34 and FIG. 36 , S23 can include: after forming the plurality of first holes 101, removing at least the portion of the stacked structure 200' located between the first holes 101 adjacently distributed in the x direction, to form the first gap 113 and the second gap 114.

[0274] Specifically, the via-sacrifice layer can be filled in the first via-hole 104, the second via-hole 105, and the third via-hole 106 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The via-sacrifice layer can include a carbon-containing material layer. The via-sacrifice layer can be formed of a material with a high deposition rate to facilitate fast filling of the above-mentioned "deep holes", and should be any material with high dry etching selectivity with respect to the first dielectric layer 210 and the gate-sacrifice layer 230 to facilitate removal in subsequent steps.

[0275] Thereafter, the first via 101 can be "enlarged" to make the plurality of first vias 101 communicate with each other to form the first gap 113 and the second gap 114 by, for example, a dry etching process or a combination of dry and wet etching processes; other fabrication processes such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. can also be performed.

[0276] Step S24

[0277] FIG. 37 is a top view schematic diagram of a structure after forming the second opening 115 according to an embodiment of the present application. FIG. 38 is a top view schematic diagram of a structure after forming the isolation void 116 according to an embodiment of the present application. FIG. 39 is a cross-sectional view schematic diagram of the spacer structure 430 according to an embodiment of the present application.

[0278] As shown in FIG. 33 , FIG. 36 to FIG. 39 , the step S24 forms a spacer structure between the first gap and the second gap, wherein the spacer structure and the plurality of second channel structures are distributed along a third direction, the third direction intersects with both the first direction and the second direction, which can include: forming the second opening 115 between the first gap 113 and the second gap 114; removing part of the gate-sacrifice layer 230 via the second opening 115 to form the isolation void 116; and filling the second opening 115 and the isolation void 116 with an insulating dielectric material to form the spacer structure 430.

[0279] Specifically, as shown in FIG. 33 and FIG. 36 , in some embodiments of the present application, forming the second opening 115 can include: forming the second via 103 through the stack structure 200' along the z direction, wherein the plurality of second vias 103 are spaced apart along the x direction, and removing at least part of the stack structure 200' between the second vias 103 adjacent in the x direction to form the second opening 115.

[0280] As an option, the second holes 103 can be formed in the same process as the first holes 101, the first trench holes 104, the second trench holes 105, and the third trench holes 106, in which the third trench structures are formed in the third trench holes 106.

[0281] The portion of the stack structure 200’ can be removed to form the plurality of second holes 103 by, for example, a dry etching process or a combination of dry and wet etching processes; other fabrication processes such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. can also be performed.

[0282] Optionally, as shown in FIG. 33 and FIG. 34 In a direction intersecting the z direction (e.g., the x direction, the y direction), the size of the second holes 103 can be equal to or greater than the size m2 of the second trench holes 105.

[0283] As shown in FIG. 33 to FIG. 36 After the plurality of second holes 103 are formed, at least the portion of the stack structure 200’ between the second holes 103 adjacent in the x direction can be removed to form the second openings 115 by, for example, a dry etching process or a combination of dry and wet etching processes; other fabrication processes such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. can also be performed.

[0284] As shown in FIG. 36 to FIG. 37 After the second openings 115 are formed, the portion of the gate sacrificial layer 230 adjacent to the second openings 115 can be removed to form the isolation gaps 116 by, for example, a dry etching process or a combination of dry and wet etching processes; other fabrication processes such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. can also be performed.

[0285] After the isolation gaps 116 are formed, as shown in FIG. 37 to FIG. 38 The insulating dielectric material can be filled in the connected second openings 115 and the isolation gaps 116 to form the spacer structures 430 by one or more thin film deposition processes.

[0286] As shown in FIG. 38 to FIG. 39 The spacer structures 430 include a plurality of isolation layers 4321, in which the isolation layers 4321 can be alternately stacked along the z direction with the first dielectric layers 210 and disposed in the same layer as the gate sacrificial layer 230. Optionally, the material of the isolation layers 4321 can include any suitable insulating dielectric material. For example, the isolation layers 4321 include a layer of insulating dielectric material such as a silicon oxide layer. As an option, the isolation layers 4321 can include the same layer of insulating dielectric material as the first dielectric layers 210, in which case there is still a boundary between the isolation layers 4321 and the first dielectric layers 210 due to the different formation processes of the isolation layers 4321 and the first dielectric layers 210.

[0287] In addition, the spacer structure 430 further comprises an isolation pillar 4322 extending along the z direction and comprising the same insulating dielectric material as the isolation layer 4321. Optionally, the isolation pillar 4322 is located at one side of the second channel structure 320 in the y direction. The isolation pillar 4322 is formed by filling the second opening 115 (as shown in FIG. 37 ).

[0288] FIG. 40 is a top view schematic diagram of a structure after forming the first opening 102 according to yet another embodiment of the present application. FIG. 41 is a top view schematic diagram of a structure after forming the spacer structure 430 according to yet another embodiment of the present application.

[0289] As shown in FIG. 10 , FIG. 40 and FIG. 41 , in some embodiments of the present application, the spacer structure 430 of the final formed semiconductor device 1000 comprises a first spacer structure 431 and a second spacer structure 432. In this embodiment, the plurality of second channel structures 320 and the spacer structure 430 are distributed along the y direction, and the size d2 of the second channel structure 320 can be greater than the size d1 of the first channel structure 310, and in addition, the second spacer structure 432 can be arranged around the first spacer structure 431.

[0290] As shown in FIG. 40 and FIG. 41 , in order to form the first spacer structure 431, the first opening 102 for accommodating the first spacer structure 431 can be formed in the process of forming the first hole 101. For example, the first opening 102 can be formed in the same process as the first hole 101, the second hole 103, the first channel hole 104, the second channel hole 105, and the third channel hole 106.

[0291] Optionally, as shown in FIG. 34 and FIG. 40 , in the direction intersecting the z direction (for example, the x direction, the y direction), the size of the first opening 102 can be equal to or greater than the size m2 of the second channel hole 105.

[0292] As shown in FIG. 35 , FIG. 40 and FIG. 41 , after forming the first opening 102, the first spacer structure 431 can be formed in the process of forming the first channel structure 310. For example, the functional layer 301 is formed in the first channel hole 104 and the first opening 102, and the channel layer 302 is formed on the surface of the functional layer 301, wherein the part of the functional layer 301 and the channel layer 302 filled in the first opening 102 is formed as the first spacer structure 431.

[0293] In other words, in order to simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device, the first spacer structure 431 can be formed in the same process as the first channel structure 310, the second channel structure 320 and the third channel structure (hereinafter, the first channel structure 310, the second channel structure 320 and the third channel structure are collectively referred to as channel structures). Specifically, the functional layer 301 of the channel structure and the first layer 401 of the first spacer structure 431 can be made of the same material, and both the functional layer 301 and the first layer 401 can include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 301 and the first layer 401 can also have structures different from the ONO configuration. In addition, the channel layer 302 and the second layer 402 can be made of a semiconductor material such as polysilicon or monocrystalline silicon, and can have conductive impurities. In addition, the channel structure can also include a channel filling medium layer 303, and the first spacer structure 431 can also include a third layer 403, and the channel filling medium layer 303 and the third layer 403 can include an insulating medium material layer such as a silicon oxide layer.

[0294] Thus, the manufacturing method of the semiconductor device provided according to at least one embodiment of the present application, the semiconductor device includes a stack structure, a gate line isolation structure, a channel structure and a spacer structure, wherein the channel structure includes a first channel structure and a second channel structure, and the spacer structure divides the gate line isolation structure into a first part and a second part which are spaced apart in the extension direction of the gate line isolation structure. This can reduce the case that the excess etching liquid flows into the other structures which have been formed in the semiconductor intermediate body through the gate line gap in the process of removing the gate electrode sacrificial layer by using the back gate process in the manufacturing of the semiconductor device, thereby improving the overall performance of the semiconductor device.

[0295] In addition, the spacer structure and the plurality of second channel structures are distributed along a direction intersecting both the stacking direction of the stack structure and the extension direction of the gate line isolation structure, and the size of the second channel structure is set to be greater than the size of the first channel structure in the direction intersecting the stacking direction, which can improve the stress of the stack structure in the part where the spacer structure is located, reduce the case of morphology deviation of the channel structure, thereby improving the uniformity of the plurality of channel structures and improving the overall performance of the semiconductor device.

[0296] FIG. 42 is a structural schematic diagram of a memory system 30000 according to an embodiment of the present application.

[0297] As FIG. 42As illustrated, at least one embodiment of another aspect of the present application further provides a memory system 30000. The memory system 30000 can include the semiconductor device 20000 and a controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the embodiments above, and the present application will not repeat the same. The semiconductor device 20000 can be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device, and the following will be described taking a three-dimensional semiconductor device as an example.

[0298] As an option, the three-dimensional semiconductor device can include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0299] The memory system 30000 can include the semiconductor device 20000 and the controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the embodiments above, and the present application will not repeat the same. The controller 32000 can control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 can perform an operation based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 can receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 can perform an internal operation corresponding to the command on the region selected by the address.

[0300] In some embodiments, the three-dimensional memory system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of an RS-MMC and a micro-SD, a secure digital card in the form of an SD, a mini-SD and a micro-SD, a storage device of a personal computer memory card international association (PCMCIA) card type, a storage device of a peripheral component interconnect (PCI) type, a storage device of a high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The memory system provided by the present application has the same beneficial effects as the semiconductor device provided by the present application due to the provision of the semiconductor device provided by the present application, and the same will not be repeated here.

[0301] Although the exemplary preparation method and structure of the semiconductor device are described herein, it can be understood that one or more features can be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of the example layers are only exemplary.

[0302] The above description is only the preferred embodiment of the present application and the explanation of the technical principles. It should be understood by those skilled in the art that the protective scope of the present application is not limited to the technical solutions formed by the selected combinations of the above technical features, and also covers other technical solutions formed by the combinations of the above technical features or their equivalent features without departing from the technical concepts. For example, the technical solutions formed by the mutual replacement of the above features and the technical features disclosed in the present application (but not limited to) with similar functions.

Claims

1. A semiconductor device, characterized by, Comprising: a stack structure comprising gate layers and first dielectric layers alternately stacked along a first direction; a gate line isolation structure extending in the stack structure along a second direction intersecting the first direction, and comprising first and second subparts spaced apart along the second direction, wherein the semiconductor device further comprises first and second spacer structures, each of the first and second spacer structures being located between the first and second subparts, and the second spacer structure being disposed around the first spacer structure.

2. The semiconductor device of claim 1, wherein, the semiconductor device further comprises a channel structure extending in the stack structure along the first direction, wherein the channel structure comprises a functional layer and a channel layer located at a surface of the functional layer; and the first spacer structure and the channel structure comprise a same layer structure.

3. The semiconductor device of claim 1, wherein, the second spacer structure comprises a plurality of spacer layers, wherein the spacer layers and the first dielectric layers are alternately stacked along the first direction, and are disposed in a same layer as the gate layers.

4. The semiconductor device of claim 3, wherein, the second spacer structure further comprises a spacer pillar, wherein the spacer pillar extends along the first direction, and comprises a same insulating dielectric material as the spacer layers.

5. The semiconductor device of claim 1, wherein, the first spacer structure comprises first and second separation structures, wherein the first separation structure is closer to the first subpart relative to the second separation structure along the second direction; and the second separation structure is closer to the second subpart relative to the first separation structure along the second direction.

6. The semiconductor device of claim 1, wherein, a dimension of the first spacer structure along the second direction is greater than a dimension of the first spacer structure along a third direction, wherein the third direction intersects the first and second directions.

7. The semiconductor device of claim 1, wherein, the first spacer structure comprises a plurality of pillar structures spaced apart from each other along the second direction.

8. The semiconductor device of claim 1, wherein, at least one surface of the gate line isolation structure comprises a curved surface, the curved surface comprising at least one of a concave surface and a convex surface.

9. The semiconductor device of claim 1, wherein, the stack structure comprises an array region and a connection region arranged along the second direction; and the gate layers comprise first portions located at the array region and second portions located at the connection region, wherein a surface of the first portions facing the connection region comprises a curved surface, the curved surface comprising at least one of a concave surface and a convex surface.

10. The semiconductor device of claim 1, wherein, the stack structure further comprises second dielectric layers disposed in a same layer as the gate layers, wherein the first and second dielectric layers comprise different insulating dielectric materials.

11. The semiconductor device of claim 1, wherein, The first sub-section or the second sub-section has a dimension in a third direction that is less than or equal to a dimension of the first spacer structure in the third direction, wherein the third direction intersects the first direction and the second direction.

12. The semiconductor device of claim 2, wherein, An extension dimension D of the second spacer structure in a direction intersecting the first direction satisfies: 400 nm ≤ D ≤ 1500 nm.

13. The semiconductor device of any one of claims 1-12, wherein, The stack structure includes an array region and a connection region arranged along the second direction, wherein the first spacer structure and the second spacer structure are both located in a first sub-region of the array region close to the connection region.

14. A semiconductor device, characterized by comprising: including: a stack structure including gate layers and first dielectric layers alternately stacked along a first direction; first channel structures and second channel structures both extending in the stack structure along the first direction; gate line isolation structures extending in the stack structure along a second direction intersecting the first direction and including first sub-sections and second sub-sections spaced apart from each other; spacer structures located between the first sub-sections and the second sub-sections, wherein the spacer structures and the second channel structures are distributed along a third direction intersecting the first direction and the second direction; and in a direction intersecting the first direction, a dimension of the second channel structures is greater than a dimension of the first channel structures.

15. The semiconductor device of claim 14, wherein, a portion of the second channel structures is located on one side of the spacer structure along the third direction, and another portion of the second channel structures is located in the spacer structure.

16. The semiconductor device of claim 14, wherein, An extension dimension D of the spacer structure in a direction intersecting the first direction satisfies: 400 nm ≤ D ≤ 1500 nm.

17. The semiconductor device of claim 14, wherein, The spacer structure includes a plurality of spacer layers, wherein the spacer layers are alternately stacked along the first direction with the first dielectric layers and are disposed in the same layer as the gate layers.

18. The semiconductor device of claim 17, wherein, The spacer structure further includes spacer columns, wherein the spacer columns extend along the first direction and include the same insulating dielectric material as the spacer layers.

19. The semiconductor device of claim 14, wherein, in a direction intersecting the first direction, a dimension d1 of the first channel structures and a dimension d2 of the second channel satisfy: 1.1d1 ≤ d2.

20. The semiconductor device of claim 14, wherein, in a direction intersecting the first direction, a dimension d2 of the second channel satisfies: 110 nm < d2 ≤ 150 nm.

21. The semiconductor device of claim 14, wherein, The first sub-section has a dimension in a third direction that is less than or equal to a dimension of the second sub-section in the third direction, wherein the third direction intersects the first direction and the second direction. ​ 22. The semiconductor device of claim 21, wherein, a size bl of the first sub-section in the third direction and a size b2 of the second sub-section in the third direction satisfy: 1.1bl≤b2.

23. The semiconductor device of claim 14, wherein, a size b2 of the second sub-section in the third direction satisfies: 300nm < b2≤900nm.

24. The semiconductor device of claim 14, wherein, the stack structure includes an array region and a connection region distributed along a second direction intersecting the first direction; and the gate layer includes a first portion located at the array region and a second portion located at the connection region, wherein a surface of the first portion facing the connection region includes a curved surface, the curved surface including at least one of a concave surface and a convex surface.

25. The semiconductor device of claim 14, wherein, the stack structure further includes a second dielectric layer disposed in a same layer as the gate layer, wherein the first dielectric layer and the second dielectric layer include different insulating dielectric materials.

26. The semiconductor device of claim 14, wherein, the spacer structure includes a first spacer structure and a second spacer structure disposed around the first spacer structure.

27. The semiconductor device of claim 26, wherein, the first spacer structure includes a first separation structure and a second separation structure, wherein the first separation structure is closer to the first sub-section than the second separation structure along the second direction; and the second separation structure is closer to the second sub-section than the first separation structure along the second direction.

28. The semiconductor device of claim 26, wherein, a size of the first spacer structure along the second direction is greater than a size of the first spacer structure along a third direction, wherein the third direction intersects the first direction and the second direction.

29. The semiconductor device of claim 26, wherein, the first channel structure and the second channel structure each include a functional layer and a channel layer located at a surface of the functional layer; and the first spacer structure and the channel structure include a same layer structure.

30. The semiconductor device of claim 14, wherein, at least one surface of the gate line isolation structure includes a curved surface, the curved surface including at least one of a concave surface and a convex surface.

31. A method of fabricating a semiconductor device, comprising: including: alternately stacking gate sacrificial layers and first dielectric layers along a first direction to form a stack structure; forming a first gap and a second gap spaced apart from each other in the stack structure, the first gap and the second gap each extending along a second direction intersecting the first direction; forming a first spacer structure between the first gap and the second gap and a second spacer structure disposed around the first spacer structure; and removing portions of the gate sacrificial layers via the first gap and the second gap to form a gate layer. forming the second spacer structure includes:

32. The method of claim 31, wherein, ​ a first opening and a second opening are formed between the first gap and the second gap, wherein the first opening and the second opening are spaced apart along the second direction; part of the gate sacrificial layer is removed via the second opening, forming an isolation gap; and an insulating medium material is filled into the second opening and the isolation gap, forming the second spacing structure.

33. The method of claim 32, wherein, The semiconductor device further comprises a channel structure, and the method further comprises: a channel hole extending in the stack structure along the first direction and the first opening are formed; and a functional layer is formed in the channel hole and the first opening, and a channel layer is formed on a surface of the functional layer, wherein the functional layer and the channel layer fill part of the first opening, forming the first spacing structure.

34. The method of claim 32, wherein, the first opening comprises at least one of a hole extending along the first direction and a slot extending along the second direction.

35. The method of claim 31, wherein, forming the first gap and the second gap comprises: forming first holes extending through the stack structure along the first direction, wherein a plurality of the first holes are spaced apart along the second direction; and at least removing portions of the stack structure between first holes adjacent in the second direction, forming the first gap and the second gap.

36. The method of claim 35, wherein, The semiconductor device further comprises a channel structure, and forming the channel structure comprises: forming a channel hole extending in the stack structure along the first direction; and a functional layer is formed in the channel hole, and a channel layer is formed on a surface of the functional layer, wherein the channel hole is formed in a process of forming the first hole.

37. The method of claim 31, wherein, removing part of the gate sacrificial layer via the first gap and the second gap, forming a gate layer comprises: filling the second gap with a first sacrificial layer; removing part of the gate sacrificial layer via the first gap, forming a first gap; filling the first gap and the first gap with a second sacrificial layer; removing the first sacrificial layer and removing part of the gate sacrificial layer via the second gap, forming a second gap in communication with the first gap; and removing the second sacrificial layer and forming the gate layer in the first gap and the second gap.

38. A method of fabricating a semiconductor device, comprising: comprises: alternately stacking gate sacrificial layers and first dielectric layers along a first direction, forming a stack structure; forming first channel structures and second channel structures extending in the stack structure along the first direction, wherein in a direction intersecting the first direction, a size of the second channel structure is greater than a size of the first channel structure; forming first gaps and second gaps spaced apart from each other in the stack structure, wherein the first gaps and the second gaps both extend along a second direction intersecting the first direction; forming spacing structures between the first gaps and the second gaps, wherein the spacing structures and a plurality of the second channel structures are distributed along a third direction intersecting the first direction and the second direction; and removing part of the gate sacrificial layer via the first gaps and the second gaps, forming a gate layer. forming the first channel structures and the second channel structures comprises:

39. The method of claim 38, wherein, ​ forming first and second channel holes, each of the first and second channel holes extending in the first direction in the stack structure, the second channel hole having a dimension in a direction intersecting the first direction that is greater than a dimension of the first channel hole; and forming a functional layer in the first and second channel holes, respectively, and forming a channel layer on a surface of the functional layer.

40. The method of claim 39, wherein, forming the first and second gaps includes: forming first holes through the stack structure in a first direction, a plurality of the first holes being spaced apart in a second direction; and removing at least portions of the stack structure between first holes adjacent in the second direction, forming the first and second gaps.

41. The method of claim 40, wherein the second channel hole has a dimension in a direction intersecting the first direction that is equal to a dimension of the first hole.

42. The method of claim 40, wherein the first and second channel holes are formed in a process of forming the first holes.

43. The method of claim 38, wherein, forming the spacer structure includes: forming a second opening between the first and second gaps; removing portions of the gate sacrificial layer via the second opening, forming an isolation void; and filling the second opening and the isolation void with an insulating dielectric material, forming the spacer structure.

44. The method of claim 43, wherein, forming the second opening includes: forming second holes through the stack structure in a first direction, a plurality of the second holes being spaced apart in a second direction; and removing at least portions of the stack structure between second holes adjacent in the second direction, forming the second opening.

45. A memory system, comprising: comprising: at least one semiconductor device as claimed in any one of claims 1-13 or 14-30; and a controller coupled to the semiconductor device and configured to control the semiconductor device to store data.

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