Semiconductor device

Abstract

The invention relates to a semiconductor device which prevents reduction of short-circuit tolerance and gate signal delay of the semiconductor device. A semiconductor device is provided with: an emitter electrode (6) disposed on a cell region; a gate wiring (51) disposed on the outside of the emitter electrode (6); and a gate finger wiring (61), one end of which is connected to the gate wiring (51) and which extends over the cell region. Emitter electrodes (6) adjacent to each other with the gate finger wiring (61) interposed therebetween are connected by an emitter electrode connection section (71) disposed in a region between the other end of the gate finger wiring (61) and the gate wiring (51). The semiconductor substrate has formed therein: a first active trench gate (111) that intersects the gate finger wiring (61); and a second active trench gate (112) that leads out the first active trench gate (111) below the emitter electrode connection part (71) to below the gate finger wiring (61).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] A longitudinal semiconductor device is known in which electrodes are provided on the surface side and the back surface side, and current is passed in the longitudinal direction, i.e., the direction in which the surface and the back surface are connected. For example, in Patent Document 1, the electrode on the surface side (hereinafter, referred to as "surface electrode") of the longitudinal semiconductor device is used for a control line, i.e., gate pad, which is divided into a plurality of gate signal transmission lines.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2006-210519

[0004] In the semiconductor device in which the surface electrode is divided into a plurality of gate pads as in Patent Document 1, the current flowing becomes unbalanced, and the short circuit resistance easily decreases. However, if the gate pad is made to be circuitous in a manner in which the surface electrode is not divided, there is a concern that the gate signal is delayed. SUMMARY

[0005] The present application has been made to solve the above-described problems, and has an object to provide a semiconductor device in which the decrease in short circuit resistance and the delay in gate signal can be prevented.

[0006] The semiconductor device of the present application includes: a plurality of active trench gates formed in a cell region of a semiconductor substrate; an emitter electrode disposed on the cell region; a gate wire disposed outside the emitter electrode and electrically connected to the plurality of active trench gates; and a gate finger wire electrically connected to the gate wire and extending on the cell region, one end of the gate finger wire being connected to the gate wire, the other end of the gate finger wire not reaching the gate wire, the emitter electrodes adjacent across the gate finger wire being electrically connected through an emitter electrode junction portion disposed in a region between the other end of the gate finger wire and the gate wire, the active trench gate including: a first active trench gate extending in a first direction intersecting the extending direction of the gate finger wire; and a second active trench gate connected to the first active trench gate below the emitter electrode junction portion, extending in a second direction parallel to the extending direction of the gate finger wire, and being led out below the gate finger wire or the gate wire.

[0007] According to the semiconductor device of the present application, the decrease in short circuit resistance and the delay in gate signal can be prevented. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a plan view of a chip of the semiconductor device of Embodiment 1.

[0009] Figure 2 is a plan view of a chip of the semiconductor device of Embodiment 1.

[0010] Figure 3 is a plan view of an IGBT region of the semiconductor device of Embodiment 1.

[0011] Figure 4 is a sectional view of the IGBT region of the semiconductor device of Embodiment 1.

[0012] Figure 5 is a sectional view of the IGBT region of the semiconductor device of Embodiment 1.

[0013] Figure 6 is a plan view of a diode region of the semiconductor device of Embodiment 1.

[0014] Figure 7 is a sectional view of the diode region of the semiconductor device of Embodiment 1.

[0015] Figure 8 is a sectional view of the diode region of the semiconductor device of Embodiment 1.

[0016] Figure 9 is a sectional view of a boundary between the IGBT region and the diode region of the semiconductor device of Embodiment 1.

[0017] Figure 10 is a plan view of a vicinity of an emitter electrode connection region of the semiconductor device of Embodiment 1.

[0018] Figure 11 is a sectional view of the vicinity of the emitter electrode connection region of the semiconductor device of Embodiment 1.

[0019] Figure 12 is a plan view of a vicinity of an emitter electrode connection region of the semiconductor device of Embodiment 2.

[0020] Figure 13 is a view showing a shape of an emitter electrode connection portion of the semiconductor device of Embodiment 2.

[0021] Figure 14 is a plan view of a vicinity of an emitter electrode connection region of the semiconductor device of Embodiment 3.

[0022] Figure 15 is a plan view of a vicinity of an emitter electrode connection region of the semiconductor device of Embodiment 4.

[0023] Figure 16 is a plan view of a vicinity of an emitter electrode connection region of the semiconductor device of Embodiment 5.

[0024] Figure 17 is a cross-sectional view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 5.

[0025] Figure 18 is a plan view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 6.

[0026] Figure 19 is a cross-sectional view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 6.

[0027] Figure 20 is a plan view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 7.

[0028] Figure 21 is a cross-sectional view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 7.

[0029] Figure 22 is a plan view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 8.

[0030] Figure 23 is a cross-sectional view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 8.

[0031] Figure 24 is a plan view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 9.

[0032] Figure 25 is a plan view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 10.

[0033] Figure 26 is a cross-sectional view of the vicinity of an emitter electrode junction region of the semiconductor device of Embodiment 11.

[0034] Figure 27 is a plan view of a chip of the semiconductor device of Embodiment 12.

[0035] BRIEF DESCRIPTION OF THE DRAWINGS － 1...n-type drift layer; 2...n-type carrier accumulation layer; 3...n-type buffer layer; 4...interlayer insulating film; 5...barrier metal; 6...emitter electrode; 7...collector; 8...trench; 9...oxide film; 10...IGBT region; 11...active trench gate; 11a...gate trench electrode; 11b...gate trench insulating film; 12...dummy trench gate; 12a...dummy trench electrode; 12b...dummy trench insulating film; 13...n + 1...p-type emitter layer; 2...n-type drift layer; 3...n-type carrier accumulation layer; 4...n-type buffer layer; 5...interlayer insulating film; 6...barrier metal; 7...emitter electrode; 8...collector; 9...oxide film; 10...IGBT region; 11...active trench gate; 11a...gate trench electrode; 11b...gate trench insulating film; 12...dummy trench gate; 12a...dummy trench electrode; 12b...dummy trench insulating film; 13...n +11…p-type emitter layer; 12…p-type contact layer; 15…p-type base layer; 16…p-type collector layer; 16a…p-type termination collector layer; 20…diode region; 21…diode trench gate; 21a…diode trench electrode; 21b…diode trench insulating film; 24…p + 11…p-type emitter layer; 12…p-type contact layer; 15…p-type base layer; 16…p-type collector layer; 16a…p-type termination collector layer; 20…diode region; 21…diode trench gate; 21a…diode trench electrode; 21b…diode trench insulating film; 24…p + 11…p-type emitter layer; 12…p-type contact layer; 15…p-type base layer; 16…p-type collector layer; 16a…p-type termination collector layer; 20…diode region; 21…diode trench gate; 21a…diode trench electrode; 21b…diode trench insulating film; 24…p DETAILED DESCRIPTION

[0036] In the following description, n and p indicate the conduction type of a semiconductor, and the first conduction type is assumed to be n-type and the second conduction type is assumed to be p-type in the present application, but the first conduction type can be assumed to be p-type and the second conduction type can be assumed to be n-type. In addition, n － indicates a concentration lower than that of n, and n + indicates a concentration higher than that of n. Similarly, p － indicates a concentration lower than that of p, and p + indicates a concentration higher than that of p.

[0037] In addition, the height of the impurity concentration of each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak concentration of impurities.

[0038] <Embodiment 1>

[0039] Hereinafter, the structure of the semiconductor device of Embodiment 1 will be described. The semiconductor element provided in the semiconductor device is assumed to be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting IGBT), or the like, but the semiconductor element will be described herein assuming an RC-IGBT.

[0040] Semiconductor elements can be made of either silicon (Si) or wide-bandgap semiconductors such as silicon carbide (SiC). Semiconductor devices using wide-bandgap semiconductors offer superior performance at high voltages, high currents, and high temperatures compared to silicon-based devices. Wide-bandgap semiconductors include not only silicon carbide but also gallium nitride (GaN)-based materials and diamond.

[0041] Figure 1 1 is a top view showing a semiconductor device as an RC-IGBT. Figure 2 It is a top view showing another structure of a semiconductor device serving as an RC-IGBT. Figure 1 The semiconductor device 100 shown is a semiconductor device in which the IGBT region 10 and the diode region 20 are arranged in a stripe shape, and can be simply referred to as a "strip type". Figure 2 The semiconductor device 100 shown has a plurality of diode regions 20 arranged in the vertical and horizontal directions, and an IGBT region 10 is provided around the diode region 20 , which can be simply referred to as an “island type”.

[0042] (1) Strip-type overall plane structure

[0043] exist Figure 1 In the embodiment, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. The IGBT region 10 and the diode region 20 extend from one end of the semiconductor device 100 to the other end, and are alternately arranged in stripes in a direction perpendicular to the extending direction of the IGBT region 10 and the diode region 20. Figure 1 In the figure, there are three IGBT regions 10 and two diode regions, and all diode regions 20 are separated by IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this. The number of IGBT regions 10 can be more than three or less than three, and the number of diode regions 20 can be more than two or less than two. In addition, Figure 1 The positions of the IGBT regions 10 and the diode regions 20 may be exchanged, or all the IGBT regions 10 may be separated by the diode regions 20. Alternatively, the IGBT regions 10 and the diode regions 20 may be arranged adjacent to each other one by one.

[0044] like Figure 1 As shown, a pad region 40 is provided adjacent to the lower side of the IGBT region 10 in the drawing. Pad region 40 is a region where control pads 41 for controlling semiconductor device 100 are provided. The IGBT region 10 and diode region 20 are collectively referred to as a cell region. As will be described later, the emitter electrode of the RC-IGBT is arranged in the cell region of semiconductor device 100.

[0045] In the present embodiment, a gate wiring region 50 is provided around the cell region, and the gate wiring region 50 is configured with a gate wiring for transmitting a gate signal for controlling the energization of the semiconductor device 100. In addition, a gate finger wiring region 60 is provided in a manner that enters the cell region from one side (the side close to the pad region 40) of the gate wiring region 50 and extends, and the gate finger wiring region 60 is configured with a gate finger wiring connected to the gate wiring. The front end of the gate finger wiring region 60 does not reach the side (the side away from the pad region 40) opposite to the gate wiring region 50. That is, one end of the gate finger wiring 61 is connected to the gate wiring 51, but the other end is not connected to the gate wiring 51.

[0046] Thus, the gate finger wiring region 60 does not completely divide the IGBT region 10, and there is a gap between the front end of the gate finger wiring region 60 and the gate wiring region 50. The gate finger wiring and the emitter electrode are formed in the same layer, and thus the emitter electrode is divided by the gate finger wiring. However, the portions of the adjacent emitter electrodes across the gate finger wiring are connected to each other via the region between the front end of the gate finger wiring region 60 and the gate wiring region 50, that is, the emitter electrode connection region 70. Regarding the gate wiring and the gate finger wiring, detailed description will be given in "(6) Configuration of Gate Wiring and Gate Finger Wiring" described later.

[0047] In order to maintain the withstand voltage of the semiconductor device 100, a termination region 30 is provided around the region in which the cell region and the pad region 40 are combined. A publicly known withstand voltage maintaining configuration can be appropriately and selectively provided in the termination region 30. The withstand voltage maintaining configuration can be configured, for example, with a FLR (Field Limiting Ring) that surrounds the region in which the cell region and the pad region 40 are combined by a p-type termination well layer of a p-type semiconductor, and a VLD (Variation of Lateral Doping) that surrounds the region in which the cell region and the pad region 40 are combined by a p-type termination well layer having a concentration gradient, on the surface side of the semiconductor device 100, that is, the first main surface side, and the number of the annular p-type termination well layers used for the FLR and the concentration distribution used for the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. In addition, the p-type termination well layer can be provided throughout substantially the entire region of the pad region 40, and the IGBT cell and the diode cell can be provided in the pad region 40.

[0048] The control pads 41 are, for example, a current-sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, a temperature-sensing diode pad 41d, 41e. The current-sensing pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is a control pad electrically connected to a part of an IGBT cell or a diode cell of the cell region in a manner that a current of a fraction of one part to several ten-thousand parts of a current flowing in the entire cell region flows in the control pad when a current flows in the cell region of the semiconductor device 100.

[0049] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on-off control of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to a p-type base layer and an n + type emitter layer of an IGBT cell, and the gate pad 41c is electrically connected to a gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via a p + type contact layer. The temperature-sensing diode pads 41d, 41e are control pads electrically connected to an anode and a cathode of a temperature-sensing diode provided in the semiconductor device 100. A voltage between an anode and a cathode of a temperature-sensing diode not shown provided in the cell region is measured, and a temperature of the semiconductor device 100 is measured.

[0050] (2) Overall planar configuration of island type

[0051] In the Figure 2 semiconductor device 100, an IGBT region 10 and a diode region 20 are provided in one semiconductor device. The diode region 20 is arranged in multiple in the longitudinal direction and the lateral direction in the semiconductor device, and the periphery of the diode region 20 is surrounded by the IGBT region 10. That is, in the IGBT region 10, the plurality of diode regions 20 are provided in an island shape. In the Figure 2 semiconductor device 100, a structure is shown in which the diode regions 20 are arranged in a matrix shape having four columns in the lateral direction on the paper and two rows in the vertical direction on the paper, but the number and arrangement of the diode regions 20 are not limited thereto, and it is only necessary that one or more diode regions 20 be provided in the IGBT region 10 so as to be dispersed and the periphery of each diode region 20 be surrounded by the IGBT region 10.

[0052] As shown in Figure 2 , a pad region 40 is provided adjacent to the lower side of the IGBT region 10 on the paper. The pad region 40 is a region in which control pads 41 for controlling the semiconductor device 100 are provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region.

[0053] In a case where the RC-IGBT is configured in an island type, a gate wiring region 50 in which a gate wiring is arranged is also provided around the cell region. In addition, a gate finger wiring region 60 in which a gate finger wiring is arranged is provided in a manner that extends from one side of the gate wiring region 50 into the cell region. An emitter electrode connection region 70 is provided in a gap between a front end of the gate finger wiring region 60 and the gate wiring region 50.

[0054] In order to maintain the withstand voltage of the semiconductor device 100, a terminal region 30 is provided around a region in which the cell region and the pad region 40 are combined. A known withstand voltage maintaining configuration can be appropriately and selectively provided in the terminal region 30. The withstand voltage maintaining configuration can be configured, for example, by a FLR (Field Limiting Ring) that surrounds a region in which the cell region and the pad region 40 are combined by a p-type terminal well layer of a p-type semiconductor, and a VLD (Variation of Lateral Doping) that surrounds a region in which the cell region and the pad region 40 are combined by a p-type terminal well layer having a concentration gradient, on the surface side of the semiconductor device 100, that is, on the first main surface side. The number of the annular p-type terminal well layers used by the FLR and the concentration distribution used by the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. In addition, the p-type terminal well layer can be provided throughout substantially the entire region of the pad region 40, and an IGBT cell and a diode cell can be provided in the pad region 40.

[0055] The control pads 41 can be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, a temperature sense diode pad 41d, 41e. The current sense pad 41a is a control pad for detecting a current flowing in the cell region of the semiconductor device 100, and is a control pad that is electrically connected to a part of the IGBT cells or the diode cells of the cell region in a manner that a current of several one-thousandths to several ten-thousandths of the current flowing in the entire cell region flows in the control pad when the current flows in the cell region of the semiconductor device 100.

[0056] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on-off control of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to a p-type base layer and an n + type emitter layer of the IGBT cell, and the gate pad 41c is electrically connected to a gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via a p +The temperature sensing diode pads 41d, 41e are control pads that are electrically connected to an anode and a cathode of a temperature sensing diode provided in the semiconductor device 100. The voltage between the anode and the cathode of the temperature sensing diode, which is not shown and is provided in the cell region, is measured, and the temperature of the semiconductor device 100 is measured.

[0057] (3) Configuration of IGBT region 10

[0058] Figure 3 is a partial enlarged plan view showing the structure of the IGBT region of the semiconductor device as an RC-IGBT. In addition, Figure 4 and Figure 5 are cross-sectional views showing the structure of the IGBT region of the semiconductor device as an RC-IGBT. Figure 3 is a view showing the region surrounded by the broken line 82 in the semiconductor device 100 shown in Figure 1 or Figure 2 Figure 4 is a cross-sectional view at the broken line A-A of the semiconductor device 100 shown in Figure 3 Figure 5 is a cross-sectional view at the broken line B-B of the semiconductor device 100 shown in Figure 3 As shown in

[0059] , in the IGBT region 10, the active trench gate 11 and the dummy trench gate 12 are provided in a strip shape. For the semiconductor device 100 of Figure 3 , the active trench gate 11 and the dummy trench gate 12 extend in the length direction of the IGBT region 10, and the length direction of the IGBT region 10 becomes the length direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, for the semiconductor device 100 of Figure 1 , the distinction between the length direction and the width direction in the IGBT region 10 is not particularly limited, but the left-right direction of the paper can be set as the length direction of the active trench gate 11 and the dummy trench gate 12, or the up-down direction of the paper can be set as the length direction of the active trench gate 11 and the dummy trench gate 12. Figure 2

[0060] The active trench gate 11 is configured by providing the gate trench electrode 11a inside the trench formed in the semiconductor substrate with the gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 is configured by providing the dummy trench electrode 12a inside the trench formed in the semiconductor substrate with the dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to the emitter electrode provided on the first main surface of the semiconductor device 100. ​​​

[0061] n + The type emitter layer 13 is provided so as to be in contact with the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. + The emitter layer 13 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 .n + The type emitter layer 13 is connected to the p-type emitter layer 13 along the extending direction of the active trench gate 11. + The p-type contact layers 14 are alternately arranged. A p-type contact layer 14 is also arranged between two adjacent virtual trench gates 12. + Type contact layer 14. p + The p-type contact layer 14 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 .

[0062] like Figure 3 As shown, in the IGBT region 10 of the semiconductor device 100, three dummy trench gates 12 are arranged next to three parallel active trench gates 11, and three active trench gates 11 are arranged next to three parallel dummy trench gates 12. The IGBT region 10 is configured such that groups of active trench gates 11 and groups of dummy trench gates 12 are alternately arranged. Figure 3 In the embodiment, the number of active trench gates 11 included in one group of active trench gates 11 is 3, but it may be 1 or more. In addition, the number of dummy trench gates 12 included in one group of dummy trench gates 12 may be 1, or the number of dummy trench gates 12 may be 0. In other words, all trenches provided in the IGBT region 10 may be set as active trench gates 11.

[0063] Figure 4 The semiconductor device 100 Figure 3 The cross-sectional view taken along the dotted line AA in FIG. 1 is a cross-sectional view of the IGBT region 10. The semiconductor device 100 includes an n-type semiconductor substrate. － Type drift layer 1. n － The drift layer 1 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 . Semiconductor substrate in Figure 4 In the middle of n + type emitter layer 13 and p + In the range from the p-type contact layer 14 to the p-type collector layer 16. Figure 4 In the+ type emitter layer 13 and p + The upper end of the p-type contact layer 14 on the paper is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. The semiconductor device 100 has an n-type contact layer 14 on the paper upper end and a p-type collector layer 16 on the paper lower end. － Type drift layer 1.

[0064] like Figure 4 As shown, in the IGBT region 10, at n － The first main surface side of the drift layer 1 is provided with a － The n-type drift layer 1 has a high concentration of n-type impurities and an n-type carrier storage layer 2. The n-type carrier storage layer 2 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 Alternatively, the semiconductor device 100 may be configured without the n-type carrier storage layer 2. Figure 4 The region of the n-type carrier storage layer 2 shown is also provided with n － The structure of the n-type drift layer 1. By providing the n-type carrier storage layer 2, the conduction loss when the current flows through the IGBT region 10 can be reduced. The n-type carrier storage layer 2 and the n-type carrier storage layer 2 can also be connected. － The drift layer 1 is collectively referred to as the drift layer.

[0065] The n-type carrier storage layer 2 is formed by introducing n-type impurities into the n － Ion implantation is performed on the semiconductor substrate of the n-type drift layer 1, and then annealing is performed to diffuse the implanted n-type impurities into the n-type drift layer 1. － The type drift layer 1 is formed in the semiconductor substrate.

[0066] A p-type base layer 15 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, an n-type base layer is provided in contact with the gate trench insulating film 11b of the active trench gate 11. + Type emitter layer 13, and p + Type contact layer 14. + type emitter layer 13 and p +The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. + In the case of the p-type contact layer 14 and the p-type base layer 15, they can be referred to separately, or the p-type base layer 15 can be referred to as the p-type contact layer 14 and the p-type base layer 15. + The p-type contact layer 14 and the p-type base layer 15 are collectively referred to as a p-type base layer.

[0067] In addition, for the semiconductor device 100, － The second main surface side of the drift layer 1 is provided with a － The n-type buffer layer 3 has a high concentration of n-type impurities in the p-type drift layer 1. The n-type buffer layer 3 is provided to suppress the breakdown of the depletion layer extending from the p-type base layer 15 to the second main surface when the semiconductor device 100 is in the off state. The n-type buffer layer 3 can be implanted with phosphorus (P) or protons (H + ) can also be formed by injecting phosphorus (P) and protons (H + The concentration of n-type impurities in the n-type buffer layer 3 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 .

[0068] Alternatively, the semiconductor device 100 may be configured without the n-type buffer layer 3. Figure 4 The region of the n-type buffer layer 3 shown is also provided with n － The structure of n-type drift layer 1 can also be formed by combining n-type buffer layer 3 and n-type － The drift layer 1 is collectively referred to as the drift layer.

[0069] The semiconductor device 100 includes a p-type collector layer 16 on the second main surface side of the n-type buffer layer 3. － A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 P-type collector layer 16 forms the second main surface of the semiconductor substrate. P-type collector layer 16 is provided not only in IGBT region 10 but also in termination region 30. The portion of p-type collector layer 16 provided in termination region 30 constitutes p-type termination collector layer 16a. Alternatively, p-type collector layer 16 may be provided so that a portion thereof protrudes from IGBT region 10 toward diode region 20.

[0070] like Figure 4 As shown, the semiconductor device 100 has a structure that penetrates the p-type base layer 15 from the first main surface of the semiconductor substrate and reaches the n-type base layer 15.－ groove of the p-type drift layer 1. The active-trench gate 11 is formed by providing the gate-trench electrode 11a in the groove with the gate-trench insulating film 11b interposed therebetween. The gate-trench electrode 11a is in ohmic contact with the p-type base layer 15 and the n-type emitter layer 13 via the gate-trench insulating film 11b and the p-type contact layer 14, and is in ohmic contact with the virtual-trench electrode 12a via the virtual-trench insulating film 12b. － groove of the p-type drift layer 1. The active-trench gate 11 is formed by providing the gate-trench electrode 11a in the groove with the gate-trench insulating film 11b interposed therebetween. The gate-trench electrode 11a is in ohmic contact with the p-type base layer 15 and the n-type emitter layer 13 via the gate-trench insulating film 11b and the p-type contact layer 14, and is in ohmic contact with the virtual-trench electrode 12a via the virtual-trench insulating film 12b. － groove of the p-type drift layer 1. The active-trench gate 11 is formed by providing the gate-trench electrode 11a in the groove with the gate-trench insulating film 11b interposed therebetween. The gate-trench electrode 11a is in ohmic contact with the p-type base layer 15 and the n-type emitter layer 13 via the gate-trench insulating film 11b and the p-type contact layer 14, and is in ohmic contact with the virtual-trench electrode 12a via the virtual-trench insulating film 12b. + emitter layer 13. If a gate drive voltage is applied to the gate-trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate-trench insulating film 11b of the active-trench gate 11.

[0071] As shown in FIG. 1, the interlayer insulating film 4 is provided on the gate-trench electrode 11a of the active-trench gate 11. The barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate on which the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. Figure 4 As shown in FIG. 1, the interlayer insulating film 4 is provided on the gate-trench electrode 11a of the active-trench gate 11. The barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate on which the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. Figure 4 The barrier metal 5 is in ohmic contact with the n-type emitter layer 13, the p-type contact layer 14, and the virtual-trench electrode 12a, and is in ohmic contact with the gate-trench electrode 11a. + emitter layer 13, the p-type contact layer 14, and the virtual-trench electrode 12a, and is in ohmic contact with the gate-trench electrode 11a. + emitter layer 13, the p-type contact layer 14, and the virtual-trench electrode 12a, and is in ohmic contact with the gate-trench electrode 11a. + emitter layer 13, the p-type contact layer 14, and the virtual-trench electrode 12a, and is in ohmic contact with the gate-trench electrode 11a. + The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can be an electrode composed of a plurality of metal films formed by chemical plating or electroplating on an electrode formed of an aluminum alloy. The plating film formed by chemical plating or electroplating can be, for example, a nickel (Ni) plating film. In the case where there is a minute region, i.e., a region in which the emitter electrode 6 cannot be embedded well, such as an adjacent interlayer insulating film 4, tungsten having a good embedding property compared to the emitter electrode 6 can be provided in the minute region, and the emitter electrode 6 can be provided on the tungsten. Alternatively, the barrier metal 5 can not be provided, and the emitter electrode 6 can be provided on the n-type emitter layer 13, the p-type contact layer 14, and the virtual-trench electrode 12a. + emitter layer 13, the p-type contact layer 14, and the virtual-trench electrode 12a, and is in ohmic contact with the gate-trench electrode 11a. + emitter layer 13, the p-type contact layer 14, and the virtual-trench electrode 12a, and is in ohmic contact with the gate-trench electrode 11a. + The barrier metal 5 can be collectively referred to as the emitter electrode together with the emitter electrode 6. In the case where the barrier metal 5 is not provided, the emitter electrode 6 can be provided on the n-type emitter layer 13 and the like. Figure 5A figure showing that no interlayer insulating film 4 is provided on the dummy trench electrode 12a of the dummy trench gate 12 is shown in FIG. 6, but an interlayer insulating film 4 can also be formed on the dummy trench electrode 12a of the dummy trench gate 12. When an interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a are electrically connected in other cross sections.

[0072] A collector 7 is provided on the second main surface side of the p-type collector layer 16. The collector 7 can also be composed of an aluminum alloy, an aluminum alloy and a plating film, like the emitter electrode 6. Alternatively, the collector 7 can be a structure different from the emitter electrode 6. The collector 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0073] Figure 3 is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1. Figure 4 is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1. Figure 5 is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1. Figure 3 is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1. + is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1. Figure 6 is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1. + is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1. + is a cross-sectional view at a dotted line B-B in the semiconductor device 100 of FIG. 1.

[0074] (4) Example of configuration of diode region 20

[0075] Figure 7 is a partial enlarged plan view showing the structure of the diode region of the semiconductor device as an RC-IGBT. In addition, Figure 8 and Figure 6 are cross-sectional views showing the structure of the diode region of the semiconductor device as an RC-IGBT. Figure 1 is a figure showing a region surrounded by a dotted line 83 in the semiconductor device 100 shown in FIG. 1 in an enlarged manner. Figure 7 is a cross-sectional view at a dotted line C-C of the semiconductor device 100 shown in FIG. 1. Figure 6 is a cross-sectional view at a dotted line D-D of the semiconductor device 100 shown in FIG. 1. Figure 8 is a cross-sectional view at a dotted line D-D of the semiconductor device 100 shown in FIG. 1. Figure 6 is a cross-sectional view at a dotted line D-D of the semiconductor device 100 shown in FIG. 1. Figure 7 is a cross-sectional view at a dotted line D-D of the semiconductor device 100 shown in FIG. 1.

[0076] The diode trench gate 21 extends from one end side of the diode region 20 serving as the unit region to the other end side thereof along the first main surface of the semiconductor device 100. The diode trench gate 21 is formed by providing a diode trench electrode 21a in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is connected to the n-type diode via the diode trench insulating film 21b. － A p-type drift layer 1 is provided between two adjacent diode trench gates 21. + Type contact layer 24 and p-type anode layer 25. + The p-type contact layer 24 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 .p + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0077] Figure 6 The semiconductor device 100 Figure 7 The cross-sectional view taken along the dotted line CC in FIG. 1 is a cross-sectional view of the diode region 20. The semiconductor device 100 also has an n-type semiconductor substrate in the diode region 20 similarly to the IGBT region 10. － Type drift layer 1. The n-type diode region 20 － n type drift layer 1 and IGBT region 10 － The drift layer 1 is continuously formed as a whole and is formed by the same semiconductor substrate. Figure 7 In the semiconductor substrate, the + Type contact layer 24 to n + The range of the cathode layer 26. Figure 7 In the + The upper end of the paper surface of the type contact layer 24 is called the first main surface of the semiconductor substrate. + The lower edge of cathode layer 26 is referred to as the second principal surface of the semiconductor substrate. The first principal surface of diode region 20 is flush with the first principal surface of IGBT region 10 , and the second principal surface of diode region 20 is flush with the second principal surface of IGBT region 10 .

[0078] like Figure 2 As shown, in the diode region 20, similarly to the IGBT region 10, －An n-type carrier storage layer 2 is provided on the first main surface side of the n-type drift layer 1. － An n-type buffer layer 3 is provided on the second main surface side of the type drift layer 1. The n-type carrier storage layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier storage layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. In addition, the IGBT region 10 and the diode region 20 do not necessarily need to be provided with the n-type carrier storage layer 2. Even when the n-type carrier storage layer 2 is provided in the IGBT region 10, the diode region 20 may be provided with no n-type carrier storage layer 2. In addition, similarly to the IGBT region 10, the n-type carrier storage layer 2 may also be provided. － The n-type drift layer 1 , the n-type carrier accumulation layer 2 , and the n-type buffer layer 3 are collectively referred to as a drift layer.

[0079] A p-type anode layer 25 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type anode layer 25 is provided on the n-type carrier storage layer 2. － Between the p-type drift layer 1 and the first main surface. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be made equal to that of the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be made lower than that of the p-type base layer 15 of the IGBT region 10, thereby reducing the amount of positive holes injected into the diode region 20 during diode operation. By reducing the amount of positive holes injected during diode operation, recovery loss during diode operation can be reduced.

[0080] On the first main surface side of the p-type anode layer 25, a p + Type contact layer 24. p + The concentration of the p-type impurities in the p-type contact layer 24 can be equal to that of the p-type impurities in the IGBT region 10. + The p-type impurities in the p-type contact layer 14 may have the same concentration or different concentrations. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. + In the case of the p-type contact layer 24 and the p-type anode layer 25, they can be referred to separately, or the p-type anode layer 25 can be referred to as + The p-type contact layer 24 and the p-type anode layer 25 are collectively referred to as a p-type anode layer.

[0081] In the diode region 20 , an n-type buffer layer 3 is provided on the second main surface side. + Type cathode layer 26. n + The cathode layer 26 is provided on the n － Between the drift layer 1 and the second main surface. +The cathode layer 26 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 .like Figure 7 As shown, n + The cathode layer 26 is provided in a part or the whole of the diode region 20. + The p-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. Although not shown in the figure, p-type impurities may be further selectively implanted into the n-type cathode layer 26 formed as described above. + The area of ​​the type cathode layer 26 forms an n + A p-type cathode layer is provided as a p-type semiconductor in a part of the region of the p-type cathode layer 26 .

[0082] like Figure 7 As shown, in the diode region 20 of the semiconductor device 100, a p-type anode layer 25 is formed from the first main surface of the semiconductor substrate to reach the n-type anode layer 25. － The diode trench electrode 21a is provided in the trench of the diode region 20 via the diode trench insulating film 21b, thereby forming the diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. － type drift layer 1 is opposite.

[0083] like Figure 7 As shown, in the diode trench electrode 21a, and p + A barrier metal 5 is provided on the type contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and the p + The contact layer 24 is in ohmic contact with the diode trench electrode and the p + The barrier metal 5 may be electrically connected to the IGBT region 10. The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. In addition, as in the case of the IGBT region 10, the barrier metal 5 may not be provided, and the diode trench electrode 21a and the p + The contact layer 24 is in ohmic contact with the emitter electrode 6. Figure 8 , the diagram shows that the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in other cross sections.

[0084] In n + A collector electrode 7 is provided on the second main surface side of the n + type cathode layer 26 ohmic contacts with the n + type cathode layer 26 is electrically connected.

[0085] Figure 6 is a sectional view at the broken line D-D in the semiconductor device 100, and is a sectional view of the diode region 20. As shown in the sectional view at the broken line C-C in the semiconductor device 100, Figure 7 is a sectional view at the broken line D-D in the semiconductor device 100, and is a sectional view of the diode region 20. As shown in the sectional view at the broken line C-C in the semiconductor device 100, Figure 7 is a sectional view at the broken line D-D in the semiconductor device 100, and is a sectional view of the diode region 20. As shown in the sectional view at the broken line C-C in the semiconductor device 100, Figure 9 is a sectional view at the broken line D-D in the semiconductor device 100, and is a sectional view of the diode region 20. As shown in the sectional view at the broken line C-C in the semiconductor device 100, + type contact layer 24 is selectively provided on the first main surface side of the p Figure 9 type contact layer 24 is selectively provided on the first main surface side of the p + type contact layer 24 is selectively provided on the first main surface side of the p

[0086] (5) Boundary region between IGBT region 10 and diode region 20

[0087] Figure 9 is a sectional view showing a structure of a boundary between an IGBT region and a diode region of a semiconductor device that is an RC-IGBT. Figure 1 is a sectional view at the broken line G-G in the semiconductor device 100 shown in Figure 9 is a sectional view at the broken line G-G in the semiconductor device 100 shown in

[0088] As shown in Figure 10 the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided so as to protrude only by a distance U1 toward the diode region 20 from the boundary between the IGBT region 10 and the diode region 20. In this way, by providing the p-type collector layer 16 so as to protrude toward the diode region 20, it is possible to increase the distance between the n + type cathode layer 26 and the active trench gate 11, even in the case where a gate drive voltage is applied to the gate trench electrode 11a when the freewheel diode is operating, it is possible to suppress current from flowing from the channel formed in adhesion with the active trench gate 11 of the IGBT region 10 to the n + type cathode layer 26. The distance U1 may, for example, be 100 μm. In addition, depending on the use of the semiconductor device 100 that is an RC-IGBT, the distance U1 can also be zero or a distance of less than 100 μm.

[0089] (6) Configuration of gate wiring and gate finger wiring

[0090] Figure 1 isFigure 2 or Figure 11 FIG. 1 is a top view of the semiconductor device 100 near the emitter electrode connection region 70. Figure 10 It is along Figure 10 A cross-sectional view along line A1-A2 is shown. Figure 11 and Figure 3 : shown in the figure: the emitter electrode 6 as the surface electrode arranged in the cell area, the gate wiring 51 arranged in the gate wiring area 50, the gate finger wiring 61 arranged in the gate finger wiring area 60, the emitter electrode connection portion 71 arranged in the emitter electrode connection area 70, and the first active trench gate 111 and the second active trench gate 112 formed in the semiconductor substrate.

[0091] The first active trench gate 111 and the second active trench gate 112 are part of the active trench gate 11. That is, the active trench gate 11 includes the first active trench gate 111 and the second active trench gate 112. The first active trench gate 111 extends in a first direction orthogonal to the extending direction of the gate finger wiring 61. The second active trench gate 112 is electrically connected to the first active trench gate 111 and extends in a second direction parallel to the extending direction of the gate finger wiring 61. The second active trench gate 112 is led out below the gate finger wiring 61. The first active trench gate 111 is the main part of the active trench gate 11. Figure 4 、 Figure 5 、 Figure 9 as well as Figure 11 The active trench gate 11 shown is equivalent to the first active trench gate 111 .

[0092] like Figure 11 As shown, the gate wiring 51 and the gate finger wiring 61 are formed on the interlayer insulating film 4 (at Figure 10 (The barrier metal 5 is omitted in the figure). Gate wiring 51 electrically connects the active trench gate 11 and the gate pad 41c. Gate finger wiring 61 is provided to be electrically connected to gate wiring 51. Thus, the gate signal input to the gate pad 41c is transmitted to the gate finger wiring 61 via the gate wiring 51.

[0093] In addition, the gate finger wiring 61 is connected to the first active trench gate 111 and the second active trench gate 112 through the contact hole formed in the interlayer insulating film 4 ( Figure 11 The diagonal rectangles shown indicate the positions of the contact holes.) Thus, the gate signal is transmitted to the active trench gate 11 not only through the gate wiring 51 but also through the gate finger wiring 61, thereby suppressing the delay of the gate signal.

[0094] Here, it is not possible to directly connect the gate finger wiring 61 to the first active-trench gate 111 under the emitter electrode connecting portion 71. In the present embodiment, the second active-trench gate 112 drawn under the gate finger wiring 61 is connected to the first active-trench gate 111 under the emitter electrode connecting portion 71, and the gate finger wiring 61 is connected to the second active-trench gate 112. Thus, the gate finger wiring 61 is also electrically connected to the first active-trench gate 111 under the emitter electrode connecting portion 71. Therefore, the emitter electrode connecting portion 71 is configured to overlap at least a portion of the second active-trench gate 112.

[0095] The gate finger wiring 61 is, for example, an aluminum wiring. The material of the gate finger wiring 61 can also be the same material as the emitter electrode 6, in which case the gate finger wiring 61 can be formed at the same time as the emitter electrode 6. However, the gate finger wiring 61 and the emitter electrode 6 are set to different potentials, so the gate finger wiring 61 and the emitter electrode 6 are separated from each other.

[0096] As Figure 12 such, the gate finger wiring 61 and the emitter electrode 6 are formed in the same layer. Therefore, the emitter electrode 6 is divided by the gate finger wiring 61. However, the adjacent emitter electrodes 6 across the gate finger wiring 61 are not completely separated. The adjacent emitter electrodes 6 across the gate finger wiring 61 are connected by the emitter electrode connecting portion 71 disposed in the emitter electrode connecting region 70. The material of the emitter electrode connecting portion 71 can be the same material as the material of the emitter electrode 6, and the emitter electrode 6 and the emitter electrode connecting portion 71 can be formed constantly.

[0097] Thus, the adjacent emitter electrodes 6 across the gate finger wiring 61 are electrically connected by the emitter electrode connecting portion 71, and the imbalance of the current is improved, and the short-circuit resistance of the semiconductor device 100 is increased.

[0098] <Embodiment 2>

[0099] Figure 13 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 of Embodiment 2. In addition, Figure 12 the shape of the emitter electrode connecting portion 71 is shown. Figure 10 The structure shown is the same as Figure 12 .

[0100] As Figure 13 and Figure 13As shown, the length of the emitter electrode linking portion 71 in the first direction (the direction perpendicular to the extension direction of the gate finger wiring 61) is represented by x, the length of the emitter electrode linking portion 71 in the second direction (the extension direction of the gate finger wiring 61) is represented by y, and the thickness of the emitter electrode linking portion 71 is represented by z. Hereinafter, x is referred to as the "length" of the emitter electrode linking portion 71, and y is referred to as the "width" of the emitter electrode linking portion 71.

[0101] like Figure 14 As shown, if it is assumed that the emitter electrode connecting portion 71 is a straight conductor with a rectangular cross-section made of metal, the inductance L [μH] of the emitter electrode connecting portion 71 can be expressed as L = 0.002x [ln (2x / (y + z)) + 0.2235 ((y + z) / x) + 0.5], and the resistance R [mΩ] of the emitter electrode connecting portion 71 can be expressed as R = ρx / yz (ρ: resistivity).

[0102] In the semiconductor device 100 of embodiment 2, when the pitch of the first active trench gate 111 is 2.4 μm, the length x, width y, and thickness z of the emitter electrode connecting portion 71 are set to satisfy the relationship of 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<5.0[μH] and ρx / yz<7.5[mΩ].

[0103] In this manner, by suppressing the resistance and inductance of the emitter electrode connecting portion 71 , the effect of improving the imbalance of the current in the emitter electrode 6 is enhanced.

[0104] In addition, if the pitch of the first active trench gate 111 is 4.0 μm, the length x, width y, and thickness z of the emitter electrode connecting portion 71 can be set so as to satisfy the relationship 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<2.5[μH] and ρx / yz<3.0[mΩ].

[0105] <Implementation Method 3>

[0106] Figure 14 1 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the third embodiment.

[0107] In the third embodiment, the semiconductor device 100 includes a third active trench gate 113 that electrically connects adjacent first active trench gates 111 below the emitter electrode linking portion 71 and extends in the second direction. Figure 15 In the example of , a plurality of third active trench gates 113 are also provided, and the active trench gates 11 passing under the emitter electrode connecting portion 71 have a ladder shape in a plan view.

[0108] The first active trench gate 111 under the emitter electrode connecting portion 71 is connected by the third active trench gate 113, so that the gate signal is easily transmitted from the gate finger wiring 61 to the first active trench gate 111 under the emitter electrode connecting portion 71, and thus the suppression effect of the gate delay is improved.

[0109] <Embodiment 4>

[0110] Figure 15 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 of Embodiment 4. In addition, is a cross-sectional view along the A1-A2 line shown in

[0111] The semiconductor device 100 of Embodiment 4 has a configuration in which the active trench gate 11 is spaced out by disposing the dummy trench gate 12 between the first active trench gates 111 (gate spacing-out configuration). The dummy trench gate 12 extends in parallel with the first active trench gate 111 (i.e., in the first direction).

[0112] As shown in Figure 16 , the dummy trench gate 12 can be disposed under the emitter electrode connecting portion 71. However, if the dummy trench gate 12 intersects the second active trench gate 112, insulation between the dummy trench gate 12 and the second active trench gate 112 cannot be ensured, and thus the dummy trench gate 12 has a pattern that is interrupted in a portion in which the second active trench gate 112 is disposed.

[0113] In this embodiment, the same effect as that of Embodiment 1 can be obtained.

[0114] <Embodiment 5>

[0115] Figure 17 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 of Embodiment 5. In addition, is a cross-sectional view along the A1-A2 line shown in Figure 16 Figure 18

[0116] In the semiconductor device 100 of Embodiment 5, the second active trench gate 112 connected to the first active trench gate 111 under the emitter electrode connecting portion 71 is led out under the gate wiring 51. The gate wiring 51 is connected to the second active trench gate 112 through a contact hole formed in the interlayer insulating film 4.

[0117] Thus, in this embodiment, the first active trench gate 111 under the emitter electrode connecting portion 71 is connected to the gate wiring 51 through the second active trench gate 112. Therefore, the gate signal is transmitted from the gate wiring 51 to the first active trench gate 111 under the emitter electrode connecting portion 71 without passing through the gate finger wiring 61.​​

[0118] In this embodiment, the same effects as Embodiment 1 can also be obtained.

[0119] Embodiment 6

[0120] Figure 19 is a plan view of the vicinity of the emitter electrode connection region 70 of the semiconductor device 100 of Embodiment 6. Also, Figure 18 is a cross-sectional view along the A1-A2 line shown in Figure 20 .

[0121] Embodiment 6 is a combination of Embodiments 1 and 5. That is, in the semiconductor device 100 of Embodiment 6, a part of the first active-trench gate 111 under the emitter electrode connection portion 71 is connected to the second active-trench gate 112 drawn under the gate finger wiring 61 as in Embodiment 1, and the other part of the first active-trench gate 111 is connected to the second active-trench gate 112 drawn under the gate wiring 51 as in Embodiment 6.

[0122] Thus, in this embodiment, the gate signal is transmitted from the gate wiring 51 to a part of the first active-trench gate 111 under the emitter electrode connection portion 71 through the gate finger wiring 61, and the gate signal is transmitted from the gate wiring 51 to the other part of the first active-trench gate 111 without passing through the gate finger wiring 61.

[0123] With this configuration, the gate signal is transmitted to the first active-trench gate 111 under the emitter electrode connection portion 71 from both the gate wiring 51 and the gate finger wiring 61, and thus the suppression effect of gate delay is improved.

[0124] Embodiment 7

[0125] Figure 21 is a plan view of the vicinity of the emitter electrode connection region 70 of the semiconductor device 100 of Embodiment 7. Also, Figure 20 is a cross-sectional view along the A1-A2 line shown in Figure 22 .

[0126] In the semiconductor device 100 of Embodiment 7, the p-type layer 91 deeper than the first active-trench gate 111 and the second active-trench gate 112 is formed in the region including the emitter electrode connection region 70 in which the emitter electrode connection portion 71 is disposed. When the p-type layer 91 is applied in Embodiment 3, the p-type layer 91 is formed deeper than the first active-trench gate 111, the second active-trench gate 112, and the third active-trench gate 113.

[0127] With this configuration, it is possible to suppress concentration of an electric field in the vicinity of the end portion of the first active trench gate 111, the second active trench gate 112, or the third active trench gate 113 located below the emitter electrode connecting portion 71.

[0128] <Embodiment 8>

[0129] Figure 23 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 of Embodiment 8. Also, Figure 22 is a cross-sectional view along the A1-A2 line shown in Figure 24 .

[0130] In the semiconductor device 100 of Embodiment 8, the emitter electrode connecting portion 71 is connected to the p + type contact layer 14 through a contact hole formed in the interlayer insulating film 4.

[0131] With this configuration, a hole drag effect can be obtained in the emitter electrode connecting region 70, and thus the SOA (Safety Operation Area) tolerance of the semiconductor device 100 is improved.

[0132] <Embodiment 9>

[0133] Figure 25 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 of Embodiment 9.

[0134] In the semiconductor device 100 of Embodiment 9, the active trench gate 11 (the first active trench gate 111, the second active trench gate 112, or the third active trench gate 113) disposed below the emitter electrode connecting portion 71 has a width wider than the width of a region other than this. That is, the width of the active trench gate 11 is locally widened in the portion disposed below the emitter electrode connecting portion 71.

[0135] With this configuration, the gate resistance of the semiconductor device 100 is reduced, and thus the suppression effect of gate delay is improved.

[0136] <Embodiment 10>

[0137] Figure 26 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 of Embodiment 10.

[0138] In the semiconductor device 100 of Embodiment 10, the corner portion of the active trench gate 11 (the first active trench gate 111, the second active trench gate 112, or the third active trench gate 113) disposed below the emitter electrode connecting portion 71 has a rounded shape (R shape).

[0139] With this configuration, it is possible to prevent the electric field from concentrating at the corner of the trench of the active trench gate 11, and thus the withstand voltage and SOA tolerance of the semiconductor device 100 are improved.

[0140] <Embodiment 11>

[0141] Figure 27 is a plan view of the vicinity of the emitter electrode connection region 70 of the semiconductor device 100 of Embodiment 11.

[0142] The semiconductor device 100 of Embodiment 11 is provided with a plurality of gate finger regions 60 in which the gate finger wires 61 are arranged. The gap between the front ends of the plurality of gate finger wires 61 and the gate wire region 50 is provided with an emitter electrode connection region 70 in which the emitter electrode connection portion 71 is arranged.

[0143] The emitter electrode 6 is divided into three or more portions by the plurality of gate finger wires 61, but these portions are electrically connected by the emitter electrode connection portion 71.

[0144] The gate signal is transmitted from the plurality of gate finger wires 61 to the active trench gate 11, and thus the suppression effect of the gate delay is improved.

[0145] <Embodiment 12>

[0146] Figure 27 is a plan view of the vicinity of the emitter electrode connection region 70 of the semiconductor device 100 of Embodiment 12.

[0147] Like Embodiment 11, the semiconductor device 100 of Embodiment 12 is provided with a plurality of gate finger regions 60 in which the gate finger wires 61 are arranged. However, unlike Embodiment 11, the plurality of gate finger wires 61 are arranged in an alternating manner in the direction extending from the gate wire 51. That is, the plurality of gate finger wires 61 are arranged in a zigzag (staggered) manner at the connection site with the gate wire 51.

[0148] For example, in ​ , the gate finger wire 61 of the left gate finger region 60 extends from the side close to the pad region 40 of the gate wire 51 in the upward direction of the paper surface, and the gate finger wire 61 of the right gate finger region 60 extends from the side away from the pad region 40 of the gate wire 51 in the downward direction of the paper surface. As a result, the plurality of emitter electrode connection regions 70 are arranged in a zigzag (staggered) manner.

[0149] Compared with Embodiment 12, the current balance within the semiconductor device 100 becomes uniform, and thus the SOA tolerance is improved.

[0150] In addition, each embodiment can be freely combined, or appropriately modified, omitted.

[0151] <Notes>

[0152] Hereinafter, each mode of the present application will be described as notes.

[0153] (Note 1)

[0154] A semiconductor device, wherein:

[0155] a plurality of active trench gates formed in a cell region of a semiconductor substrate;

[0156] an emitter electrode disposed on the cell region;

[0157] a gate wiring disposed outside the emitter electrode and electrically connected to the plurality of active trench gates; and

[0158] a gate finger wiring electrically connected to the gate wiring and extending over the cell region,

[0159] one end of the gate finger wiring is connected to the gate wiring, and the other end of the gate finger wiring does not reach the gate wiring,

[0160] the emitter electrodes adjacent across the gate finger wiring are electrically connected through an emitter electrode junction portion disposed in a region between the other end of the gate finger wiring and the gate wiring,

[0161] the active trench gate includes:

[0162] a first active trench gate extending in a first direction intersecting an extending direction of the gate finger wiring; and

[0163] a second active trench gate connected to the first active trench gate under the emitter electrode junction portion, extending in a second direction parallel to the extending direction of the gate finger wiring, and led out under the gate finger wiring or the gate wiring.

[0164] (Note 2)

[0165] The semiconductor device according to Note 1, wherein,

[0166] a pitch of the first active trench gate is 2.4 μm,

[0167] if a length of the first direction of the emitter electrode junction portion is set as x, a length of the second direction of the emitter electrode junction portion is set as y, a thickness of the emitter electrode junction portion is set as z, and a resistivity of the emitter electrode junction portion is set as p,

[0168] then the relationship of 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<5.0[μH] and ρx / yz<7.5[mΩ] is satisfied.

[0169] (Paragraph 3)

[0170] The semiconductor device according to any one of Paragraphs 1 to 3, wherein

[0171] The first active-trench gate has a pitch of 4.0 μm,

[0172] If a length of the emitter electrode connecting portion in the first direction is set as x, a length of the emitter electrode connecting portion in the second direction is set as y, a thickness of the emitter electrode connecting portion is set as z, and a resistivity of the emitter electrode connecting portion is set as ρ,

[0173] then the relationship of 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<2.5[μH] and ρx / yz<3.0[mΩ] is satisfied.

[0174] (Paragraph 4)

[0175] The semiconductor device according to any one of Paragraphs 1 to 3, wherein

[0176] The third active-trench gate electrically connects between the first active-trench gates adjacent to each other and extends in the second direction under the emitter electrode connecting portion.

[0177] (Paragraph 5)

[0178] The semiconductor device according to any one of Paragraphs 1 to 4, wherein

[0179] The dummy trench gate is arranged between the first active-trench gates,

[0180] The dummy trench gate extends in the first direction and has a pattern that is interrupted in a portion where the second active-trench gate is arranged.

[0181] (Paragraph 6)

[0182] The semiconductor device according to any one of Paragraphs 1 to 5, wherein

[0183] Both the second active-trench gate that is led out under the gate finger wiring and the second active-trench gate that is led out under the gate wiring are provided.

[0184] (Paragraph 7)

[0185] The semiconductor device according to any one of the Embodiments 1 to 6, wherein

[0186] The p-type layer deeper than the active trench gate is formed under the emitter electrode connecting portion in the semiconductor substrate.

[0187] (Embodiment 8)

[0188] The semiconductor device according to any one of the Embodiments 1 to 7, wherein

[0189] The emitter electrode connecting portion is connected to a p-type contact layer formed in the semiconductor substrate.

[0190] (Embodiment 9)

[0191] The semiconductor device according to any one of the Embodiments 1 to 8, wherein

[0192] The width of the active trench gate is locally widened under the emitter electrode connecting portion.

[0193] (Embodiment 10)

[0194] The semiconductor device according to any one of the Embodiments 1 to 9, wherein

[0195] The corner portion of the active trench gate disposed under the emitter electrode connecting portion is in a rounded shape.

[0196] (Embodiment 11)

[0197] The semiconductor device according to any one of the Embodiments 1 to 10, wherein

[0198] A plurality of the gate finger wirings are provided.

[0199] (Embodiment 12)

[0200] The semiconductor device according to Embodiment 11, wherein

[0201] The plurality of gate finger wirings are arranged in a staggered manner at portions connected to the gate wiring.

Claims

1. A semiconductor device, characterized by comprising: Possessing: a plurality of active trench gates formed in a cell region of a semiconductor substrate; an emitter electrode disposed on the cell region; a gate wiring disposed outside the emitter electrode and electrically connected to the plurality of active trench gates; and a gate finger wiring electrically connected to the gate wiring and extending over the cell region, one end of the gate finger wiring is connected to the gate wiring, the other end of the gate finger wiring does not reach the gate wiring, the emitter electrodes adjacent across the gate finger wiring are electrically connected through an emitter electrode junction portion disposed in a region between the other end of the gate finger wiring and the gate wiring, the active trench gate includes: a first active trench gate extending in a first direction intersecting the extending direction of the gate finger wiring; and a second active trench gate connected to the first active trench gate under the emitter electrode junction portion, extending in a second direction parallel to the extending direction of the gate finger wiring, and led out under the gate finger wiring or the gate wiring.

2. The semiconductor device according to claim 1, wherein the pitch of the first active trench gate is 2.4 μm, if a length of the first direction of the emitter electrode junction portion is set as x, a length of the second direction of the emitter electrode junction portion is set as y, a thickness of the emitter electrode junction portion is set as z, and a resistivity of the emitter electrode junction portion is set as p, then the following relationships are satisfied: 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<5.0[μH], and p x / yz<7.5[mΩ].

3. The semiconductor device according to claim 1, wherein the pitch of the first active trench gate is 4.0 μm, if a length of the first direction of the emitter electrode junction portion is set as x, a length of the second direction of the emitter electrode junction portion is set as y, a thickness of the emitter electrode junction portion is set as z, and a resistivity of the emitter electrode junction portion is set as p, then the following relationships are satisfied: 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<2.5[μH], and p x / yz<3.0[mΩ].

4. The semiconductor device according to any one of claims 1 to 3, wherein a third active trench gate electrically connecting the adjacent first active trench gates under the emitter electrode junction portion and extending in the second direction is provided.

5. The semiconductor device according to any one of claims 1 to 4, wherein a dummy trench gate is disposed between the first active trench gates, the dummy trench gate extends in the first direction and has a pattern that is interrupted in a portion where the second active trench gate is disposed.

6. The semiconductor device according to any one of claims 1 to 5, wherein ​ ​ Both the second active-trench gate led out below the gate finger wiring and the second active-trench gate led out below the gate wiring are provided.

7. The semiconductor device according to any one of Claims 1 to 6, wherein A p-type layer deeper than the active-trench gate is formed under the emitter electrode connecting portion in the semiconductor substrate.

8. The semiconductor device according to any one of Claims 1 to 7, wherein The emitter electrode connecting portion is connected with a p-type contact layer formed in the semiconductor substrate.

9. The semiconductor device according to any one of Claims 1 to 8, wherein The width of the active-trench gate is locally widened under the emitter electrode connecting portion.

10. The semiconductor device according to any one of Claims 1 to 9, wherein The corner portion of the active-trench gate disposed under the emitter electrode connecting portion is in a rounded shape.

11. The semiconductor device according to any one of Claims 1 to 10, wherein A plurality of the gate finger wirings are provided.

12. The semiconductor device according to Claim 11, wherein The plurality of gate finger wirings are arranged in a staggered manner at the portions connected with the gate wiring.

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