Semiconductor device with through-vias and method for manufacturing a semiconductor device

Abstract

A semiconductor device having a through via and a method for manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor chip including: a cell region including a memory cell; a peripheral circuit region stacked on the cell region in a first direction and including a peripheral circuit element electrically connected to the memory cell; a through via penetrating the cell region and the peripheral circuit region in the first direction; a backside pad disposed below the cell region and electrically connected to the through via; and a frontside pad disposed above the peripheral circuit region and electrically connected to the through via. The cell region includes a cell insulating layer surrounding the memory cell and a cell substrate disposed below the cell insulating layer. The peripheral circuit region includes a peripheral circuit insulating layer surrounding the peripheral circuit element and a peripheral circuit substrate disposed below the peripheral circuit insulating layer. The through via penetrates the cell substrate, the cell insulating layer, the peripheral circuit substrate, and the peripheral circuit insulating layer along the first direction.

Description

Technical Field

[0001] The exemplary embodiments of this disclosure relate to semiconductor chips, semiconductor packages, and methods for manufacturing semiconductor chips. Background Technology

[0002] With the development of the electronics industry, the demand for high functionality, high speed, and miniaturization of electronic components is increasing. In response to this trend, various semiconductor chips can be stacked and mounted within a package wiring structure, or one package can be stacked on top of another. For example, package-in-package (PIP) semiconductor packages or package-on-package (POP) semiconductor packages can be used.

[0003] Meanwhile, as semiconductor packages have become highly integrated, vertical wiring structures that stack semiconductor chips vertically and electrically connect them are being used more and more. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor chip with improved capacity and a method for manufacturing the same.

[0005] Another aspect of this disclosure provides a semiconductor package with reduced warpage risk.

[0006] The technical objectives of this disclosure are not limited to those described above, and those skilled in the art can clearly understand other unstated technical objectives from the following example embodiments.

[0007] According to one aspect of this disclosure, a semiconductor device includes a semiconductor chip, the semiconductor chip comprising: a cell region including a memory cell; a peripheral circuit region stacked on the cell region in a first direction and including peripheral circuit elements electrically connected to the memory cell; a through-path penetrating the cell region and the peripheral circuit region in the first direction; a back pad disposed below the cell region and electrically connected to the through-path; and a front pad disposed above the peripheral circuit region and electrically connected to the through-path. The cell region includes a cell insulating layer surrounding the memory cell and a cell substrate disposed below the cell insulating layer. The peripheral circuit region includes a peripheral circuit insulating layer surrounding the peripheral circuit elements and a peripheral circuit substrate disposed below the peripheral circuit insulating layer, such that the peripheral circuit substrate is located between the peripheral circuit insulating layer and the cell insulating layer. The through-path penetrates the cell substrate, the cell insulating layer, the peripheral circuit substrate, and the peripheral circuit insulating layer along the first direction.

[0008] According to another aspect of this disclosure, a semiconductor device includes: a packaging substrate; a first semiconductor chip located on the packaging substrate; and a second semiconductor chip bonded to the first semiconductor chip and disposed on the first semiconductor chip in a first direction. The first semiconductor chip includes: a first cell region including a memory cell; a first peripheral circuit region including peripheral circuit elements and disposed together with the first cell region in the first direction; a first through-path penetrating the first cell region and the first peripheral circuit region; a first back pad facing the first cell region such that the first cell region is at a vertical height between the first back pad and the first peripheral circuit region, and connected to the first through-path; and a first front pad facing the first peripheral circuit region such that the first peripheral circuit region is at a vertical height between the first front pad and the first cell region, and electrically connected to the first through-path. The second semiconductor chip includes: a second cell region including a memory cell; a second peripheral circuit region including peripheral circuit elements and disposed together with the second cell region in the first direction; a second through-path penetrating the second cell region and the second peripheral circuit region; a second back pad facing the second cell region such that the second cell region is located at a vertical height between the second back pad and the second peripheral circuit region, and connected to the second through-path; and a second front pad facing the second peripheral circuit region such that the second peripheral circuit region is located at a vertical height between the second front pad and the second cell region, and electrically connected to the second through-path. The first front pad and the second front pad are bonded to each other. The first cell region includes a first cell substrate and a first cell insulating layer, and the first peripheral circuit region includes a first peripheral circuit substrate and a first peripheral circuit insulating layer. The first through-path penetrates the first unit substrate, the first unit insulating layer, the first peripheral circuit substrate, and the first peripheral circuit insulating layer along the first direction. The second unit region includes the second unit substrate and the second unit insulating layer. The second peripheral circuit region includes the second peripheral circuit substrate and the second peripheral circuit insulating layer. The second through-path penetrates the second unit substrate, the second unit insulating layer, the second peripheral circuit substrate, and the second peripheral circuit insulating layer along the first direction.

[0009] According to another aspect of this disclosure, a semiconductor device includes: a first semiconductor chip; a second semiconductor chip, the second semiconductor chip being bonded to the first semiconductor chip and disposed on the first semiconductor chip in a first direction; and a third semiconductor chip, the third semiconductor chip being bonded to the second semiconductor chip and disposed on the second semiconductor chip in the first direction. The first semiconductor chip includes: a first cell region including a vertical channel transistor; a first peripheral circuit region including peripheral circuit elements electrically connected to the vertical channel transistor of the first cell region and disposed together with the first cell region in the first direction; and a first through-path penetrating the first cell region and the first peripheral circuit region. The second semiconductor chip includes: a second cell region including a vertical channel transistor; a second peripheral circuit region including peripheral circuit elements electrically connected to the vertical channel transistor of the second cell region and disposed together with the second cell region in the first direction; and a second through-path penetrating the second cell region and the second peripheral circuit region. The third semiconductor chip includes: a third cell region including a vertical channel transistor; a third peripheral circuit region including peripheral circuit elements electrically connected to the vertical channel transistor in the third cell region and arranged together with the third cell region in the first direction; and a third through-path penetrating the third cell region and the third peripheral circuit region. In the first direction, the top of the first peripheral circuit region faces the bottom of the second peripheral circuit region, and the top of the second cell region faces the bottom of the third cell region.

[0010] According to another aspect of this disclosure, a method for manufacturing a semiconductor chip includes: forming memory cells and a cell insulating layer covering the memory cells on a cell substrate; forming peripheral circuit elements and a peripheral circuit insulating layer covering the peripheral circuit elements on a peripheral circuit substrate; disposing the peripheral circuit substrate on the cell substrate and bonding the peripheral circuit substrate to the cell substrate; forming a through-path penetrating the cell substrate and the peripheral circuit substrate; forming a chip wiring structure electrically connected to the through-path and the peripheral circuit elements on the through-path and the peripheral circuit elements; forming a front pad electrically connected to the chip wiring structure on the chip wiring structure; and forming a back pad connected to the through-path below the cell substrate and the through-path.

[0011] According to another aspect of this disclosure, the through-path includes: a first portion, the first portion penetrating the unit substrate and the unit insulating layer; and a second portion, the second portion penetrating the peripheral circuit substrate and the peripheral circuit insulating layer, and forming the through-path includes: forming the first portion penetrating the unit substrate and the unit insulating layer before bonding the peripheral circuit substrate to the unit substrate; forming the second portion penetrating the peripheral circuit substrate and the peripheral circuit insulating layer before bonding the peripheral circuit substrate to the unit substrate; and connecting the first portion and the second portion.

[0012] According to another aspect of this disclosure, the through-path includes: a first portion, the first portion penetrating the cell substrate and the cell insulating layer; and a second portion, the second portion penetrating the peripheral circuit substrate and the peripheral circuit insulating layer, and forming the through-path includes: forming the first portion penetrating the cell substrate and the cell insulating layer before bonding the peripheral circuit substrate to the cell substrate; forming a trench penetrating the second portion of the peripheral circuit substrate and the peripheral circuit insulating layer and exposing at least a portion of the first portion after bonding the peripheral circuit substrate to the cell substrate; and forming the second portion within the trench of the second portion.

[0013] According to another aspect of this disclosure, bonding the peripheral circuit substrate to the unit substrate includes bonding the unit insulating layer and the peripheral circuit substrate.

[0014] According to another aspect of this disclosure, forming the through-path includes: after bonding the peripheral circuit substrate onto the unit substrate, forming a through-path trench that penetrates the unit substrate, the unit insulating layer, the peripheral circuit substrate, and the peripheral circuit insulating layer; and forming a through-path insulating layer surrounding the through-path and the through-path within the through-path trench.

[0015] Details of exemplary embodiments of this disclosure are included in the detailed description and the accompanying drawings. Attached Figure Description

[0016] These and / or other aspects, features, and advantages of this disclosure will become clear and more readily understood from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic diagram showing a cross-section of a semiconductor chip according to some example embodiments; Figure 2A It is shown Figure 1 An exemplary enlarged view of part P; Figure 2B It is shown Figure 2A An exemplary enlarged view of part of Q; Figure 3 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments; Figure 4 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments; Figure 5 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments; Figure 6 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments; Figure 7 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments; Figure 8 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments; Figure 9 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments; Figure 10 This is a schematic diagram showing a cross-section of a semiconductor package according to some example embodiments; Figures 11 to 15 This is an exemplary diagram illustrating intermediate operations used to explain the method for manufacturing the semiconductor chip shown in FIG2; Figures 16 to 22 This is to illustrate the use of [materials] in manufacturing. Figure 5 An exemplary diagram of intermediate operations of a method for a semiconductor chip is shown. Detailed Implementation

[0017] The exemplary embodiments described in this specification and the configurations shown in the accompanying drawings represent merely exemplary embodiments of this disclosure and do not cover all the technical concepts of this disclosure. Therefore, it should be understood in this application that various equivalent forms and modifications are possible and can be used as alternatives.

[0018] In the following description, elements described in the singular may apply to elements shown as provided in the plural, unless otherwise clearly indicated by the context. Terms such as “comprising or including” should be understood to indicate the presence of features, quantities, steps, operations, elements, components, or combinations thereof described in this specification, and these terms do not preclude the presence or possibility of one or more additional features, quantities, steps, operations, elements, components, or combinations thereof. Throughout the specification, when an component is described as “comprising” a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context otherwise indicates. On the other hand, the term “composed of” indicates that an component is formed solely by the listed (one or more) elements.

[0019] Furthermore, terms such as "first" and "second" can be used to describe various components, but components are not limited by the terms, and these terms can simply be used to distinguish one component from another. Within the scope of the technical concept of this disclosure, in the specification or claims, a first component may be designated as a second component, and similarly, a second component may be designated as a first component. Additionally, in the drawings, the shape or size of components may be exaggerated to emphasize clarity of description.

[0020] Furthermore, in the following description, terms such as above, upper part, lower part, lower part, side surface, front side, and back side are expressed based on the orientation shown in the accompanying drawings, and the expressions may be expressed differently when the orientation changes.

[0021] An element, layer, or portion of an element / layer is described as extending "longitudinally" in a particular direction, having a length in that direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0022] It will be understood that when an element is described as being "connected" or "bonded" to another element or "on" another element, it is capable of being directly connected or bonded to or on another element, or there may be intermediate elements present. In contrast, when an element is described as being "directly connected" or "directly bonded" to another element or "in contact" with another element or "in contact with" another element (or any form of using the word "in contact"), there are no intermediate elements at the point of contact. Elements described as being "connected" can be physically connected and / or electrically connected.

[0023] In the following description, exemplary embodiments according to the present disclosure are described with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram showing a cross-section of a semiconductor chip according to some example embodiments. Figure 2A It is shown Figure 1An exemplary enlarged view of part P. Figure 2B It is shown Figure 2A An exemplary enlarged view of part Q.

[0025] refer to Figure 1 , Figure 2A and Figure 2B According to some example embodiments, the semiconductor chip 10 may include a cell region 100, a peripheral circuit region 200, a through path 300, a chip wiring structure 420, a back pad 430, and a front pad 440.

[0026] According to some example embodiments, semiconductor chip 10 may be an integrated circuit (IC) in which hundreds to millions of semiconductor devices or more devices are integrated on a single chip. For example, semiconductor chip 10 may be a volatile memory chip such as dynamic random access memory (DRAM) or static random access memory (SRAM). Alternatively, semiconductor chip 10 may be a non-volatile memory chip such as flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (RRAM). As another example, semiconductor chip 10 may be a logic chip. Semiconductor chip 10 may be an application processor (AP), such as a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, or microcontroller, but is not limited thereto.

[0027] According to some example embodiments, cell region 100 may include a variety of semiconductor elements. Cell region 100 may include a variety of microelectronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) such as complementary metal-oxide-semiconductor (CMOS) transistors, system-level integration (LSI), flash memory, DRAM, SRAM, electrically erasable programmable read-only memory (EEPROM), PRAM, MRAM, RRAM, image sensors such as CMOS imaging sensors (CIS), microelectromechanical systems (MEMS), active elements, and passive elements.

[0028] According to some example embodiments, cell region 100 may include cell substrate 110, cell insulating layer 120, memory cells (a combination of 130 and 140) and cell wiring 150.

[0029] According to some example embodiments, the unit substrate 110 may be, for example, bulk silicon or silicon-on-insulator (SOI). As another example, the unit substrate 110 may be a silicon substrate. As yet another example, the unit substrate 110 may include, but is not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead bismuthide, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0030] According to some example embodiments, the cell substrate 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures. The cell substrate 110 may have various element isolation structures, such as shallow trench isolation (STI) structures.

[0031] According to some example embodiments, the cell insulating layer 120 may be disposed on the cell substrate 110 in a first direction D1. The first direction D1 may indicate the orientation in which the cell substrate 110 and the cell insulating layer 120 are arranged. For example, the first direction D1 may indicate a direction intersecting the upper or lower surface of the cell substrate 110, and may be a vertical direction perpendicular to the top surface of the cell substrate 110. The cell substrate 110 and the cell insulating layer 120 may be arranged relative to each other in the first direction D1. The cell insulating layer 120 may be disposed between the cell substrate 110 and the peripheral circuit substrate 210 in the first direction D1. The cell insulating layer 120 may surround the memory cells (a combination of 130 and 140). The cell insulating layer 120 may cover the memory cells (a combination of 130 and 140).

[0032] According to some example embodiments, the unit insulating layer 120 may include at least one of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), tetraethyl orthosilicate (TEOS), and combinations thereof. The unit insulating layer 120 may include a material different from the material of the unit substrate 110.

[0033] According to some example embodiments, memory cells (a combination of 130 and 140) may be disposed in cell region 100. The memory cells (a combination of 130 and 140) may be disposed above cell substrate 110. The memory cells (a combination of 130 and 140) may be disposed within cell insulating layer 120. For example, the memory cells (a combination of 130 and 140) may be DRAM cells. Each memory cell (a combination of 130 and 140) may each include a vertical channel transistor 130 and a capacitor 140. The memory cells may be arranged in an array pattern to form a memory cell array.

[0034] According to some example embodiments, each vertical channel transistor (VCT) 130 may include a channel layer 131, a gate electrode 132, a gate insulating layer 133, and a bit line 134. Multiple channel layers 131 may be connected to the bit line 134.

[0035] According to some example embodiments, the channel layer 131 may extend in a first direction D1. The channel layer 131 may extend longitudinally in the first direction D1, which intersects with the cell substrate 110. For example, VCT may indicate a structure in which the channel length of the channel layer 131 extends from the cell substrate 110 in a vertical direction. For example, the channel layer 131 may extend longitudinally in a vertical direction (e.g., the first direction D1).

[0036] According to some example embodiments, the channel layer 131 may be one of a plurality of channel layers 131 arranged in a matrix, the plurality of channel layers 131 being spaced apart at a vertical height below the bit line 134 in a second direction D2 and a third direction D3. The second direction D2 and the third direction D3 may intersect with the first direction D1. The second direction D2 and the third direction D3 may intersect each other. The second direction D2 and the third direction D3 may represent directions parallel to the upper or lower surface of the cell substrate 110. The second direction D2 and the third direction D3 may be horizontal directions perpendicular to each other and perpendicular to the vertical direction. Each channel layer 131 may have a first width along the second direction D2 and a height along the first direction D1, and the height may be greater than the width. For example, the height of the channel layer 131 may be approximately two to ten times the width of the channel layer 131, but is not limited thereto. Each channel layer 131 may also have a second width along the third direction D3. The bottom of the channel layer 131 can be used as a first source / drain region, and the upper part of the channel layer 131 can be used as a second source / drain region. The portion of the channel layer 131 located between the first source / drain region and the second source / drain region can be used as a channel region (not shown).

[0037] According to some example embodiments, the channel layer 131 may include an oxide semiconductor, such as indium gallium zinc oxide (InxGayZnzO), indium gallium silicon oxide (InxGaySizO), indium tin zinc oxide (InxSnyZnzO), indium zinc oxide (InxZnyO), zinc oxide (ZnxO), zinc tin oxide (ZnxSnyO), zinc oxynitride (ZnxOyN), zirconium tin zinc oxide (ZrxZnySnzO), tin oxide (SnxO), hafnium indium zinc oxide (HfxInyZnzO), gallium zinc tin oxide (GaxZnySnzO), aluminum zinc tin oxide (AlxZnySnzO), yttrium gallium zinc oxide (YbxGayZnzO), indium gallium oxide (InxGayO), or combinations thereof. The channel layer 131 may comprise a single layer or multiple layers of the oxide semiconductor. In some example embodiments, the channel layer 131 may have a bandgap energy greater than that of silicon. For example, channel layer 131 may have a bandgap energy of approximately 1.5 eV to 5.6 eV. For example, channel layer 131 may have optimal channel performance with a bandgap energy of approximately 2.0 eV to 4.0 eV. For example, channel layer 131 may be polycrystalline or amorphous, but is not limited thereto. In some example embodiments, channel layer 131 may comprise a two-dimensional (2D) semiconductor material, and for example, the 2D semiconductor material may comprise graphene, carbon nanotubes, or combinations thereof.

[0038] According to some example embodiments, the gate electrode 132 may extend on two side surfaces of the channel layer 131 in a first direction D1 and a third direction D3. The gate electrode 132 may include two gate electrodes 132 (e.g., two gate sub-electrodes) facing opposing side surfaces of the channel layer 131 arranged in a second direction D2. Each gate electrode 132 may extend longitudinally in the third direction D3. Since a channel layer 131 is disposed between the two gate electrodes 132, the semiconductor device can have a dual-gate transistor structure. However, this disclosure is not limited thereto, and a single-gate transistor structure can also be implemented when one of the two gate electrodes 132 is omitted and a single gate electrode 132 is formed facing one side surface of the channel layer 131.

[0039] According to some example embodiments, the gate electrode 132 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the gate electrode 132 may be composed of doped polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), niobium nitride (NbN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicon silicide (TaSi), tantalum silicon nitride (TaSiN), titanium ruthenium nitride (RuTiN), nickel silicide (NiSi), cobalt silicide (CoSi), iridium oxide (IrOx), ruthenium oxide (RuOx), or combinations thereof, but is not limited thereto.

[0040] According to some example embodiments, the gate insulating layer 133 may surround the side surface of the channel layer 131 and be located between the channel layer 131 and the gate electrode 132. For example, the entire side surface of the channel layer 131 may be surrounded by the gate insulating layer 133 (e.g., when viewed from a top view and the channel layer 131 has a circular or polygonal shape), and a portion of the side surface of the gate electrode 132 may contact the gate insulating layer 133. In other example embodiments, the gate insulating layer 133 may extend in the extension direction of the gate electrode 132 (i.e., the first direction D1 and the third direction D3), and among the side surfaces of the channel layer 131, only the two side surfaces facing the gate electrode 132 may contact the gate insulating layer 133.

[0041] According to some example embodiments, the gate insulating layer 133 may be composed of a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. The high-k dielectric layer may be composed of a metal oxide or a metal oxynitride. For example, the high-k dielectric layer that can be used as the gate insulating layer 133 may be composed of hafnium dioxide (HfO2), hafnium silicate (HfSiO), hafnium oxysilane (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof, but is not limited thereto.

[0042] According to some example embodiments, bit line 134 may be disposed over channel layer 131 and gate electrode 132 in a first direction D1. Bit line 134 may extend in a second direction D2 (e.g., longitudinally).

[0043] According to some example embodiments, bit line 134 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, bit line 134 may be composed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof, but is not limited thereto. Bit line 134 may comprise a single layer or multiple layers of the above-described materials. In some example embodiments, bit line 134 may comprise a 2D semiconductor material, for example, a 2D semiconductor material may comprise graphene, carbon nanotubes, or combinations thereof.

[0044] According to some example embodiments, a connection pad 135 may be disposed between the vertical channel transistor 130 and the capacitor 140. The connection pad 135 may connect the vertical channel transistor 130 and the capacitor 140. The connection pad 135 may overlap with the channel layer 131 of the vertical channel transistor 130 and the first electrode 141 of the capacitor 140 in the first direction D1. The connection pad 135 may be composed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof, but is not limited thereto.

[0045] According to some example embodiments, capacitor 140 may be connected to vertical channel transistor 130. Capacitor 140 may be arranged together with vertical channel transistor 130 in a first direction D1. Capacitor 140 may include a first electrode 141, a dielectric layer 142, a second electrode 143, and a support structure 144.

[0046] According to some example embodiments, the first electrode 141 may be disposed above the unit substrate 110. The first electrode 141 may be disposed below the bonding pad 135. The first electrode 141 may be connected to the bonding pad 135. Each first electrode 141 may have a pillar shape. The first electrode 141 may extend longitudinally in the thickness direction of the unit substrate 110. The length of the first electrode 141 extending in the first direction D1 is greater than the length of the first electrode 141 extending in the second direction D2 parallel to the unit substrate 110.

[0047] According to some example embodiments, a set of first electrodes 141 may be repeatedly arranged along a second direction D2 and a third direction D3. The first electrodes 141 repeatedly arranged in the second direction D2 may not be arranged in a straight line along the second direction D2. The first electrodes 141 repeatedly arranged in the second direction D2 may be arranged in a zigzag pattern.

[0048] According to some example embodiments, the first electrode 141 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide), but is not limited thereto.

[0049] According to some example embodiments, a dielectric layer 142 may be formed on the first electrode 141 and the support structure 144. The dielectric layer 142 may extend along the surface of the first electrode 141 and the surface of the support structure 144.

[0050] According to some example embodiments, the dielectric layer 142 may include, for example, a high dielectric constant material, including silicon oxide, silicon nitride, silicon oxynitride, and metals. The dielectric layer 142 is shown as a single layer for ease of illustration only, but is not limited thereto.

[0051] According to some example embodiments, dielectric layer 142 may include a stacked layer structure in which zirconium oxide, aluminum oxide and zirconium oxide are stacked sequentially.

[0052] According to some example embodiments, dielectric layer 142 may be a dielectric layer including hafnium (Hf). Dielectric layer 142 may have a stacked structure of ferroelectric material layer and paraelectric material layer.

[0053] According to some example embodiments, the ferroelectric material layer may possess ferroelectric properties. The ferroelectric material layer may have a thickness sufficient to possess ferroelectric properties. The range of the thickness of the ferroelectric material layer with ferroelectric properties may vary depending on the ferroelectric material.

[0054] For example, the ferroelectric material layer may include a single metal oxide. The ferroelectric material layer may include a single metal oxide layer. Here, the single metal oxide may be a binary compound composed of a metal and oxygen. The ferroelectric material layer including the single metal oxide may have an orthorhombic crystal system.

[0055] As an example, the metal included in the single metal oxide layer can be hafnium (Hf). The single metal oxide layer can be a hafnium oxide layer (HfO). Here, the hafnium oxide layer can have a chemical formula corresponding to stoichiometry or a chemical formula not corresponding to stoichiometry.

[0056] As another example, the metal included in the single metal oxide layer can be one of the rare earth metals belonging to the lanthanides. The single metal oxide layer can be a rare earth metal oxide layer belonging to the lanthanides. Here, the rare earth metal oxide layer belonging to the lanthanides can have a chemical formula corresponding to stoichiometry or a chemical formula not corresponding to stoichiometry. When the ferroelectric material layer includes a single metal oxide layer, the ferroelectric material layer can have a thickness, for example, greater than or equal to 1 nanometer (nm) and equal to or less than 10 nm.

[0057] For example, the ferroelectric material layer may include a bimetallic oxide layer. Here, the bimetallic oxide may be a ternary compound composed of two metals and oxygen. The ferroelectric material layer including the bimetallic oxide may have an orthorhombic crystal system.

[0058] According to some example embodiments, the metals included in the bimetallic oxide layer may be, for example, hafnium (Hf) and zirconium (Zr). The bimetallic oxide layer may be a hafnium zirconium oxide layer (Hf... x Zr (1-x) O). In the bimetallic oxide layer, x can be greater than or equal to 0.2 and equal to or less than 0.8. Here, the hafnium zirconium oxide layer (Hf x Zr (1-x) O) may have a chemical formula corresponding to stoichiometry or a chemical formula not corresponding to stoichiometry. When the ferroelectric material layer includes a bimetallic oxide layer, the ferroelectric material layer may have a thickness, for example, greater than or equal to 1 nm and equal to or less than 20 nm.

[0059] For example, the paraelectric material layer can be a dielectric layer including zirconium (Zr) or a stacked layer including zirconium (Zr), but is not limited to these. Even with the same chemical formula, depending on the crystal structure of the dielectric material, it may exhibit ferroelectric or paraelectric properties.

[0060] According to some example embodiments, paraelectric materials can have a positive dielectric constant, and ferroelectric materials can have a negative dielectric constant within a predetermined range. For example, paraelectric materials can have a positive capacitance, and ferroelectric materials can have a negative capacitance.

[0061] Generally, when two or more capacitors with positive capacitance are connected in series, the sum of their capacitances decreases. However, when a negative capacitor with negative capacitance and a positive capacitor with positive capacitance are connected in series, the sum of their capacitances increases.

[0062] According to some example embodiments, the second electrode 143 may be disposed on the dielectric layer 142. The second electrode 143 may be disposed between two support structures 144 spaced apart in the first direction D1. The second electrode 143 may be disposed below the first electrode 141 and the support structures 144. The second electrode 143 may extend along the contour of the dielectric layer 142. The second electrode 143 may include, for example, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, or tantalum), conductive metal oxides (e.g., iridium oxide or niobium oxide), etc., but is not limited thereto.

[0063] According to some example embodiments, a plurality of support structures 144 may be spaced apart in a first direction D1. The support structures 144 may overlap with the first electrodes 141 in a second direction D2. The support structures 144 may be disposed between the plurality of first electrodes 141 spaced apart in the second direction D2. The support structures 144 may support the first electrodes 141.

[0064] According to some example embodiments, the support structure 144 may include an insulating material. For example, the support structure 144 may include at least one of silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonoxylate, silicon oxynitride, silicon oxide, and silicon carbonoxylate.

[0065] According to some example embodiments, cell wiring 150 may be disposed in cell region 100. Cell wiring 150 may be disposed within cell insulating layer 120. Cell wiring 150 may be electrically connected to vertical channel transistor 130 and capacitor 140 in cell region 100.

[0066] According to some example embodiments, the cell wiring 150 may include metal wiring layers and via plugs. For example, the cell wiring 150 may be a multilayer structure in which two or more metal wiring layers or two or more via plugs are stacked alternately. The cell wiring 150 may include a conductive material. For example, the cell wiring 150 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but is not limited thereto.

[0067] According to some example embodiments, a peripheral circuit region 200 may be disposed on a unit region 100. The peripheral circuit region 200 may be arranged together with the unit region 100 in a first direction D1. The peripheral circuit region 200 may overlap with the unit region 100 in the first direction D1. The peripheral circuit region 200 may be coupled to the unit region 100 in the first direction D1. The peripheral circuit region 200 may include peripheral circuitry for operating the storage units (a combination of 130 and 140) of the control unit region 100.

[0068] According to some example embodiments, the peripheral circuit region 200 may include a peripheral circuit substrate 210, a peripheral circuit insulating layer 220, a peripheral circuit element 230, a connection path 240, and a peripheral circuit wiring 250.

[0069] According to some example embodiments, a peripheral circuit substrate 210 may be disposed above the unit substrate 110 and the unit insulating layer 120. The peripheral circuit substrate 210 may be bonded to the unit insulating layer 120, for example, via a direct insulator-to-insulator bonding. The peripheral circuit substrate 210 may be disposed between the unit insulating layer 120 and the peripheral circuit insulating layer 220 in a first direction D1.

[0070] According to some example embodiments, the peripheral circuit substrate 210 may be, for example, bulk silicon or silicon-on-insulator (SOI). As another example, the peripheral circuit substrate 210 may be a silicon substrate. As yet another example, the peripheral circuit substrate 210 may include, but is not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead bismuthide, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0071] According to some example embodiments, the peripheral circuit substrate 210 may include conductive regions, such as impurity-doped wells or impurity-doped structures. The peripheral circuit substrate 210 may have various element isolation structures, such as STI structures.

[0072] According to some example embodiments, the peripheral circuit insulating layer 220 may be disposed on the peripheral circuit substrate 210 in a first direction D1. The peripheral circuit substrate 210 and the peripheral circuit insulating layer 220 may be arranged together on each other in the first direction D1. The peripheral circuit insulating layer 220 may be disposed between the peripheral circuit substrate 210 and the interlayer insulating layer 410 in the first direction D1. The peripheral circuit insulating layer 220 may surround the peripheral circuit element 230. The peripheral insulating layer 220 may cover the peripheral circuit element 230.

[0073] According to some example embodiments, the peripheral circuit insulating layer 220 may include at least one of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), TEOS, and combinations thereof.

[0074] According to some example embodiments, the semiconductor chip 10 may have a cell-on-periphery (COP) structure, wherein cell regions 100 and peripheral circuit regions 200 are stacked vertically. The capacity of the semiconductor chip 10 can be improved by vertically stacking the cell regions 100 and peripheral circuit regions 200. According to example embodiments of this disclosure, the capacity of the semiconductor chip can be improved. Cell substrate 110, cell insulating layer 120, peripheral circuit substrate 210, and peripheral circuit insulating layer 220 may be stacked sequentially in a first direction D1. Cell substrate 110 and peripheral circuit substrate 210 may include materials or material compositions different from those of cell insulating layer 120 and peripheral circuit insulating layer 220. Cell insulating layer 120 and peripheral circuit insulating layer 220 may include materials or material compositions different from those of cell substrate 110 and peripheral circuit substrate 210. For example, cell insulating layer 120 and peripheral circuit insulating layer 220 may include silicon oxide but not bulk silicon, and cell substrate 110 and peripheral circuit substrate 210 may include bulk silicon.

[0075] According to some example embodiments, peripheral circuit element 230 may be disposed on peripheral circuit substrate 210. Peripheral circuit element 230 may be disposed within peripheral circuit insulating layer 220. Peripheral circuit element 230 may be connected to memory cells (a combination of 130 and 140) via connection path 240. For example, peripheral circuit element 230 may be configured with various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, subword line drivers, or data input / output circuits, but is not limited thereto.

[0076] According to some example embodiments, the connection path 240 can connect (e.g., electrically connect) the cell region 100 and the peripheral circuit region 200. For example, the connection path 240 can connect the peripheral circuit wiring 250 of the peripheral circuit region 200 and the cell wiring 150 of the cell region 100. The connection path 240 can extend in a first direction D1. The connection path 240 can penetrate the peripheral circuit substrate 210. The connection path 240 can include a conductive material. For example, the connection path 240 can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but is not limited thereto.

[0077] According to some example embodiments, peripheral circuit wiring 250 may be disposed in peripheral circuit region 200. Peripheral circuit wiring 250 may be disposed above peripheral circuit substrate 210. Peripheral circuit wiring 250 may be disposed within peripheral circuit insulating layer 220. Peripheral circuit wiring 250 may be electrically connected to peripheral circuit element 230.

[0078] According to some example embodiments, peripheral circuit wiring 250 may include metal wiring layers and via plugs. For example, peripheral circuit wiring 250 may be a multilayer structure in which more than two metal wiring layers or more than two via plugs are stacked alternately. Peripheral circuit wiring 250 may include conductive materials. For example, peripheral circuit wiring 250 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but is not limited thereto.

[0079] According to some example embodiments, the through-path 300 can penetrate at least a portion of the semiconductor chip 10. The through-path 300 can penetrate the cell region 100 and the peripheral circuit region 200. The through-path 300 can penetrate the cell substrate 110, the cell insulating layer 120, the peripheral circuit substrate 210, and the peripheral circuit insulating layer 220. The through-path 300 can extend in a first direction D1. The through-path 300 can be electrically connected to the chip wiring structure 420. The through-path 300 can be spaced apart from the memory cells (a combination of 130 and 140), cell wiring 150, peripheral circuit elements 230, and peripheral circuit wiring 250 in a second direction D2. Multiple through-paths 300 can be configured to be spaced apart in the second direction D2 and the third direction D3.

[0080] According to some example embodiments, the width of the through-path 300 in the second direction D2 can decrease along the direction from the peripheral circuit region 200 toward the cell region 100 (e.g., in the vertical direction from the peripheral circuit substrate 210 toward the cell substrate 110). The width of the through-path 300 in the second direction D2 can decrease as the distance from the backside pad 430 decreases. The cross-section of the through-path 300 can have a gradually narrowing shape.

[0081] According to some example embodiments, the through-path 300 may be electrically connected to the back pad 430 and the front pad 440. The through-path 300 may contact (e.g., be directly physically connected to) the back pad 430. The through-path 300 may be electrically connected to the front pad 440 via the chip wiring structure 420. As described above, "front" refers to the active surface of a semiconductor device or portion (e.g., the active surface of a cell region or peripheral circuit region forming active circuit elements such as transistors), and "back" refers to the surface opposite the active surface (e.g., a passive surface that does not include active circuit elements). As described herein, a semiconductor device may refer to a semiconductor chip such as a memory chip or a logic chip (e.g., an integrated circuit formed on a bare die from a wafer), or may refer to a semiconductor package comprising a plurality of semiconductor chips formed on a package substrate, or a portion thereof.

[0082] exist Figure 1 In Figure 2, the through-path 300 is shown as a single layer, but the example embodiment is not limited thereto. For example, the through-path 300 may include multiple conductive layers.

[0083] According to some example embodiments, the through-path 300 may include or be formed of a conductive material. For example, the through-path 300 may be formed of a metal or alloy thereof, including, but not limited to, metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti).

[0084] exist Figure 1 In the semiconductor chip 10, the memory cells (a combination of 130 and 140) and peripheral circuit elements 230 are shown as being disposed only outside the through-paths 300 (e.g., outside the region including the through-paths 300), but the example embodiment is not limited thereto. For example, the memory cells (a combination of 130 and 140) and peripheral circuit elements 230 may be disposed between two adjacent through-paths 300 in the second direction D2 (e.g., between at least two through-paths 300 in a region including multiple through-paths 300).

[0085] According to some example embodiments, a via insulating layer 350 may surround a through-path 300. The via insulating layer 350 may cover a side surface of the through-path 300. The via insulating layer 350 may surround a side surface of the through-path 300. The via insulating layer 350 may electrically insulate the through-path 300 from the memory cells (combination of 130 and 140), cell wiring 150, peripheral circuit elements 230, and peripheral circuit wiring 250. The via insulating layer 350 may include one or more of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof.

[0086] According to some example embodiments, the chip wiring structure 420 can be disposed on the through-path 300 and the peripheral circuit region 200. The chip wiring structure 420 can be electrically connected to the through-path 300 and the peripheral circuit wiring 250. The chip wiring structure 420 can be disposed in a first direction D1 between the through-path 300 and the front pad 440.

[0087] According to some example embodiments, the chip wiring structure 420 may include metal wiring layers and via plugs. For example, the chip wiring structure 420 may be a multilayer structure in which two or more metal wiring layers or two or more via plugs are stacked alternately. The chip wiring structure 420 may include conductive materials. For example, the chip wiring structure 420 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but is not limited thereto.

[0088] According to some example embodiments, the chip wiring structure 420 may be disposed within the interlayer insulating layer 410. The interlayer insulating layer 410 can protect the chip wiring structure 420 from external impacts or moisture. The interlayer insulating layer 410 may include one or more of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), TEOS, and combinations thereof.

[0089] According to some example embodiments, a back-side pad 430 may be disposed below the cell region 100. The back-side pad 430 may face the cell region 100 in a first direction D1. For example, in the cell region 100 and the peripheral circuit region 200, the back-side pad 430 may be vertically closer to the cell region 100. The back-side pad 430 may be electrically connected to the through-path 300. The back-side pad 430 may penetrate at least a portion of the back-side passivation layer 431 and at least a portion of the back-side bonding layer 435. The bottom surface of the back-side pad 430 may be exposed to the outside from the back-side passivation layer 431 and the back-side bonding layer 435. The back-side passivation layer 431 and the back-side bonding layer 435 may surround the side surface of the back-side pad 430. The back-side passivation layer 431 and the back-side bonding layer 435 may be disposed below the cell region 100.

[0090] According to some example embodiments, the back-side pad 430 may include at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au), but is not limited thereto. The back-side passivation layer 431 may be selected from organic compounds such as photosensitive polyimide (PSPI) and inorganic compounds such as silicon oxide, silicon nitride, and silicon oxynitride. The back-side bonding layer 435 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof. The back-side bonding layer 435 may include, but is not limited to, a non-conductive film (NCF), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin. The back-side bonding layer 435 may be an adhesive tape that can fix the semiconductor chip 10 to each other. The back-side bonding layer 435 may be, for example, an adhesive tape including an epoxy component. In some example embodiments, the back-side bonding layer 435 may include silicon oxide. The back-side bonding layer 435 may include a different material than the front-side bonding layer 445.

[0091] According to some example embodiments, a front pad 440 may be disposed above the peripheral circuit region 200. The front pad 440 may be disposed on the chip wiring structure 420. The front pad 440 may be electrically connected to the chip wiring structure 420. The front pad 440 may penetrate at least a portion of the front passivation layer 441 and at least a portion of the front bonding layer 445. The top surface of the front pad 440 may be exposed to the outside of the semiconductor chip 10 from the front passivation layer 441 and the front bonding layer 445. The front passivation layer 441 and the front bonding layer 445 may surround the side surfaces of the front pad 440. The front passivation layer 441 and the front bonding layer 445 may be disposed above the peripheral circuit region 200.

[0092] According to some example embodiments, the front pad 440 may include at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au), or be formed from at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au), but is not limited thereto. The front passivation layer 441 may be selected from organic compounds such as PSPI, and inorganic compounds such as silicon oxide, silicon nitride, and silicon oxynitride. The front bonding layer 445 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof, or be formed from at least one selected from silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof. The front bonding layer 445 may include NCF, NCP, an insulating polymer, or an epoxy resin, or may be NCF, NCP, an insulating polymer, or an epoxy resin, but is not limited thereto. The front bonding layer 445 may be an adhesive tape that can fix the semiconductor chip 10 to each other. The front bonding layer 445 may be, for example, an adhesive tape comprising an epoxy component. In some example embodiments, the front bonding layer 445 may comprise silicon carbonitride (SiCN). The front bonding layer 445 may comprise a material different from the material that may comprise the back bonding layer 435.

[0093] Figure 3 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to other example embodiments. To illustrate a semiconductor chip according to other example embodiments, description and reference may be primarily made to... Figure 1 The differences from the description in Figure 2.

[0094] refer to Figure 3 The through passage 300 may include a first part 310 and a second part 320. The first part 310 and the second part 320 may be connected in a first direction D1.

[0095] According to some example embodiments, a first portion 310 may be disposed between the back-side pad 430 and the second portion 320 in a first direction D1. The first portion 310 may penetrate the cell region 100. The first portion 310 may penetrate the cell substrate 110 and the cell insulating layer 120. The first portion 310 may overlap with the cell substrate 110 and the cell insulating layer 120 in a second direction D2. The first portion 310 may overlap with the memory cells (a combination of 130 and 140) and the cell wiring 150 in the second direction D2. As the distance from the peripheral circuit region 200 decreases, the width of the first portion 310 in the second direction D2 may increase. As the distance from the back-side pad 430 decreases, the width of the first portion 310 in the second direction D2 may decrease.

[0096] According to some example embodiments, the second portion 320 may be disposed between the first portion 310 and the chip wiring structure 420 in the first direction D1. The second portion 320 may penetrate the peripheral circuit region 200. The second portion 320 may penetrate the peripheral circuit substrate 210 and the peripheral circuit insulating layer 220. The second portion 320 may overlap with the peripheral circuit substrate 210 and the peripheral circuit insulating layer 220 in the second direction D2. The second portion 320 may overlap with the peripheral circuit element 230 and the peripheral circuit wiring 250 in the second direction D2. As the distance from the cell region 100 decreases, the width of the second portion 320 in the second direction D2 may decrease. As the distance from the chip wiring structure 420 decreases, the width of the second portion 320 in the second direction D2 may increase.

[0097] According to some exemplary embodiments, the through path 300 may have steps on the boundary surface of the unit region 100 and the peripheral circuit region 200. The first portion 310 and the second portion 320 may be connected by steps on the boundary surface of the unit region 100 and the peripheral circuit region 200. For example, the side surfaces of the first portion 310 and the second portion 320 may not be connected on the same plane, but rather are staggered. The top surface of the first portion 310 and the bottom surface 320BS of the second portion 320, which are in contact with each other, may not have the same width in the second direction D2. The width of the top surface of the first portion 310 may be greater than the width of the bottom surface 320BS of the second portion 320. However, the exemplary embodiments are not limited to this. The width of the top surface of the first portion 310 may be less than the width of the bottom surface 320BS of the second portion 320.

[0098] According to some example embodiments, the first portion 310 and the second portion 320 of the through-path 300 may have different degrees of gradual narrowing towards the back pad 430. Specifically, in the second direction D2, the slope of the side surface of the first portion 310 may be different from the slope of the side surface of the second portion 320. As the distance from the back pad 430 decreases, the width of the second portion 320 in the second direction D2 may decrease more sharply than the width of the first portion 310 in the second direction D2.

[0099] According to some example embodiments, a first channel insulating layer 351 may surround a first portion 310. The first channel insulating layer 351 may cover a side surface of the first portion 310. A second channel insulating layer 352 may surround a second portion 320. The second channel insulating layer 352 may cover a side surface of the second portion 320.

[0100] Figure 4 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to other example embodiments. To illustrate a semiconductor chip according to other example embodiments, the description can be primarily based on and with reference to FIG2 and... Figure 3 The differences in the descriptions.

[0101] refer to Figure 4 At least a portion of the second part 320 may be inserted into the first part 310. At least a portion of the second part 320 may overlap with the first part 310 in the second direction D2. At least a portion of the second part 320 may be surrounded by the first part 310 (e.g., when viewed from a top view). The bottom surface 320BS of the second part and the top surface 310US of the first part may not be on the same plane. The bottom surface 320BS of the second part may be set lower than the top surface 310US of the first part. The width of the bottom surface 320BS of the second part in the second direction D2 may be less than the width of the top surface 310US of the first part in the second direction D2.

[0102] Figure 5 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to other example embodiments. To illustrate a semiconductor chip according to other example embodiments, the description can be primarily based on and referenced to Figures 2 to 3. Figure 4 The differences in the descriptions.

[0103] refer to Figure 5In the direction of movement toward cell region 100, the width of the second portion 320 in the second direction D2 may increase. In the direction of movement toward chip wiring structure 420, the width of the second portion 320 in the second direction D2 may decrease. On the boundary surface between cell region 100 and peripheral circuit region 200, the side surfaces of the first portion 310 and the second portion 320 may join at a predetermined angle. The width of the top surface 310US of the first portion in the second direction D2 and the width of the bottom surface 320BS of the second portion in the second direction D2 may be the same where they meet. However, the exemplary embodiment is not limited to this. For example, the width of the top surface 310US of the first portion in the second direction D2 and the width of the bottom surface 320BS of the second portion in the second direction D2 may be different from each other.

[0104] Figure 6 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to other example embodiments. To illustrate a semiconductor chip according to other example embodiments, the description and references are primarily intended to... Figure 1 The differences from the description in Figure 2.

[0105] refer to Figure 6 The widths of portions of the penetrating unit substrate 110 and peripheral circuit substrate 210 of the through-path 300, as well as the widths of portions of the penetrating unit insulating layer 120 and peripheral circuit insulating layer 220 of the through-path 300, can be different. In the second direction D2, the width of portions of the penetrating unit substrate 110 and peripheral circuit substrate 210 of the through-path 300 can be smaller than the width of portions of the penetrating unit insulating layer 120 and peripheral circuit insulating layer 220 of the through-path 300.

[0106] According to some example embodiments, the portions of the through-path 300 that overlap with the unit substrate 110 and the peripheral circuit substrate 210 in the second direction D2, and the portions of the through-path 300 that overlap with the unit insulating layer 120 and the peripheral circuit insulating layer 220 in the second direction D2, can be connected to each other with steps. The portions of the through-path 300 that overlap with the unit substrate 110 and the peripheral circuit substrate 210 in the second direction D2 can be more recessed than the portions of the through-path 300 that overlap with the unit insulating layer 120 and the peripheral circuit insulating layer 220 in the second direction D2. The portions of the through-path 300 that overlap with the unit insulating layer 120 and the peripheral circuit insulating layer 220 in the second direction D2 can be more protruding outward than the portions of the through-path 300 that overlap with the unit substrate 110 and the peripheral circuit substrate 210 in the second direction D2.

[0107] According to some example embodiments, the side surface of the through-path 300 may have protruding portions and recessed portions. For example, the side surface of the through-path 300 may include a portion protruding outward along the second direction D2 and a portion recessed into the through-path 300 along the second direction D2. It should be noted that in some embodiments, the recess and protrusion may also be formed on the third direction D3. Within the unit insulating layer 120 and the peripheral circuit insulating layer 220, the side surface of the through-path 300 may protrude further outward along the second direction D2 than the side surface of the through-path 300 disposed within the unit substrate 110 and the peripheral circuit insulating layer 210. Within the unit substrate 110 and the peripheral circuit insulating layer 210, the side surface of the through-path 300 may be recessed further inward along the second direction D2 than the side surface of the through-path 300 disposed within the unit insulating layer 120 and the peripheral circuit insulating layer 220.

[0108] Figure 7 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to other example embodiments. To illustrate a semiconductor chip according to other example embodiments, the description and references are primarily intended to... Figure 6 The differences in the descriptions.

[0109] refer to Figure 7 The width of a portion of the penetrating unit substrate 110 and the peripheral circuit substrate 210 of the through-path 300 in the second direction D2 may be greater than the width of a portion of the penetrating unit insulating layer 120 and the peripheral circuit insulating layer 220 of the through-path 300 in the second direction D2.

[0110] According to some example embodiments, the portions of the through-path 300 that overlap with the unit substrate 110 and the peripheral circuit substrate 210 in the second direction D2, and the portions of the through-path 300 that overlap with the unit insulating layer 120 and the peripheral circuit insulating layer 220 in the second direction D2, can be connected to each other with steps. The portions of the through-path 300 that overlap with the unit substrate 110 and the peripheral circuit substrate 210 in the second direction D2 can protrude further outward than the portions of the through-path 300 that overlap with the unit insulating layer 120 and the peripheral circuit insulating layer 220 in the second direction D2. The portions of the through-path 300 that overlap with the unit insulating layer 120 and the peripheral circuit insulating layer 220 in the second direction D2 can be more recessed inward than the portions of the through-path 300 that overlap with the unit substrate 110 and the peripheral circuit substrate 210 in the second direction D2.

[0111] According to some example embodiments, the side surface of the through-path 300 may have protruding portions and recessed portions. For example, the side surface of the through-path 300 may include a portion protruding outward along the second direction D2 and a portion recessed into the through-path 300 along the second direction D2. Within the unit substrate 110 and the peripheral circuit substrate 210, the side surface of the through-path 300 may protrude further outward along the second direction D2 than the side surfaces of the through-path 300 disposed within the unit insulating layer 120 and the peripheral circuit insulating layer 220. Within the unit insulating layer 120 and the peripheral circuit insulating layer 220, the side surface of the through-path 300 may be more recessed inward along the second direction D2 than the side surfaces of the through-path 300 disposed within the unit substrate 110 and the peripheral circuit substrate 210.

[0112] Figure 8 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to other example embodiments. To illustrate the semiconductor chip according to other example embodiments, the differences from the description referring to FIG2 will be mainly explained.

[0113] According to some example embodiments, the thickness of the back pad 430 in the first direction D1 and the thickness of the front pad 440 in the first direction D1 may be different from each other. For example, the thickness of the back pad 430 in the first direction D1 may be greater than the thickness of the front pad 440 in the first direction D1. Figure 8 The example shows that the thickness of the back pad 430 in the first direction D1 is greater than the thickness of the front pad 440 in the first direction D1, but the example embodiment is not limited to this. For example, the thickness of the back pad 430 in the first direction D1 may be thinner than the thickness of the front pad 440 in the first direction D1.

[0114] Figure 9 It is shown Figure 1 Part P is used to illustrate an exemplary enlarged view of a semiconductor chip according to some other example embodiments. To illustrate the semiconductor chip according to some other example embodiments, the differences from the description with reference to FIG2 will be mainly explained.

[0115] refer to Figure 9The side surface of the front pad 440 may have a step. The front pad 440 may include a first pad portion 440a and a second pad portion 440b. The widths of the first pad portion 440a and the second pad portion 440b in the second direction D2 may be different from each other. The first pad portion 440a may be configured to be closer to the chip wiring structure 420 than the second pad portion 440b. The width of the first pad portion 440a in the second direction D2 may be smaller than the width of the second pad portion 440b in the second direction D2. For example, the front pad 440 may be formed using a dual damascene process.

[0116] exist Figure 9 The example shows only the front pad 440, which includes a first pad portion 440a and a second pad portion 440b; however, the example embodiment is not limited to this. The back pad 430 may include a first pad portion and a second pad portion with different widths in the second direction D2.

[0117] Figure 10 This is a schematic diagram showing a cross-section of a semiconductor package according to some example embodiments.

[0118] refer to Figure 10 According to some example embodiments, a semiconductor package may include a package die 50, a plurality of semiconductor chips 10A, 10B, 10C and 10D, and a molding layer 500.

[0119] According to some example embodiments, a package die 50 may be disposed beneath a plurality of semiconductor chips 10A, 10B, 10C, and 10D. The package die 50 may be electrically connected to the plurality of semiconductor chips 10A, 10B, 10C, and 10D. The plurality of semiconductor chips 10A, 10B, 10C, and 10D may exchange electrical signals with external devices through the package die 50.

[0120] According to some example embodiments, the package die 50 can be a wiring structure for packaging. For example, the package die 50 can be a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, the package die 50 can also be a wiring structure for a wafer-level package (WLP) manufactured at the wafer level. The package die 50 can be a semiconductor chip including semiconductor elements. The package die 50 can serve as a support substrate for a semiconductor package. The package die 50 can be a buffer chip connected to multiple semiconductor chips 10A, 10B, 10C, and 10D.

[0121] In some example embodiments, the encapsulation die 50 may be an encapsulation substrate and may be a glass substrate, a ceramic substrate, or a plastic substrate, but is not limited thereto. For example, the encapsulation die 50 may include a resin impregnated together with an inorganic filler in a core material such as glass fiber, glass cloth, glass fabric, etc., such as prepreg, Ajinomoto deposited film (ABF), FR-4, or bismaleimide triazine (BT).

[0122] According to some example embodiments, the package die 50 may include, for example, bulk silicon or silicon-on-insulator (SOI). As another example, the package die 50 may be a silicon substrate. As yet another example, the package die 50 may include, but is not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead bismuthide, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0123] According to some example embodiments, the package die 50 may include conductive regions, such as impurity-doped wells or impurity-doped structures. The package die 50 may have various element isolation structures, such as STI structures.

[0124] According to some example embodiments, the package die 50 may include a body portion 51, a lower bonding pad 52, and an upper bonding pad 53.

[0125] According to some example embodiments, when the package die 50 is a PCB, the body portion 51 may be composed of at least one material selected from phenolic resin, epoxy resin, and polyimide. The package die 50 may include at least one material selected from tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene oxide, BT, thermomount, cyanate ester, and liquid crystal polymer.

[0126] According to some example embodiments, the body portion 51 may include a photoimageable dielectric. For example, the body portion 51 may include a photoimageable polymer. The photoimageable polymer may be formed as at least one of, for example, a photoimageable polyimide, polybenzoxazole, a phenolic polymer, or a benzocyclobutene polymer. As another example, the body portion 51 may be formed as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0127] Although not shown, the surface of the body portion 51 may be covered by an upper insulating layer and a lower insulating layer. The upper and lower insulating layers can protect the substrate wiring structures and other structures within the body portion 51 from external impacts or moisture. The upper and lower insulating layers may include solder resist. However, the example embodiment is not limited thereto.

[0128] According to some example embodiments, the lower bonding pad 52 may be disposed at the lower part of the body portion 51. The upper bonding pad 53 may contact the first back-side pad 430A of the first semiconductor chip 10A.

[0129] Although not shown, a substrate wiring structure may be provided within the main body portion 51. The substrate wiring structure may include wiring layers and wiring pathways connecting each wiring layer. For example, the substrate wiring structure may be a multilayer structure in which two or more wiring layers or two or more wiring pathways are stacked alternately. For example, the wiring layers may extend in a second direction D2 or in a direction intersecting the first direction D1 and the second direction D2. The wiring pathways may connect wiring layers spaced apart in the first direction D1.

[0130] According to some example embodiments, the substrate wiring structure may include or be formed of a conductive material. For example, the substrate wiring structure may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, or may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but is not limited thereto.

[0131] According to some example embodiments, external connection terminals 55 may be formed beneath the package die 50. External connection terminals 55 may be disposed on the lower bonding pad 52. External connection terminals 55 may contact the lower bonding pad 52. External connection terminals 55 may include solder balls or solder bumps, or may be solder balls or solder bumps. External connection terminals 55 may be, for example, spherical or elliptical in shape, but are not limited thereto. The number, spacing, arrangement, and shape of external connection terminals 55 may not be limited to those shown and may vary depending on the design. External connection terminals 55 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but are not limited thereto.

[0132] According to some example embodiments, the external connection terminal 55 can electrically connect the package die 50 to an external device. Therefore, the external connection terminal 55 can provide electrical signals to or from the package die 50 to an external device. For example, the external connection terminal 55 can be provided with signals input to multiple semiconductor chips 10A, 10B, 10C, and 10D. The external connection terminal 55 can also be provided with signals output from the multiple semiconductor chips 10A, 10B, 10C, and 10D.

[0133] According to some example embodiments, multiple semiconductor chips 10A, 10B, 10C, and 10D can be stacked on a package die 50. The multiple semiconductor chips 10A, 10B, 10C, and 10D can be stacked on the package die 50 in a first direction D1. Each of the multiple semiconductor chips 10A, 10B, 10C, and 10D may include a cell region 100A, 100B, 100C, or 100D, a peripheral circuit region 200A, 200B, 200C, or 200D, and a through path 300A, 300B, or 300C. The through paths 300A, 300B, and 300C included in the multiple semiconductor chips 10A, 10B, and 10C may overlap each other in the first direction D1. Elements described as “overlapping” in a particular direction are arranged relative to each other such that straight lines extending in the particular direction intersect.

[0134] According to some example embodiments, each of the plurality of semiconductor chips 10A, 10B, 10C, and 10D may be a volatile memory chip such as dynamic random access memory (DRAM) or static random access memory (SRAM). As another example, each of the plurality of semiconductor chips 10A, 10B, 10C, and 10D may be a non-volatile memory chip such as flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (RRAM). Each of the plurality of semiconductor chips 10A, 10B, 10C, and 10D may include a vertical channel transistor.

[0135] According to some example embodiments, a plurality of semiconductor chips 10A, 10B, 10C, and 10D may include a first semiconductor chip 10A, an additional second semiconductor chip 10B, an additional third semiconductor chip 10C, and an additional fourth semiconductor chip 10D. The first semiconductor chip 10A, the second semiconductor chip 10B, the third semiconductor chip 10C, and the fourth semiconductor chip 10D may be sequentially stacked on the package die 50 in a first direction D1.

[0136] According to some example embodiments, a first semiconductor chip 10A may include a first cell region 100A, a first peripheral circuit region 200A, and a first through-path 300A. The first cell region 100A may include a first cell substrate 110A and a first cell insulating layer 120A. The first peripheral circuit region 200A may include a first peripheral circuit substrate 210A and a first peripheral circuit insulating layer 220A. The first through-path 300A may penetrate the first cell substrate 110A, the first cell insulating layer 120A, the first peripheral circuit substrate 210A, and the first peripheral circuit insulating layer 220A in a first direction D1.

[0137] According to some example embodiments, each additional semiconductor chip may include additional components that may have the same structure and / or function as the components of the first semiconductor chip 10A. For example, the second semiconductor chip 10B may include a second cell region 100B, a second peripheral circuit region 200B, and a second through-path 300B. The second cell region 100B may include a second cell substrate 110B and a second cell insulating layer 120B. The second peripheral circuit region 200B may include a second peripheral circuit substrate 210B and a second peripheral circuit insulating layer 220B. The second through-path 300B may penetrate the second cell substrate 110B, the second cell insulating layer 120B, the second peripheral circuit substrate 210B, and the second peripheral circuit insulating layer 220B in a first direction D1.

[0138] According to some example embodiments, the third semiconductor chip 10C may include a third unit region 100C, a third peripheral circuit region 200C, and a third through-path 300C. The third unit region 100C may include a third unit substrate 110C and a third unit insulating layer 120C. The third peripheral circuit region 200C may include a third peripheral circuit substrate 210C and a third peripheral circuit insulating layer 220C. The third through-path 300C may penetrate the third unit substrate 110C, the third unit insulating layer 120C, the third peripheral circuit substrate 210C, and the third peripheral circuit insulating layer 220C in a first direction D1.

[0139] According to some example embodiments, unlike the first semiconductor chip 10A, the second semiconductor chip 10B, and the third semiconductor chip 10C, the fourth semiconductor chip 10D may not include through-paths and back pads.

[0140] According to some example embodiments, the first semiconductor chip 10A, the second semiconductor chip 10B, the third semiconductor chip 10C, and the fourth semiconductor chip 10D can be connected to each other in a hybrid bonding manner. For example, the first front pad 440A of the first semiconductor chip 10A and the second front pad 440B of the second semiconductor chip 10B can contact each other, thereby bonding the first semiconductor chip 10A and the second semiconductor chip 10B. The first front bonding layer 445A of the first semiconductor chip 10A and the second front bonding layer 445B of the second semiconductor chip 10B can be directly bonded.

[0141] According to some example embodiments, the first front pad 440A and the second front pad 440B can be bonded, enabling the first semiconductor chip 10A and the second semiconductor chip 10B to be physically and electrically connected. The first front bonding layer 445A of the first semiconductor chip 10A and the second front bonding layer 445B of the second semiconductor chip 10B can be bonded. The first front bonding layer 445A and the second front bonding layer 445B can be bonded via NH bonds and OH bonds, which can be achieved by bonding the first front bonding layer 445A and the second bonding layer 445B using a plasma process with N2 and O2 gases.

[0142] According to some example embodiments, the first peripheral circuit region 200A of the first semiconductor chip 10A and the second peripheral circuit region 200B of the second semiconductor chip 10B may face each other in the first direction D1. For example, the top surface of the first peripheral circuit region 200A of the first semiconductor chip 10A may face the bottom surface of the second peripheral circuit region 200B of the second semiconductor chip 10B. The first through-path 300A of the first semiconductor chip 10A and the second through-path 300B of the second semiconductor chip 10B may be electrically connected via a first front pad 440A and a second front pad 440B.

[0143] According to some example embodiments, the second back-side pad 430B of the second semiconductor chip 10B and the third back-side pad 430C of the third semiconductor chip 10C can be in contact. The second back-side pad 430B and the third back-side pad 430C can be bonded, thereby connecting the second semiconductor chip 10B and the third semiconductor chip 10C. The second back-side bonding layer 435B of the second semiconductor chip 10B and the third back-side bonding layer 435C of the third semiconductor chip 10C can be bonded. The second back-side bonding layer 435B and the third back-side bonding layer 435C can be bonded via NH bonds and OH bonds, which can be caused by bonding the second back-side bonding layer 435B and the third back-side bonding layer 435C using a plasma process with N2 gas and O2 gas.

[0144] According to some example embodiments, the second cell region 100B of the second semiconductor chip 10B and the third cell region 100C of the third semiconductor chip 10C may face each other in the first direction D1. For example, the top surface of the second cell region 100B of the second semiconductor chip 10B may face the bottom surface of the third cell region 100C of the third semiconductor chip 10C. The second through-path 300B of the second semiconductor chip 10B and the third through-path 300C of the third semiconductor chip 10C may be electrically connected through the second back-side pad 430B and the third back-side pad 430C.

[0145] According to some example embodiments, the third front pad 440C of the third semiconductor chip 10C and the fourth front pad 440D of the fourth semiconductor chip 10D can be in contact with each other. The third front pad 440C and the fourth front pad 440D can be bonded, thereby connecting the third semiconductor chip 10C and the fourth semiconductor chip 10D. The third front bonding layer 445C of the third semiconductor chip 10C and the fourth front bonding layer 445D of the fourth semiconductor chip 10D can be bonded. The third front surface bonding layer 445C and the fourth front surface bonding layer 445D can be bonded by NH bonds and OH bonds, which can be caused by bonding the third front surface bonding layer 445C and the fourth front surface bonding layer 445D using a plasma process with N2 gas and O2 gas.

[0146] According to some example embodiments, the third peripheral circuit region 200C of the third semiconductor chip 10C and the fourth peripheral circuit region 200D of the fourth semiconductor chip 10D may face each other in the first direction D1.

[0147] According to some example embodiments, some of a plurality of semiconductor chips 10A, 10B, 10C, and 10D can be bonded via front pads 440A, 440B, 440C, and 440D, and some of them can be bonded via back pads 430B and 430C. For example, with the first front pad 440A of the first semiconductor chip 10A and the second front pad 440B of the second semiconductor chip 10B bonded, each of the front surfaces of the first semiconductor chip 10A and the second semiconductor chip 10B can be bonded. The stacking direction of the first semiconductor chip 10A in the first direction D1 and the stacking direction of the second semiconductor chip 10B in the first direction D1 can be opposite, such that certain components can have mirror symmetry with respect to each other across the planes in which the two semiconductor chips are bonded. As another example, with the second back pad 430B of the second semiconductor chip 10B and the third back pad 430C of the third semiconductor chip 10C bonded, each of the back surfaces of the second semiconductor chip 10B and the third semiconductor chip 10C can be bonded. Therefore, the stacking direction of the second semiconductor chip 10B in the first direction D1 and the stacking direction of the third semiconductor chip 10C in the first direction D1 can be opposite. As described above, the stacking directions of the plurality of semiconductor chips 10A, 10B, 10C, and 10D in the first direction D1 can be set to be opposite to each other, which can reduce the warpage risk that occurs when the plurality of semiconductor chips 10A, 10B, 10C, and 10D are stacked in the same direction, causing the plurality of semiconductor chips 10A, 10B, 10C, and 10D to warp. According to the exemplary embodiments of this disclosure, the warpage risk of semiconductor packages can be reduced.

[0148] According to some example embodiments, since multiple semiconductor chips 10A, 10B, 10C, and 10D are related to a reference... Figures 1 to 9 The semiconductor chips 10 described are substantially the same, so descriptions of the various semiconductor chips 10A, 10B, 10C, and 10D are omitted below. Figure 10 The example shows four stacked semiconductor chips 10A, 10B, 10C, and 10D, but the example embodiment is not limited thereto. The number of stacked semiconductor chips 10A, 10B, 10C, and 10D may vary depending on the example embodiment.

[0149] According to some example embodiments, molding layer 500 may be formed on package die 50. Molding layer 500 may cover multiple semiconductor chips 10A, 10B, 10C, and 10D. Molding layer 500 may include polymers such as resins. For example, molding layer 500 may include epoxy molding compound (EMC), but is not limited thereto.

[0150] Although a specific example type of through path is shown as used for Figure 10 In various semiconductor chips (e.g., Figure 1 as well as Figure 2A and Figure 2B (as shown in the image), but Figure 10 Semiconductor chips can have the following properties: Figure 1 , Figure 2A , Figure 2B and Figures 3 to 9 Any different through paths described.

[0151] Figures 11 to 15 This is an exemplary diagram illustrating intermediate operations used to explain the method for manufacturing the semiconductor chip shown in FIG2.

[0152] refer to Figure 11 A unit insulating layer 120 and a peripheral circuit region 200 can be formed on the prefabricated unit substrate 110P.

[0153] According to some example embodiments, a vertical channel transistor 130, a capacitor 140, and a cell wiring 150 can be formed within a cell insulating layer 120 above a prefabricated cell substrate 110P. A peripheral circuit element 230, a peripheral circuit wiring 250, and a peripheral circuit insulating layer 220 can be formed on a peripheral circuit substrate 210. Subsequently, the peripheral circuit substrate 210 can be bonded over the prefabricated cell substrate 110P. Specifically, the peripheral circuit substrate 210, on which the peripheral circuit element 230, the peripheral circuit wiring 250, and the peripheral circuit insulating layer 220 are formed, can be bonded to the cell insulating layer 120 where the vertical channel transistor 130, the capacitor 140, and the cell wiring 150 are formed.

[0154] refer to Figure 12A through-path trench 300T is formed, penetrating at least a portion of the prefabricated unit substrate 110P, the unit insulating layer 120, the peripheral circuit substrate 210, and the peripheral circuit insulating layer 220. The through-path trench 300T may not completely penetrate the prefabricated unit substrate 110P. The through-path trench 300T may be formed as at least a portion of the prefabricated unit substrate 110P, the unit insulating layer 120, the peripheral circuit substrate 210, and the peripheral circuit insulating layer 220 are removed. From a top view, the through-path trench 300T may have a circular or polygonal shape, but other shapes may be used.

[0155] refer to Figure 13 ,exist Figure 12 A through-path insulation layer 350 and a through-path 300 are formed within the through-path trench 300T. The through-path insulation layer 350 can extend along... Figure 12 The through-path trench 300T extends to the bottom and side surfaces. The through-path 300 can be formed on the through-path insulating layer 350. The through-path insulating layer 350 and the through-path 300 can be filled. Figure 12 The through-path trench is 300T.

[0156] refer to Figure 14 An interlayer insulating layer 410 and a chip wiring structure 420 are formed on the peripheral circuit region 200. A front passivation layer 441, a front bonding layer 445, and a front pad 440 are formed above the interlayer insulating layer 410 and the chip wiring structure 420.

[0157] refer to Figure 15 , can follow Figure 14 A portion of the prefabricated cell substrate 110P is removed to expose the bottom surface 300BS of the through-path to form the cell substrate 110. The through-path 300 may protrude below the cell substrate 110.

[0158] Subsequently, referring to FIG2, a back-side passivation layer 431, a back-side bonding layer 435, and a back-side pad 430 can be formed under the unit substrate 110.

[0159] Figures 16 to 22 This is to illustrate the use of [materials] in manufacturing. Figure 5 The diagram illustrates an exemplary intermediate operation of a method for a semiconductor chip. For ease of explanation, the explanation will primarily focus on the intermediate operations and references. Figures 11 to 15 The differences in the descriptions.

[0160] refer to Figure 16A peripheral circuit element 230 and a peripheral circuit insulating layer 220 are formed on a peripheral circuit substrate 210. The peripheral circuit insulating layer 220 and the peripheral circuit element 230 can be formed on a first surface 210S1 of the peripheral circuit substrate. The peripheral circuit insulating layer 220 can cover the first surface 210S1 of the peripheral circuit substrate. A connection trench 240T can be formed within the peripheral circuit substrate 210. The connection trench 240T can be formed from the first surface 210S1 toward the second surface 210S2 of the peripheral circuit substrate. An insulating layer can be formed within the connection trench 240T. The second surface 210S2 of the peripheral circuit substrate can refer to the surface opposite to the first surface 210S1 in the first direction D1, wherein the peripheral circuit insulating layer 220 and the peripheral circuit element 230 are disposed on the first surface 210S1.

[0161] refer to Figure 17 A peripheral circuit substrate 210 and a peripheral circuit insulating layer 220 are bonded over a carrier substrate 15. Specifically, the peripheral circuit insulating layer 220 can be bonded over the carrier substrate 15 via a carrier bonding layer 17, such that the carrier substrate 15 and the first surface 210S1 of the peripheral circuit substrate face each other. A portion of the peripheral circuit substrate on the second surface 210S2 of the peripheral circuit substrate 210 can be removed to expose a connection trench 240T over the carrier substrate 15. The insulating layer within the connection trench 240T can be exposed through the second surface 210S2 of the peripheral circuit substrate.

[0162] According to some example embodiments, the carrier bonding layer 17 may be formed of different materials selected from silicon oxide, silicon nitride, silicon carbonitride, or silicon carbonitride oxycarbonate. The carrier bonding layer 17 may include, but is not limited to, a non-conductive film (NCF), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin. The carrier bonding layer 17 may be an adhesive tape that mutually fixes the carrier substrate 15 and the peripheral circuit insulating layer 220. The carrier bonding layer 17 may be, for example, an adhesive tape comprising an epoxy component.

[0163] refer to Figure 18 A second portion 320 is formed, penetrating the peripheral circuit substrate 210 and the peripheral circuit insulating layer 220. Specifically, a portion of the peripheral circuit substrate 210 and a portion of the peripheral circuit insulating layer 220 may be removed to form a trench of the second portion 320. A second via insulating layer 352 may be formed on the side surface of the trench, and the second portion 320 may be formed on the second via insulating layer 352 to fill the trench. The bonding surface 320B of the second portion 320 may be exposed outside the peripheral circuit substrate 210. The bonding surface 320B of the second portion 320 may be disposed on the same plane as the second surface 210S2 of the peripheral circuit substrate 210.

[0164] refer to Figure 19 Memory cells (a combination of 130 and 140), cell wiring 150, and cell insulating layer 120 are formed above the prefabricated cell substrate 110P. Subsequently, a first portion 310 penetrating at least a portion of the prefabricated cell substrate 110P and the cell insulating layer 120 can be formed. Specifically, a trench penetrating at least a portion of the prefabricated cell substrate 110P and the first portion 310 of the cell insulating layer 120 can be formed. Within the trench, a first via insulating layer 351 can be formed to cover the bottom and side surfaces of the trench, and the first portion 310 can be formed to fill the trench on the first via insulating layer 351. The bonding surface 310B of the first portion 310 can be exposed and not covered by the cell insulating layer 120. The bonding surface 310B of the first portion 310 can be disposed on the same plane as one surface of the cell insulating layer 120.

[0165] refer to Figure 20 The unit insulating layer 120 and the peripheral circuit substrate 210 are joined together. Specifically, the unit insulating layer 120 and the peripheral circuit substrate 210 are in contact with each other, such that the second surface 210S2 of the peripheral circuit substrate faces the unit insulating layer 120 in the first direction D1. The carrier substrate 15 may be disposed above the unit insulating layer 120, the peripheral circuit substrate 210 and the peripheral circuit insulating layer 220.

[0166] According to some example embodiments, the bonding surface 310B of the first portion 310 and the bonding surface 320B of the second portion 320 are brought into contact. As the unit insulating layer 120 comes into contact with the second surface 210S2 of the peripheral circuit substrate, the bonding surface 310B of the first portion 310 and the bonding surface 320B of the second portion 320 can be bonded to each other.

[0167] According to some example embodiments, a first portion 310 and a second portion 320 may be formed before the peripheral circuit substrate 210 is bonded over the prefabricated unit substrate 110P. The first portion 310 and the second portion 320 may be connected as the peripheral circuit substrate 210 is bonded over the prefabricated unit substrate 110P.

[0168] With Figure 18 and Figure 20As shown, a first portion 310 can be formed before the peripheral circuit substrate 210 is bonded over the prefabricated unit substrate 110P, and a second portion 320 can be formed after the peripheral circuit substrate 210 is bonded over the prefabricated unit substrate 110P. In this case, the peripheral circuit substrate 210 and the peripheral circuit insulating layer 220 can be bonded to the first portion 310, and a trench of the second portion 320 can be formed as a portion of the peripheral circuit substrate 210 and a portion of the peripheral circuit insulating layer 220 are removed to expose the first portion 310. Subsequently, the second portion 320 can be formed within the trench of the second portion 320 to connect to the first portion 310.

[0169] refer to Figure 21 Remove Figure 20 The carrier bonding layer 17 and Figure 20 The carrier substrate 15. The top surface of the peripheral circuit insulating layer 220 and the second part 320 is exposed.

[0170] refer to Figure 22 A connection path 240 and peripheral circuit wiring 250 are formed within the peripheral circuit insulation layer 220. The connection path 240 can penetrate... Figure 21 The insulation layer inside the 240T connection channel trench. Figure 22 Subsequent operations and references Figure 16 and Figure 17 The descriptions are essentially the same, and therefore, are omitted.

[0171] While some exemplary embodiments of this disclosure have been described in detail above, those skilled in the art should understand that the scope of this disclosure is not limited thereto, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Furthermore, some elements in the foregoing exemplary embodiments may be omitted for implementation purposes, and each exemplary embodiment may be combined for implementation purposes.

Claims

1. A semiconductor device, the semiconductor device comprising: Semiconductor chip, the semiconductor chip comprising: A unit region, wherein the unit region includes storage units; A peripheral circuit region, which is stacked on the cell region in a first direction, and includes peripheral circuit elements electrically connected to the memory cell; A through-path, wherein the through-path penetrates the unit region and the peripheral circuit region in the first direction; Back pads, the back pads being disposed below the cell region and electrically connected to the through path; and A front pad is disposed above the peripheral circuit area and electrically connected to the through path. The cell region includes a cell insulating layer surrounding the memory cell and a cell substrate disposed beneath the cell insulating layer. The peripheral circuit region includes: A peripheral circuit insulating layer surrounding the peripheral circuit element and a peripheral circuit substrate disposed below the peripheral circuit insulating layer, such that the peripheral circuit substrate is located between the peripheral circuit insulating layer and the unit insulating layer, and The through-path penetrates the unit substrate, the unit insulating layer, the peripheral circuit substrate, and the peripheral circuit insulating layer along the first direction.

2. The semiconductor device according to claim 1, further comprising: A chip wiring structure is disposed on the peripheral circuit area and electrically connected to the front pad and the through path.

3. The semiconductor device according to claim 2, wherein, The chip wiring structure is disposed in the first direction between the front pad and the through-path.

4. The semiconductor device according to claim 1, wherein, The connecting passage includes: The first portion penetrates the unit region; and The second part is connected to the first part in the first direction and penetrates the peripheral circuit area. The width of the first portion in the second direction intersecting the first direction decreases as the distance from the peripheral circuit region increases.

5. The semiconductor device according to claim 1, wherein, The semiconductor chip is a first semiconductor chip, and the semiconductor device further includes: A packaging substrate, the packaging substrate being located beneath the first semiconductor chip; and A second semiconductor chip, stacked on and above the first semiconductor chip, the second semiconductor chip comprising: Additional unit area, the additional unit area including additional storage units; An additional peripheral circuit region is stacked on the additional cell region in the first direction and includes additional peripheral circuit elements electrically connected to the additional memory cell, such that the additional peripheral circuit region is located between the semiconductor chip and the additional cell region. An additional through-path, the additional through-path penetrating the additional unit region and the additional peripheral circuit region in the first direction; An additional front pad is connected to the front pad, disposed below the additional peripheral circuit region and between the additional peripheral circuit region and the front pad, and electrically connected to the additional through-path; and An additional back pad is provided, which is disposed above the additional cell area and electrically connected to the additional through-path.

6. The semiconductor device according to claim 5, wherein, The additional through-path includes: The first portion penetrates the additional unit region; and The second part is connected to the first part in the first direction and penetrates the additional peripheral circuit area, and The width of the first portion in the second direction decreases as the distance from the first semiconductor chip increases.

7. The semiconductor device according to claim 5, wherein: The additional back pad contacts the additional through-path; and The additional front pad is bonded to the front pad.

8. The semiconductor device according to claim 5, wherein: The additional cell region includes an additional cell insulating layer surrounding the additional memory cell and an additional cell substrate disposed above the additional cell insulating layer. The additional peripheral circuit region includes: an additional peripheral circuit insulating layer surrounding the additional peripheral circuit element and an additional peripheral circuit substrate disposed above the additional peripheral circuit insulating layer, such that the additional peripheral circuit substrate is located between the additional peripheral circuit insulating layer and the additional unit insulating layer, and The additional through-path penetrates the additional unit substrate, the additional unit insulating layer, the additional peripheral circuit substrate, and the additional peripheral circuit insulating layer along the first direction.

9. The semiconductor device according to claim 4, wherein, The width of the second portion in the second direction increases as the distance from the unit region decreases.

10. The semiconductor device according to claim 4, wherein, At least a portion of the second part is inserted into the first part.

11. The semiconductor device according to claim 1, wherein, The unit substrate, the unit insulating layer, the peripheral circuit substrate, and the peripheral circuit insulating layer are stacked sequentially from bottom to top in the first direction.

12. The semiconductor device according to claim 1, wherein, The through path has steps on the boundary surface between the unit area and the peripheral circuit area.

13. The semiconductor device according to claim 1, wherein, The memory cell includes a vertical channel transistor.

14. The semiconductor device according to claim 13, wherein, The cell region also includes a capacitor electrically connected to the vertical channel transistor.

15. The semiconductor device according to claim 1, wherein, The unit insulating layer and the peripheral circuit insulating layer each comprise materials different from those of the unit substrate and the peripheral circuit substrate, respectively.

16. The semiconductor device of claim 1, further comprising: A front bonding layer is disposed above the peripheral circuit area and is penetrated by at least a portion of the front pads; as well as A back-side bonding layer is disposed below the cell region and penetrated by at least a portion of the back-side pads. The front bonding layer comprises a different material than the back bonding layer.

17. A semiconductor device, the semiconductor device comprising: Packaging substrate; A first semiconductor chip, wherein the first semiconductor chip is located on the packaging substrate; as well as A second semiconductor chip, which is bonded to the first semiconductor chip and disposed on the first semiconductor chip in a first direction. The first semiconductor chip includes: The first unit region includes a storage unit; A first peripheral circuit region, the first peripheral circuit region including peripheral circuit elements and arranged together with the first unit region in the first direction; The first through-path penetrates the first unit region and the first peripheral circuit region; A first back-side pad faces the first cell region, such that the first cell region is located at a vertical height between the first back-side pad and the first peripheral circuit region, and the first back-side pad is connected to the first through-path; and A first front pad faces the first peripheral circuit region, such that the first peripheral circuit region is located at the vertical height between the first front pad and the first cell region, and the first front pad is electrically connected to the first through-path. The second semiconductor chip includes: The second unit region includes a storage unit; The second peripheral circuit region includes peripheral circuit elements and is arranged together with the second unit region in the first direction; The second through-path penetrates the second unit region and the second peripheral circuit region; A second back pad faces the second cell region, such that the second cell region is located at a vertical height between the second back pad and the second peripheral circuit region, and the second back pad is connected to the second through-path; and The second front pad faces the second peripheral circuit region, such that the second peripheral circuit region is located at the vertical height between the second front pad and the second cell region, and the second front pad is electrically connected to the second through path. The first front pad and the second front pad are joined together. The first unit region includes a first unit substrate and a first unit insulating layer. The first peripheral circuit region includes a first peripheral circuit substrate and a first peripheral circuit insulating layer. The first through-path penetrates the first unit substrate, the first unit insulating layer, the first peripheral circuit substrate, and the first peripheral circuit insulating layer along the first direction. The second unit region includes a second unit substrate and a second unit insulating layer. The second peripheral circuit region includes a second peripheral circuit substrate and a second peripheral circuit insulating layer, and The second through-path penetrates the second unit substrate, the second unit insulating layer, the second peripheral circuit substrate, and the second peripheral circuit insulating layer along the first direction.

18. The semiconductor device of claim 17, further comprising: A third semiconductor chip, which is bonded to the second semiconductor chip and disposed on the second semiconductor chip in the first direction. The third semiconductor chip includes: The third unit region includes a storage unit; A third peripheral circuit region, the third peripheral circuit region including peripheral circuit elements and arranged together with the third unit region in the first direction; The third through-path penetrates the third unit region and the third peripheral circuit region; A third back-side pad, the third back-side pad facing the third unit region and connected to the third through-path; and The third front pad faces the third peripheral circuit area and is electrically connected to the third through path. The second back pad and the third back pad are bonded to each other.

19. The semiconductor device according to claim 17, in, The first semiconductor chip further includes a first front bonding layer, which is penetrated by the first front pad and faces the second semiconductor chip. The second semiconductor chip further includes a second front bonding layer, which is penetrated by the second front pad, faces the first semiconductor chip, and is bonded to the first front bonding layer. The first front bonding layer and the second front bonding layer are bonded by NH bonds and OH bonds.

20. A semiconductor device, the semiconductor device comprising: First semiconductor chip; A second semiconductor chip is bonded to the first semiconductor chip and disposed on the first semiconductor chip in a first direction; as well as A third semiconductor chip, which is bonded to the second semiconductor chip and disposed on the second semiconductor chip in the first direction. The first semiconductor chip includes: A first cell region, the first cell region including a vertical channel transistor; A first peripheral circuit region, comprising peripheral circuit elements electrically connected to the vertical channel transistor of the first cell region, and arranged together with the first cell region in the first direction; and The first through-path penetrates both the first unit region and the first peripheral circuit region. The second semiconductor chip includes: The second unit region includes a vertical channel transistor; A second peripheral circuit region, comprising peripheral circuit elements electrically connected to the vertical channel transistor of the second unit region, and arranged together with the second unit region in the first direction; and The second through-path penetrates both the second unit region and the second peripheral circuit region. The third semiconductor chip includes: The third unit region includes a vertical channel transistor; A third peripheral circuit region, the third peripheral circuit region including peripheral circuit elements electrically connected to the vertical channel transistor of the third unit region, and arranged together with the third unit region in the first direction; and The third through-path penetrates both the third unit region and the third peripheral circuit region. In the first direction, the top of the first peripheral circuit region faces the bottom of the second peripheral circuit region, and In the first direction, the top of the second unit region faces the bottom of the third unit region.

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