Insulated gate bipolar transistor based on P-type diamond and preparation method thereof

Abstract

The embodiment of the invention provides an insulated gate bipolar transistor based on P-type diamond and a preparation method thereof, and belongs to the technical field of semiconductors. The insulated gate bipolar transistor comprises a collector layer, a P-type diamond injection layer, a gradient transition layer, an N-type buffer layer, an N-drift layer, a P-type base region and an N + emission layer which are stacked in sequence, wherein the P-type diamond injection layer is used for injecting holes; the gradient transition layer is used for inhibiting lattice mismatch and thermal mismatch between the P-type diamond injection layer and the N-type buffer layer. According to the invention, the performance of the IGBT can be optimized, so that the IGBT can be better suitable for high temperature, high voltage, high frequency and other scenes, and the reliability of the IGBT can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor based on P-type diamond and a preparation method thereof. Background Art

[0002] The insulated-gate bipolar transistor (IGBT) combines the advantages of the metal-oxide-semiconductor field-effect transistor (MOSFET) and the bipolar junction transistor (BJT), becoming a core electronic component in modern power electronics circuits. The IGBT combines the MOSFET's ease of driving, low input impedance, and fast switching speed with the BJT's high on-state current density, low on-state voltage drop, low losses, and excellent stability. Due to its outstanding performance, the IGBT is widely used in transportation, communications, household appliances, and aerospace applications.

[0003] In related technologies, an IGBT includes a collector layer, a P+ injection layer, an N-type buffer layer, an N-drift layer, a P-type base region, and an N+ emitter layer stacked in sequence. The P+ injection layer is used to inject holes and is made of SiC.

[0004] However, due to the influence of deep energy level defects in SiC materials, its carrier mobility is low and its conductivity modulation capability is poor. When SiC materials are used as P+ injection layers to inject holes, there are problems such as high on-resistance, difficulty in increasing the breakdown voltage, and poor high-temperature stability, which will affect the performance of IGBT and its reliability in high-temperature, high-voltage and high-frequency scenarios. Summary of the Invention

[0005] The present disclosure provides an insulated gate bipolar transistor based on P-type diamond and a method for manufacturing the same, which can optimize the performance of the IGBT, making it more suitable for high-temperature, high-voltage, and high-frequency scenarios, and improving the reliability of the IGBT. The technical solution includes at least the following solutions: On the one hand, an insulated gate bipolar transistor is provided, comprising a collector layer, a P-type diamond injection layer, a gradient transition layer, an N-type buffer layer, an N-drift layer, a P-type base region and an N+ emitter layer stacked in sequence, wherein the P-type diamond injection layer is used to inject holes; and the gradient transition layer is used to suppress the lattice mismatch and thermal mismatch between the P-type diamond injection layer and the N-type buffer layer.

[0006] Optionally, the doping concentration of the P-type diamond injection layer is 1×10 18cm -3 to 5x10 19 cm -3 .

[0007] Optionally, the thickness of the P-type diamond injection layer is 5 μm to 10 μm.

[0008] Optionally, the gradient transition layer comprises an Al x Ga 1-x N layer, 0.1≤x≤0.6, and the Al component content in at least part of the gradient transition layer increases in a direction away from the P-type diamond injection layer.

[0009] Optionally, the gradient transition layer is a superlattice layer comprising a plurality of periodic structures stacked one by one, each of the periodic structures comprising an AlN layer and a first SiC layer stacked one by one in a direction away from the P-type diamond injection layer, and the Al component content in the plurality of periodic structures increases in a direction away from the P-type diamond injection layer.

[0010] Optionally, the number of the periodic structures in the gradient transition layer is 5 to 20.

[0011] Optionally, the gradient transition layer comprises a polycrystalline diamond layer, a SiN layer and a second SiC layer stacked one by one in a direction away from the P-type diamond injection layer.

[0012] Optionally, the average lattice constant of the gradient transition layer is 3 angstroms to 4.4 angstroms.

[0013] Optionally, the thermal expansion coefficient of the gradient transition layer is 1.0x10 -6 / K to 5.6x10 -6 / K.

[0014] In another aspect, a method for manufacturing an insulated gate bipolar transistor is provided, comprising: forming a P-type diamond injection layer on a collector layer, the P-type diamond injection layer being used for injecting holes; forming a gradient transition layer on the P-type diamond injection layer; forming an N-type buffer layer on the gradient transition layer, the gradient transition layer being used for inhibiting lattice mismatch and thermal mismatch between the P-type diamond injection layer and the N-type buffer layer; forming an N-drift layer on the N-type buffer layer; forming a P-base region on the N-drift layer; and forming an N+ emitter layer on the P-base region.

[0015] The technical scheme provided by the embodiments of the present disclosure has at least the following beneficial effects: In the embodiments of the present disclosure, by setting the P-type diamond injection layer, the diamond has high breakdown field strength and high carrier mobility, and the P-type diamond injection layer is used to inject holes, which is conducive to enhancing the conductance modulation effect, reducing the on-state voltage drop of the IGBT, and improving the breakdown voltage, thereby optimizing the performance of the IGBT. Moreover, the diamond has high-temperature resistance and extremely high thermal conductivity, and the P-type diamond injection layer can quickly conduct the heat inside the IGBT, thereby improving the heat dissipation efficiency and high-temperature resistance of the IGBT, so that the IGBT can be better applied to high-temperature, high-voltage and high-frequency scenes. By setting the gradient transition layer between the P-type diamond injection layer and the N-type buffer layer, the gradient transition layer can cooperate with the P-type diamond injection layer to give full play to the physical advantages of the diamond while suppressing the lattice mismatch and thermal mismatch between the P-type diamond injection layer and the N-type buffer layer, thereby reducing the interface dislocation density and interface thermal stress and reducing the probability of interface cracking during high-temperature operation, which is conducive to prolonging the service life of the device and improving the reliability of the IGBT. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a structure schematic diagram of an IGBT provided by an embodiment of the present disclosure; Figure 2 is another structure schematic diagram of an IGBT provided by an embodiment of the present disclosure; Figure 3 is still another structure schematic diagram of an IGBT provided by an embodiment of the present disclosure; Figure 4 is a flowchart of a preparation method of an IGBT provided by an embodiment of the present disclosure.

[0018] Reference signs: 10: collector layer; 20: P-type diamond injection layer; 30: gradient transition layer; 31: AlN layer; 32: first SiC layer; 33: polycrystalline diamond layer; 34: SiN layer; 35: second SiC layer; 40: N-type buffer layer; 50: N-drift layer; 60: P-type base region; 70: N+-emitter layer. DETAILED DESCRIPTION

[0019] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar terms used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprising" mean that the elements or objects preceding "include" or "comprising" encompass the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "A and / or B" indicates three situations: A, B, and A and B.

[0020] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0021] Example 1: Figure 1 This is a schematic diagram of the structure of an IGBT provided by an embodiment of the present disclosure. Figure 1 As shown, the IGBT includes a collector layer 10, a P-type diamond implantation layer 20, a gradient transition layer 30, an N-type buffer layer 40, an N-drift layer 50, a P-type base region 60, and an N+ emitter layer 70, which are stacked in sequence. The P-type diamond implantation layer 20 is used to inject holes. The gradient transition layer 30 is used to suppress the lattice mismatch and thermal mismatch between the P-type diamond implantation layer 20 and the N-type buffer layer 40.

[0022] In the embodiment of the present disclosure, by providing the P-type diamond injection layer 20, the diamond has a high breakdown field strength (>10MV / cm) and a high carrier mobility (about 3800cm 2The P-type diamond injection layer 20 is used to inject holes, which is beneficial to enhance the effect of conductivity modulation, reduce the on-state voltage drop of the IGBT, and improve the breakdown voltage (more than 10 kV), thereby optimizing the performance of the IGBT. Moreover, the diamond has high-temperature resistance (can withstand a working temperature of more than 600 DEG C) and extremely high thermal conductivity (> 2000 W / m·K), and the P-type diamond injection layer 20 can quickly conduct the heat inside the IGBT, thereby improving the heat dissipation efficiency and high-temperature resistance of the IGBT, and making the IGBT better applicable to high-temperature, high-voltage, and high-frequency scenes. By arranging the gradient transition layer 30 between the P-type diamond injection layer 20 and the N-type buffer layer 40, the gradient transition layer 30 can cooperate with the P-type diamond injection layer 20 to fully exert the physical advantages of the diamond while inhibiting the lattice mismatch and thermal mismatch between the P-type diamond injection layer 20 and the N-type buffer layer 40, thereby reducing the interface dislocation density and interface thermal stress and reducing the probability of interface cracking at high temperature, which is beneficial to prolong the service life of the device and improve the reliability of the IGBT.

[0023] Optionally, the material of the collector layer 10 can be a metal material. For example, the metal material can be one of Mo and Cu. In this way, it is beneficial to reduce the contact resistance of the collector layer 10 and reduce the on-state loss of the IGBT.

[0024] In other embodiments, the material of the collector layer 10 can also be adjusted to other metal materials according to actual needs, and the present disclosure does not limit this.

[0025] Exemplarily, the material of the P-type diamond injection layer 20 can be boron-doped diamond.

[0026] Optionally, the doping concentration of the P-type diamond injection layer 20 is 1 x 10 18 cm -3 - 5 x 10 19 cm -3 -1. The doping concentration of the P-type diamond injection layer 20 in this range can ensure a high hole mobility, which is beneficial to enhance the effect of conductivity modulation and reduce the on-state voltage drop of the IGBT.

[0027] Exemplarily, the doping concentration of the P-type diamond injection layer 20 can be 1 x 10 18 cm -3 , 2 x 10 18 cm -3 , 3 x 10 19 cm -3 , or 5 x 10 19 cm -3 , etc.

[0028] Optionally, the thickness of the P-type diamond implant layer 20 is 5 μm to 10 μm. The thickness of the P-type diamond implant layer 20 in this range can effectively improve the heat dissipation efficiency and high temperature resistance of the IGBT.

[0029] Illustratively, the thickness of the P-type diamond implant layer 20 can be 5 μm, 8 μm, or 10 μm, etc.

[0030] Illustratively, the material of the N-type buffer layer 40 can be nitrogen-doped SiC.

[0031] Optionally, the doping concentration of the N-type buffer layer 40 is 1 x 10 16 cm -3 to 5 x 10 17 cm -3 . The doping concentration of the N-type buffer layer 40 in this range can effectively suppress the punch-through effect.

[0032] Illustratively, the doping concentration of the N-type buffer layer 40 can be 1 x 10 16 cm -3 , 5 x 10 16 cm -3 , 3 x 10 17 cm -3 , or 5 x 10 17 cm -3 , etc.

[0033] Optionally, the thickness of the N-type buffer layer 40 is 0.5 μm to 2 μm.

[0034] Illustratively, the thickness of the N-type buffer layer 40 can be 0.5 μm, 1.5 μm, or 2 μm, etc.

[0035] Optionally, the average lattice constant of the gradient transition layer 30 is 3 angstroms to 4.4 angstroms. The lattice constant of diamond material is about 3.57 angstroms, and the lattice constant of SiC material is about 3.07 angstroms. The average lattice constant of the gradient transition layer 30 in this range can effectively suppress the lattice mismatch between the P-type diamond implant layer 20 and the N-type buffer layer 40, reduce the interface dislocation density, and improve the reliability of the IGBT.

[0036] Illustratively, the average lattice constant of the gradient transition layer 30 can be 3.11 angstroms, 3.19 angstroms, or 4.36 angstroms, etc.

[0037] Optionally, the thermal expansion coefficient of the gradient transition layer 30 is 1.0 x 10 -6 / K to 5.6 x 10 -6 / K. The thermal expansion coefficient of diamond material is about 1.0 x 10 -6 / K, and the thermal expansion coefficient of SiC material is about 4.0 x 10 -6 / K, the thermal expansion coefficient of the gradient transition layer 30 can effectively inhibit thermal mismatch between the P-type diamond injection layer 20 and the N-type buffer layer 40, reduce interface thermal stress, thereby reducing the probability of interface cracking when the IGBT works at high temperature, and is conducive to prolonging the service life of the device.

[0038] Exemplarily, the thermal expansion coefficient of the gradient transition layer 30 can be 1.0×10 -6 / K, 4.5×10 -6 / K or 5.6×10 -6 / K or the like.

[0039] In this embodiment, the gradient transition layer 30 includes an Al x Ga 1-x N layer, 0.1≤x≤0.6, and the Al component content in at least part of the gradient transition layer 30 increases in a direction away from the P-type diamond injection layer 20. Through the gradient change of the Al component content, the gradient change of the lattice constant and the thermal expansion coefficient of the gradient transition layer 30 can be realized, thereby ensuring that the effects of inhibiting lattice mismatch and thermal mismatch are good.

[0040] Exemplarily, the gradient transition layer 30 includes an Al x Ga 1-x N layer, 0.1≤x≤0.6. In the lower part of the gradient transition layer 30, the Al component content increases from 0.1 to 0.6 in a direction away from the P-type diamond injection layer 20, the lattice constant gradually changes from 3.19 angstroms to 3.11 angstroms, and the thermal expansion coefficient gradually changes from 5.6×10 -6 / K to 4.5×10 -6 / K; in the upper part of the gradient transition layer 30, the Al component content can remain unchanged at 0.6. In other embodiments, the Al component content in the entire gradient transition layer 30 can increase in a direction away from the P-type diamond injection layer 20, and the present disclosure does not limit this.

[0041] Exemplarily, the total thickness of the Al x Ga 1-x N layer can be 100 nm to 300 nm.

[0042] Exemplarily, the material of the N-drift layer 50 can be nitrogen-doped SiC. The N-drift layer 50 can withstand high pressure and transmit carriers.

[0043] Optionally, the doping concentration of the N-drift layer 50 is 1×10 14 cm -3 to 5×10 15 cm -3The doping concentration of the N-drift layer 50 can form a gradient doping with the N-type buffer layer 40 in this range, which can make the electric field distribution in the IGBT more uniform, and is beneficial to improve the breakdown voltage of the IGBT.

[0044] For example, the doping concentration of the N-drift layer 50 can be 1×10 14 cm -3 , 2×10 14 cm -3 , 3×10 15 cm -3 , or 5×10 15 cm -3 , etc.

[0045] Optionally, the thickness of the N-drift layer 50 is 50 μm to 100 μm.

[0046] For example, the thickness of the N-drift layer 50 can be 50 μm, 80 μm, or 100 μm, etc.

[0047] For example, the material of the P-type base region 60 can be aluminum-doped SiC. The P-type base region 60 can form a PN junction with the N-drift layer 50, and a reverse type layer is formed in this region by the gate voltage of the IGBT to control the conduction and turn-off of the IGBT.

[0048] Optionally, the doping concentration of the P-type base region 60 is 5×10 16 cm -3 to 1×10 18 cm -3 .

[0049] For example, the doping concentration of the P-type base region 60 can be 5×10 16 cm -3 , 5×10 17 cm -3 , or 1×10 18 cm -3 , etc.

[0050] Optionally, the depth of the P-type base region 60 is 1 μm to 3 μm.

[0051] For example, the depth of the P-type base region 60 can be 1 μm, 2 μm, or 3 μm, etc.

[0052] For example, the material of the N+ emitter layer 70 can be phosphorus-doped SiC. The N+ emitter layer 70 can serve as an electron injection source to provide high-concentration electrons when the IGBT is turned on, and the holes injected by the P-type diamond injection layer 20 are recombined to form a current.

[0053] Optionally, the doping concentration of the N+ emitter layer 70 is greater than 1×10 19 cm-3 . For example, the doping concentration of the N+emitter layer 70 can be 2x10 19 cm -3 or 2x10 19 cm -3 , etc.

[0054] Optionally, the thickness of the N+emitter layer 70 is 0.2-0.5 μm.

[0055] For example, the depth of the N+emitter layer 70 can be 0.2 μm, 0.4 μm or 0.5 μm, etc.

[0056] Optionally, the IGBT can further include an emitter disposed on the N+emitter layer 70.

[0057] For example, the emitter can be a metal material. For example, the emitter can be an Al layer, a Ti layer, a Ni layer and an Au layer stacked in sequence.

[0058] Embodiment 2: Figure 2 is another structure diagram of an IGBT provided by the embodiments of the present disclosure. As Figure 2 shown, the difference between the present embodiment and Embodiment 1 is only that the structure of the gradient transition layer 30 is different.

[0059] In the present embodiment, the gradient transition layer 30 is a superlattice layer, which includes a plurality of periodic structures stacked in sequence, each periodic structure including an AlN layer 31 and a first SiC layer 32 stacked in sequence in a direction away from the P-type diamond injection layer 20, and the Al component content in the plurality of periodic structures increases in sequence in the direction away from the P-type diamond injection layer 20. Here, the Al component content in the plurality of periodic structures increases in sequence means that, in any two adjacent periodic structures, the Al component content in the periodic structure away from the P-type diamond injection layer 20 is greater than the Al component content in the periodic structure close to the P-type diamond injection layer 20. By gradiently changing the Al component content in the periodic structure of the superlattice layer, the interface dislocation density and the interface thermal stress can be effectively reduced, and the reliability of the IGBT can be improved.

[0060] For example, the Al component content in the periodic structure can be changed by changing the thickness ratio of the AlN layer 31 in the periodic structure. For example, in any two adjacent periodic structures, the thickness ratio of the AlN layer 31 in the periodic structure away from the P-type diamond injection layer 20 is greater than the thickness ratio of the AlN layer 31 in the periodic structure close to the P-type diamond injection layer 20.

[0061] Optionally, the Al content in the periodic structure is greater than 0% and less than or equal to 30%. For example, in multiple periodic structures in the superlattice layer, the Al content can increase sequentially in a direction away from the P-type diamond implantation layer 20 up to 30%.

[0062] Optionally, the number of periodic structures in the gradient transition layer 30 is 5 to 20. When the number of periodic structures in the gradient transition layer 30 is within this range, the lattice mismatch and thermal mismatch between the P-type diamond implantation layer 20 and the N-type buffer layer 40 can be effectively suppressed. In this embodiment, the overall lattice mismatch rate of the IGBT is less than 3%.

[0063] For example, the number of periodic structures in the gradient transition layer 30 may be 5, 15, or 20.

[0064] For example, the total thickness of the plurality of periodic structures may be 50 nm to 200 nm.

[0065] Example 3: Figure 3 This is a structural diagram of another IGBT provided by the embodiment of the present disclosure. Figure 3 As shown, the difference between this embodiment and embodiment 1 is only the structure of the gradient transition layer 30 .

[0066] In this embodiment, the gradient transition layer 30 includes a polycrystalline diamond layer 33, a SiN layer 34, and a second SiC layer 35, which are stacked in sequence in a direction away from the P-type diamond implantation layer 20. By gradually transitioning from the polycrystalline diamond layer 33 to the SiN layer 34, and then from the SiN layer 34 to the second SiC layer 35, the lattice mismatch and thermal mismatch between the P-type diamond implantation layer 20 and the N-type buffer layer 40 are suppressed.

[0067] Illustratively, the thickness of the polycrystalline diamond layer 33 may be 1 μm to 5 μm.

[0068] By way of example, the thickness of the SiN layer 34 may be 50 nm to 200 nm.

[0069] Illustratively, the thickness of the second SiC layer 35 may be 0.5 μm to 2 μm.

[0070] Optionally, the second SiC layer 35 includes a 3C-SiC layer and a 4H-SiC layer stacked sequentially in a direction away from the P-type diamond implantation layer 20. The lattice constant of 3C-SiC is approximately 4.36 angstroms, and the lattice constant of 4H-SiC is approximately 3.07 angstroms, which helps match the lattice constant of the N-type buffer layer 40, thereby suppressing lattice mismatch.

[0071] In a possible implementation, the gradient transition layer 30 further comprises an amorphous carbon buffer layer, which is arranged between the SiN layer 34 and the second SiC layer 35. The interface stress can be effectively inhibited through the amorphous carbon buffer layer.

[0072] Exemplarily, the thickness of the amorphous carbon buffer layer can be 2 nm to 3 nm.

[0073] Figure 4 is a flowchart of a preparation method of an IGBT provided by an embodiment of the present disclosure. As shown in the figure, the preparation method comprises the following steps. Figure 4 S1, S2, S3, S4, S5 and S6. In step S1, a P-type diamond injection layer is formed on the collector layer.

[0074] The P-type diamond injection layer is used for injecting holes.

[0075] In step S2, a gradient transition layer is formed on the P-type diamond injection layer.

[0076] In step S3, an N-type buffer layer is formed on the gradient transition layer.

[0077] The gradient transition layer is used for inhibiting the lattice mismatch and thermal mismatch between the P-type diamond injection layer and the N-type buffer layer.

[0078] In step S4, an N-drift layer is formed on the N-type buffer layer.

[0079] In step S5, a P-type base region is formed on the N-drift layer.

[0080] In step S6, an N+ emitter layer is formed on the P-type base region.

[0081] It should be noted that the manufacturing method embodiment is based on the same inventive concept as the above-mentioned embodiments 1 to 3, and the beneficial effects of the embodiment of the present disclosure can be referred to the above-mentioned embodiments 1 to 3, which will not be described here again.

[0082] Referring to Figures 1 to 3 Optionally, step S1 can comprise the following steps. The boron-doped diamond is grown on the collector layer 10 through a microwave plasma chemical vapor deposition (MPCVD) technology, to obtain the P-type diamond injection layer 20.

[0083] Optionally, the growth temperature of the boron-doped diamond can be 800℃ to 1000℃.

[0084] For example, a high-purity Mo substrate can be selected and placed in an MPCVD device after mechanical polishing and Ar plasma cleaning. Boron-doped diamond is grown at a growth rate of 5 μm / h under the conditions of a flow ratio of CH4, H2, and B2H6 of 1:100:0.05, a pressure of 70 Torr, and a temperature of 900°C to obtain a P-type diamond implantation layer 20. The boron doping concentration of the P-type diamond implantation layer 20 is 2×10 18 cm -3 The thickness of the P-type diamond implantation layer 20 is 8 μm.

[0085] Optionally, according to different structures of the gradient transition layer 30 in different embodiments, step S2 may adopt the following different preparation processes: In Example 1, Figure 1 As shown, step S2 may include the following steps: Al is deposited on the P-type diamond implantation layer 20 by atomic layer deposition (ALD) technology. x Ga 1-x N layer, 0.1≤x≤0.6, a gradient transition layer 30 is obtained, and the Al component content in at least a portion of the gradient transition layer 30 increases in a direction away from the P-type diamond injection layer 20.

[0086] For example, the precursor can use trimethylaluminum (TMA) as Al source, trimethylgallium (TMGa) as Ga source, and NH3 as N source, and the ratio of TMA and TMGa can be linearly adjusted by a mass flow controller (MFC) to control the Al x Ga 1-x The Al content gradient in the N layer changes continuously. For example, the ALD device can be set to a pulse cycle of 300. During the first 200 pulse cycles, the Al content is controlled to increase by 0.25% each time from 10% to 60%. During the next 100 pulse cycles, the Al content is maintained at 60%.

[0087] For example, after each 5 nm deposition, annealing may be performed in a H 2 atmosphere at 700° C. for 1 minute to eliminate interface defects.

[0088] In Example 2, Figure 2 As shown, step S2 may include the following steps: The superlattice layer is grown on the P-type diamond injection layer 20 by a molecular beam epitaxy (MBE) technique to obtain the gradient transition layer 30. The superlattice layer includes a plurality of stacked period structures, each of which includes an AlN layer 31 and a first SiC layer 32 stacked in sequence in a direction away from the P-type diamond injection layer 20. In the direction away from the P-type diamond injection layer 20, the Al component content in the plurality of period structures increases in sequence.

[0089] Illustratively, the Al source and the N source can be alternately turned on to grow the AlN layer 31, and then the first SiC layer 32 is grown to obtain one period structure. The growth process is repeated multiple times to obtain the plurality of stacked period structures.

[0090] Illustratively, the surface morphology can be monitored by a real-time reflection high energy electron diffraction (RHEED) instrument, and the growth rate is adjusted to 0.1 nm / s to 0.5 nm / s to ensure the steepness of the interface.

[0091] Illustratively, after the growth is completed, annealing can be performed at a temperature greater than 1000℃ to eliminate stress.

[0092] In Embodiment 3, as shown in FIG. 3, step S2 can include the following steps: Figure 3 First, a polycrystalline diamond layer 33 is formed on the P-type diamond injection layer 20.

[0093] Illustratively, the MPCVD technique can be used, and a mixed gas of H2 and CH4 with a concentration of 2% is introduced at a flow rate of 500 sccm. The polycrystalline diamond layer 33 is grown at a growth rate of 5 μm / h to 10 μm / h under the conditions of a temperature of 900℃ to 1000℃, a pressure of 150 Torr to 200 Torr, and a microwave power of 3 kW to 5 kW.

[0094] Illustratively, after the growth is completed, the polycrystalline diamond layer 33 can be subjected to surface treatment: hydrogen plasma is activated under the conditions of H2 at a flow rate of 50 sccm and a power of 800 W for 10 min to form a C-H bond terminated surface, so as to ensure the nucleation quality of the subsequent SiN layer 34. For example, the nucleation density of the subsequent SiN layer 34 can be greater than 1010cm-2. 11 -2 .

[0095] Second, the SiN layer 34 is formed on the polycrystalline diamond layer 33.

[0096] ​​Exemplarily, a plasma enhanced chemical vapor deposition (PECVD) technology can be adopted, in which, in an initial stage, SiH4 with a flow rate of 20 sccm, H2 with a flow rate of 200 sccm, NH3 with a flow rate gradually increased from 0 to 50 sccm, and CH4 with a flow rate gradually increased from 0 to 5 sccm are introduced, the power is adjusted to 300 W, and the pressure is adjusted to 1 Torr to 2 Torr; then the flow rate ratio of SiH4 and NH3 is dynamically adjusted, for example, the flow rate ratio of SiH4 and NH3 is gradually changed from 5:1 to 1:2, and SiC is grown. y N z The layer is gradually changed from diamond to SiN in the direction away from the P-type diamond injection layer 20, y is gradually changed from 0.1 to 0, and z is gradually changed from 0.3 to 1, so as to realize a chemical bond transition from diamond to SiN, and the SiN layer 34 is obtained.

[0097] Exemplarily, after the growth is completed, an amorphous carbon buffer layer can be further formed on the SiN layer 34, and interface optimization is performed.

[0098] In a third step, a second SiC layer 35 is formed on the SiN layer 34.

[0099] Exemplarily, a high-temperature chemical vapor deposition (HTCVD) technology can be adopted, in which, SiH4 with a flow rate of 30 sccm, C3H8 with a flow rate of 15 sccm, H2 with a flow rate of 500 sccm, and NH3 with a flow rate gradually reduced to 0 are introduced, a temperature gradient is set to be from 600 ℃ to 1500 ℃, a temperature rising rate is set to be 10 ℃ / min, a 3C-SiC layer is grown under a low-temperature condition (a temperature less than 1000 ℃), and a 4H-SiC layer is grown under a high-temperature condition (a temperature greater than 1300 ℃ and less than 1500 ℃), and the second SiC layer 35 is obtained. By replacing CH4 with C3H8, the pollution of free C to the interface can be reduced.

[0100] Exemplarily, the growth time of the second SiC layer 35 is less than 2 h. By limiting the growth temperature and the growth time of the second SiC layer 35, and introducing H2, the formation of graphite phase can be effectively inhibited.

[0101] Exemplarily, after the growth is completed, annealing can be performed under an Ar atmosphere at a temperature of 1600 ℃ for 1 h, so as to reduce the dislocation density to less than 10 5 cm -2 .

[0102] Through the above first step to the third step, the gradient transition layer 30 in the embodiment 3 is obtained.

[0103] Referring toFigures 1 to 3 Optionally, step S3 may include the following steps: Nitrogen-doped SiC is grown on the gradient transition layer 30 by hydride vapor phase epitaxy (HVPE) technology to obtain the N-type buffer layer 40 .

[0104] For example, a mixed gas of SiH4, C3H8 and NH3 may be introduced with a V / III ratio of 100 to 500, for example, a V / III ratio of 300, and N2 with a flow rate of 50 sccm to grow nitrogen-doped SiC to obtain the N-type buffer layer 40. The nitrogen doping concentration of the N-type buffer layer 40 is 5×10 16 cm -3 .

[0105] Optionally, step S4 may include the following steps: Nitrogen-doped SiC is grown on the N-type buffer layer 40 through multiple epitaxial growth and in-situ doping processes to obtain the N-drift layer 50 .

[0106] For example, the thickness of the N-drift layer 50 may be 80 μm, and the nitrogen doping concentration of the N-drift layer 50 may be 2×10 14 cm -3 .

[0107] Optionally, step S5 may include the following steps: Aluminum-doped SiC is formed on the N-drift layer 50 by an ion implantation process and a rapid thermal annealing (RTA) process to obtain a P-type base region 60 .

[0108] Optionally, the ion implantation energy may be 50 keV to 200 keV.

[0109] For example, the region can be defined by photolithography, and the aluminum ion implantation energy is 150 keV and the dose is 1×10 13 cm -2 , and then annealed at 1700℃ for 2min to ensure the activation rate is greater than 90%.

[0110] Optionally, step S6 may include the following steps: Phosphorus-doped SiC is formed on the P-type base region 60 by an ion implantation process and an RTA process to obtain an N+ emitter layer 70 .

[0111] For example, the phosphorus ion implantation energy may be 80 keV, and the dose may be 5×10 15 cm -2 , and then annealed at 1600℃ for 1min.

[0112] Optionally, after step S6 is completed, the preparation method can further include back metalization and forming an emitter on the N+emitter layer 70.

[0113] Illustratively, a Ti layer, a Pt layer and an Au layer can be formed in sequence on the high-purity Mo substrate in a direction away from the P-type diamond injection layer 20, and annealed at 600℃ for 30s to perform back metalization. The thickness of the Ti layer can be 20nm, the thickness of the Pt layer can be 50nm, and the thickness of the Au layer can be 200nm.

[0114] Illustratively, an Al layer, a Ti layer, a Ni layer and an Au layer can be formed in sequence on the N+emitter layer 70 in a direction away from the P-type diamond injection layer 20 to obtain an emitter.

[0115] Optionally, the preparation method can further include passivation and packaging.

[0116] Illustratively, 300nm of SiN x , the laser drilling precision is ±2μm; Au 80 Sn 20 solder is used for vacuum reflow soldering, and the peak temperature is 310℃, thereby completing passivation and packaging of the IGBT. The specific process of passivation and packaging can refer to related technologies, and the present disclosure will not be described in detail here.

[0117] It should be noted that the structure, material and thickness of each film layer in the preparation method embodiment can refer to the related structure embodiment, and the detailed description is omitted here. Figures 1 to 3

[0118] The above only describes optional embodiments of the present disclosure, and does not limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.​

Claims

1. An insulated gate bipolar transistor, characterized by, The P-type diamond injection layer is used for injecting holes. The gradient transition layer is used for inhibiting lattice mismatch and thermal mismatch between the P-type diamond injection layer and the N-type buffer layer. The P-type diamond injection layer has a thickness of 5-10 μm.

2. The insulated gate bipolar transistor of claim 1, wherein The P-type diamond implant layer has a doping concentration of 1 x 10 18 cm -3 to 5 x 10 19 cm -3 .

3. The insulated gate bipolar transistor of claim 1, wherein The gradient transition layer is a superlattice layer, comprising a plurality of period structures stacked in sequence, each of the period structures comprising an AlN layer and a first SiC layer stacked in sequence in a direction away from the P-type diamond injection layer, and the Al component content in the plurality of period structures increases in sequence in the direction away from the P-type diamond injection layer.

4. The insulated gate bipolar transistor of claim 1, wherein the gradient transition layer includes Al x Ga 1-x N layer, 0.1≤x≤0.6, at least a portion of the gradient transition layer having an increasing Al composition in a direction away from the P-type diamond implant layer.

5. The insulated gate bipolar transistor of claim 1, wherein The gradient transition layer has a number of the period structures of 5-20.

6. The insulated gate bipolar transistor of claim 5, wherein The gradient transition layer comprises a polycrystalline diamond layer, a SiN layer and a second SiC layer stacked in sequence in a direction away from the P-type diamond injection layer.

7. The insulated gate bipolar transistor of claim 1, wherein The gradient transition layer has an average lattice constant of 3-4.4 angstroms.

8. The insulated gate bipolar transistor according to any one of claims 1 to 7, characterized in that The P-type diamond injection layer is used for injecting holes.

9. The insulated gate bipolar transistor according to any one of claims 1 to 7, characterized in that The coefficient of thermal expansion of the gradient transition layer is 1.0 x 10 -6 / K to 5.6 x 10 -6 / K.

10. A method of manufacturing an insulated gate bipolar transistor, characterized by, The gradient transition layer is used for inhibiting lattice mismatch and thermal mismatch between the P-type diamond injection layer and the N-type buffer layer. The N-type buffer layer is formed on the gradient transition layer. The N- drift layer is formed on the N-type buffer layer. The P-type base region is formed on the N- drift layer. The N+ emitter layer is formed on the P-type base region. ​ ​

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