Gallium nitride-based epitaxial structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, and provides a gallium nitride-based epitaxial structure and a preparation method thereof. The gallium nitride-based epitaxial structure comprises a Si substrate, a graphene layer, a high-temperature AlN starting layer, a stepped Al < x > Ga < 1-x > N buffer layer, an N-type GaN active layer, a stepped Al < y > GaN barrier layer, an electron blocking layer, a P-type GaN contact layer and a passivation layer, wherein the surface of the Si substrate is provided with a pyramid-shaped nano structure. Through the synergistic effect of the structured Si substrate and the graphene layer and in combination with the design of the stepped buffer layer and the barrier layer, lattice mismatch stress is effectively relieved, dislocation density is reduced, carrier mobility and device breakdown voltage are improved, high-temperature working stability is enhanced, and the structure is suitable for high-frequency and high-power semiconductor devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a gallium nitride-based epitaxial structure and a preparation method thereof. BACKGROUND

[0002] An epitaxial structure refers to a thin film material with specific crystal structure and properties deposited on a substrate material through epitaxial growth. A gallium nitride-based epitaxial structure is usually a multi-layer material system based on GaN grown on a sapphire (Al2O3), silicon carbide (SiC) or silicon (Si) substrate, which has a complex structure and multiple functions such as stress regulation, electrical and optical performance optimization. Lattice mismatch refers to the difference in lattice constant between the epitaxial layer material and the substrate material. This difference can cause stress concentration, resulting in defects such as dislocations, cracks, etc., affecting the performance and reliability of semiconductor devices. In order to solve the problem of lattice mismatch, the existing epitaxial structure often uses a thick buffer layer to solve the problem, relying on natural stress relief by thick buffer layer to release stress, although it can reduce the interface stress initially, but the greater the thickness, the more significant the residual thermal stress accumulation of the overall structure, especially during high-temperature growth and cooling, the thick buffer layer cannot release stress in time, which is prone to form cracks, warping or even peeling, affecting the performance and reliability of semiconductor devices.

[0003] After searching, the invention patent with publication number CN119767735A discloses an epitaxial structure of a gallium nitride semiconductor chip, which includes a Si substrate, an AlN nucleation layer, a step gradient AlGaN buffer layer, a C-doped GaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, an AlGaN barrier layer and a Si passivation layer. The step gradient AlGaN buffer layer contains four sub-buffer layers, and the Al component of each layer gradually increases to relieve lattice mismatch. However, this technical solution still has significant defects: although the Al component incremental design of the step gradient buffer layer can achieve partial stress relief, the thickness distribution of the four sub-buffer layers does not consider the dynamic stress release requirement, and the Al component gradient change rate is fixed, which leads to the formation of stress concentration zones in the buffer layer, especially at the interface of the sub-buffer layers, which is prone to dislocation accumulation, and cannot completely solve the problem of residual thermal stress caused by thick buffer layer, affecting the long-term working stability of the device. SUMMARY

[0004] In view of the above problems, the present application aims to provide a gallium nitride-based epitaxial structure and a preparation method, which can solve the technical problems that the thick buffer layer in the prior art cannot release stress in time, is prone to form cracks, warping or even peeling, thereby affecting the performance and reliability of semiconductor devices.

[0005] The technical solution of the present application is as follows: On the one hand, the present application provides a gallium nitride-based epitaxial structure, comprising: a Si substrate with a structured surface, the surface of the Si substrate being provided with a plurality of pyramid-shaped nanostructures; a graphene layer provided on the Si substrate; a high-temperature AlN initiation layer provided on the graphene layer; a stepped Al x Ga 1-x N buffer layer provided on the high-temperature AlN initiation layer; an N-type GaN active layer provided on the stepped Al x Ga 1-x N buffer layer; a stepped Al y GaN barrier layer provided on the N-type GaN active layer; an electron blocking layer provided on the stepped Al y GaN barrier layer; a P-type GaN contact layer provided on the electron blocking layer; and a passivation layer provided on the P-type GaN contact layer.

[0006] Preferably, the stepped Al x Ga 1-x N buffer layer comprises a first-stage Al 0.73 Ga 0.27 N buffer layer, a second-stage Al 0.47 Ga 0.53 N buffer layer, a third-stage Al 0.34 Ga 0.66 N buffer layer, a fourth-stage Al 0.21 Ga 0.79 N buffer layer, and a fifth-stage Al 0.12 Ga 0.88 N buffer layer, the first-stage Al 0.73 Ga 0.27 N buffer layer, the second-stage Al 0.47 Ga 0.53 N buffer layer, the third-stage Al 0.34 Ga 0.66 N buffer layer, the fourth-stage Al 0.21 Ga 0.79 N buffer layer, and the fifth-stage Al 0.12 Ga 0.88 N buffer layer, the aluminum component of which is arranged in a gradient decreasing manner.

[0007] Preferably, the first-stage Al 0.73 Ga 0.27 N buffer layer has a thickness of 60-80 nm, the second-stage Al 0.47Ga 0.53 The thickness of the N buffer layer is 90-110 nm, the fourth-stage Al 0.34 Ga 0.66 The thickness of the N buffer layer is 110-130 nm, the fourth-stage Al 0.21 Ga 0.79 The thickness of the N buffer layer is 190-210 nm, the fifth-stage Al 0.12 Ga 0.88 The thickness of the N buffer layer is 370-390 nm.

[0008] As preferred, the stepped Al y The GaN barrier layer comprises, in order from bottom to top, a first-stage Al 0.4 The GaN barrier layer, a second-stage AlGaN graded barrier layer, and a third-stage Al 0.2 The GaN barrier layer, the Al molar fraction in the second-stage AlGaN graded barrier layer gradually changes from 40% to 20%.

[0009] As preferred, the first-stage Al 0.4 The thickness of the GaN barrier layer is 20-40 nm, the thickness of the second-stage AlGaN graded barrier layer is 190-210 nm, and the thickness of the third-stage Al 0.2 The thickness of the GaN barrier layer is 20-40 nm.

[0010] As preferred, the N-type GaN active layer is formed with 5 pairs of InGaN potential well layers and GaN barrier layers alternately stacked to form an indium component graded quantum well structure, and the energy band of the indium component graded quantum well changes in an asymmetric trapezoidal shape.

[0011] As preferred, the indium component graded quantum well is close to the stepped Al x Ga 1-x The energy band gradually changes in thickness by 0.4-0.6 nm on the side close to the N buffer layer, the energy band maintains in thickness by 1.0-1.2 nm in the middle of the indium component graded quantum well, and the energy band gradually changes in thickness by 1.2-1.4 nm on the side close to the stepped Al y GaN barrier layer.

[0012] In another aspect, a method for preparing the above-mentioned GaN-based epitaxial structure is also provided, comprising the following steps: S1, constructing a simulation model of the GaN-based epitaxial structure, the simulation model describes the electric potential distribution, charge conservation, and carrier current density in a semiconductor device through Poisson equation, continuity equation of electrons and holes, and drift-diffusion current equation of electrons and holes; S2, determining breakdown voltage of the gallium nitride-based epitaxial structure under various structure parameters by the simulation model, the breakdown voltage being the maximum voltage value that the structure can withstand under reverse bias; S3, determining optimal structure parameters of the gallium nitride-based epitaxial structure according to the breakdown voltage under various structure parameters, wherein the step of determining the optimal structure parameters of the gallium nitride-based epitaxial structure comprises determining by a meerkat optimization algorithm; The structure parameters include thickness of each layer in the gallium nitride-based epitaxial structure, size parameters of the pyramid-shaped nanostructure on the Si substrate, doping concentration in the AlGaN buffer layer, and doping concentration in the AlGaN barrier layer. x Ga 1-x N buffer layer, and doping concentration in the AlGaN barrier layer. y GaN barrier layer.

[0013] The meerkat optimization algorithm comprises initializing meerkat individuals by Sine chaotic mapping, each meerkat individual representing a set of structure parameters, and the initialization generates initial positions of the meerkat individuals by Sine chaotic mapping.

[0014] S4, performing surface structuring treatment on the Si substrate to prepare a plurality of pyramid-shaped nanostructures according to the optimal structure parameters; S5, depositing a graphene layer on the Si substrate by chemical vapor deposition; S6, increasing the growth temperature to 1000-1200℃, and depositing a high-temperature AlN starting layer on the graphene layer by chemical vapor deposition; S7, depositing a stepped AlGaN buffer layer on the high-temperature AlN starting layer by chemical vapor deposition; x Ga 1-x N buffer layer; S8, depositing an N-type GaN active layer on the stepped AlGaN buffer layer by chemical vapor deposition; x Ga 1-x N buffer layer; S9, depositing a stepped AlGaN barrier layer on the N-type GaN active layer by chemical vapor deposition; y GaN barrier layer; S10, depositing an electron blocking layer on the stepped AlGaN barrier layer by chemical vapor deposition; y GaN barrier layer; S11, depositing a P-type GaN contact layer on the electron blocking layer by chemical vapor deposition; S12, and performing surface passivation treatment on the P-type GaN contact layer to deposit a passivation layer. Compared with the prior art, the present application has the following advantages: (1) The present application realizes the step-by-step transition of stress and lattice mismatch, timely releases stress, and improves the performance and reliability of semiconductor devices by designing a stepped Al x Ga 1-x N buffer layer and adopting stepped aluminum component regulation.

[0015] (2) The present application introduces a non-planar growth interface by setting multiple pyramid-shaped nano structures on the surface of a silicon substrate, effectively disperses stress and suppresses dislocation vertical penetration, reduces cracks and warping caused by stress accumulation, and at the same time, the three-dimensional micro structure provides polycrystalline growth sites, promotes self-organization nucleation and crystal quality improvement of the epitaxial layer, and lays a foundation for high-quality growth of subsequent graphene layers and epitaxial materials.

[0016] (3) The present application reduces the interface energy level by adopting a graphene layer as an intermediate layer, optimizes the lattice mismatch and stress release of GaN, and provides a flexible buffer platform for GaN epitaxial growth with the virtual substrate characteristics, suppresses dislocation propagation and crack generation, and improves the crystalline quality and structural integrity of the epitaxial layer.

[0017] (4) The present application suppresses the chemical reaction of silicon at high temperature by adopting a high-temperature AlN starting layer, significantly reduces dislocation density, and provides a high-quality initial template with higher lattice matching degree, which provides a stable lattice transition platform for subsequent stepped Al x Ga 1-x N buffer layer, effectively reduces the interface dislocation density and stress concentration, and improves the crystalline quality and reliability of the overall epitaxial structure. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are for the purpose of illustrating preferred embodiments of the present application only, and are not to be construed as limiting the present application, wherein the same reference notations in different drawings represent the same elements. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0019] Figure 1 is a structural schematic diagram of a gallium nitride-based epitaxial structure provided by an embodiment of the present application.

[0020] Figure 2 is a structural schematic diagram of a stepped Al x Ga 1-x N buffer layer provided by an embodiment of the present application.

[0021] Figure 3 is a structural schematic diagram of a stepped Al y GaN barrier layer provided by an embodiment of the present application.

[0022] Figure 4This is a schematic diagram of the energy band variation of an indium composition gradient quantum well provided by an embodiment of the present invention.

[0023] Figure 5 It is a schematic flow chart of a preparation method provided by an embodiment of the present invention.

[0024] Explanation of reference numerals: 1-Si substrate; 2-graphene layer; 3-high temperature AlN starting layer; 4-stepped Al x Ga 1-x N buffer layer; 41-first level Al 0.73 Ga 0.27 N buffer layer; 42-second level Al 0.47 Ga 0.53 N buffer layer; 43-third level Al 0.34 Ga 0.66 N buffer layer; 44- fourth level Al 0.21 Ga 0.79 N buffer layer; 45-fifth level Al 0.12 Ga 0.88 N buffer layer; 5-N-type GaN active layer; 6-stepped Al y GaN barrier layer; 61-first level Al 0.4 GaN barrier layer; 62- second level AlGaN graded barrier layer; 63- third level Al 0.2 GaN barrier layer; 7-electron blocking layer; 8-P-type GaN contact layer; 9-passivation layer. DETAILED DESCRIPTION

[0025] The present invention is further described below in conjunction with the accompanying drawings and Examples, but is not intended to limit the scope of the present invention and is only illustrative. It should be noted that, in the case of no conflict, the technical features in the embodiments and embodiments of the present application can be combined with each other. Unless otherwise specified, all technical and scientific terms used in this application have the same meanings as those generally understood by those of ordinary skill in the art to which this application belongs. The experimental methods used in the following examples are conventional methods unless otherwise specified. Materials, reagents, etc. used in the following examples, unless otherwise specified, can all be obtained from commercial sources.

[0026] Reference Manual Figure 1 , showing a structural schematic diagram of a gallium nitride-based epitaxial structure provided by an embodiment of the present invention.

[0027] The embodiment of the present invention provides a GaN-based epitaxial structure, comprising: a Si substrate 1, a graphene layer 2, a high-temperature AlN starting layer 3, a stepped Al x Ga 1-x N buffer layer 4, N-type GaN active layer 5, stepped Al yGaN barrier layer 6, electron blocking layer 7, P-type GaN contact layer 8 and passivation layer 9.

[0028] Si substrate 1 is the basis of the epitaxial structure, Si substrate 1 adopts a structured surface, and the surface of Si substrate 1 is provided with a plurality of pyramid-shaped nanostructures. The micro-nano patterning design can effectively expand the stress relief channel, reduce the in-plane stress accumulation, inhibit the generation of cracks, and promote the directional growth of epitaxial nucleation, which is beneficial to obtain better crystal quality.

[0029] Optionally, the recommended height of the pyramid-shaped nanostructure is 100nm to 300nm, the recommended top angle is 60° to 90°, and the recommended spacing is 200nm to 500nm.

[0030] It should be noted that the pyramid-shaped surface can form a plurality of stress relief channels through its sharp tip and inclined side when stress is applied. These channels help to disperse the stress generated during epitaxial layer growth to the surrounding area, rather than concentrating in a single location. Without a microstructured surface, the stress generated during epitaxial growth can concentrate in a small area, leading to the formation of dislocations. The nanostructured surface reduces the stress concentration area by increasing the stress relief channel, thereby reducing the dislocation density. X-ray diffraction (XRD) tests show that after using a pyramid-shaped nanostructure with a height of 200nm and a top angle of 75°, the dislocation density is reduced from 1×10 9 cm -2 to 5×10 8 cm -2 , with a reduction of about 30% to 50% (compared to a flat Si substrate sample), and the specific value depends on the height, spacing and top angle of the pyramid.

[0031] The graphene layer 2 is arranged on the Si substrate 1, and the graphene layer 2 serves as an interface control layer, which can form a high-quality intermediate transition interface between Si and AlN, for reducing the interface energy level, and providing a “decoupling” type virtual lattice template for subsequent epitaxial layers, and improving the GaN lattice mismatch and stress release.

[0032] The high-temperature AlN starting layer 3 is arranged on the graphene layer 2, and the high-temperature AlN starting layer 3 is used to prevent silicon fusion and etching, and because its lattice constant is close to GaN, it becomes a bridge layer for lattice transition, and provides a lattice transition layer for the subsequent step Al x Ga 1-x N buffer layer 4.

[0033] The step Al x Ga 1-x N buffer layer 4 is arranged on the high-temperature AlN starting layer 3. The step Al x Ga 1-xThe N buffer layer 4 adopts a design of gradually decreasing aluminum components, and stress is released step by step through a multi-layer gradient mode to realize smooth transition from AlN to GaN lattice, thereby significantly reducing the penetrating dislocation density and improving the lattice matching degree and overall thermodynamic stability between the buffer layer and the active layer.

[0034] The N-type GaN active layer 5 is arranged on the stepped Al x Ga 1-x N buffer layer 4.

[0035] The stepped Al y GaN barrier layer 6 is arranged on the N-type GaN active layer 5.

[0036] The electron blocking layer 7 is arranged on the stepped Al y GaN barrier layer 6.

[0037] The N-type GaN active layer 5, the stepped Al y GaN barrier layer 6 and the electron blocking layer 7 form a heterostructure system to construct an ideal two-dimensional electron gas channel 2DEG, which has high electron mobility and high current carrying capacity.

[0038] The P-type GaN contact layer 8 is arranged on the electron blocking layer 7.

[0039] The passivation layer 9 is arranged on the P-type GaN contact layer 8.

[0040] The technical scheme provided by the embodiment of the application has at least the following beneficial effects: (1) In the embodiment of the application, the stepped Al x Ga 1-x N buffer layer is designed, the aluminum components in the buffer layer are changed step by step, the stress and lattice mismatch are transitioned layer by layer, the stress is released in time, and the performance and reliability of the semiconductor device are improved.

[0041] (2) In the embodiment of the application, a plurality of pyramid-shaped nano structures are arranged on the surface of the silicon substrate.

[0042] (3) In the embodiment of the present application, the graphene layer is used as the intermediate layer, which can reduce the interface energy level, improve the GaN lattice mismatch and stress release, the virtual substrate characteristics of the graphene layer provide a flexible buffer platform for the GaN epitaxial growth, which helps to inhibit the dislocation propagation and crack generation, thereby improving the crystalline quality and structural integrity of the epitaxial layer.

[0043] (4) In the embodiment of the present application, the high-temperature AlN starting layer can inhibit the chemical reaction of silicon at high temperature, significantly reduce the dislocation density, provide an initial template with high quality and lattice closer to GaN, and provide a stable lattice transition platform for the subsequent step-by-step Al x Ga 1-x N buffer layer, effectively reduce the interface dislocation density and stress concentration, thereby improving the crystalline quality and reliability of the overall epitaxial structure.

[0044] The accompanying drawings referred to in the description Figure 2 illustrate a structure schematic diagram of a step-by-step Al x Ga 1-x N buffer layer provided by the embodiment of the present application.

[0045] In a possible implementation, the step-by-step Al x Ga 1-x N buffer layer 4 includes a first-stage Al 0.73 Ga 0.27 N buffer layer 41, a second-stage Al 0.47 Ga 0.53 N buffer layer 42, a third-stage Al 0.34 Ga 0.66 N buffer layer 43, a fourth-stage Al 0.21 Ga 0.79 N buffer layer 44, and a fifth-stage Al 0.12 Ga 0.88 N buffer layer 45.

[0046] Optionally, the thickness of the first-stage Al 0.73 Ga 0.27 N buffer layer 41 is 70 nm, the thickness of the second-stage Al 0.47 Ga 0.53 N buffer layer 42 is 100 nm, the thickness of the third-stage Al 0.34 Ga 0.66 N buffer layer 43 is 120 nm, the thickness of the fourth-stage Al 0.21 Ga 0.79 N buffer layer 44 is 200 nm, and the thickness of the fifth-stage Al 0.12 Ga 0.88 N buffer layer 45 is 380 nm.

[0047] In the embodiment of the present invention, different aluminum contents and thicknesses are set in sequence, from Al 0.73 Ga 0.27 N gradually transitions to Al 0.12 Ga 0.88 N enables progressive control of lattice constants and stress, effectively alleviating stress concentration issues caused by the lattice mismatch and thermal expansion differences between GaN and Si. By gradually reducing the x value, the lattice parameter gradually approaches that of GaN, helping to suppress threading dislocation formation and the accumulation of interface defects. The gradually increasing thickness design also balances stress release and nucleation stability, ensuring that each buffer layer functions as both a bridge for transitional lattices and a buffer for absorbing and conducting stress, significantly improving the overall crystal quality and structural integrity of the epitaxial structure.

[0048] Reference Manual Figure 3 , showing a stepped Al y Schematic diagram of the structure of the GaN barrier layer.

[0049] In one possible embodiment, the stepped Al y The GaN barrier layer 6 includes a first-level Al 0.4 GaN barrier layer 61, second-level AlGaN graded barrier layer 62 and third-level Al 0.2 The Al mole fraction in the GaN barrier layer 63 and the second-level AlGaN graded barrier layer 62 gradually changes from 40% to 20%.

[0050] It should be noted that the first layer uses Al2O3 with an aluminum content of 40%. 40 GaN, the design of this aluminum ratio is to provide sufficient difference in the transition process of the lattice constant, so as to better connect with the next gradient layer. The aluminum content makes this layer have a higher polarization field, which can effectively increase the carrier density and help improve the electron mobility. The second-level layer adopts a gradient aluminum mole fraction, which gradually decreases from 40% to 20%. This gradient design is crucial to achieve a smooth transition of the lattice constant. Gradually reducing the aluminum content can effectively reduce the lattice stress caused by the difference in aluminum content and make the structure more uniform. The aluminum content of the third layer is designed to be 20%, which is close to the aluminum mole fraction of GaN, and further achieves lattice matching with the GaN layer. By reducing the aluminum content, Al 0.2 The GaN layer can form a better lattice connection with the GaN active layer, avoiding the influence of thermal expansion mismatch.

[0051] Optionally, the first stage Al 0.4 The thickness of the GaN barrier layer 61 is 30 nm, the thickness of the second-level AlGaN graded barrier layer 62 is 200 nm, and the thickness of the third-level Al 0.2The thickness of the GaN barrier layer 63 is 30 nm.

[0052] It should be noted that the thickness of the first barrier layer is 30 nm, and this layer is relatively thin in design, and the main purpose is to provide a preliminary polarization field in the epitaxial structure, while avoiding excessive stress accumulation. The thickness of the second barrier layer is 200 nm, which is significantly increased compared to the first level. The main role of this layer is to slowly adjust the lattice constant and release stress by gradually changing the mole fraction of aluminum (from 40% to 20%). The thickness of the third barrier layer is reduced to 30 nm again, and this layer is designed to be thin, and the purpose is to form a better match with the GaN layer and maintain a small polarization effect of the layer, thereby improving the carrier injection efficiency and electron mobility.

[0053] In the embodiment of the present application, the Al y The GaN barrier layer 6 can form a high-quality two-dimensional electron gas (2DEG) in the AlGaN / GaN heterojunction, the first Al 0.4 The GaN barrier layer 61 provides a strong polarization field to enhance the carrier density, the graded layer smooths the band change, reduces the interface potential mutation and carrier scattering, and releases the lattice stress caused by the difference in aluminum content. The third Al 0.2 The GaN barrier layer 63 helps to build a stable top electron regulation zone. The three-layer ladder barrier not only improves the electron mobility and device stability, but also enhances the tolerance to thermal stress and structural defects, which is beneficial to realize high-performance, high-reliability power or radio frequency devices.

[0054] Referring to the drawings accompanying the specification Figure 4 , a band change schematic diagram of an indium component graded quantum well provided by an embodiment of the present application is shown.

[0055] In a possible implementation, the N-type GaN active layer 5 is formed with 5 pairs of indium component graded quantum well structures in which InGaN potential well layers and GaN barrier layers are alternately stacked.

[0056] Optionally, the band change of the indium component graded quantum well is in an asymmetric trapezoidal shape.

[0057] Optionally, the indium component graded quantum well is close to the GaN barrier layer 6 side. x Ga 1-x The band change thickness of the indium component graded quantum well close to the GaN barrier layer 6 side is 1.3 nm. y The band change thickness of the indium component graded quantum well close to the GaN barrier layer 6 side is 1.3 nm.

[0058] In the embodiment of the present application, the asymmetric band design makes the potential barrier near the buffer layer side steeper (0.5 nm of gradual thickness), which is beneficial to limit the leakage of carriers to the substrate; while the gentle slope transition (1.3 nm of gradual thickness) near the barrier layer side helps to improve the carrier injection efficiency and recombination probability, and the steady band width (1.1 nm) in the middle provides a stable excitation state region. This ladder distribution optimizes the band tilt and quantum confinement effect, enhances the wave function overlap of electrons and holes, and thus significantly improves the light emission intensity and response performance of the epitaxial structure in light emitting devices (such as LEDs) or high-speed electronic devices, while suppressing adverse effects such as thermal escape and non-radiative recombination.

[0059] FIG. 1 shows a flowchart of a preparation method according to an embodiment of the present application. Figure 5 , shows a flowchart of a preparation method provided by an embodiment of the present application.

[0060] The preparation method provided by the embodiment of the present application is used for preparing the gallium nitride-based epitaxial structure described above, and the preparation method comprises the following steps: S1: constructing a gallium nitride-based epitaxial structure simulation model.

[0061] Specifically, the gallium nitride-based epitaxial structure simulation model is described by Poisson equation, continuity equation of electrons and holes, and drift-diffusion current equation of electrons and holes.

[0062] Poisson equation is used to calculate the potential distribution in the semiconductor device, and its expression is as follows: wherein, ε ε represents the dielectric constant of the semiconductor, ∇ represents a gradient operation, φ represents the potential, q e represents the elementary charge of the electron, p p represents the hole density, n n represents the electron density, N D N D represents the ionized donor concentration, N A N A represents the ionized acceptor concentration.

[0063] The continuity equation of electrons and holes describes the conservation of charge, and is respectively as follows: wherein, J n J n represents the current density of the electron, J p J p represents the current density of the hole, R n U n represents the recombination rate of the electron, R p U p represents the recombination rate of the hole,G n denotes the generation rate of electrons, G p denotes the generation rate of holes, denotes the partial derivative operation, t denotes time.

[0064] The drift-diffusion current equations of the electrons and holes are respectively: wherein, μ n denotes the mobility of electrons, μ p denotes the mobility of holes, D n denotes the diffusion coefficient of electrons, D p denotes the diffusion coefficient of holes.

[0065] S2: Determine the breakdown voltage of the gallium nitride-based epitaxial structure under various structure parameters through the simulation model.

[0066] wherein, the breakdown voltage refers to the maximum voltage value that the gallium nitride-based epitaxial structure can withstand under reverse bias, and after exceeding the value, the material will undergo avalanche breakdown or tunneling breakdown, resulting in conduction of the insulating layer and dramatic increase of the current.

[0067] S3: Determine the optimal structure parameters of the gallium nitride-based epitaxial structure according to the breakdown voltage under various structure parameters.

[0068] Optionally, the structure parameters include: thickness of each layer, size parameters of the pyramid-shaped nano structure on the Si substrate, thickness of the step-shaped Al x GaN buffer layer, and doping concentration in the step-shaped Al 1-x GaN barrier layer. y GaN barrier layer.

[0069] In one possible implementation, S3 specifically includes: determining the optimal structure parameters of the gallium nitride-based epitaxial structure according to the breakdown voltage under various structure parameters through the Honey Badger optimization algorithm.

[0070] wherein, the Honey Badger optimization algorithm (HBA) is a kind of swarm intelligence optimization algorithm simulating the foraging behavior of Honey Badger in the wild, and has strong global exploration ability and local development ability. The present application adopts a brand-new Honey Badger optimization algorithm to determine the optimal structure parameters of the gallium nitride-based epitaxial structure.

[0071] Specifically, the breakdown voltage can be used as the fitness function of the Honey Badger optimization algorithm.

[0072] The meerkat individual is initialized by using Sine chaotic mapping, each meerkat individual represents a feasible set of structure parameters, each meerkat individual is composed of multiple dimension components, and each component represents a structure parameter: wherein, x i represents the initial position of the meerkat individual, i lb i represents the lower bound of the feasible solution, i ub i represents the upper bound of the feasible solution, i y i represents the chaotic number corresponding to the meerkat individual, i y i-1 represents the chaotic number corresponding to the meerkat individual, i μ represents a chaotic parameter, generally 0.99.

[0073] It should be noted that the structure parameter represented by each component is specifically the layer thickness mentioned above, the size parameter of the pyramid-shaped nano structure on the Si substrate, the doping concentration in the stepped Al x Ga 1-x N buffer layer, and the doping concentration in the stepped Al y GaN barrier layer.

[0074] In the embodiment of the application, the initial position of the meerkat individual is generated by using Sine chaotic mapping, which has stronger population diversity and ergodicity, can effectively avoid initial solution distribution concentration or repetition, improve early global exploration ability, lay a broader search foundation for subsequent search, and help to jump out of local optimum.

[0075] An elite selection strategy is adopted, and the half of meerkat individuals with higher fitness values are reserved, and the other half of meerkat individuals are discarded, so as to filter the initial population.

[0076] In the embodiment of the application, the half of meerkat individuals with higher fitness values are reserved, which is equivalent to introducing a "survival of the fittest" mechanism in evolution, ensuring that excellent genes are inherited, reducing the interference of inferior solutions on the search direction, and significantly improving the stability and convergence efficiency of the search.

[0077] In the mining stage, a random number r 1, between searching around the global optimal individual or the current individual, parallel selection is selected, and the individual position is updated: When : ;​​​​​ when hour: .

[0078] in, Indicates in t +1 iteration i The location of honey badger individuals, ω t Indicates in t The nonlinear weight factor at the iteration, Indicates in t The first iteration i The location of honey badger individuals, x best represents the location of the global optimal individual, F Indicates the search direction control parameter, β Indicates the ability of a honey badger to obtain food, usually with a fixed value of 6. I i Indicates the i The intensity factor of each honey badger individual, α represents the density factor, r 1 、r 2. r 3 and r 4 represents a random number between 0 and 1.

[0079] In the embodiment of the present invention, the random number r 1. Parallel selection between searching around the global optimal individual or the current individual makes the search path both directional and perturbative, balances global exploration and local development, and effectively enhances the ability to escape from the local optimum.

[0080] in, t Indicates the current iteration number, T Indicates the maximum number of iterations.

[0081] In the embodiment of the present invention, as the iteration proceeds, the weight gradually decreases, so that the early stage maintains strong exploratory nature and the later stage focuses on local fine search, reflecting a time-adaptive search strategy, preventing premature convergence while ensuring the accuracy of the later search.

[0082] in, r 5 represents a random number between 0 and 1, S Indicates the concentration intensity.

[0083] In the embodiment of the present application, the search intensity is adaptively adjusted according to the distance between the individual and the global optimal solution, the exploration force is enhanced when far away from the optimal solution, the search range is slowed down when close to the optimal solution, the individual is prevented from gathering in the optimal area too early, and the synergy efficiency of global search and local convergence is improved.

[0084] wherein, C represents a density constant, and exp represents an exponential function with a natural constant as a base number.

[0085] In the embodiment of the present application, the "focus degree" of the search area is controlled, a large range search is allowed in the early stage, and the meerkat is prompted to concentrate near the optimal solution in the later stage, the search space is gradually focused, and the final solution accuracy is improved, which meets the optimization requirement of gradually approaching the global optimal solution.

[0086] wherein, r 6 represents a random number between 0 and 1.

[0087] In the embodiment of the present application, the direction disturbance is introduced, the search direction is prevented from being solidified, the diversity of the search path is enhanced, it is helpful to prevent falling into a symmetric solution or a dead loop path, and the robustness and adaptability of the algorithm are further improved.

[0088] In the honey collecting stage, the individual position is updated as follows: wherein, r 7 represents a random number between 0 and 1.

[0089] In the embodiment of the present application, by moving the current individual towards the global optimal solution direction, the moving range is controlled by combining a moderate disturbance factor, efficient local fine search is realized, the optimal structure parameter is quickly found near the global optimal solution, and the optimization result is more accurate.

[0090] The fitness value of each meerkat individual and the global optimal individual are updated.

[0091] It is judged whether the current iteration number reaches the maximum iteration number. If yes, the structure parameter set represented by the meerkat individual with the highest fitness is output. Otherwise, the iteration is continued.

[0092] In an embodiment of the present invention, a breakdown voltage-based Honey Badger optimization algorithm is used to intelligently optimize the multilayer parameters of a GaN-based epitaxial structure (such as component ratios, layer thicknesses, and buffer layer structures). This allows for efficient search within a complex, high-dimensional design space for the optimal structural parameter combination that maximizes the breakdown voltage. This approach significantly improves the electrical performance and reliability of the epitaxial structure, while shortening the R&D cycle and reducing manufacturing costs.

[0093] S4: performing surface structuring treatment on the Si substrate 1 according to the optimal structural parameters, and preparing a plurality of pyramid-shaped nanostructures on the surface of the Si substrate 1 .

[0094] Alternatively, multiple pyramid-shaped nanostructures can be fabricated using photolithography. Specifically, a layer of photoresist is first uniformly coated on the surface of a Si substrate. Using ultraviolet (UV) exposure equipment, light is directed through a mask through the photoresist to define a pyramid-shaped pattern. During the exposure process, the photosensitive material chemically reacts in the exposed areas, forming soluble regions. After exposure, a developer removes the photoresist from the unexposed areas, forming the desired pyramid-shaped pattern. Unprotected portions of the silicon surface are removed using dry etching (e.g., plasma etching) or wet etching (e.g., solutions such as hydrofluoric acid) to form the pyramid-shaped structures. S5: forming a graphene layer 2 on the Si substrate 1 by chemical vapor deposition.

[0095] S6: Raise the growth temperature to a high temperature zone, and deposit a high-temperature AlN starting layer 3 on the graphene layer 2 by chemical vapor deposition.

[0096] S7: Deposit a stepped AlN layer on the high temperature AlN starting layer 3 by chemical vapor deposition. x Ga 1-x N buffer layer 4.

[0097] S8: By chemical vapor deposition, on the step-wise Al x Ga 1-x An N-type GaN active layer 5 is deposited on the N buffer layer 4 .

[0098] S9: Deposit a stepped Al layer on the N-type GaN active layer 5 by chemical vapor deposition. y GaN barrier layer 6 .

[0099] S10: By chemical vapor deposition, on the step-type Al y An electron blocking layer 7 is deposited on the GaN barrier layer 6 .

[0100] S11: Forming a P-type GaN contact layer 8 by chemical vapor deposition on the electron blocking layer 7.

[0101] S12: Carrying out surface passivation treatment on the P-type GaN contact layer 8 to deposit a passivation layer 9.

[0102] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the technical solution of the present application, and any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A gallium nitride based epitaxial structure, characterized by, Comprise: A Si substrate with a structured surface, the surface of the Si substrate is provided with a plurality of pyramid-shaped nanostructures; A graphene layer provided on the Si substrate; A high-temperature AlN starting layer provided on the graphene layer; staircase Al x Ga 1-x N buffer layer disposed on the high-temperature AlN starting layer; an N-type GaN active layer disposed on the stepped Al x Ga 1-x N buffer layer; staircase Al y a GaN barrier layer disposed on the N-type GaN active layer; an electron blocking layer disposed on the stepped Al y GaN barrier layer; A P-type GaN contact layer provided on the electron blocking layer; and A passivation layer provided on the P-type GaN contact layer. The N-type GaN active layer has 5 pairs of InGaN well layers and GaN barrier layers alternately stacked to form an indium composition gradient quantum well structure, and the energy band of the indium composition gradient quantum well changes in an asymmetric trapezoidal shape.

2. The gallium nitride based epitaxial structure of claim 1 wherein, the stepped Al x Ga 1-x N buffer layer includes a first-stage Al 0.73 Ga 0.27 N buffer layer, a second-stage Al 0.47 Ga 0.53 N buffer layer, a third-stage Al 0.34 Ga 0.66 N buffer layer, a fourth-stage Al 0.21 Ga 0.79 N buffer layer and a fifth-stage Al 0.12 Ga 0.88 N buffer layer, the aluminum component of the first-stage Al 0.73 Ga 0.27 N buffer layer, the aluminum component of the second-stage Al 0.47 Ga 0.53 N buffer layer, the aluminum component of the third-stage Al 0.34 Ga 0.66 N buffer layer, the aluminum component of the fourth-stage Al 0.21 Ga 0.79 N buffer layer and the aluminum component of the fifth-stage Al 0.12 Ga 0.88 N buffer layer is arranged in a gradient decreasing manner.

3. The gallium nitride based epitaxial structure of claim 2 wherein, the first-stage Al 0.73 Ga 0.27 N buffer layer has a thickness of 60-80 nm, the second-stage Al 0.47 Ga 0.53 N buffer layer has a thickness of 90-110 nm, the third-stage Al 0.34 Ga 0.66 N buffer layer has a thickness of 110-130 nm, the fourth-stage Al 0.21 Ga 0.79 N buffer layer has a thickness of 190-210 nm, the fifth-stage Al 0.12 Ga 0.88 N buffer layer has a thickness of 370-390 nm.

4. The gallium nitride based epitaxial structure of claim 1 wherein, the stepped Al y The GaN barrier layer includes, in order from bottom to top, a first-stage Al 0.4 The GaN barrier layer, the second-stage AlGaN graded barrier layer, and a third-stage Al 0.2 The GaN barrier layer, the Al mole fraction in the second-stage AlGaN graded barrier layer is graded from 40% to 20%.

5. The gallium nitride based epitaxial structure of claim 4 wherein, The first-stage Al 0.4 The thickness of the GaN barrier layer is 20-40 nm, the thickness of the second-stage AlGaN graded barrier layer is 190-210 nm, and the thickness of the third-stage Al 0.2 The thickness of the GaN barrier layer is 20-40 nm.

6. The gallium nitride based epitaxial structure of claim 1 wherein, Comprise the following steps:

7. The gallium nitride based epitaxial structure of claim 6 wherein, The indium composition gradient quantum well near the stepped Al x Ga 1-x The band gap gradient thickness near the GaN buffer layer side is 0.4-0.6 nm, the band gap maintaining thickness in the middle of the indium composition gradient quantum well is 1.0-1.2 nm, and the band gap gradient thickness near the stepped Al y GaN barrier layer side is 1.2-1.4 nm.

8. A method of producing a gallium nitride based epitaxial structure as claimed in any one of claims 1 to 7, characterised by, S1, constructing the simulation model of the gallium nitride-based epitaxial structure, the simulation model describes the potential distribution, charge conservation and carrier current density in the semiconductor device through Poisson equation, continuity equation of electrons and holes and drift-diffusion current equation of electrons and holes; S2, determine the breakdown voltage of the gallium nitride-based epitaxial structure under various structure parameters through the simulation model, the breakdown voltage is the maximum voltage value that the structure can withstand under reverse bias; S3, according to the breakdown voltage under various structure parameters, determine the optimal structure parameters of the gallium nitrate-based epitaxial structure, wherein the step of determining the optimal structure parameters of the gallium nitrate-based epitaxial structure comprises determining by the meerkat optimization algorithm; S4, according to the optimal structure parameters, surface structuring treatment is carried out on the Si substrate to prepare a plurality of pyramid-shaped nanostructures; S5, depositing a graphene layer on the Si substrate by chemical vapor deposition; S6, increase the growth temperature to 1000-1200℃, deposit a high-temperature AlN starting layer on the graphene layer by chemical vapor deposition; S11, depositing a P-type GaN contact layer on the electron blocking layer by chemical vapor deposition; S7, depositing a stepwise AlN buffer layer on the high-temperature AlN starting layer by chemical vapor deposition x Ga 1-x N buffer layer; S8, by chemical vapor deposition on the stepped Al x Ga 1-x An N-type GaN active layer is deposited on the N buffer layer; S9, depositing a step AlGaN barrier layer by chemical vapor deposition on the N-type GaN active layer y GaN barrier layer; S10, depositing an electron blocking layer on the stepped Al y GaN barrier layer by chemical vapor deposition; S12, and surface passivation treatment is carried out on the P-type GaN contact layer to deposit a passivation layer. The meerkat optimization algorithm comprises initializing meerkat individuals by Sine chaotic mapping, each meerkat individual represents a set of structure parameters, and the initialization generates the initial position of the meerkat individual by Sine chaotic mapping.

9. The method of claim 8, wherein the method further comprises: The structural parameters include: the thickness of each layer in the GaN-based epitaxial structure, the size parameters of the pyramid-shaped nanostructure on the Si substrate, the x Ga 1-x The doping concentration of the N buffer layer and the stepped Al y Doping concentration in the GaN barrier layer.

10. The method of claim 8, wherein the method further comprises: ​

Images