Semiconductor device

Abstract

A semiconductor device includes: a lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; an active cutout including a first portion and a second portion, where a lower surface of the second portion is on an upper surface of the insulating pattern; a first source / drain region on a first side of the active cut-out on the insulating pattern; a second source / drain region on a second side of the active cutout opposite to a first side of the active cutout on the insulating pattern in the first horizontal direction; and a bottom source / drain contact penetrating the lower interlayer insulating layer and the insulating pattern in a vertical direction.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0049995, filed on April 15, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including a multi-bridge channel field effect transistor (MBCFET TM ). BACKGROUND

[0003] As a scaling technique for increasing the density of integrated circuit devices, the concept of a multi-gate transistor has been proposed in which a silicon body in the form of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

[0004] The multi-gate transistor utilizes its three-dimensional (3D) channel, thereby allowing easy scaling up and down both. Additionally, the multi-gate transistor provides improved control of current without the need to increase the gate length. Furthermore, the multi-gate transistor effectively mitigates short channel effects (SCE), which is a phenomenon in which the potential of a channel region is affected by the drain voltage. SUMMARY

[0005] Semiconductor devices designed to have active cutouts formed from the backside are provided, which can reduce the complexity of forming the active cutouts and prevent etching of the source / drain regions during the formation of the active cutouts.

[0006] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent by describing in detail the following disclosure presented herein.

[0007] According to aspects of the present disclosure, a semiconductor device includes: an underlayer interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the underlayer interlayer insulating layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; an active cutout including a first portion and a second portion, the first portion penetrating the underlayer interlayer insulating layer and the insulating pattern in the vertical direction, the second portion separating the plurality of nanosheets in the first horizontal direction on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern, and wherein the second portion is on inner side walls of the plurality of nanosheets in the first horizontal direction; a first source / drain region on a first side of the active cutout on the insulating pattern, wherein the first source / drain region is on first outer side walls of the plurality of nanosheets; a second source / drain region on a second side of the active cutout opposite the first side of the active cutout on the insulating pattern in the first horizontal direction, wherein the second source / drain region is on second outer side walls of the plurality of nanosheets; and a bottom source / drain contact penetrating the underlayer interlayer insulating layer and the insulating pattern in the vertical direction, wherein the bottom source / drain contact is electrically connected to the second source / drain region, and wherein the bottom source / drain contact overlaps the first portion of the active cutout in the first horizontal direction, wherein a width of an upper surface of the first portion of the active cutout in the first horizontal direction is less than a width of a lower surface of the first portion of the active cutout in the first horizontal direction.

[0008] According to aspects of the present disclosure, a semiconductor device includes: an under interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the under interlayer insulating layer; a first gate electrode extending in a second horizontal direction on the insulating pattern, wherein the second horizontal direction is different from the first horizontal direction; a second gate electrode extending in the second horizontal direction on the insulating pattern, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction; an active cutout including a first portion penetrating the under interlayer insulating layer and the insulating pattern in a vertical direction and a second portion on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern; a liner layer between the first portion of the active cutout and each of the under interlayer insulating layer and the insulating pattern, wherein the liner layer is on two side walls of the first portion of the active cutout in the first horizontal direction; a first cap pattern on an upper surface of the first gate electrode, wherein the first cap pattern extends in the second horizontal direction; a second cap pattern on an upper surface of the second gate electrode, wherein the second cap pattern extends in the second horizontal direction; and a third cap pattern on an upper surface of the second portion of the active cutout, wherein the third cap pattern extends in the second horizontal direction, wherein an upper surface of the first cap pattern, an upper surface of the second cap pattern, and an upper surface of the third cap pattern are on a same plane, wherein the upper surface of the second portion of the active cutout is lower than the upper surface of the third cap pattern, and wherein a width of the upper surface of the first portion of the active cutout in the first horizontal direction is less than a width of a lower surface of the first portion of the active cutout in the first horizontal direction.

[0009] According to an aspect of the present disclosure, a semiconductor device includes: an under-interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the under-interlayer insulating layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; a first gate electrode extending in a second horizontal direction on the insulating pattern, wherein the second horizontal direction is different from the first horizontal direction; a second gate electrode extending in the second horizontal direction on the insulating pattern, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction; an active cutout extending in the second horizontal direction between the first gate electrode and the second gate electrode, wherein the active cutout includes a first portion penetrating the under-interlayer insulating layer and the insulating pattern in the vertical direction and a second portion separating the plurality of nanosheets in the first horizontal direction on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern, and wherein the second portion is on inner side walls of the plurality of nanosheets in the first horizontal direction; a first source / drain region on the insulating pattern between the first gate electrode and the active cutout, wherein the first source / drain region is on first outer side walls of the plurality of nanosheets; a second source / drain region on the insulating pattern between the active cutout and the second gate electrode, wherein the second source / drain region is on second outer side walls of the plurality of nanosheets; a liner layer between the first portion of the active cutout and each of the under-interlayer insulating layer and the insulating pattern, wherein the liner layer is on both side walls of the first portion of the active cutout in the first horizontal direction; a cap pattern on an upper surface of the second portion of the active cutout, wherein the cap pattern extends in the second horizontal direction; a gate spacer on both side walls of the second portion of the active cutout in the first horizontal direction on an upper surface of an uppermost nanosheet among the plurality of nanosheets, wherein the gate spacer is on the second portion of the active cutout; and a bottom source / drain contact penetrating the under-interlayer insulating layer and the insulating pattern in the vertical direction, wherein the bottom source / drain contact is electrically connected to the second source / drain region, and wherein the bottom source / drain contact overlaps the first portion of the active cutout in the first horizontal direction, wherein an upper surface of the second portion of the active cutout is lower than an upper surface of the cap pattern, wherein at least a portion of the second portion of the active cutout overlaps the plurality of nanosheets in the vertical direction between adjacent nanosheets among the plurality of nanosheets, and wherein a width of the upper surface of the first portion of the active cutout in the first horizontal direction is smaller than a width of the lower surface of the first portion of the active cutout in the first horizontal direction.

[0010] It should be noted that effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a layout diagram of a semiconductor device according to an embodiment.

[0013] Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 according to an embodiment.

[0014] Figure 3 is a cross-sectional view taken along line B-B' of Figure 1 according to an embodiment.

[0015] Figure 4 is a cross-sectional view taken along line C-C' of Figure 1 according to an embodiment.

[0016] Figures 5 to 36 is a cross-sectional view for explaining an intermediate step of a method of manufacturing a semiconductor device according to an embodiment.

[0017] Figure 37 is a cross-sectional view for explaining a semiconductor device according to an embodiment.

[0018] Figure 38 is a cross-sectional view for explaining a semiconductor device according to an embodiment.

[0019] Figure 39 is a cross-sectional view for explaining a semiconductor device according to an embodiment.

[0020] Figure 40 is a cross-sectional view for explaining a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0021] A semiconductor device according to some embodiments of the present disclosure is shown in the accompanying drawings as including a multi-bridge channel field effect transistor (MBCFET TM ) having nanosheets, but embodiments are not limited thereto. In some embodiments, a semiconductor device according to some embodiments of the present disclosure can include a fin-type field effect transistor (FinFET), a tunneling field effect transistor (FET), or a three-dimensional (3D) transistor having a fin-shaped pattern channel region. Further, a semiconductor device according to some embodiments of the present disclosure can include a bipolar junction transistor or a lateral double-diffused metal oxide semiconductor (LDMOS) transistor.

[0022] A semiconductor device according to some embodiments of the present disclosure is described below with reference to Figures 1 to 4 .

[0023] Figure 1is a layout diagram for explaining a semiconductor device according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view taken along Figure 1 line A-A' of Figure 3 is a cross-sectional view taken along Figure 1 line B-B' of Figure 4 is a cross-sectional view taken along Figure 1 line C-C' of

[0024] Referring to Figures 1 to 4 , a semiconductor device according to some embodiments of the present disclosure includes an under-interlayer dielectric layer 100, an insulating pattern 101, a first sacrificial pattern 102, a field insulating layer 105, a first plurality of nanosheets NW1, a second plurality of nanosheets NW2, a third plurality of nanosheets NW3, a first gate electrode G1, a second gate electrode G2, a first gate spacer 111, a second gate spacer 112, a third gate spacer 113, a first gate insulating layer 121, a second gate insulating layer 122, a first cap pattern 131, a second cap pattern 132, a third cap pattern 133, a first source / drain region SD1, a second source / drain region SD2, a first etch stop layer 140, a first upper-interlayer dielectric layer 150, an active cutout 160, a liner layer 170, a gate contact CB, an upper source / drain contact UCA, a bottom source / drain contact BCA, an upper silicide layer USL, a lower silicide layer BSL, a second etch stop layer 180, a second upper-interlayer dielectric layer 185, a first via V1, and a second via V2.

[0025] The under-interlayer dielectric layer 100 can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material can be, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ, fluorosilicate glass (FSG), polyimide nanocellulose (such as polypropylene oxide), carbon-doped oxide silicon (CDO), organosilicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but embodiments are not limited thereto.

[0026] In the following description, a first horizontal direction DR1 and a second horizontal direction DR2 can be defined as directions parallel to an upper surface of the lower interlayer insulation layer 100. The second horizontal direction DR2 can be defined as a direction different from the first horizontal direction DR1. A vertical direction DR3 can be defined as a direction perpendicular to both the first horizontal direction DR1 and the second horizontal direction DR2. For example, the vertical direction DR3 can be defined as a direction perpendicular to the upper surface of the lower interlayer insulation layer 100.

[0027] The insulation pattern 101 can extend on the upper surface of the lower interlayer insulation layer 100 in the first horizontal direction DR1. The insulation pattern 101 can protrude from the upper surface of the lower interlayer insulation layer 100 in the vertical direction DR3. A lower surface of the insulation pattern 101 can be in contact with the upper surface of the lower interlayer insulation layer 100. The insulation pattern 101 can include an insulating material. For example, the insulation pattern 101 can include the same material as the lower interlayer insulation layer 100.

[0028] The field insulation layer 105 can be disposed on the upper surface of the lower interlayer insulation layer 100. The field insulation layer 105 can surround a sidewall of the insulation pattern 101. For example, an upper surface of the insulation pattern 101 can protrude beyond an upper surface of the field insulation layer 105 in the vertical direction DR3, but embodiments are not limited thereto. In some embodiments, the upper surface of the insulation pattern 101 can be formed on the same plane as the upper surface of the field insulation layer 105. The field insulation layer 105 can include, for example, an oxide film, a nitride film, a nitride oxide film, or a combination thereof.

[0029] A first plurality of nanosheets NW1 can be disposed on the insulation pattern 101. The first plurality of nanosheets NW1 can be disposed at an intersection of the insulation pattern 101 and the first gate electrode G1. A second plurality of nanosheets NW2 can be disposed on the insulation pattern 101. The second plurality of nanosheets NW2 can be disposed at an intersection of the insulation pattern 101 and the second gate electrode G2. The second plurality of nanosheets NW2 can be spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1.

[0030] A third plurality of nanosheets NW3 can be disposed on the insulation pattern 101. The third plurality of nanosheets NW3 can be disposed at an intersection of the insulation pattern 101 and the active cut 160. The third plurality of nanosheets NW3 can be disposed between the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2. The third plurality of nanosheets NW3 can be spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1. The second plurality of nanosheets NW2 can be spaced apart from the third plurality of nanosheets NW3 in the first horizontal direction DR1. For example, the third plurality of nanosheets NW3 can include a first portion and a second portion spaced apart from the first portion in the first horizontal direction DR1. For example, the second portion of the third plurality of nanosheets NW3 can be spaced apart from the first portion of the third plurality of nanosheets NW3 in the first horizontal direction DR1.

[0031] The first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 can include a stack of a plurality of nanosheets vertically spaced apart in the vertical direction DR3. In Figure 2 and Figure 3 In the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 are shown as including a stack of three nanosheets stacked to be spaced apart from another stack in the vertical direction DR3, but embodiments are not limited thereto. In some embodiments, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 can include a stack of four or more nanosheets stacked to be spaced apart from another stack in the vertical direction DR3. For example, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 can include silicon (Si), but embodiments are not limited thereto. In some embodiments, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 can include silicon germanium (SiGe).

[0032] The first gate electrode G1 can extend on the insulating pattern 101 and the field insulating layer 105 in the second horizontal direction DR2. The first gate electrode G1 can surround the first plurality of nanosheets NW1. The second gate electrode G2 can extend on the insulating pattern 101 and the field insulating layer 105 in the second horizontal direction DR2. The second gate electrode G2 can surround the second plurality of nanosheets NW2. The second gate electrode G2 can be spaced apart from the first gate electrode G1 in the first horizontal direction DR1.

[0033] The first gate electrode G1 and the second gate electrode G2 can include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. The first gate electrode G1 and the second gate electrode G2 can include a conductive metal oxide or a conductive metal oxynitride, and can also include an oxidized form of any of the foregoing materials.

[0034] The first source / drain region SD1 may be disposed between the first plurality of nanosheets NW1 and the first outer sidewalls of the third plurality of nanosheets NW3 on the insulating pattern 101. For example, the first source / drain region SD1 may contact the sidewalls of the first plurality of nanosheets NW1 in the first horizontal direction DR1 and the first outer sidewalls of the third plurality of nanosheets NW3 in the first horizontal direction DR1. The second source / drain region SD2 may be disposed between the second outer sidewalls of the third plurality of nanosheets NW3 and the second plurality of nanosheets NW2 on the insulating pattern 101. The second outer sidewalls of the third plurality of nanosheets NW3 may be defined as the sidewalls of the third plurality of nanosheets NW3 that are opposite to the first outer sidewalls of the third plurality of nanosheets NW3 in the first horizontal direction DR1. For example, the second source / drain region SD2 may contact the second outer sidewalls of the third plurality of nanosheets NW3 and the sidewalls of the second plurality of nanosheets NW2 in the first horizontal direction DR1.

[0035] A first sacrificial pattern 102 may be disposed below the first source / drain region SD1. The first sacrificial pattern 102 may contact a lower surface of the first source / drain region SD1. The first sacrificial pattern 102 may penetrate the insulating pattern 101 and the lower interlayer insulating layer 100 in the vertical direction DR3. For example, the lower interlayer insulating layer 100 may cover the lower surface of the first sacrificial pattern 102. For example, a sidewall of the first sacrificial pattern 102 in the first horizontal direction DR1 may contact the insulating pattern 101 and the lower interlayer insulating layer 100. The first sacrificial pattern 102 may include a material different from that of the lower interlayer insulating layer 100 and the insulating pattern 101. For example, the first sacrificial pattern 102 may include SiGe.

[0036] For example, the first trench T1 may penetrate the lower interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. For example, the first trench T1 may be formed below the third plurality of nanosheets NW3. For example, the upper surface of the first trench T1 may be formed to be higher than the upper surface of the insulating pattern 101. The sidewall of the first trench T1 in the first horizontal direction DR1 may have a continuously inclined profile in a direction toward the upper surface of the first trench T1. For example, the sidewall of the first trench T1 in the first horizontal direction DR1 may not be stepped.

[0037] The spacer layer 170 can be disposed along the sidewall of the first trench T1. For example, the spacer layer 170 can be in contact with the underlayer interlayer insulating layer 100 and the insulating pattern 101. For example, the spacer layer 170 can be conformally formed. For example, an upper surface of the spacer layer 170 can be formed higher than an upper surface of the insulating pattern 101. For example, a lower surface of the spacer layer 170 can be formed on the same plane as a lower surface of the underlayer interlayer insulating layer 100. However, embodiments are not limited thereto. In some embodiments, the underlayer interlayer insulating layer 100 can cover the lower surface of the spacer layer 170. For example, the spacer layer 170 can be spaced apart from the first sacrificial pattern 102 in the first horizontal direction DR1. For example, the spacer layer 170 can include a different material from the underlayer interlayer insulating layer 100 and the insulating pattern 101. The spacer layer 170 can include an insulating material. For example, the spacer layer 170 can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), silicon carbon oxide (SiOC), and combinations thereof, but embodiments are not limited thereto.

[0038] The active cut 160 can extend between the first gate electrode G1 and the second gate electrode G2 in the second horizontal direction DR2. For example, the active cut 160 can be disposed between the first source / drain region SD1 and the second source / drain region SD2. For example, the first source / drain region SD1 can be disposed on a first side of the active cut 160, and the second source / drain region SD2 can be disposed on a second side of the active cut 160 opposite the first side of the active cut 160 in the first horizontal direction DR1. The active cut 160 can penetrate the underlayer interlayer insulating layer 100, the insulating pattern 101, and the third plurality of nanosheets NW3 in the vertical direction DR3. For example, the active cut 160 can separate the insulating pattern 101 in the first horizontal direction DR1. For example, the active cut 160 can separate the third plurality of nanosheets NW3 in the first horizontal direction DR1. For example, the active cut 160 can separate the third plurality of nanosheets NW3 into a first portion and a second portion. For example, the first portion of the third plurality of nanosheets NW3 can be in contact with the first source / drain region SD1, and the second portion of the third plurality of nanosheets NW3 can be in contact with the second source / drain region SD2.

[0039] For example, the active cutout 160 can include a first portion 161 and a second portion 162. The first portion 161 of the active cutout 160 can be disposed between portions of the liner layer 170 within the first trench T1. For example, the first portion 161 of the active cutout 160 can completely fill an interior of the first trench T1 along a sidewall of the liner layer 170. The first portion 161 of the active cutout 160 can penetrate both the lower interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. For example, sidewalls of the first portion 161 in the first horizontal direction DR1 can be spaced apart from the lower interlayer insulating layer 100 and the insulating pattern 101, respectively. For example, the liner layer 170 can be disposed between the first portion 161 of the active cutout 160 and each of the lower interlayer insulating layer 100 and the insulating pattern 101.

[0040] For example, a sidewall of the first portion 161 of the active cutout 160 in the first horizontal direction DR1 can be in contact with the liner layer 170. The first portion 161 of the active cutout 160 can be superposed on the first sacrificial pattern 102 in the first horizontal direction DR1. In some embodiments, the first portion 161 of the active cutout 160 can be spaced apart from the first sacrificial pattern 102 in the first horizontal direction DR1. An upper surface 161a of the first portion 161 of the active cutout 160 can be formed higher than an upper surface of the insulating pattern 101. For example, a lower surface 161b of the first portion 161 of the active cutout 160 can be formed on the same plane as a lower surface of the lower interlayer insulating layer 100. However, embodiments are not limited thereto. In some embodiments, the lower interlayer insulating layer 100 can cover the lower surface 161b of the first portion 161 of the active cutout 160.

[0041] For example, a width W1 of the upper surface 161a of the first portion 161 of the active cutout 160 in the first horizontal direction DR1 can be less than a width W2 of the lower surface 161b of the first portion 161 in the first horizontal direction DR1. For example, the width of the first portion 161 in the first horizontal direction DR1 can continuously decrease closer to the upper surface 161a of the first portion 161 of the active cutout 160. For example, a sidewall of the first portion 161 of the active cutout 160 in the first horizontal direction DR1 can have a continuously sloped profile. For example, the sidewall of the first portion 161 of the active cutout 160 in the first horizontal direction DR1 can not be stepped.

[0042] The second portion 162 of the active cutout 160 can be disposed on the upper surface 161a of the first portion 161. For example, the second portion 162 of the active cutout 160 can be in contact with the upper surface 161a of the first portion 161. For example, the second portion 162 of the active cutout 160 can be in contact with the upper surface of the spacer layer 170. For example, at least a portion of the second portion 162 of the active cutout 160 can be in contact with the sidewall of the spacer layer 170 in the first horizontal direction DR1. For example, the second portion 162 of the active cutout 160 can separate the third plurality of nanosheets NW3 into a first portion in contact with the first source / drain region SD1 and a second portion in contact with the second source / drain region SD2. The second portion 162 of the active cutout 160 can be in contact with both the inner sidewall of the first portion of the third plurality of nanosheets NW3 in the first horizontal direction DR1 and the inner sidewall of the second portion of the third plurality of nanosheets NW3 in the first horizontal direction DR1.

[0043] For example, the second portion 162 of the active cutout 160 can surround the third plurality of nanosheets NW3. For example, between the upper surface of the insulating pattern 101 and the lower surface of the lowermost nanosheet among the third plurality of nanosheets NW3, at least a portion of the second portion 162 of the active cutout 160 can be superposed on the third plurality of nanosheets NW3 in the vertical direction DR3. Also, between adjacent nanosheets from among the third plurality of nanosheets NW3, at least a portion of the second portion 162 of the active cutout 160 can be superposed on the third plurality of nanosheets NW3 in the vertical direction DR3. For example, the second portion 162 of the active cutout 160 can be in contact with the upper surface and the lower surface of each of the third plurality of nanosheets NW3. For example, at least a portion of the second portion 162 of the active cutout 160 can be superposed on the lower interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3.

[0044] For example, at least a portion of the first portion 161 of the active cutout 160 can extend into an interior of the second portion 162 of the active cutout 160. For example, at least a portion of the second portion 162 of the active cutout 160 can overlap the first portion 161 of the active cutout 160 in the first horizontal direction DR1. For example, a lower surface of the second portion 162 of the active cutout 160 can be formed lower than an upper surface 161a of the first portion 161. The lower surface of the second portion 162 of the active cutout 160 can be in contact with an upper surface of the insulating pattern 101. For example, between the upper surface of the insulating pattern 101 and a lower surface of a lowermost nanosheet among the third plurality of nanosheets NW3, a sidewall of the second portion 162 of the active cutout 160 in the first horizontal direction DR1 can be in contact with both the first source / drain region SD1 and the second source / drain region SD2. Further, between adjacent nanosheets among the third plurality of nanosheets NW3, a sidewall of the second portion 162 of the active cutout 160 in the first horizontal direction DR1 can be in contact with both the first source / drain region SD1 and the second source / drain region SD2.

[0045] For example, the second portion 162 of the active cutout 160 can be integrally formed with the first portion 161 of the active cutout 160. For example, the first portion 161 and the second portion 162 of the active cutout 160 can include the same material. The active cutout 160 can include an insulating material. For example, the active cutout 160 can include at least one of SiN, SiON, SiCN, SiOCN, SiOC, and combinations thereof. However, embodiments are not limited thereto. For example, the active cutout 160 can include a different material from the liner layer 170, but embodiments are not limited thereto. In some embodiments, the active cutout 160 can include the same material as the liner layer 170.

[0046] The first gate spacer 111 can extend in the second horizontal direction DR2 along two sidewalls of the first gate electrode G1 on the field insulating layer 105 and an upper surface of an uppermost nanosheet of the first plurality of nanosheets NW1. The second gate spacer 112 can extend in the second horizontal direction DR2 along two sidewalls of the second gate electrode G2 on the field insulating layer 105 and an upper surface of an uppermost nanosheet of the second plurality of nanosheets NW2. The third gate spacer 113 can extend in the second horizontal direction DR2 along two sidewalls of the second portion 162 of the active cutout 160 on the field insulating layer 105 and an upper surface of an uppermost nanosheet of the third plurality of nanosheets NW3. For example, the third gate spacer 113 can be in contact with the sidewalls of the second portion 162 of the active cutout 160 in the first horizontal direction DR1. The first gate spacer 111, the second gate spacer 112, and the third gate spacer 113 can include at least one of SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof, although embodiments are not limited thereto. In some embodiments, the third gate spacer 113 can be on two sidewalls of the second portion 162 of the active cutout 160 in the first horizontal direction DR1 on the upper surface of an uppermost nanosheet among the third plurality of nanosheets NW3.

[0047] The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the insulating pattern 101. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the field insulating layer 105. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the first gate spacer 111. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the first plurality of nanosheets NW1. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the first source / drain region SD1. For example, the first gate insulating layer 121 can contact the first source / drain region SD1.

[0048] The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the insulating pattern 101. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the field insulating layer 105. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the second gate spacer 112. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the second plurality of nanosheets NW2. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the second source / drain region SD2. For example, the second gate insulating layer 122 can contact the second source / drain region SD2.

[0049] The first gate insulating layer 121 and the second gate insulating layer 122 can include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a larger dielectric constant than silicon oxide. The high-k material can include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0050] A semiconductor device according to some embodiments of the disclosure can include a negative capacitance (NC) FET using a negative capacitor. For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0051] The ferroelectric material film can have a negative capacitance, and the paraelectric material film can have a positive capacitance. For example, if two or more capacitors are connected in series and have positive capacitances, a total capacitance of the two or more capacitors can be lower than a capacitance of each of the two or more capacitors. As another example, if at least one of the two or more capacitors has a negative capacitance, a total capacitance of the two or more capacitors can have a positive value and can be greater than an absolute value of the capacitance of each of the two or more capacitors.

[0052] If the ferroelectric material film having a negative capacitance and the paraelectric material film having a positive capacitance are connected in series, a total capacitance of the ferroelectric material film and the paraelectric material film can increase. Accordingly, a transistor having the ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV per decade at room temperature.

[0053] The ferroelectric material film can have ferroelectric properties. The ferroelectric material film can include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, the hafnium zirconium oxide can be a material obtained by doping hafnium oxide with zirconium (Zr). In another example, the hafnium zirconium oxide can be a compound of hafnium (Hf), Zr, and oxygen (O).

[0054] The ferroelectric material film can further include a dopant. For example, the dopant can include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), Si, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), Ge, scandium (Sc), strontium (Sr), and Sn. The type of the dopant can vary according to the type of the material of the ferroelectric material film.

[0055] If the ferroelectric material film includes hafnium oxide, the dopant of the ferroelectric material film can include, for example, at least one of Gd, Si, Zr, Al, and Y.

[0056] If the dopant of the ferroelectric material film is Al, the ferroelectric material film can include Al in a range of about 3 atomic percent (at%) to about 8 at%. Here, the ratio of the dopant in the ferroelectric material film can represent a ratio of a sum of amounts of Hf and Al to the amount of Al in the ferroelectric material film.

[0057] If the dopant of the ferroelectric material film is Si, the ferroelectric material film can include Si in a range of about 2 at% to about 10 at%. If the dopant of the ferroelectric material film is Y, the ferroelectric material film can include Y in a range of about 2 at% to about 10 at%. If the dopant of the ferroelectric material film is Gd, the ferroelectric material film can include Gd in a range of about 1 at% to about 7 at%. If the dopant of the ferroelectric material film is Zr, the ferroelectric material film can include Zr in a range of about 50 at% to about 80 at%.

[0058] The paraelectric material film can have paraelectric properties. The paraelectric material film can include, for example, at least one of silicon oxide and a high-k metal oxide. The high-k metal oxide can include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but embodiments are not limited thereto.

[0059] The ferroelectric material film and the paraelectric material film can include the same material. The ferroelectric material film can have ferroelectric properties, but the paraelectric material film can not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the hafnium oxide included in the ferroelectric material film can have a different crystal structure from the hafnium oxide included in the paraelectric material film.

[0060] The ferroelectric material film can be thick enough to exhibit ferroelectric properties. The ferroelectric material film can have, for example, a thickness of about 0.5 nanometers (nm) to about 10 nm, but embodiments are not limited thereto. A critical thickness at which ferroelectric properties can be exhibited can vary according to the type of ferroelectric material, and thus, the thickness of the ferroelectric material film can vary according to the type of ferroelectric material included in the ferroelectric material film.

[0061] For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a ferroelectric material film. In another example, each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a plurality of ferroelectric material films spaced apart from each other. Each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a stack of a plurality of ferroelectric material films and a plurality of paraelectric material films alternately stacked with the ferroelectric material films.

[0062] A first etch stop layer 140 can be disposed on sidewalls of each of the first gate spacer 111, the second gate spacer 112, and the third gate spacer 113 in the first horizontal direction DR1. The first etch stop layer 140 can also be disposed on upper surfaces of the first source / drain region SD1 and the second source / drain region SD2. In some embodiments, the first etch stop layer 140 can be disposed on sidewalls of each of the first source / drain region SD1 and the second source / drain region SD2 in the second horizontal direction DR2. For example, the first etch stop layer 140 can be conformally formed. The first etch stop layer 140 can include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0063] The first cap pattern 131 can extend over each of the first gate spacer 111, the first gate insulating layer 121, and the first gate electrode G1 in the second horizontal direction DR2. The second cap pattern 132 can extend over each of the second gate spacer 112, the second gate insulating layer 122, and the second gate electrode G2 in the second horizontal direction DR2. The third cap pattern 133 can extend over the second portion 162 of the active cutout 160 and the third gate spacer 113 in the second horizontal direction DR2. For example, the third cap pattern 133 can be in contact with an upper surface of the second portion 162 of the active cutout 160. For example, a lowermost surface of the third cap pattern 133 can be formed lower than an uppermost surface of the second portion 162 of the active cutout 160. For example, at least a portion of the second portion 162 of the active cutout 160 can extend into an interior of the third cap pattern 133. For example, at least a portion of the second portion 162 of the active cutout 160 can overlap the third cap pattern 133 in the first horizontal direction DR1.

[0064] For example, upper surfaces of the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133 can be formed on the same plane. For example, an upper surface of the second portion 162 of the active cutout 160 can be formed lower than an upper surface of the third cap pattern 133. For example, a lower surface of the first cap pattern 131 can be in contact with an upper surface of the first gate spacer 111. A lower surface of the second cap pattern 132 can be in contact with an upper surface of the second gate spacer 112. A lower surface of the third cap pattern 133 can be in contact with an upper surface of the third gate spacer 113. For example, lower surfaces of the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133 can be in contact with the first etch stop layer 140, but embodiments are not limited thereto. In some embodiments, sidewalls of the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133 can be in contact with the first etch stop layer 140.

[0065] For example, the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133 can include an insulating material. The first cap pattern 131, the second cap pattern 132, and the third cap pattern 133 can include, for example, at least one of SiN, SiON, SiO2, SiCN, SiOCN, and combinations thereof, although embodiments are not limited thereto. For example, the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133 can include a different material from the active cutout 160, although embodiments are not limited thereto. In some embodiments, the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133 can include the same material as the active cutout 160.

[0066] The first upper interlayer insulating layer 150 can be disposed on the first etch stop layer 140. The first upper interlayer insulating layer 150 can be disposed on sidewalls of each of the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133. The first upper interlayer insulating layer 150 can cover each of the first source / drain region SD1 and the second source / drain region SD2 on the field insulating layer 105. For example, an upper surface of the first upper interlayer insulating layer 150 can be formed on the same plane as upper surfaces of the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133. However, embodiments are not limited thereto. In some embodiments, the first upper interlayer insulating layer 150 can cover the upper surfaces of the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133. The first upper interlayer insulating layer 150 can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0067] The upper source / drain contact UCA can be disposed between the first gate electrode G1 and the second gate electrode G2. The upper source / drain contact UCA can be disposed over the first source / drain region SD1. The upper source / drain contact UCA can extend into the first source / drain region SD1 by penetrating the first upper interlayer insulating layer 150 and the first etch stop layer 140 in the vertical direction DR3. The upper source / drain contact UCA can be electrically connected to the first source / drain region SD1. In Figure 2 In the middle, the upper source / drain contact UCA is shown as being formed as a single layer, although embodiments are not limited thereto. In some embodiments, the upper source / drain contact UCA can be formed as multiple layers.

[0068] For example, an upper surface of the upper source / drain contact UCA can be formed on the same plane as an upper surface of the first upper interlayer insulating layer 150, although embodiments are not limited thereto. In some embodiments, an upper surface of the upper source / drain contact UCA can be formed higher than an upper surface of the first upper interlayer insulating layer 150. For example, an upper surface of the upper source / drain contact UCA can be formed higher than an upper surface of the second portion 162 of the active cutout 160. The upper source / drain contact UCA can include a conductive material. An upper silicide layer USL can be disposed between the upper source / drain contact UCA and the first source / drain region SD1. The upper silicide layer USL can be disposed along a boundary between the upper source / drain contact UCA and the first source / drain region SD1. For example, the upper silicide layer USL can include a metal silicide material.

[0069] The gate contact CB can be located above the first gate electrode G1. The gate contact CB can be connected to the first gate electrode G1 by penetrating the first cap pattern 131 in the vertical direction DR3. In Figure 3 In the middle, the gate contact CB is shown as being formed as a single layer, although embodiments are not limited thereto. In some embodiments, the gate contact CB can be formed as multiple layers. For example, an upper surface of the gate contact CB can be formed on the same plane as upper surfaces of the upper source / drain contact UCA and the first upper interlayer insulating layer 150, although embodiments are not limited thereto. The gate contact CB can include a conductive material.

[0070] The bottom source / drain contact BCA can be disposed between the active cutout 160 and the second gate electrode G2. The bottom source / drain contact BCA can be disposed below the second source / drain region SD2. The bottom source / drain contact BCA can be electrically connected to the second source / drain region SD2 by penetrating the lower interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. For example, the bottom source / drain contact BCA can overlap the first portion 161 of the active cutout 160 in the first horizontal direction DR1. For example, the bottom source / drain contact BCA can be spaced apart from the first portion 161 of the active cutout 160 in the first horizontal direction DR1. However, embodiments are not limited thereto. In some embodiments, the bottom source / drain contact BCA can be in contact with the first portion 161 of the active cutout 160.

[0071] For example, the bottom source / drain contact BCA can be formed as a single layer, although embodiments are not limited thereto. In some embodiments, the bottom source / drain contact BCA can be formed as multiple layers. For example, two sidewalls of the bottom source / drain contact BCA in the first horizontal direction DR1 can contact the insulating pattern 101 and the lower interlayer insulating layer 100. For example, a lower surface of the bottom source / drain contact BCA can be formed on a same plane as a lower surface of the lower interlayer insulating layer 100. The bottom source / drain contact BCA can include a conductive material. A lower silicide layer BSL can be disposed between the bottom source / drain contact BCA and the second source / drain region SD2. The lower silicide layer BSL can be disposed along a boundary between the bottom source / drain contact BCA and the second source / drain region SD2. The lower silicide layer BSL can include, for example, a metal silicide material.

[0072] A second etch stop layer 180 can be disposed on an upper surface of the upper source / drain contact UCA, the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133, and the first upper interlayer insulating layer 150. For example, the second etch stop layer 180 can be spaced apart from an upper surface of the second portion 162 of the active cut 160 in the vertical direction DR3. In some embodiments, the second etch stop layer 180 can be disposed on an upper surface of the first upper interlayer insulating layer 150. Figure 2 and Figure 4 In, the second etch stop layer 180 is shown as being formed as a single layer, although embodiments are not limited thereto. In some embodiments, the second etch stop layer 180 can be formed as multiple layers. The second etch stop layer 180 can include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. A second upper interlayer insulating layer 185 can be disposed on the second etch stop layer 180. The second upper interlayer insulating layer 185 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0073] A first via V1 can be connected to the upper source / drain contact UCA by penetrating the second upper interlayer insulating layer 185 and the second etch stop layer 180 in the vertical direction DR3. Similarly, a second via V2 can be connected to the gate contact CB by penetrating the second upper interlayer insulating layer 185 and the second etch stop layer 180 in the vertical direction DR3. In some embodiments, the first via V1 and the second via V2 can be formed as multiple layers. Figure 2 and Figure 3 In , the first via V1 and the second via V2 are shown as being formed as a single layer, although embodiments are not limited thereto. In some embodiments, the first via V1 and the second via V2 can be formed as multiple layers. The first via V1 and the second via V2 can include a conductive material.

[0074] Examples of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure are described below with reference to Figure 2 and Figures 5 to 36

[0075] Figures 5 to 36 is a cross-sectional view for explaining an intermediate step of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0076] Referring to Figure 5 and Figure 6 A substrate 10 can be provided. The substrate 10 can be a Si substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 10 can include SiGe, silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but embodiments are not limited thereto.

[0077] Thereafter, a stack structure 20 can be formed on an upper surface of the substrate 10. The stack structure 20 can include first semiconductor layers 21 stacked on the upper surface of the substrate 10 and second semiconductor layers 22 alternating with the first semiconductor layers 21. For example, the first semiconductor layers 21 can be formed at a bottom of the stack structure 20, and the second semiconductor layers 22 can be formed at a top of the stack structure 20. However, embodiments are not limited thereto. In some embodiments, the first semiconductor layers 21 can also be formed at the top of the stack structure 20. The first semiconductor layers 21 can include, for example, SiGe. The second semiconductor layers 22 can include, for example, Si.

[0078] Thereafter, a portion of the stack structure 20 can be etched. During the etching of the stack structure 20, a portion of the substrate 10 can also be etched. Through the etching process, an active pattern 11 can be defined under the stack structure 20 on the upper surface of the substrate 10. The active pattern 11 can protrude from the upper surface of the substrate 10 in a vertical direction DR3. The active pattern 11 can extend in a first horizontal direction DR1.

[0079] Thereafter, a field insulating layer 105 can be formed on the upper surface of the substrate 10. The field insulating layer 105 can surround sidewalls of the active pattern 11. For example, an upper surface of the active pattern 11 can be formed higher than an upper surface of the field insulating layer 105. Thereafter, a pad oxide layer 30 can be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls of the active pattern 11, and the sidewalls and the upper surface of the stack structure 20. For example, the pad oxide layer 30 can be formed conformally. The pad oxide layer 30 can include, for example, SiO2.

[0080] Referring to Figure 7 and Figure 8A first dummy gate DG1, a second dummy gate DG2, and a third dummy gate DG3, which can extend in a second horizontal direction DR2, and a first dummy cap pattern DC1, a second dummy cap pattern DC2, and a third dummy cap pattern DC3, which can also extend in the second horizontal direction DR2, can be formed on the pad oxide layer 30, on the stack structure 20, and the field insulating layer 105. For example, the third dummy gate DG3 can be spaced apart from the first dummy gate DG1 in a first horizontal direction DR1, and the second dummy gate DG2 can be spaced apart from the third dummy gate DG3 in the first horizontal direction DR1. The first dummy cap pattern DC1 can be disposed on the first dummy gate DG1. The second dummy cap pattern DC2 can be disposed on the second dummy gate DG2. The third dummy cap pattern DC3 can be disposed on the third dummy gate DG3.

[0081] During the formation of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, and the first dummy cap pattern DC1, the second dummy cap pattern DC2, and the third dummy cap pattern DC3, a portion of the entire pad oxide layer 30 except for a portion overlaid with the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 in a vertical direction DR3 can be removed.

[0082] Thereafter, a spacer material layer SM can be formed to cover side walls of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, side walls and an upper surface of the first dummy cap pattern DC1, the second dummy cap pattern DC2, and the third dummy cap pattern DC3, and an exposed upper surface of the stack structure 20. For example, the spacer material layer SM can be conformally formed. The spacer material layer SM can include, for example, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof.

[0083] Referring to Figure 9 The first source / drain trench ST1 and the second source / drain trench ST2 can be formed by etching the stack structure 20 and the active pattern 11 using the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, and the first dummy cap pattern DC1, the second dummy cap pattern DC2, and the third dummy cap pattern DC3 as masks. The first source / drain trench ST1 can be formed between the first dummy gate DG1 and the third dummy gate DG3. The second source / drain trench ST2 can be formed between the second dummy gate DG2 and the third dummy gate DG3.

[0084] Additionally, a first sacrificial pattern trench 102T can be formed below the first source / drain trench ST1, and a second sacrificial pattern trench 103T can be formed below the second source / drain trench ST2. For example, the first sacrificial pattern trench 102T and the second sacrificial pattern trench 103T can penetrate the active pattern 11 in the vertical direction DR3 and extend into the interior of the substrate 10. For example, a lower surface of the first sacrificial pattern trench 102T and the second sacrificial pattern trench 103T can be defined by the substrate 10. For example, a width of the first sacrificial pattern trench 102T and the second sacrificial pattern trench 103T in the first horizontal direction DR1 can be smaller than a width of each of the first source / drain trench ST1 and the second source / drain trench ST2 in the first horizontal direction DR1, although embodiments are not limited thereto.

[0085] For example, during formation of the first source / drain trench ST1 and the second source / drain trench ST2 and the first sacrificial pattern trench 102T and the second sacrificial pattern trench 103T, portions of the first dummy cap pattern DC1, the second dummy cap pattern DC2, and the third dummy cap pattern DC3 and portions of the spacer material layer SM on upper surfaces of the first dummy cap pattern DC1, the second dummy cap pattern DC2, and the third dummy cap pattern DC3 can be etched. Portions of the spacer material layer SM remaining on sidewalls of each of the first dummy cap pattern DC1, the second dummy cap pattern DC2, and the third dummy cap pattern DC3 and on sidewalls of each of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 can be defined as the first gate spacer 111, the second gate spacer 112, and the third gate spacer 113.

[0086] After formation of the first source / drain trench ST1 and the second source / drain trench ST2 and the first sacrificial pattern trench 102T and the second sacrificial pattern trench 103T, the second semiconductor layer 22 remaining on the active pattern 11 under the first dummy gate DG1 can be defined as a first plurality of nanosheets NW1. After formation of the first source / drain trench ST1 and the second source / drain trench ST2 and the first sacrificial pattern trench 102T and the second sacrificial pattern trench 103T, the second semiconductor layer 22 remaining on the active pattern 11 under the second dummy gate DG2 can be defined as a second plurality of nanosheets NW2. After formation of the first source / drain trench ST1 and the second source / drain trench ST2 and the first sacrificial pattern trench 102T and the second sacrificial pattern trench 103T, the second semiconductor layer 22 remaining on the active pattern 11 under the third dummy gate DG3 can be defined as a third plurality of nanosheets NW3.

[0087] Referring to Figure 10The first sacrificial pattern 102 can be formed in the first sacrificial pattern trench 102T. Additionally, the second sacrificial pattern 103 can be formed in the second sacrificial pattern trench 103T. For example, upper surfaces of the first sacrificial pattern 102 and the second sacrificial pattern 103 can be formed lower than an uppermost surface of the active pattern 11. For example, sidewalls of each of the first sacrificial pattern 102 and the second sacrificial pattern 103 in the first horizontal direction DR1 can be in contact with the active pattern 11 and the substrate 10, respectively. Lower surfaces of the first sacrificial pattern 102 and the second sacrificial pattern 103 can be in contact with the substrate 10. For example, the first sacrificial pattern 102 and the second sacrificial pattern 103 can include SiGe.

[0088] Thereafter, a first source / drain region SD1 can be formed in the first source / drain trench ST1. For example, a lower surface of the first source / drain region SD1 can be in contact with the first sacrificial pattern 102. For example, the first source / drain region SD1 can be in contact with sidewalls of both the first plurality of nanosheets NW1 and the third plurality of nanosheets NW3 in the first horizontal direction DR1. Additionally, a second source / drain region SD2 can be formed in the second source / drain trench ST2. For example, a lower surface of the second source / drain region SD2 can be in contact with the second sacrificial pattern 103. The second source / drain region SD2 can be in contact with sidewalls of both the second plurality of nanosheets NW2 and the third plurality of nanosheets NW3 in the first horizontal direction DR1.

[0089] Referring to Figure 11 A first etching stop layer 140 can be formed on exposed sidewalls of each of the first gate spacer 111, the second gate spacer 112, and the third gate spacer 113, exposed upper surfaces of the first dummy cap pattern DC1, the second dummy cap pattern DC2, and the third dummy cap pattern DC3, and exposed surfaces of the first source / drain region SD1 and the second source / drain region SD2. Thereafter, a first upper interlayer insulating layer 150 can be formed on the first etching stop layer 140. Thereafter, upper surfaces of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 can be exposed by a planarization process.

[0090] Referring to Figure 12 and Figure 13The first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, the pad oxide layer 30, and the first semiconductor layer 21 can each be etched. For example, a location from which the first dummy gate DG1, the pad oxide layer 30, and the first semiconductor layer 21 have been removed can be defined as a first gate trench GT1. Similarly, a location from which the second dummy gate DG2, the pad oxide layer 30, and the first semiconductor layer 21 have been removed can be defined as a second gate trench GT2. A location from which the third dummy gate DG3, the pad oxide layer 30, and the first semiconductor layer 21 have been removed can be defined as a third gate trench GT3.

[0091] Referring to Figure 14 and Figure 15 A first gate insulating layer 121, a first gate electrode G1, and a first cap pattern 131 can be sequentially formed in the first gate trench GT1. Additionally, a second gate insulating layer 122, a second gate electrode G2, and a second cap pattern 132 can be sequentially formed in the second gate trench GT2, and a third gate insulating layer 123, a third gate electrode G3, and a third cap pattern 133 can be sequentially formed in the third gate trench GT3. For example, the first gate electrode G1 can surround the first plurality of nanosheets NW1, the second gate electrode G2 can surround the second plurality of nanosheets NW2, and the third gate electrode G3 can surround the third plurality of nanosheets NW3.

[0092] Referring to Figures 16 to 18 An upper source / drain contact UCA can be formed on the first source / drain region SD1. The upper source / drain contact UCA can extend into the first source / drain region SD1 by penetrating the first upper interlayer insulating layer 150 and the first etch stop layer 140 in the vertical direction DR3. Additionally, an upper silicide layer USL can be formed between the first source / drain region SD1 and the upper source / drain contact UCA. Further, a gate contact CB can be formed that connects to the first gate electrode G1 by penetrating the first cap pattern 131 in the vertical direction DR3.

[0093] Thereafter, a second etch stop layer 180 and a second upper interlayer insulating layer 185 can be sequentially formed on the upper surfaces of the first upper interlayer insulating layer 150, the first cap pattern 131, the second cap pattern 132, and the third cap pattern 133, and the upper source / drain contact UCA. Thereafter, a first via V1 can be formed that connects to the upper source / drain contact UCA by penetrating the second etch stop layer 180 and the second upper interlayer insulating layer 185 in the vertical direction DR3. Further, a second via V2 can be formed that connects to the gate contact CB by penetrating the second etch stop layer 180 and the second upper interlayer insulating layer 185 in the vertical direction DR3.

[0094] Referring to Figure 19 and Figure 20A mask pattern M can be formed on the lower surface of the substrate 10. For example, the mask pattern M can expose the substrate 10 formed under the third gate electrode G3. Thereafter, using the mask pattern M as a mask, the substrate 10 and the active pattern 11 can be etched, thereby forming a first trench T1. For example, the first trench T1 can be formed between the first sacrificial pattern 102 and the second sacrificial pattern 103. The first trench T1 can extend in the second horizontal direction DR2.

[0095] For example, the first trench T1 can be etched through the third gate insulating layer 123 to extend into the inside of the third gate electrode G3. Accordingly, the third gate electrode G3 can be exposed by the upper surface of the first trench T1. For example, the upper surface of the first trench T1 can be formed higher than the uppermost surface of the active pattern 11. For example, the upper surface of the first trench T1 can be formed lower than the lower surface of the lowermost nanosheet of the third plurality of nanosheets NW3. For example, the width of the first trench T1 in the first horizontal direction DR1 can continuously decrease in a direction toward the upper surface of the first trench T1.

[0096] Referring to Figure 21 and Figure 22 A liner material layer 170M can be formed along the upper surface and the sidewall of the first trench T1. For example, the liner material layer 170M can be formed even on the lower surface of the mask pattern M. For example, the liner material layer 170M can be conformally formed. For example, the liner material layer 170M can include an insulating material. For example, the liner material layer 170M can include at least one of SiN, SiON, SiCN, SiOCN, SiOC, and combinations thereof.

[0097] Referring to Figure 23 and Figure 24 A portion of the liner material layer 170M can be etched by performing a back-etching process. For example, a portion of the liner material layer 170M formed on the upper surface of the first trench T1 can be etched away. As a result, the third gate electrode G3 can be exposed on the upper surface of the first trench T1. Additionally, a portion of the liner material layer 170M formed on the lower surface of the mask pattern M can be etched away. As a result, the lower surface of the mask pattern M can be exposed.

[0098] Referring to Figure 25 and Figure 26 Both the third gate electrode G3 and the third gate insulating layer 123 that can be exposed through the first trench T1 can be etched. For example, the third gate electrode G3 and the third gate insulating layer 123 can be etched by a wet etching process. A space formed between the liner material layer 170M and the region from which the third gate electrode G3 and the third gate insulating layer 123 have been etched can be defined as a first active cut trench CT1.

[0099] Referring to Figure 27 and Figure 28A portion of the third plurality of nanosheets NW3 exposed through the first active cut trench CT1 can be etched. For example, a portion of the third cap pattern 133 can also be etched while etching the portion of the third plurality of nanosheets NW3. For example, the portion of the third plurality of nanosheets NW3 can be etched using a dry etching process. For example, the first active cut trench CT1 and the region from which the portion of the third plurality of nanosheets NW3 has been etched can be defined as a second active cut trench CT2. For example, the third plurality of nanosheets NW3 can be divided into a first portion in contact with the first source / drain region SD1 and a second portion in contact with the second source / drain region SD2 by the second active cut trench CT2.

[0100] Referring to Figure 29 and Figure 30 An active cut 160 can be formed within the second active cut trench CT2. Thereafter, a lower surface of the substrate 10 can be exposed by performing a planarization process. A liner material layer 170M remaining after the planarization process can be defined as a liner layer 170. For example, the liner layer 170 can be formed along sidewalls of the first trench T1. For example, the active cut 160 can include a first portion 161 and a second portion 162. For example, the first portion 161 of the active cut 160 can be defined as a portion filling between portions of the liner layer 170 within a portion of the first trench T1. The second portion 162 of the active cut 160 can be defined as a portion filling an unfilled portion of the second active cut trench CT2 on an upper surface 161a of the first portion 161 of the active cut 160.

[0101] For example, an upper surface of the first portion 161 of the active cut 160 can be formed higher than an uppermost surface of the active pattern 11. For example, a lower surface of the first portion 161 of the active cut 160 can be formed on the same plane as a lower surface of the substrate 10. For example, the second portion 162 of the active cut 160 can be in contact with an upper surface and a lower surface of each of the third plurality of nanosheets NW3. For example, the second portion 162 of the active cut 160 can be in contact with inner sidewalls of each of the third plurality of nanosheets NW3 separated in the first horizontal direction DR1. For example, the second portion 162 of the active cut 160 can be in contact with the third gate spacer 113. For example, the second portion 162 of the active cut 160 can be in contact with a lower surface of the third cap pattern 133. For example, at least a portion of the second portion 162 of the active cut 160 can extend into an inside of the third cap pattern 133.

[0102] Referring to Figure 31 and Figure 32 The substrate 10 and the active pattern 11 can be etched. As a result, the first sacrificial pattern 102 and the second sacrificial pattern 103 can be exposed.

[0103] Referring to Figure 33 andFigure 34 A lower interlayer insulating layer 100 and an insulating pattern 101 can be formed on the etched portions of the substrate 10 and the active pattern 11. For example, the insulating pattern 101 can be formed on the etched portions of the active pattern 11. The insulating pattern 101 can be in contact with the first and second gate insulating layers 121 and 122, the first and second source / drain regions SD1 and SD2, the field insulating layer 105, and the first and second sacrificial patterns 102 and 103. The insulating pattern 101 can surround a portion of a sidewall of each of the first and second sacrificial patterns 102 and 103.

[0104] Additionally, the lower interlayer insulating layer 100 can be formed on the etched portions of the substrate 10. The lower interlayer insulating layer 100 can be in contact with the field insulating layer 105 and the first and second sacrificial patterns 102 and 103. The lower interlayer insulating layer 100 can surround a remaining portion of a sidewall of each of the first and second sacrificial patterns 102 and 103. Furthermore, the lower interlayer insulating layer 100 can cover a lower surface of the first and second sacrificial patterns 102 and 103. Thereafter, the lower surface 161b of the first portion 161 of the active cut 160 can be exposed by performing a planarization process.

[0105] Referring to Figure 35 A second trench T2 that can expose a lower surface of the second sacrificial pattern 103 can be formed within the lower interlayer insulating layer 100. For example, the second trench T2 can extend in the vertical direction DR3 from a lower surface of the lower interlayer insulating layer 100.

[0106] Referring to Figure 36 The second sacrificial pattern 103 that can be exposed by the second trench T2 can be etched. As a result, a third trench T3 can be defined. For example, the second source / drain region SD2 can be exposed by the third trench T3.

[0107] Referring to Figure 37 A bottom source / drain contact BCA can be formed within the third trench T3. For example, a lower surface of the bottom source / drain contact BCA can be formed on the same plane as a lower surface of the lower interlayer insulating layer 100. For example, the bottom source / drain contact BCA can be spaced apart from the first portion 161 of the active cut 160 in the first horizontal direction DR1. The bottom source / drain contact BCA can also be spaced apart from the pad layer 170 in the first horizontal direction DR1. Additionally, a lower silicide layer BSL can be formed between the bottom source / drain contact BCA and the second source / drain region SD2. Accordingly, a semiconductor device of Figure 2

[0108] ​In the example method of manufacturing a semiconductor device according to some embodiments of the disclosure discussed above, the active cutout 160 can be formed from below the third gate electrode G3. For example, the active cutout 160 can be formed as the first trench T1 that penetrates the substrate 10 and the active pattern 11 in the vertical direction DR3. As a result, compared to a case where the cap pattern 133 is formed to penetrate from above the third gate electrode G3 in the vertical direction DR3, the amount of etching required can be reduced, and the difficulty of manufacturing can be lowered. Additionally, by forming the active cutout 160 from below the third gate electrode G3, the process margin can be increased. Thus, the first source / drain region SD1 and the second source / drain region SD2 can be prevented from being etched during formation of the active cutout 160.

[0109] In the semiconductor device manufactured by the example method according to some embodiments of the disclosure, the active cutout 160 can be in contact with a lower surface of the third cap pattern 133. Further, in the semiconductor device manufactured by the example method according to some embodiments of the disclosure, a width of the first portion 161 of the active cutout 160 that penetrates the lower interlayer insulating layer 100 in the first horizontal direction DR1 can continuously decrease in a direction toward an upper surface 161a of the active cutout 160. Additionally, in the semiconductor device manufactured by the example method according to some embodiments of the disclosure, the bottom source / drain contact BCA can be spaced apart from the first portion 161 of the active cutout 160 in the first horizontal direction DR1.

[0110] Reference will now be made to Figure 37 Examples of a semiconductor device according to some embodiments of the disclosure are described, focusing mainly on differences from the examples described above with reference to Figures 1 to 4 Examples of a semiconductor device according to some embodiments of the disclosure are described, focusing mainly on differences from the examples described above with reference to

[0111] Figure 37 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the disclosure.

[0112] Reference will now be made to Figure 37 In the semiconductor device according to some embodiments of the disclosure, the second portion 262 of the active cutout 260 can not extend into an interior of the third cap pattern 233. For example, during formation of a trench for forming the active cutout 260, a lower surface of the third cap pattern 233 can not be etched. As a result, an upper surface of the second portion 262 of the active cutout 260 can be in contact with the lower surface of the third cap pattern 233. For example, a lowermost surface of the third cap pattern 233 can be formed at the same height as a lowermost surface of the first cap pattern 131 and a lowermost surface of the second cap pattern 132.

[0113] Reference will now be made to Figure 38 Examples of a semiconductor device according to some embodiments of the disclosure are described, focusing mainly on differences from the examples described above with reference to Figures 1 to 4 Examples of a semiconductor device according to some embodiments of the disclosure are described, focusing mainly on differences from the examples described above with reference to

[0114] Figure 38 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the disclosure.

[0115] Referring to Figure 38 In a semiconductor device according to some embodiments of the disclosure, a third gate insulating layer 323 can be disposed between the active cutout 360 and the third gate spacer 113.

[0116] For example, the third gate insulating layer 323 can be disposed between the second portion 362 of the active cutout 360 and the third gate spacer 113. The third gate insulating layer 323 can be disposed between the second portion 362 of the active cutout 360 and the first source / drain region SD1. The third gate insulating layer 323 can be disposed between the second portion 362 of the active cutout 360 and the second source / drain region SD2. The third gate insulating layer 323 can be disposed between the upper surface of the insulating pattern 101 and the second portion 362 of the active cutout 360. The third gate insulating layer 323 can be disposed between the second portion 362 of the active cutout 360 and the upper surface of the third plurality of nanosheets NW3. The third gate insulating layer 323 can be disposed between the second portion 362 of the active cutout 360 and the lower surface of the third plurality of nanosheets NW3.

[0117] For example, the third gate insulating layer 323 can not be disposed between the inner sidewall of the third plurality of nanosheets NW3 and the second portion 362 of the active cutout 360. The third gate insulating layer 323 can contact the second portion 362 of the active cutout 360, the third cap pattern 133, the third gate spacer 113, the first and second source / drain regions SD1 and SD2, the insulating pattern 101, and the third plurality of nanosheets NW3. The third gate insulating layer 323 can contact a portion of the sidewall of the liner layer 170 in the first horizontal direction DR1. For example, the third gate insulating layer 323 can include the same material as the first and second gate insulating layers 121 and 122.

[0118] Referring to Figure 39 Examples of a semiconductor device according to some embodiments of the disclosure are described below, mainly focusing on differences from the examples described above with reference to Figures 1 to 4 .

[0119] Figure 39 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the disclosure.

[0120] Referring to Figure 39In some embodiments according to the present disclosure, a third gate insulating layer 423 can be disposed between the active cutout 460 and the third gate spacer 113. Additionally, a third gate electrode G43 can be disposed between the second portion 462 of the active cutout 460 and the third gate insulating layer 423.

[0121] For example, a sidewall of the second portion 462 of the active cutout 460 in the first horizontal direction DR1 can have a continuous slope profile. For example, the second portion 462 of the active cutout 460 can extend up to the third cap pattern 133, penetrating the plurality of third plurality of nanosheets NW3, the third gate electrode G43, and the third gate insulating layer 423 in the vertical direction DR3.

[0122] For example, the third gate electrode G43 can be disposed on a sidewall of the second portion 462 of the active cutout 460 in the first horizontal direction DR1 between an upper surface of the insulating pattern 101 and a lower surface of a lowermost nanosheet of the third plurality of nanosheets NW3. The third gate electrode G43 can be disposed on a sidewall of the second portion 462 of the active cutout 460 in the first horizontal direction DR1 from between adjacent nanosheets among the third plurality of nanosheets NW3. The third gate electrode G43 can be disposed on a sidewall of the second portion 462 of the active cutout 460 in the first horizontal direction DR1 above an upper surface of an uppermost nanosheet of the third plurality of nanosheets NW3. For example, the third gate electrode G43 can be in contact with the sidewall of the second portion 462 of the active cutout 460 in the first horizontal direction DR1. For example, an upper surface of the third gate electrode G43 can be in contact with a lower surface of the third cap pattern 133. For example, the upper surface of the third gate electrode G43 can be formed lower than an upper surface of the second portion 462 of the active cutout 460. For example, the third gate electrode G43 can include the same material as the first gate electrode G1 and the second gate electrode G2.

[0123] For example, the third gate insulating layer 423 can be disposed between the third gate electrode G43 and the third gate spacer 113. The third gate insulating layer 423 can be disposed between the third gate electrode G43 and the first source / drain region SD1. The third gate insulating layer 423 can be disposed between the third gate electrode G43 and the second source / drain region SD2. The third gate insulating layer 423 can be disposed between the third gate electrode G43 and an upper surface of the insulating pattern 101. The third gate insulating layer 423 can be disposed between the third gate electrode G43 and the third plurality of nanosheets NW3.

[0124] Reference is made below to Figure 40 Examples of semiconductor devices according to some embodiments of the present disclosure are described, focusing mainly on differences from the examples described above with reference to Figures 1 to 4 Examples of semiconductor devices according to some embodiments of the present disclosure are described, focusing mainly on differences from the examples described above with reference to

[0125] Figure 40is a cross-sectional view illustrating a semiconductor device according to some embodiments of the disclosure.

[0126] Referring to Figure 40 In a semiconductor device according to some embodiments of the disclosure, a third internal spacer 593 can be disposed on both side walls of the second portion 562 of the active cutout 560 in the first horizontal direction DR1.

[0127] For example, the first internal spacer 591 can be disposed on a side wall of the first gate electrode G51 in the first horizontal direction DR1 between an upper surface of the insulating pattern 101 and a lower surface of a lowermost nanosheet of the first plurality of nanosheets NW1. The first internal spacer 591 can be disposed between adjacent nanosheets from among the first plurality of nanosheets NW1 along a side wall of the first gate electrode G51 in the first horizontal direction DR1. For example, the first internal spacer 591 can be disposed between the first gate insulating layer 521 and the first source / drain region SD1. For example, the first internal spacer 591 can be in contact with the first gate insulating layer 521 and the first source / drain region SD1.

[0128] For example, the second internal spacer 592 can be located on a side wall of the second gate electrode G52 in the first horizontal direction DR1 between an upper surface of the insulating pattern 101 and a lower surface of a lowermost nanosheet of the second plurality of nanosheets NW2. The second internal spacer 592 can be disposed between adjacent nanosheets from among the second plurality of nanosheets NW2 along a side wall of the second gate electrode G52 in the first horizontal direction DR1. For example, the second internal spacer 592 can be disposed between the second gate insulating layer 522 and the second source / drain region SD2. For example, the second internal spacer 592 can be in contact with the second gate insulating layer 522 and the second source / drain region SD2.

[0129] For example, the third internal spacer 593 can be disposed on a side wall of the second portion 562 of the active cutout 560 in the first horizontal direction DR1 between an upper surface of the insulating pattern 101 and a lower surface of a lowermost nanosheet of the third plurality of nanosheets NW3. The third internal spacer 593 can be disposed between adjacent nanosheets from among the third plurality of nanosheets NW3 along a side wall of the second portion 562 of the active cutout 560 in the first horizontal direction DR1. For example, the third internal spacer 593 can be in contact with the second portion 562 of the active cutout 560 and the first source / drain region SD1 and the second source / drain region SD2. The first internal spacer 591, the second internal spacer 592, and the third internal spacer 593 can include at least one of SiN, SiON, SiO2, SiOCN, SiBN, SIOBN, SiOC, and combinations thereof.

[0130] While some embodiments are described herein according to a technical spirit of the present disclosure with reference to the accompanying drawings, it is understood that the embodiments are not limited thereto. The embodiments can be manufactured in various different forms, and those of ordinary skill in the art will understand that the embodiments can be performed in other specific forms without changing the scope of the present disclosure. Therefore, the above-described embodiments should be considered in all aspects as illustrative and not restrictive.

Claims

1. A semiconductor device comprising: an underlayer interlevel dielectric layer; an insulating pattern extending in a first horizontal direction on an upper surface of the underlayer interlevel dielectric layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; an active cutout including a first portion penetrating the underlayer interlevel dielectric layer and the insulating pattern in the vertical direction and a second portion separating the plurality of nanosheets in the first horizontal direction on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern, and wherein the second portion is on inner side walls of the plurality of nanosheets in the first horizontal direction; a first source / drain region on a first side of the active cutout in the first horizontal direction and on the insulating pattern, wherein the first source / drain region is on first outer side walls of the plurality of nanosheets; a second source / drain region on a second side of the active cutout opposite the first side of the active cutout and on the insulating pattern, wherein the second source / drain region is on second outer side walls of the plurality of nanosheets; and a bottom source / drain contact penetrating the underlayer interlevel dielectric layer and the insulating pattern in the vertical direction, wherein the bottom source / drain contact is electrically connected to the second source / drain region, and wherein the bottom source / drain contact overlaps the first portion of the active cutout in the first horizontal direction, wherein a width of the upper surface of the first portion of the active cutout in the first horizontal direction is less than a width of the lower surface of the first portion of the active cutout in the first horizontal direction.

2. The semiconductor device of claim 1, further comprising: a spacer layer between the first portion of the active cutout and each of the underlayer interlevel dielectric layer and the insulating pattern, wherein the spacer layer is on two side walls of the first portion of the active cutout in the first horizontal direction.

3. The semiconductor device according to claim 2, wherein an upper surface of the spacer layer is on the second portion of the active cutout.

4. The semiconductor device of claim 1, further comprising: a cap pattern on the upper surface of the second portion of the active cutout, wherein the cap pattern extends in a second horizontal direction different from the first horizontal direction.

5. The semiconductor device according to claim 1, further comprising: an upper source / drain contact over the first source / drain region, wherein the upper source / drain contact is electrically connected to the first source / drain region.

6. The semiconductor device according to claim 5, wherein an upper surface of the upper source / drain contact is higher than the upper surface of the second portion of the active cutout.

7. The semiconductor device according to claim 1, wherein at least a portion of the second portion of the active cutout overlaps the plurality of nanosheets in the vertical direction between adjacent nanosheets among the plurality of nanosheets.

8. The semiconductor device according to claim 1, wherein the second portion of the active cutout is on an upper surface and a lower surface of each of the plurality of nanosheets.

9. The semiconductor device of claim 1, further comprising: a gate spacer on two side walls of the second portion of the active cutout in the first horizontal direction on an upper surface of an uppermost nanosheet among the plurality of nanosheets, wherein the gate spacer is on the second portion of the active cutout.

10. The semiconductor device of claim 1, further comprising: a gate spacer on two side walls of the second portion of the active cutout in the first horizontal direction on an upper surface of an uppermost nanosheet among the plurality of nanosheets; and ​ A gate insulating layer is between the second portion of the active cutout and the gate spacer.

11. The semiconductor device according to claim 10, further comprising: A gate electrode is between the second portion of the active cutout and the gate insulating layer, wherein the gate electrode is on the second portion of the active cutout.

12. The semiconductor device according to claim 1, further comprising: An internal spacer is between the second portion of the active cutout and each of the first source / drain region and the second source / drain region and between adjacent nanosheets from among the plurality of nanosheets.

13. A semiconductor device comprising: lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a first gate electrode extending in a second horizontal direction on the insulating pattern, wherein the second horizontal direction is different from the first horizontal direction; a second gate electrode extending in a second horizontal direction on the insulating pattern, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction; an active cutout comprising a first portion and a second portion, the first portion penetrating the lower interlayer insulating layer and the insulating pattern in a vertical direction, the second portion being on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern; a liner layer between the first portion of the active cutout and each of the lower interlayer insulating layer and the insulating pattern, wherein the liner layer is on both sidewalls of the first portion of the active cutout in a first horizontal direction; a first capping pattern on an upper surface of the first gate electrode, wherein the first capping pattern extends in a second horizontal direction; a second capping pattern on an upper surface of the second gate electrode, wherein the second capping pattern extends in a second horizontal direction; and a third cover pattern on an upper surface of the second portion of the active cutout, wherein the third cover pattern extends in a second horizontal direction, The upper surface of the first cover pattern, the upper surface of the second cover pattern and the upper surface of the third cover pattern are on the same plane. wherein an upper surface of the second portion of the active cutout is lower than an upper surface of the third cover pattern, and The width of the upper surface of the first portion of the active cutout in the first horizontal direction is smaller than the width of the lower surface of the first portion of the active cutout in the first horizontal direction.

14. The semiconductor device according to claim 13, further comprising: a first source / drain region between the first gate electrode and the active cutout and on the insulating pattern; a second source / drain region between the active cutout and the second gate electrode and on the insulating pattern; and The bottom source / drain contacts penetrate the lower interlayer insulating layer and the insulating pattern in the vertical direction, wherein the bottom source / drain contact is electrically connected to the second source / drain region, and The bottom source / drain contact overlaps the first portion of the active cutout in a first horizontal direction.

15. The semiconductor device according to claim 14, wherein The bottom source / drain contact is spaced apart from the first portion of the active notch in a first horizontal direction.

16. The semiconductor device according to claim 14, further comprising: a sacrificial pattern under the first source / drain region, wherein the sacrificial pattern overlaps the first portion of the active cutout in a first horizontal direction, The first portion of the active cut is spaced apart from the sacrificial pattern in the first horizontal direction.

17. The semiconductor device according to claim 13, wherein At least a portion of a sidewall of the spacer layer in the first horizontal direction is on the second portion of the active cut.

18. The semiconductor device according to claim 13, wherein At least a portion of the second portion of the active cut is superposed with a third cap pattern in the first horizontal direction.

19. The semiconductor device according to claim 13, wherein A lower surface of the first portion of the active cut is on a same plane as a lower surface of the lower interlayer insulating layer.

20. A semiconductor device, comprising: a lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; a first gate electrode extending in a second horizontal direction on the insulating pattern, wherein the second horizontal direction is different from the first horizontal direction; a second gate electrode extending in the second horizontal direction on the insulating pattern, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction; an active cut extending in the second horizontal direction between the first gate electrode and the second gate electrode, wherein the active cut includes a first portion penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction and a second portion separating the plurality of nanosheets in the first horizontal direction on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern, and wherein the second portion is on inner sidewalls of the plurality of nanosheets in the first horizontal direction; a first source / drain region between the first gate electrode and the active cut and on the insulating pattern, wherein the first source / drain region is on first outer sidewalls of the plurality of nanosheets; a second source / drain region between the active cut and the second gate electrode and on the insulating pattern, wherein the second source / drain region is on second outer sidewalls of the plurality of nanosheets; a spacer layer between the first portion of the active cut and each of the lower interlayer insulating layer and the insulating pattern, wherein the spacer layer is on both sidewalls of the first portion of the active cut in the first horizontal direction; a cap pattern on an upper surface of the second portion of the active cut, wherein the cap pattern extends in the second horizontal direction; a gate spacer on both sidewalls of the second portion of the active cut in the first horizontal direction on an upper surface of an uppermost nanosheet of the plurality of nanosheets, wherein the gate spacer is on the second portion of the active cut; and a bottom source / drain contact penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction, wherein the bottom source / drain contact is electrically connected to the second source / drain region, and wherein the bottom source / drain contact is superposed with the first portion of the active cut in the first horizontal direction, wherein an upper surface of the second portion of the active cut is lower than an upper surface of the cap pattern, wherein at least a portion of the second portion of the active cut is superposed with the plurality of nanosheets in the vertical direction between adjacent nanosheets from among the plurality of nanosheets, and wherein a width of an upper surface of the first portion of the active cut in the first horizontal direction is less than a width of a lower surface of the first portion of the active cut in the first horizontal direction.

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