Semiconductor device and method for manufacturing the same

Abstract

There is provided a semiconductor device including: a power distribution network layer on a lower surface of a substrate; a gate electrode on the substrate; a first source / drain pattern and a second source / drain pattern on the substrate, the first source / drain pattern and the second source / drain pattern each including a first pattern and a second pattern spaced apart from each other, the gate electrode between the first pattern and the second pattern; a via structure penetrating the substrate and extending in a direction perpendicular to an upper surface of the substrate, the via structure connecting the power distribution network layer with a first pattern of the first source / drain pattern; and a backside power via extending from below the second pattern of the first source / drain patterns to below the second pattern of the second source / drain patterns.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0052101, filed on Apr. 18, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] Semiconductor devices include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices decrease, the scaling rate of MOSFETs is also accelerating. As MOSFETs shrink, the operating characteristics of semiconductor devices may deteriorate. Accordingly, various methods are being researched to create semiconductor devices with improved performance while overcoming the limitations imposed by the high integration density of semiconductor devices. Summary of the Invention

[0005] The present disclosure provides semiconductor devices that exhibit improved power consumption.

[0006] The present disclosure also provides a semiconductor device that can be designed more easily.

[0007] The technical objectives of the present disclosure are not limited to the above objectives, and those skilled in the art can clearly understand other technical objectives and advantages not mentioned from the following description.

[0008] Some implementations of the present disclosure provide a semiconductor device including: a power distribution network layer on a lower surface of a substrate; a gate electrode on the substrate; a first source / drain pattern and a second source / drain pattern on the substrate, the first source / drain pattern and the second source / drain pattern each including a first pattern and a second pattern spaced apart from each other, with the gate electrode between the first pattern and the second pattern; a through-hole structure penetrating the substrate and extending in a direction perpendicular to the upper surface of the substrate, the through-hole structure connecting the power distribution network layer with the first pattern of the first source / drain pattern; and a back-side power via extending from under the second pattern of the first source / drain pattern to under the second pattern of the second source / drain pattern.

[0009] In some implementations of the present disclosure, a semiconductor device includes: a power distribution network layer on a lower surface of a substrate; a gate electrode on the substrate; a first source / drain pattern and a second source / drain pattern on the substrate, the first source / drain pattern and the second source / drain pattern each including a first pattern and a second pattern spaced apart from each other, with the gate electrode between the first pattern and the second pattern; a through-hole structure penetrating the substrate and extending in a direction perpendicular to an upper surface of the substrate, the through-hole structure connecting the power distribution network layer with the first pattern of the first source / drain pattern; a back power rail extending below the second source / drain pattern in a direction parallel to the upper surface of the substrate; and a back power via extending from below the second pattern of the first source / drain pattern to the upper surface of the back power rail.

[0010] In some implementations of the present disclosure, a semiconductor device includes: a power distribution network layer on a lower surface of a substrate; a gate electrode on the substrate; a first source / drain pattern and a second source / drain pattern on the substrate, the first source / drain pattern and the second source / drain pattern each including a first pattern and a second pattern spaced apart from each other, with the gate electrode between the first pattern and the second pattern; a first channel pattern between the first pattern and the second pattern of the first source / drain pattern; a through-hole structure penetrating the substrate and extending in a direction perpendicular to the upper surface of the substrate, the through-hole structure connecting the power distribution network layer with the first pattern of the first source / drain pattern; an active contact on the first pattern of the second source / drain pattern; a back power rail extending below the second source / drain pattern in a direction parallel to the upper surface of the substrate; and a back power via extending from below the second pattern of the first source / drain pattern to the upper surface of the back power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to further understand the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate implementations according to the present disclosure and, together with the specification, are used to explain its principles. In the accompanying drawings:

[0012] Figure 1 is a plan view showing an example of a semiconductor device;

[0013] Figure 2A is a block diagram illustrating an example of a semiconductor device including a power gating circuit;

[0014] Figure 2B yes Figure 1 A partial enlarged view of some configurations;

[0015] Figures 3A-3D Along Figure 1 Cross-sectional views taken along lines AA', BB', CC' and DD';

[0016] Figure 4is a plan view showing an example of a semiconductor device;

[0017] Figures 5A-5C are cross-sectional views taken along lines B-B', C-C', and D-D' of Figure 4

[0018] Figures 6A-10D is a diagram showing an example of a method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0019] Examples in accordance with this disclosure will be described in greater detail below with reference to the accompanying drawings, in which:

[0020] Figure 1 is a plan view showing a semiconductor device in accordance with some embodiments of the disclosure. Figure 2A is a block diagram showing a semiconductor device including a power gating circuit in accordance with some embodiments of the disclosure. Figure 2B is a partial enlarged view of some configurations of Figure 1 Figures 3A-3D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 1

[0021] Referring to Figure 1 and Figures 3A-3D , the substrate 200 includes a first single-height cell SHC1 and a second single-height cell SHC2. For example, the substrate 200 can include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), a silicon oxide (Si02) film, a silicon nitride (SiN) film, or a silicon oxynitride (SiON) film. As used herein, phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C,” etc. can each include any one of or all possible combinations of the items listed together.

[0022] The first single-height cell SHC1 and the second single-height cell SHC2 can each constitute one logic cell. As used herein, a logic cell refers to a logic device (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. For example, a logic cell can include transistors constituting a logic device and lines connecting the transistors to each other. For example, the first single-height cell SHC1 and the second single-height cell SHC2 can each constitute one power gating cell, e.g., as described later in this disclosure.

[0023] ​​​The first single-height cell SHC1 and the second single-height cell SHC2 can be adjacent to each other in the first direction D1. For example, a plurality of single-height cells can be adjacent to the first single-height cell SHC1 and the second single-height cell SHC2 in the first direction D1 and the second direction D2. The plurality of single-height cells can each constitute one logical cell as described above. The first direction D1 and the second direction D2 can each be parallel to the upper surface of the substrate 200 and can be perpendicular to each other.

[0024] The first single-height cell SHC1 and the second single-height cell SHC2 can each include a first active region AR1 and a second active region AR2 on the substrate 200. The first active region AR1 and the second active region AR2 can each extend along the second direction D2 and can be spaced apart from each other in the first direction D1. For example, the first active region AR1 of the first single-height cell SHC1 can be adjacent to the first active region AR1 of the second single-height cell SHC2 in the first direction D1. For example, the first active region AR1 of the first single-height cell SHC1 and the first active region AR1 of the second single-height cell SHC2 can be interposed between the second active region AR2 of the first single-height cell SHC1 and the second active region AR2 of the second single-height cell SHC2. For example, the first active region AR1 can be an NMOS region, and the second active region AR2 can be a PMOS region.

[0025] A first active pattern AP1 can be disposed in the first active region AR1. A second active pattern AP2 can be disposed in the second active region AR2. The first active pattern AP1 and the second active pattern AP2 can each be defined by a trench on the substrate 200. The first active pattern AP1 and the second active pattern AP2 can be a portion of the substrate 200. For example, the portion of the substrate 200 can protrude in a third direction D3. The third direction D3 can be a direction perpendicular to the upper surface of the substrate 200. For ease of description, unless otherwise specified, the substrate 200 is defined as a portion of the substrate 200 other than the first active pattern AP1 and the second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can each extend along the second direction D2.

[0026] A device isolation pattern ST can be disposed on the substrate 200 and fill the trench. The device isolation pattern ST can at least partially surround the first active pattern AP1 and the second active pattern AP2. The device isolation pattern ST can include an insulating material. For example, the device isolation pattern ST can include silicon oxide (SiO2).

[0027] A first channel pattern CH1 (for example, as shown in FIG. 1A) can be disposed on the first active pattern AP1, and a second channel pattern CH2 (for example, as shown in FIG. 1A) can be disposed on the second active pattern AP2. Figure 3B Figure 3D ​The first channel pattern CH1 can be provided as a plurality, and the plurality of first channel patterns CH1 can be spaced apart from each other in the second direction D2. The second channel pattern CH2 can be provided as a plurality, and the plurality of second channel patterns CH2 can be spaced apart from each other in the second direction D2. The first channel pattern CH1 and the second channel pattern CH2 can each include the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 adjacent to or spaced apart from each other in the third direction D3, but are not limited thereto. For example, the first channel pattern CH1 and the second channel pattern CH2 can each include four or more semiconductor patterns. For example, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can each include crystalline silicon.

[0028] The first recessed portion RS1 can be defined between the first channel patterns CH1 adjacent to each other in the second direction D2. The second recessed portion RS2 can be defined between the second channel patterns CH2 adjacent to each other in the second direction D2.

[0029] The first source / drain pattern SD1 can be provided on the first active pattern AP1, and the second source / drain pattern SD2 can be provided on the second active pattern AP2. The first source / drain pattern SD1 can fill the first recessed portion RS1, and the second source / drain pattern SD2 can fill the second recessed portion RS2. The first source / drain pattern SD1 and the second source / drain pattern SD2 can each be connected to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. As used herein, the meaning of A and B "connected" includes not only the case where A and B are electrically connected by direct contact, but also the case where A and B are indirectly electrically connected through C (for example, a conductive component) therebetween. Here, the component C can be a single component or a plurality of components.

[0030] The first source / drain pattern SD1 can be an impurity region having a first conductivity type (for example, n-type), and the second source / drain pattern SD2 can be an impurity region having a second conductivity type (for example, p-type). For example, a pair of first source / drain patterns SD1 adjacent to each other in the second direction D2 can be connected through the first channel pattern CH1. For example, a pair of second source / drain patterns SD2 adjacent to each other in the second direction D2 can be connected through the second channel pattern CH2.

[0031] The first source / drain pattern SD1 can include the same semiconductor element (for example, Si) as the first channel pattern CH1. The second source / drain pattern SD2 can include a semiconductor element (for example, SiGe) having a larger lattice constant than the semiconductor element of the second channel pattern CH2. Accordingly, a pair of second source / drain patterns SD2 can provide compressive stress to the second channel pattern CH2 therebetween.

[0032] The second source / drain pattern SD2 can include a buffer layer BFL covering inner surfaces of the second recessed portions RS2, and a main layer MAL filling most of the remaining portions of the second recessed portions RS2. For example, the buffer layer BFL and the main layer MAL can each include silicon germanium (SiGe). The buffer layer BFL can include a relatively low concentration of germanium (Ge). The main layer MAL can include a relatively high concentration of germanium (Ge). As another example, the buffer layer BFL can include only silicon (Si).

[0033] The first source / drain pattern SD1 can include first patterns T1 connected with the via structures PVS described later, and second patterns T2 in contact with the first back surface conductive contacts BCA1 described later. The second source / drain pattern SD2 can include first patterns T1 in contact with the active contacts CA described later, and second patterns T2 in contact with the second back surface conductive contacts BCA2 described later. The first patterns T1 and the second patterns T2 of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be spaced apart from each other with the gate electrodes GE interposed therebetween.

[0034] The first lower recessed portions LRS1 can be disposed below each of the first patterns T1 of the first source / drain pattern SD1. The second lower recessed portions LRS2 can be disposed below each of the second patterns T2 of the second source / drain pattern SD2. The sacrificial contact patterns PLH can fill the inside of each of the first lower recessed portions LRS1 and the second lower recessed portions LRS2. For example, the sacrificial contact patterns PLH can include silicon germanium (SiGe).

[0035] The gate electrodes GE can be disposed on and cross the first channel patterns CH1 and the second channel patterns CH2. The gate electrodes GE can be disposed as a plurality. The gate electrodes GE can each extend along the first direction D1 and can be spaced apart from each other in the second direction D2.

[0036] The gate electrodes GE can include inner electrodes PO1 and outer electrodes PO2. The inner electrodes PO1 of the gate electrodes GE can be disposed between the uppermost semiconductor pattern SP3 among the plurality of semiconductor patterns SP1, SP2, and SP3 and the first active pattern AP1 and the second active pattern AP2. The outer electrodes PO2 of the gate electrodes GE can be disposed on the uppermost semiconductor pattern SP3. For example, the inner electrodes PO1 of the gate electrodes GE can include three electrode portions, but are not limited thereto. For example, the inner electrodes PO1 of the gate electrodes GE can include four or more electrode portions.

[0037] The gate electrode GE can include a first metal pattern, and a second metal pattern on the first metal pattern. The first metal pattern can include a work function metal that controls a threshold voltage of the transistor. For example, the first metal pattern can include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the first metal pattern can further include carbon (C). For example, the first metal pattern can include a metal material having a different work function.

[0038] For example, the second metal pattern can include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) having a lower resistance than the first metal pattern.

[0039] For example, the inner electrode PO1 of the gate electrode GE can include the first metal pattern. For example, the outer electrode PO2 of the gate electrode GE can include the first metal pattern and the second metal pattern.

[0040] The cut pattern CT can be interposed between the gate electrodes GE adjacent to each other in the first direction D1. The cut pattern CT can be provided as a plurality of cut patterns. The cut patterns CT can be adjacent to each other in the second direction D2. For example, the cut pattern CT can include an insulating material.

[0041] The gate capping pattern GP can be provided on an upper surface of the gate electrode GE. For example, the gate capping pattern GP can include at least one of SiON, SiCN, SiOCN, or SiN.

[0042] The outer gate spacer OGS can be provided on a side surface of the outer electrode PO2 of the gate electrode GE, and can extend to a side surface of the gate capping pattern GP, respectively. The outer gate spacer OGS can include a single layer film or a composite film. For example, the outer gate spacer OGS can include at least one of SiON, SiCN, SiOCN, or SiN.

[0043] The gate insulating pattern GI can be interposed between the gate electrode GE and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating pattern GI can cover the upper surface, the lower surface, and the two side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating pattern GI can cover the upper surface of the device isolation pattern ST under the gate electrode GE. The gate insulating pattern GI can be interposed between the outer electrode PO2 and the outer gate spacer OGS. For example, the gate insulating pattern GI can include at least one of silicon oxide (SiO2), silicon oxynitride (SiON), or a high dielectric material. As used herein, a high dielectric material is defined as a material having a dielectric constant higher than that of silicon oxide.

[0044] The inner gate spacer IGS can be interposed between the second source / drain pattern SD2 and the inner electrode PO1 of the gate electrode GE. For example, the inner gate spacer IGS can include an insulating material.

[0045] The first interlayer insulating film ILD1 can be disposed on the substrate 200. The first interlayer insulating film ILD1 can cover the outer gate spacer OGS as well as the first source / drain pattern SD1 and the second source / drain pattern SD2. The upper surface of the first interlayer insulating film ILD1 can be located substantially at the same level as the upper surface of the gate cap pattern GP and the upper surface of the outer gate spacer OGS.

[0046] The second interlayer insulating film ILD2 can cover the gate cap pattern GP on the first interlayer insulating film ILD1. The third interlayer insulating film ILD3 can be disposed on the second interlayer insulating film ILD2. For example, the first interlayer insulating film ILD1, the second interlayer insulating film ILD2, and the third interlayer insulating film ILD3 can include silicon oxide (SiO2).

[0047] The active contact CA can penetrate the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 in the third direction D3. The active contact CA can be provided as a plurality, and the lower portion of each active contact CA can be buried in the upper portion of the first pattern T1 of the second source / drain pattern SD2. For example, the active contact CA can include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.). The active contact CA can be connected to the first pattern T1 of the second source / drain pattern SD2.

[0048] The gate contact portions GC can penetrate the second interlayer insulating film ILD2 and the gate capping pattern GP along the third direction D3. The gate contact portions GC can each be buried in an upper portion of the outer electrode PO2 of the gate electrode GE. For example, the gate contact portions GC can include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0049] The isolation pattern DB can be disposed on both sides of each of the first single-height unit SHC1 and the second single-height unit SHC2. For example, the isolation pattern DB can include an insulating material. The first single-height unit SHC1 and the second single-height unit SHC2 can be electrically separated from other units adjacent in the second direction D2 by the isolation pattern DB.

[0050] The metal pattern MT can be disposed in the third interlayer insulating film ILD3. The via VI can be disposed between the metal pattern MT and the active contact portion CA and between the metal pattern MT and the gate contact portion GC. The metal pattern MT can be electrically connected to the active contact portion CA and the gate contact portion GC through the via VI. For example, although not shown in the drawing, the metal pattern MT and the via VI can be respectively disposed as multiple layers, and each metal pattern MT and each via VI can be alternately stacked. The metal pattern MT and the via VI can include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0051] The power distribution network layer PDN can be disposed on a lower surface of the substrate 200. The power distribution network layer PDN can include a plurality of lower wirings connected to the first pattern T1 of the first source / drain pattern SD1 through a via structure PVS described later. For example, the power distribution network layer PDN can include a wiring network for applying a source voltage. For example, the power distribution network layer PDN can include a wiring network for applying a drain voltage.

[0052] The via structure PVS can extend in the third direction D3 on the power distribution network layer PDN. The via structure PVS can penetrate the substrate 200. For example, the via structure PVS can be interposed between the first single-height unit SHC1 and the second single-height unit SHC2. For example, the via structure PVS can be interposed between the first patterns T1 of the first source / drain pattern SD1 adjacent to each other in the first direction D1.

[0053] As Figure 3AAs shown, the via structure PVS can include an upper power via UPV interposed between the first patterns T1 of the first source / drain patterns SD1 adjacent to each other in the first direction D1, and a lower power via LPV between the power distribution network layer PDN and the upper power via UPV. For example, the upper power via UPV can include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal nitride (e.g., nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or a metal silicide (e.g., silicide of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.). For example, the lower power via LPV can include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0054] The upper power via UPV can be connected to the power distribution network layer PDN through the lower power via LPV. The upper power via UPV can be connected to the first patterns T1 of the first source / drain patterns SD1. For example, the upper power via UPV can be in contact with the first patterns T1 of the first source / drain patterns SD1. Specifically, for example, the metal silicide in the upper power via UPV and the first patterns T1 of the first source / drain patterns SD1 can be in contact with each other. Thus, the metallic material in the upper power via UPV can be connected to the first patterns T1 of the first source / drain patterns SD1 through the metal silicide and the metal nitride in the upper power via UPV. In summary, the via structure PVS including the upper power via UPV and the lower power via LPV can connect the power distribution network layer PDN with the first patterns T1 of the first source / drain patterns SD1.

[0055] A portion of the upper power via UPV can further protrude in the first direction D1 from another portion thereof. The portion of the upper power via UPV can partially cover the upper surfaces of each of the first patterns T1 of the first source / drain patterns SD1.

[0056] The lower power via LPV can be in contact with a lower surface of the upper power via UPV. For example, a width of the lower power via LPV in a horizontal direction of the substrate 200 can be smaller in the third direction D3.

[0057] Figure 3D The upper insulating pattern UIP shown in the middle can be disposed on each of the upper power via UPV adjacent to the gate contact GC and the active contact CA adjacent to the gate contact GC. For example, the upper insulating pattern UIP can include an insulating material.

[0058] The first liner insulating film LS1 may be interposed between the first active pattern AP1 and the upper power via UPV and between the second active pattern AP2 and the upper power via UPV. The first liner insulating film LS1 may be partially interposed between the upper power via UPV and the first pattern T1 of the first source / drain pattern SD1. For example, the first liner insulating film LS1 may include an insulating material.

[0059] The second liner insulating film LS2 may be interposed between the substrate 200 and the lower power via LPV. For example, the second liner insulating film LS2 may include an insulating material.

[0060] like Figure 3D As shown, a backside power via MPV may be disposed in the substrate 200. The backside power via MPV may be buried in the substrate 200. The backside power via MPV may extend along a first direction D1. Specifically, the backside power via MPV may extend along the first direction D1 from below the second pattern T2 of the first source / drain pattern SD1 to below the second pattern T2 of the second source / drain pattern SD2. The backside power via MPV may vertically overlap each of the second pattern T2 of the first source / drain pattern SD1 and the second pattern T2 of the second source / drain pattern SD2. For example, the backside power via MPV may include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0061] A back-side conductive contact (BCA) may be disposed on the upper surface of the back-side power via (MPV). For example, the back-side conductive contact (BCA) and the back-side power via (MPV) may contact each other, with a step interposed between the back-side conductive contact (BCA) and the back-side power via (MPV). The back-side conductive contact (BCA) may include a first back-side conductive contact (BCA1) between the second pattern (T2) of the first source / drain pattern (SD1) and the back-side power via (MPV), and a second back-side conductive contact (BCA2) between the second pattern (T2) of the second source / drain pattern (SD2) and the back-side power via (MPV). The first back-side conductive contact (BCA1) and the second back-side conductive contact (BCA2) may each comprise at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0062] The first back conductive contact BCA1 can be connected to each of the second pattern T2 of the first source / drain pattern SD1 and the back power via MPV. For example, the first back conductive contact BCA1 can be in contact with each of a lower surface of the second pattern T2 of the first source / drain pattern SD1 and an upper surface of the back power via MPV. The back power via MPV can be connected to the second pattern T2 of the first source / drain pattern SD1 through the first back conductive contact BCA1.

[0063] The second back conductive contact BCA2 can be connected to each of the second pattern T2 of the second source / drain pattern SD2 and the back power via MPV. For example, the second back conductive contact BCA2 can be in contact with each of a lower surface of the second pattern T2 of the second source / drain pattern SD2 and an upper surface of the back power via MPV. The back power via MPV can be connected to the second pattern T2 of the second source / drain pattern SD2 through the second back conductive contact BCA2.

[0064] The back power rail MPR can be disposed in the substrate 200. The back power rail MPR can be buried in the substrate 200. The back power rail MPR can be disposed under and vertically overlap the second source / drain pattern SD2. For example, the back power rail MPR can not vertically overlap the first source / drain pattern SD1. The back power rail MPR can extend along the second direction D2 under the second source / drain pattern SD2. The back power rail MPR can be connected to the back power via MPV under the second source / drain pattern SD2. For example, an upper surface of the back power rail MPR can be in contact with a lower surface of the back power via MPV. For example, the back power rail MPR can include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0065] Hereinafter, referring to Figure 2A , Figure 2B and Figures 3A-3D , how a voltage applied from the power distribution network layer PDN is transmitted through various components to other logic units adjacent to the first single height unit SHC1 and the second single height unit SHC2 will be described based on connections between the components.

[0066] First, referring to Figure 1 and Figure 2AThe first single-height cell SHC1 and the second single-height cell SHC2 can each constitute a power gating unit including a power gating circuit PGC. For example, the power gating circuit PGC can be disposed on the first active region AR1 of each of the first single-height cell SHC1 and the second single-height cell SHC2. The power gating circuit PGC can provide power to the second active region AR2 of the first single-height cell SHC1, the second active region AR2 of the second single-height cell SHC2, and other logic cells adjacent to the first single-height cell SHC1 and the second single-height cell SHC2.

[0067] The power gating circuit PGC can be connected to a power distribution network layer PDN that provides a global power voltage V GP . The power gating circuit PGC can include a first connection line PA1, a power gating transistor PTR, and a second connection line PA2. The global power voltage V GP applied from the power distribution network layer PDN can be transmitted to the power gating transistor PTR through the first connection line PA1.

[0068] A gate voltage V G can be applied to the power gating transistor PTR. The gate voltage V G may correspond to a voltage for turning on the power gating transistor PTR. For example, when a voltage equal to or greater than the gate voltage V G is applied to the power gating transistor PTR, the power gating transistor PTR can be turned on, and thus, the first connection line PA1 and the second connection line PA2 can be connected to each other. Accordingly, the power voltage V DD may be transmitted to the second connection line PA2. The power voltage V DD may be transmitted to logic cells adjacent to the first single-height cell SHC1 and the second single-height cell SHC2 through the second connection line PA2.

[0069] As another example, when a voltage less than the gate voltage V G is applied to the power gating transistor PTR, the power gating transistor PTR can be turned off, and thus, the first connection line PA1 and the second connection line PA2 can not be connected to each other. Accordingly, the power voltage V DD may not be transmitted to the second connection line PA2, and the second connection line PA2 can be floated.

[0070] The power gating circuit PGC in the power gating unit can selectively transmit the power voltage V DD to the second connection line PA2 or selectively float the second connection line PA2. Accordingly, the power gating unit can selectively transmit the power voltage V DDOnly the logic unit that needs power is transmitted to. Thus, the power usage of the semiconductor device can be reduced, thereby reducing the power consumption of the semiconductor device.

[0071] Referring to Figure 2B and Figures 3A-3D , a global power voltage V GP can be applied from a power distribution network layer PDN. As described above, the power distribution network layer PDN can be connected to a via structure PVS. Accordingly, the global power voltage V GP can be transmitted to the via structure PVS. As described above, the via structure PVS can be connected to a first pattern T1 of a first source / drain pattern SD1. Accordingly, the first pattern T1 of the first source / drain pattern SD1 can be connected to the power distribution network layer PDN through the via structure PVS. The via structure PVS and the first pattern T1 of the first source / drain pattern SD1 can constitute a first connection line PA1 as described with reference to Figure 2A .

[0072] The first pattern T1 and a second pattern T2 of the first source / drain pattern SD1, a first channel pattern CH1 between the first pattern T1 and the second pattern T2, and a gate electrode GE crossing the first channel pattern CH1 can constitute a power-gated transistor PTR as described with reference to Figure 2A .

[0073] For example, when a voltage equal to or greater than a gate voltage V G is applied to the gate electrode GE, the power-gated transistor PTR (refer to Figure 2A ) can be turned on, and thus, the first pattern T1 of the first source / drain pattern SD1 can be electrically connected to the second pattern T2 of the first source / drain pattern SD1 through the first channel pattern CH1. Thus, the global power voltage V GP transmitted through the first connection line PA1 can be transmitted to the second pattern T2 of the first source / drain pattern SD1. The voltage received by the second pattern T2 of the first source / drain pattern SD1 is defined as a power voltage V DD .

[0074] As described above, the backside power via MPV can be connected to the second pattern T2 of the first source / drain pattern SD1 through a first backside conductive contact BCA1. Accordingly, the power voltage V DD may be transmitted to the backside power via MPV through the first backside conductive contact BCA1.

[0075] As described above, the backside power via MPV can be connected to the second pattern T2 of the second source / drain pattern SD2 through a second backside conductive contact BCA2. Accordingly, the power voltage V DD may be transmitted to the second pattern T2 of the second source / drain pattern SD2 through the second backside conductive contact BCA2.

[0076] As described above, the back power via MPV can be connected to the back power rail MPR. Accordingly, the power voltage V DD Can be sent to the back power rail MPR.

[0077] The second pattern T2 of the first source / drain pattern SD1, the first back side conductive contact BCA1, the back side power via MPV and the back side power rail MPR may constitute a reference Figure 2A The second connecting line PA2 is described.

[0078] As mentioned above and Figure 3D As shown, the back power rail MPR may extend along the second direction D2 below the second source / drain pattern SD2. Accordingly, the power voltage V DD The power voltage V DD The power may be transmitted to other logic cells adjacent to the second single-height cell SHC2 in the second direction D2 through the back side power rail MPR in the second single-height cell SHC2.

[0079] The power distribution network layer PDN may be connected to the first connection line PA1 (eg, the through hole structure PVS and the first pattern T1 of the first source / drain pattern SD1). Accordingly, the global power voltage V applied from the power distribution network layer PDN is GP can be sent to the first connection line PA1. In addition, when the power gate transistor is turned on, the first connection line PA1 can be connected to the second connection line PA2 (for example, the second pattern T2 of the first source / drain pattern SD1, the first back conductive contact BCA1, the back power via MPV, and the back power rail MPR). Accordingly, the power voltage V DD Can be sent to the second connection line PA2, and the power voltage V DD The first and second connection lines PA1 and PA2 can be buried in the substrate 200 to provide a greater degree of freedom in arranging various components for driving the power gate unit. This makes it easier to design a semiconductor device.

[0080] Below, we will refer to Figures 4-5C The semiconductor device according to some embodiments of the present disclosure is described. In order to simplify the description, the description repeated with the above description will not be provided, and the difference from the above description will be mainly described; Figures 1-3D The description provided also applies to Figures 4-5C , unless otherwise stated or the context implies otherwise.

[0081] Figure 4 is a plan view showing an example of a semiconductor device. Figures 5A-5C are cross-sectional views taken along lines Figure 4 B-B', C-C' and D-D' of

[0082] Referring to Figure 4 and Figures 5A-5C , unlike what is described with reference to Figure 1 and Figures 3A-3D , the back surface conductive contact portion BCA can be omitted.

[0083] The back surface power via MPV can penetrate the first active pattern AP1, and can be in contact with the second pattern T2 of the first source / drain pattern SD1. Accordingly, the back surface power via MPV can be connected to the second pattern T2 of the first source / drain pattern SD1 without the first back surface conductive contact portion BCA1.

[0084] The back surface power via MPV can penetrate the second active pattern AP2, and can be in contact with the second pattern T2 of the second source / drain pattern SD2. Accordingly, the back surface power via MPV can be connected to the second pattern T2 of the second source / drain pattern SD2 without the second back surface conductive contact portion BCA2.

[0085] Figures 6A-10D is a plan view showing an example of a semiconductor device. Figure 6A , Figure 7A , Figure 9A and Figure 10A are cross-sectional views taken along line Figure 1 A-A' of Figure 6B , Figure 7B , Figure 8 , Figure 9B , Figure 10B are cross-sectional views taken along line Figure 1 B-B' of Figure 10C are cross-sectional views taken along line Figure 1 C-C' of Figure 7C and Figure 10D are cross-sectional views taken along line Figure 1 D-D' of

[0086] Referring to Figure 1 , Figure 6A and Figure 6BA semiconductor substrate 100 including a first active area AR1 and a second active area AR2 may be provided. For example, the semiconductor substrate 100 may be a semiconductor substrate including a semiconductor material, such as a single crystal silicon substrate, a silicon germanium substrate, and an SOI substrate. A stack pattern STP may be formed on the first active area AR1 and the second active area AR2. For example, forming the stack pattern STP may include: alternately stacking semiconductor layers ACL and sacrificial layers SAL on the semiconductor substrate 100; forming a mask pattern (not shown) extending along a second direction D2; and performing a patterning process using the mask pattern as an etching mask. During the patterning process, a portion of the semiconductor substrate 100 may be removed, and trenches defining the first active pattern AP1 and the second active pattern AP2 may be formed. Device isolation patterns ST may be formed to fill the trenches.

[0087] The sacrificial layer SAL may include a material that exhibits etching selectivity with the semiconductor layer ACL. Accordingly, when the process for removing the sacrificial layer SAL, described later, is performed, the semiconductor layer ACL may not be removed or may be slightly removed even when the sacrificial layer SAL is removed. For example, the semiconductor layer ACL may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layer SAL may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe) that is a different material from the semiconductor layer ACL.

[0088] Reference Figure 1 and Figures 7A-7C A sacrificial pattern PP extending along a first direction D1 may be formed on the semiconductor substrate 100. The sacrificial pattern PP may be formed to cover the upper surface of the device isolation pattern ST and the side and upper surfaces of the stacked pattern STP. For example, forming the sacrificial pattern PP may include: forming a sacrificial film (not shown) on the front surface of the semiconductor substrate 100; forming a hard mask pattern MP on the sacrificial film; and partially removing the sacrificial film using the hard mask pattern MP as an etching mask to form the sacrificial pattern PP. For example, the sacrificial pattern PP may include polysilicon. Thereafter, outer gate spacers OGS may be formed on the side surfaces of the sacrificial pattern PP.

[0089] The first recess RS1 may be formed in the stacked pattern STP on the first active pattern AP1. The second recess RS2 may be formed in the stacked pattern STP on the second active pattern AP2. For example, the first and second recesses RS1 and RS2 may be formed by partially removing the stacked pattern STP using the hard mask pattern MP as an etching mask.

[0090] The semiconductor layer ACL on the first active pattern AP1 can be divided into first channel patterns CH1 spaced apart from each other in the second direction D2 by the first recessed portions RS1. The semiconductor layer ACL on the second active pattern AP2 can be divided into second channel patterns CH2 spaced apart from each other in the second direction D2 by the second recessed portions RS2. The first channel patterns CH1 and the second channel patterns CH2 can include first, second, and third semiconductor patterns SP1, SP2, and SP3, respectively.

[0091] The sacrificial layer SAL exposed by the second recessed portions RS2 can be partially replaced by an insulating material, and thus, an unillustrated inner spacer can be formed on both side surfaces of the sacrificial layer SAL.

[0092] A first lower recessed portion LRS1 can be formed under the first recessed portions RS1. A second lower recessed portion LRS2 can be formed under the second recessed portions RS2. A sacrificial contact pattern PLH can be formed to fill the interiors of the lower recessed portions LRS1 and LRS2 by an SEG process using the semiconductor substrate 100 as a seed.

[0093] A first source / drain pattern SD1 can be formed in the first recessed portions RS1. The first source / drain pattern SD1 can be formed by a selective epitaxial growth (SEG) process using the sacrificial contact pattern PLH and the first, second, and third semiconductor patterns SP1, SP2, and SP3 on the first active region AR1 as seeds.

[0094] For example, in the process of forming the first source / drain pattern SD1, an impurity (e.g., phosphorus, arsenic, or antimony) that allows the first source / drain pattern SD1 to have an n-type can be implanted in situ into the first source / drain pattern SD1. As another example, after the first source / drain pattern SD1 is formed, an impurity can be implanted into the first source / drain pattern SD1.

[0095] A second source / drain pattern SD2 can be formed in the second recessed portions RS2. The second source / drain pattern SD2 can be formed by an SEG process using the sacrificial contact pattern PLH and the first, second, and third semiconductor patterns SP1, SP2, and SP3 on the second active region AR2 as seeds.

[0096] For example, in the process of forming the second source / drain pattern SD2, an impurity (e.g., boron, gallium, or indium) that allows the second source / drain pattern SD2 to have a p-type can be implanted in situ into the second source / drain pattern SD2. As another example, after the second source / drain pattern SD2 is formed, an impurity can be implanted into the second source / drain pattern SD2.

[0097] Referring to Figure 1 andFigure 8 The first interlayer insulating film ILD1 can be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2 (see Figure 7C ), the hard mask pattern MP, and the outer gate spacer OGS. Thereafter, the first interlayer insulating film ILD1 on the upper surface of the sacrificial pattern PP can be removed. In the removal process, the hard mask pattern MP can be removed together, and the sacrificial pattern PP can be exposed.

[0098] Thereafter, the exposed sacrificial pattern PP can be removed, and an outer region ORG can be formed in the region where the sacrificial pattern PP is removed. The first channel pattern CH1, the second channel pattern CH2 (see Figure 7C ), and the sacrificial layer SAL can be exposed to the outside through the outer region ORG.

[0099] Thereafter, the exposed sacrificial layer SAL can be selectively removed. Here, due to the high etching selectivity of the sacrificial layer SAL, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can not be removed or can be slightly removed.

[0100] An inner region IRG can be formed in the region where the sacrificial layer SAL is removed. Specifically, the inner region IRG can be formed between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0101] A gate insulating pattern GI can be formed in each of the inner region IRG and the outer region ORG. The gate insulating pattern GI can be formed to surround each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0102] Referring to Figure 1 , Figure 9A and Figure 9B , a gate electrode GE can be formed on the gate insulating pattern GI. The gate electrode GE can include an inner electrode PO1 formed in each of the inner region IRG and an outer electrode PO2 formed in the outer region ORG. Thereafter, a gate capping pattern GP can be formed on the outer electrode PO2 of the gate electrode GE.

[0103] A second interlayer insulating film ILD2 can be formed on the first interlayer insulating film ILD1 and the gate capping pattern GP. An active contact CA can be formed to penetrate the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 and to be partially connected to the second source / drain pattern SD2.

[0104] The first liner insulating film LS1 can be formed to partially cover the first active pattern AP1 and the first source / drain pattern SD1. The upper power via UPV can be formed between the first source / drain patterns SD1. For example, forming the first liner insulating film LS1 and the upper power via UPV can include partially exposing the first source / drain pattern SD1 by partially removing each of the device isolation pattern ST, the first interlayer insulating film ILD1, and the second interlayer insulating film ILD2, forming the first liner insulating film LS1 covering the first source / drain pattern SD1, partially removing the first liner insulating film LS1 to partially expose the first source / drain pattern SD1, and filling a region in which each of the device isolation pattern ST, the first interlayer insulating film ILD1, and the second interlayer insulating film ILD2 is partially removed with the upper power via UPV.

[0105] A portion of each of the active contact CA and the upper power via UPV can be removed, and an upper insulating pattern UIP can be formed to fill the removed region.

[0106] The gate contact GC can be formed to penetrate the second interlayer insulating film ILD2 and the gate cap pattern GP and be connected to the gate electrode GE.

[0107] A third interlayer insulating film ILD3 can be formed on the second interlayer insulating film ILD2. A metal pattern MT and a via VI can be formed in the third interlayer insulating film ILD3.

[0108] Referring to Figure 1 and Figures 10A-10D , after a back end of line (BEOL) process is completed, the semiconductor substrate 100 described with reference to Figure 6A and Figure 6B can be upside down. Accordingly, a lower surface of the semiconductor substrate 100 (with reference to Figure 6A and Figure 6B ) can be exposed. Since the semiconductor substrate 100 (with reference to Figure 6A and Figure 6B ) is upside down, when described below with reference to Figures 10A-10D , the terms "upper surface" and "upper portion" can mean "lower surface" and "lower portion", respectively, with reference to the fabricated semiconductor device described with reference to Figures 3A-3D , and the terms "lower surface" and "lower portion" can mean "upper surface" and "upper portion", respectively, with reference to the fabricated semiconductor device described with reference to Figures 3A-3D .

[0109] The semiconductor substrate 100 (with reference to Figure 6A and Figure 6B ) can be planarized by performing a planarization process on an exposed surface of the semiconductor substrate 100 (with reference to Figure 6A andFigure 6B The thickness of the semiconductor substrate 100 (refer to Figure 6A and Figure 6B ) can be completely removed or only partially removed by a planarization process.

[0110] An insulating film (not shown) including an insulating material can be formed to fill the removed region of the semiconductor substrate 100 (refer to Figure 6A and Figure 6B ). The insulating film and the remaining portion of the semiconductor substrate 100 (refer to Figure 6A and Figure 6B ) can constitute a substrate 200.

[0111] A hole on the upper power via UPV can be formed by performing a patterning process on the substrate 200. A second layer insulating film LS2 covering the hole can be formed. Thereafter, a lower power via LPV filling a remaining portion of the hole can be formed.

[0112] The sacrificial contact pattern PLH on the second pattern T2 of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be removed. A first hole HL1 on the second pattern T2 of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed by a removal process. Thereafter, a first back surface conductive contact BCA1 filling the first hole HL1 on the second pattern T2 of the first source / drain pattern SD1 can be formed. A second back surface conductive contact BCA2 filling the first hole HL1 on the second pattern T2 of the second source / drain pattern SD2 can be formed.

[0113] A second hole HL2 can be formed on the first back surface conductive contact BCA1 and the second back surface conductive contact BCA2. The second hole HL2 can be formed to extend from an upper surface of the first back surface conductive contact BCA1 to an upper surface of the second back surface conductive contact BCA2. The upper surface of the first back surface conductive contact BCA1 and the upper surface of the second back surface conductive contact BCA2 can be exposed through the second hole HL2.

[0114] A back surface power via MPV can be formed to fill an inside of the second hole HL2. As another example, the process of forming the first hole HL1 and the process of forming the first back surface conductive contact BCA1 and the second back surface conductive contact BCA2 can be skipped, and the second hole HL2 can be formed to expose the upper surface of the second pattern T2 of the first source / drain pattern SD1 and the upper surface of the second pattern T2 of the second source / drain pattern SD2. Here, the back surface power via MPV can be formed to fill the inside of the second hole HL2, and thus, the back surface power via MPV described with reference to Figure 4 and Figures 5A-5C can be formed.

[0115] A backside power rail MPR can be formed on the upper surface of the backside power via MPV.

[0116] Referring back Figure 1 and Figures 3A-3D A power distribution network layer PDN can be formed on the lower surface of the substrate 200.

[0117] Accordingly, the semiconductor device can include a power gating unit. Accordingly, the power gating unit can selectively send a power voltage only to a logic unit that needs power. Accordingly, power usage of the semiconductor device can be minimized, and thus, power consumption of the semiconductor device can be reduced.

[0118] Further, some lines for driving the power gating unit can be buried in the substrate. Accordingly, a degree of freedom in arrangement of various components for driving the power gating unit can be improved. Accordingly, the semiconductor device can be easily designed.

[0119] Further, the power gating unit can be driven through the lower surface of the substrate, thereby providing better design flexibility.

[0120] Further, a power voltage can be provided to a PMOS device (e.g., in a second active region AR2) through an NMOS device (e.g., in a first active region AR1), as shown in Figure 2B and Figure 3C The power voltage can be provided through the MPV. The power can then be routed (e.g., along direction D2) to other devices in the same cell / active region as the PMOS device (e.g., using the MPR).

[0121] While the present disclosure contains many specifics, these should not be construed as limiting the scope of the claims. Some features outside the spirit of the present disclosure can be practiced separately from other features. Conversely, some features may be practiced in combinations other than those described herein in combinations with each other and / or with features described in the following claims. Still other features can be practiced in the absence of any of the features described herein. Moreover, although features can be described above as acting in certain combinations and / or with respect to the apparatus and / or methods described herein, one or more features from a described combination can be excised from the combination and be employed with other combinations reported herein.

[0122] While various examples have been described herein, it will be apparent to those of ordinary skill in the art that many modifications, substitutions and changes can be made to the examples without departing from the scope of the present disclosure. Accordingly, the terminology used herein is for the purpose of describing specific examples. The use of particular terms to describe non-limiting examples should not be taken to limit the scope of the present disclosure.

Claims

1. A semiconductor device comprising: a power distribution network layer on a lower surface of a substrate; a gate electrode on the substrate; a first source / drain pattern and a second source / drain pattern on the substrate, each of the first source / drain pattern and the second source / drain pattern including a first pattern and a second pattern spaced apart from each other, the gate electrode being between the first pattern and the second pattern; a via structure extending in the substrate in a direction perpendicular to an upper surface of the substrate, the via structure connecting the power distribution network layer with the first pattern of the first source / drain pattern; and a backside power via extending from a first location below the second pattern of the first source / drain pattern to a second location below the second pattern of the second source / drain pattern.

2. The semiconductor device of claim 1, wherein, The backside power via is connected to each of the second pattern of the first source / drain pattern and the second pattern of the second source / drain pattern.

3. The semiconductor device of claim 1, wherein, The second pattern of the first source / drain pattern and the second pattern of the second source / drain pattern each vertically overlap the backside power via.

4. The semiconductor device of claim 1, wherein, The via structure is connected to the backside power via through the first pattern and the second pattern of the first source / drain pattern.

5. The semiconductor device of claim 1, comprising: a backside power rail in contact with a lower surface of the backside power via below the second pattern of the second source / drain pattern.

6. The semiconductor device of claim 5, wherein, The backside power rail extends below the second source / drain pattern in a direction parallel to the upper surface of the substrate.

7. The semiconductor device of claim 5, wherein, The backside power rail vertically overlaps the second source / drain pattern.

8. The semiconductor device of claim 5, wherein, The via structure is connected to the backside power rail through the first pattern and the second pattern of the first source / drain pattern and through the backside power via.

9. The semiconductor device of claim 5, wherein, The backside power via extends in a direction perpendicular to a direction in which the backside power rail extends.

10. The semiconductor device of claim 1, further comprising: a first backside conductive contact between the backside power via and the second pattern of the first source / drain pattern; and a second backside conductive contact between the backside power via and the second pattern of the second source / drain pattern. The backside power via is in contact with each of the second pattern of the first source / drain pattern and the second pattern of the second source / drain pattern.

11. The semiconductor device of claim 1, wherein, a first channel pattern between the first pattern and the second pattern of the first source / drain pattern, 12. The semiconductor device of claim 1, further comprising: wherein the first pattern and the second pattern of the first source / drain pattern are connected through the first channel pattern.

13. A semiconductor device comprising: a power distribution network layer on a lower surface of a substrate; a gate electrode on the substrate; a first source / drain pattern and a second source / drain pattern on the substrate, each of the first source / drain pattern and the second source / drain pattern including a first pattern and a second pattern spaced apart from each other, the gate electrode being between the first pattern and the second pattern; a via structure in the substrate and extending in a direction perpendicular to an upper surface of the substrate, the via structure connecting the power distribution network layer with the first pattern of the first source / drain pattern; ​ a backside power rail extending below the second source / drain pattern in a first direction parallel to the upper surface of the substrate; and a backside power via extending from a first location below the second pattern of the first source / drain pattern to an upper surface of the backside power rail.

14. The semiconductor device of claim 13, wherein, The backside power via is connected to each of the second pattern of the first source / drain pattern and the second pattern of the second source / drain pattern.

15. The semiconductor device of claim 13, wherein, The via structure is connected to the backside power rail through the first pattern and the second pattern of the first source / drain pattern and through the backside power via.

16. The semiconductor device of claim 13, wherein, The backside power via extends from the first location to a second location below the second pattern of the second source / drain pattern.

17. The semiconductor device of claim 13, wherein, The backside power via extends in a second direction perpendicular to the first direction in which the backside power rail extends.

18. The semiconductor device of claim 13, comprising: a first channel pattern between the first pattern and the second pattern of the first source / drain pattern, wherein the first pattern and the second pattern of the first source / drain pattern are connected through the first channel pattern.

19. A semiconductor device, comprising: a power distribution network layer on a lower surface of a substrate; a gate electrode on the substrate; a first source / drain pattern and a second source / drain pattern on the substrate, the first source / drain pattern and the second source / drain pattern each comprising a first pattern and a second pattern spaced apart from each other, the gate electrode being between the first pattern and the second pattern; a first channel pattern between the first pattern and the second pattern of the first source / drain pattern; a via structure in the substrate and extending in a direction perpendicular to an upper surface of the substrate, the via structure connecting the power distribution network layer with the first pattern of the first source / drain pattern; an active contact on the first pattern of the second source / drain pattern; a backside power rail extending below the second source / drain pattern in a direction parallel to the upper surface of the substrate; and a backside power via extending from a first location below the second pattern of the first source / drain pattern to an upper surface of the backside power rail.

20. The semiconductor device of claim 19, wherein, The via structure is connected to the backside power rail through the first pattern of the first source / drain pattern, the first channel pattern, the second pattern of the first source / drain pattern, and the backside power via.

Images