Display panel and display device including same

Abstract

A display panel and a display device including the same are disclosed. The display panel includes: a substrate; a transistor on the substrate; a storage capacitor on the substrate and electrically connected to the transistor; a metal layer between the substrate and the transistor; a first insulating layer on the metal layer and having a first contact hole; and a wiring connected to the metal layer through the first contact hole, in which the first insulating layer has a first hole spaced apart from the transistor.

Description

[0001] This application is a divisional application of the invention patent application with the application date of 2020.03.19, the application number of 202010195378.7, and the invention name of "Display panel and display device including the same". TECHNICAL FIELD

[0002] Aspects of the present application relate to a display panel having a transmissive area and a display device including the same. BACKGROUND

[0003] Recently, the application fields of display devices have become more diversified. As display devices have become thinner and lighter, their range of use has gradually expanded.

[0004] As the area occupied by the display area of a display device increases, functions that can be combined or associated with the display device are being added. As a way of adding various functions while increasing the display area, research is being conducted on display devices in which various elements can be arranged in the display area. SUMMARY

[0005] Aspects of some of the embodiments relate to a display panel and a display device including the same, the display panel including an area in which various suitable kinds of components can be arranged inside a display area. However, it should be understood that the embodiments described herein should be considered in a descriptive sense only and not as a limitation on the disclosure.

[0006] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the description, or can be learned by practice of the presented embodiments.

[0007] According to some embodiments, there is provided a display panel, the display panel comprising: a substrate; a transistor on the substrate; a storage capacitor on the substrate and electrically connected to the transistor; a metal layer between the substrate and the transistor; a first insulating layer on the metal layer and having a first contact hole; and a wiring connected to the metal layer through the first contact hole, wherein the first insulating layer has a first hole spaced apart from the transistor.

[0008] In some embodiments, the first insulating layer includes a plurality of sub-layers.

[0009] In some embodiments, the number of layers defining the first contact hole is the same as the number of layers defining the first hole.

[0010] In some embodiments, a material change of a side surface of the first contact hole in a depth direction of the first contact hole is the same as a material change of a side surface of the first hole in a depth direction of the first hole.

[0011] In some embodiments, the display panel further includes a second insulating layer on the first insulating layer and having a second contact hole for connection between a source electrode or a drain electrode of the transistor and a semiconductor layer of the transistor.

[0012] In some embodiments, the second insulating layer further has a second contact hole for connection between a source electrode or a drain electrode of the transistor and a semiconductor layer of the transistor.

[0013] In some embodiments, the number of layers defining the second contact hole is the same as the number of layers defining the second hole.

[0014] In some embodiments, the material variation of the side surface of the second contact hole in the depth direction of the second contact hole is the same as the material variation of the side surface of the second hole in the depth direction of the second hole.

[0015] In some embodiments, the width of the second hole is different from the width of the first hole.

[0016] In some embodiments, the metal layer has a voltage level that is the same as a voltage level of a gate electrode of the transistor.

[0017] In some embodiments, the display panel further includes a drive voltage line electrically connected to the transistor and the storage capacitor, wherein the metal layer has a voltage level that is the same as a voltage level of the drive voltage line.

[0018] According to some embodiments, there is provided a display device including: a substrate; a transistor and a storage capacitor on the substrate; a metal layer between the substrate and the transistor; a first insulating layer on the metal layer and having a first contact hole; a wiring connected to the metal layer through the first contact hole; and an assembly arranged below the substrate, wherein the first insulating layer has a first hole spaced apart from the transistor, and wherein the assembly corresponds to the first hole.

[0019] In some embodiments, the number of layers defining the first contact hole is the same as the number of layers defining the first hole.

[0020] In some embodiments, the material variation of the side surface of the first contact hole in the depth direction of the first contact hole is the same as the material variation of the side surface of the first hole in the depth direction of the first hole.

[0021] In some embodiments, the display device further includes a second insulating layer on the first insulating layer and having a second hole superimposed on the first hole.

[0022] In some embodiments, the second insulating layer further has a second contact hole for connection between a source electrode or a drain electrode of the transistor and a semiconductor layer of the transistor.

[0023] In some embodiments, the number of layers defining the second contact hole is the same as the number of layers defining the second hole.

[0024] In some embodiments, the material variation of the side surface of the second contact hole in the depth direction of the second contact hole is the same as the material variation of the side surface of the second hole in the depth direction of the second hole.

[0025] In some embodiments, the width of the second hole is different from the width of the first hole.

[0026] In some embodiments, the metal layer has a voltage level that is the same as a voltage level of a gate electrode of the transistor.

[0027] In some embodiments, the display device further includes a drive voltage line electrically connected to the transistor and the storage capacitor, wherein the metal layer has a voltage level that is the same as a voltage level of the drive voltage line.

[0028] In some embodiments, the substrate includes a first region in which the first display element is located, a second region in which the second display element is located, and a third region in which the first hole is located, wherein the transistor, the storage capacitor, and the metal layer are located in the second region, and wherein the transistor and the storage capacitor are electrically connected to the second display element.

[0029] In some embodiments, the assembly corresponds to the second region and the third region, and the metal layer overlaps a portion of the assembly.

[0030] In some embodiments, the assembly includes an electronic element that emits and / or receives light.

[0031] In some embodiments, the display device further includes a second assembly corresponding to the second region and different from the assembly.

[0032] These and / or other aspects will become apparent and more readily appreciated from the following description, considered in connection with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] These and / or other aspects will become apparent and more readily appreciated from the following description, considered in connection with the accompanying drawings, in which:

[0034] Figure 1 is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0035] Figure 2 is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0036] Figure 3 is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0037] Figure 4is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0038] Figures 5A-5D is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0039] Figure 6 is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0040] Figure 7 is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0041] Figure 8 is a cross-sectional view of one process of manufacturing a display panel according to an example embodiment;

[0042] Figure 9 is a cross-sectional view of a display panel according to another example embodiment;

[0043] Figure 10 is a cross-sectional view of a display panel according to another example embodiment;

[0044] Figure 11 is a cross-sectional view of a display panel according to another example embodiment;

[0045] Figure 12 is a cross-sectional view of a display panel according to another example embodiment;

[0046] Figure 13 is a cross-sectional view of a display panel according to another example embodiment;

[0047] Figure 14 is a cross-sectional view of a display panel according to another example embodiment;

[0048] Figure 15 is a cross-sectional view of a display panel according to another example embodiment;

[0049] Figure 16 is a cross-sectional view of a display panel according to another example embodiment;

[0050] Figure 17 is a cross-sectional view of a display panel according to another example embodiment;

[0051] Figure 18 is a perspective view of a display device according to an example embodiment;

[0052] Figure 19 is a cross-sectional view of a display device according to an example embodiment;

[0053] Figure 20 is a plan view of a display panel according to an example embodiment;

[0054] Figure 21 is an equivalent circuit diagram of one of pixels of a display panel according to an example embodiment;

[0055] Figure 22 is a plan view of a first component area, a second component area, and their vicinity of a display panel according to an example embodiment;

[0056] Figure 23 is a cross-sectional view of a display panel according to an example embodiment;

[0057] Figure 24 is a cross-sectional view of a display panel according to another embodiment; and

[0058] Figure 25 is a cross-sectional view of a display panel according to another example embodiment. DETAILED DESCRIPTION

[0059] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects of the present description.

[0060] Since the disclosure allows various changes and numerous embodiments, example embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the disclosure and methods of achieving the same will be apparent when the embodiments described in the written description are referenced in conjunction with the accompanying drawings. However, the disclosure can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein.

[0061] Hereinafter, the disclosure will be described more fully with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. When described with reference to the drawings, like reference numerals in the drawings denote like or corresponding elements, and repetitive description thereof will be omitted.

[0062] For ease of explanation, the sizes of the elements in the drawings can be exaggerated. In other words, since the sizes and thicknesses of the components in the drawings are arbitrarily shown for the ease of explanation, the following embodiments are not limited thereto.

[0063] When a certain embodiment can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two continuously described processes can be performed substantially simultaneously or in an order opposite to the described sequence.

[0064] Figures 1-8 is a cross-sectional view of a process of manufacturing a display panel according to an embodiment.

[0065] Referring toFigure 1 The substrate 100 may include a first area A1, a second area A2, and a third area A3. The substrate 100 may include a transparent material. For example, the substrate 100 may include a glass material or a polymer resin.

[0066] A metal layer ML is formed in the second area A2 of the substrate 100. The metal layer ML may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, etc. The metal layer ML may include a single layer or multiple layers including the above materials. In an embodiment, the metal layer ML may include a layer including Mo.

[0067] The buffer layer 201 may be formed on the substrate 100 on which the metal layer ML is formed. The buffer layer 201 may include silicon nitride (SiN x , x>0), silicon oxynitride (SiON) and silicon oxide (SiO x , x>0) inorganic insulating material. The buffer layer 201 may include a single layer or multiple layers containing the above-mentioned inorganic insulating material. The buffer layer 201 may be formed on the substrate 100 to cover the entire surface of the first area A1, the second area A2, and the third area A3.

[0068] Then, a first semiconductor layer Act1 and a second semiconductor layer Act2 are formed in the first area A1 and the second area A2, respectively. The first semiconductor layer Act1 and the second semiconductor layer Act2 may include polycrystalline silicon. In another embodiment, the first semiconductor layer Act1 and the second semiconductor layer Act2 may include amorphous silicon. In another embodiment, the first semiconductor layer Act1 and the second semiconductor layer Act2 may include an oxide semiconductor containing In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and / or Zn. For example, the first semiconductor layer Act1 and the second semiconductor layer Act2 may include an oxide semiconductor such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO).

[0069] The second semiconductor layer Act2 may overlap the metal layer ML. In an embodiment, the width of the second semiconductor layer Act2 may be smaller than the width of the metal layer ML. Therefore, when viewed in a direction perpendicular to the substrate 100, the entire surface of the second semiconductor layer Act2 may overlap the metal layer ML.

[0070] The first semiconductor layer Act1 and the second semiconductor layer Act2 may be covered by a gate insulating layer 203. The gate insulating layer 203 may include a silicon nitride (SiN x , x>0), silicon oxynitride (SiON) and silicon oxide (SiO xAn inorganic insulating material having a composition of SiOx (x > 0) can be used as the inorganic insulating material. The gate insulating layer 203 can include a single layer or multiple layers including the inorganic insulating material described above. The gate insulating layer 203 can be formed over the substrate 100 to cover the entire surface of the first region Al, the second region A2, and the third region A3.

[0071] Referring to Figure 2 The first contact hole (i.e., first contact opening) CNT1 and the first hole (i.e., first opening) H1 are formed. The first contact hole CNT1 and the first hole H1 can be formed to pass through the first insulating layer IL1 on the substrate 100 and / or the metal layer ML. For example, the first contact hole CNT1 and the first hole H1 can be formed to pass through the buffer layer 201 and the gate insulating layer 203.

[0072] The first contact hole CNT1 can be formed to pass through the buffer layer 201 and the gate insulating layer 203 positioned in the second region A2. A portion of the metal layer ML disposed in the second region A2 can be exposed through the first contact hole CNT1. The first hole H1 can be formed to pass through a portion of the buffer layer 201 and the gate insulating layer 203 positioned in the third region A3. A portion of a layer positioned under the buffer layer 201 (e.g., the substrate 100) can be exposed through the first hole H1.

[0073] The first contact hole CNT1 can be formed during the same process as the process of forming the first hole H1. The side surface of the first insulating layer IL1 surrounding the first contact hole CNT1 can define the first contact hole CNT1. The side surface of the first insulating layer IL1 surrounding the first hole H1 can define the first hole H1. For example, it can be understood that the side surface of the first insulating layer IL1 surrounding the first contact hole CNT1 is the side surface of the first contact hole CNT1, and the side surface of the first insulating layer IL1 surrounding the first hole H1 is the side surface of the first hole H1.

[0074] The material variation of the first insulating layer IL1 in the depth (thickness) direction of the first contact hole CNT1 can be the same as the material variation of the first insulating layer IL1 in the depth (thickness) direction of the first hole H1. Likewise, the material variation of the side surface of the first contact hole CNT1 in the depth (thickness) direction of the first contact hole CNT1 can be substantially the same as the material variation of the side surface of the first hole H1 in the depth (thickness) direction of the first hole H1.

[0075] For example, a case in which the buffer layer 201 as a sub-layer of the first insulating layer IL1 includes a double layer of a silicon nitride layer and a silicon oxide layer and the gate insulating layer 203 as a sub-layer of the first insulating layer IL1 includes a single layer of a silicon oxide layer is described. Referring to Figure 2An enlarged view of the second region A2, the material variation in the thickness (depth) direction (e.g., ar1 direction) of the first insulating layer IL1 defining the first contact hole CNT1 can occur in the order of silicon oxide-silicon oxide-silicon nitride. As shown in the enlarged view of the third region A3, Figure 2 As shown in the enlarged view of the third region A3, since the first hole H1 is formed through the same insulating layer during the same process as that of forming the first contact hole CNT1, the material variation in the thickness (depth) direction (e.g., ar2 direction) of the first insulating layer IL1 defining the first hole H1 can also occur in the order of silicon oxide-silicon oxide-silicon nitride.

[0076] The first contact hole CNT1 is formed during the same process as that of forming the first hole H1, and the number of layers defining the first contact hole CNT1 is the same as the number of layers defining the first hole H1. In an embodiment, in a case where the buffer layer 201 as a sub-layer of the first insulating layer IL1 includes a double layer of a silicon nitride layer and a silicon oxide layer and the gate insulating layer 203 as a sub-layer of the first insulating layer IL1 includes a single layer of a silicon oxide layer, the number of layers defining the first contact hole CNT1 is three, which is equal to the three layers defining the first hole H1. The number of layers defining the first contact hole CNT1 and the first hole H1 can be determined by the number of interfaces between the layers.

[0077] Referring to Figure 3 The first gate electrode G1 and the second gate electrode G2 are formed over the substrate 100 in which the first contact hole CNT1 and the first hole H1 are formed. The first gate electrode G1 can be positioned over the first semiconductor layer Act1 in the first region A1, and the second gate electrode G2 can be positioned over the second semiconductor layer Act2 in the second region A2.

[0078] Each of the first gate electrode G1 and the second gate electrode G2 can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, etc. The first gate electrode G1 and the second gate electrode G2 can include a single layer or a plurality of layers including the above-described materials. In an embodiment, the first gate electrode G1 and the second gate electrode G2 can include the same material as that of the metal layer ML or a different material from that of the metal layer ML.

[0079] The wiring GCL can be formed during a process of forming the first gate electrode G1 and the second gate electrode G2. The wiring GCL can include the same material as that of the first gate electrode G1 and the second gate electrode G2. The wiring GCL can be connected to the metal layer ML through the first contact hole CNT1 and can transmit a signal (e.g., a predetermined signal), for example, a gate signal. In the second area A2, the metal layer ML can be utilized as a gate electrode. In this case, the metal layer ML can have the same voltage level as that of the second gate electrode G2. For example, the second gate electrode G2 can serve as a top gate electrode, and the metal layer ML can serve as a bottom gate electrode.

[0080] After the first gate electrode G1 and the second gate electrode G2 are formed, the first semiconductor layer Act1 and the second semiconductor layer Act2 can be doped with impurities by using the first gate electrode G1 and the second gate electrode G2, respectively, as a self-aligned mask. The first semiconductor layer Act1 can include a first channel region CR1, a first source region SR1, and a first drain region DR1. The first channel region CR1 can overlap the first gate electrode G1, and the first source region SR1 and the first drain region DR1 can be doped with impurities. The second semiconductor layer Act2 can include a second channel region CR2, a second source region SR2, and a second drain region DR2. The second channel region CR2 can overlap the second gate electrode G2, and the second source region SR2 and the second drain region DR2 can be doped with impurities.

[0081] Referring to Figure 4 The first interlayer insulating layer 205 is formed over the substrate 100 over which the first gate electrode G1, the second gate electrode G2, and the wiring GCL are formed. Then, the first electrode layer CE1b and the second electrode layer CE2b are formed, which overlap the first gate electrode G1 and the second gate electrode G2, respectively.

[0082] The first interlayer insulating layer 205 can include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and can include a single layer or a plurality of layers including the above-described inorganic insulating material.

[0083] In the first area A1, the first electrode layer CE1b can overlap the first gate electrode G1 thereunder. The first gate electrode G1 and the first electrode layer CE1b can constitute a first storage capacitor Cst1, which overlap each other with the first interlayer insulating layer 205 therebetween. The first gate electrode G1 can serve as a lower electrode CE1a of the first storage capacitor Cst1, and the first electrode layer CE1b can serve as an upper electrode thereof.

[0084] In the second region A2, the second electrode layer CE2b can be superposed with the second gate electrode G2 thereunder. The second gate electrode G2 and the second electrode layer CE2b can constitute the second storage capacitor Cst2, the second gate electrode G2 and the second electrode layer CE2b being superposed with each other with the first interlayer insulating layer 205 therebetween. The second gate electrode G2 can serve as a lower electrode CE2a of the second storage capacitor Cst2, and the second electrode layer CE2b can serve as an upper electrode of the second storage capacitor Cst2.

[0085] The first electrode layer CE1b and the second electrode layer CE2b can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, and the like, and can include a single layer or a plurality of layers including the above-described materials.

[0086] Then, the second interlayer insulating layer 207 is formed. The second interlayer insulating layer 207 can include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and can include a single layer or a plurality of layers including the above-described inorganic insulating material. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 can cover the entire surface of the substrate 100. Accordingly, the first hole H1 in the third region A3 can be covered with the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0087] Referring to Figure 5A , the second contact hole (i.e., second contact opening) CNT2 and the second hole (i.e., second opening) H2 are formed. The second contact hole CNT2 and the second hole H2 can be formed to pass through the second insulating layer IL2. The second contact hole CNT2 is formed in the first region A1 and the second region A2. The second hole H2 is formed in the third region A3. The second contact hole CNT2 can be formed to pass through the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. The second hole H2 can be formed to pass through the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0088] The second hole H2 can be defined by the side surface of the second insulating layer IL2 surrounding the second hole H2. For example, in a case where the first interlayer insulating layer 205 is a single layer and the second interlayer insulating layer 207 is a single layer (the first interlayer insulating layer 205 and the second interlayer insulating layer 207 are sub-layers of the second insulating layer IL2), the number of layers defining the second hole H2 can be two. The number of layers defining the second hole H2 can be the same as the number of layers between the wiring GCL and the second source electrode SE2 (see Figure 6 ) to be formed during a process to be described below. The number of layers defining the second hole H2 can be the same as the number of layers between the wiring GCL and the second drain electrode DE2 (see Figure 6 ) to be formed during a process to be described below.Figure 6 ) between the layers, the second drain electrode DE2 (see Figure 6 ) will be formed during the processes described below.

[0089] In the first region A1, the first source region SR1 and / or the first drain region DR1 of the first semiconductor layer Act1 can be exposed through the second contact hole CNT2. In the second region A2, the second source region SR2 and / or the second drain region DR2 of the second semiconductor layer Act2 can be exposed through the second contact hole CNT2.

[0090] The second hole H2 formed in the third region A3 overlaps the first hole H1. As shown in Figure 5A , the width W2 of the second hole H2 can be smaller than the width W1 of the first hole H1. In another embodiment, as shown in Figure 5B , the width W2 of the second hole H2 can be larger than the width W1 of the first hole H1. In an embodiment, depending on whether the materials of the gate insulating layer 203 and the first interlayer insulating layer 205 are different from each other and / or the conditions of the process (e.g., etching process) of forming the second hole H2, as shown in Figure 5B , the connecting portion of the second hole H2 and the first hole H1 can constitute a step difference, or as shown in Figure 5C , the connecting portion of the second hole H2 and the first hole H1 can constitute an inclined surface (a gently inclined surface or an inclined surface with a curve), or as shown in Figure 5D , the side surface of the first insulating layer IL1 constituting the first hole H1 itself can have a step difference while removing a portion of the side surface of the first insulating layer IL1 defining the first hole H1 during the etching process of forming the second hole H2. In the following drawings, for ease of description, as shown in Figure 5A , the case where the width W2 of the second hole H2 is smaller than the width W1 of the first hole H1 is described.

[0091] Referring to Figure 6 , the source electrode and / or the drain electrode are formed over the substrate 100 on which the second contact hole CNT2 and the second hole H2 are formed. In this regard, it is shown in Figure 6 that the first source electrode SE1 and the first drain electrode DE1 are formed in the first region A1, and the second source electrode SE2 and the second drain electrode DE2 are formed in the second region A2.

[0092] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can include Mo, Al, Cu, and / or Ti, etc., and can include a single layer or multiple layers containing the above-mentioned materials. In an embodiment, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can include multiple layers of Ti / Al / Ti.

[0093] Referring to Figure 7 A planarization layer 209 is formed. The planarization layer 209 can cover the first transistor TR1 and the first storage capacitor Cst1 in the first area A1 and the second transistor TR2 and the second storage capacitor Cst2 in the second area A2. The planarization layer 209 can include an organic insulating material. The organic insulating material can include a general-purpose polymer, a polymer derivative having a phenol group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof. In an embodiment, the planarization layer 209 can include polyimide.

[0094] Then, a third contact hole (i.e., a third contact opening) CNT3 is formed in the planarization layer 209. The third contact hole CNT3 can be formed in each of the first area A1 and the second area A2. The planarization layer 209 can include a third hole (i.e., a third opening) H3 positioned in the third area A3. The third hole H3 can be formed during the same process as the process of forming the third contact hole CNT3 or a separate process. The third hole H3 overlaps the first hole H1 and the second hole H2.

[0095] Next, a first pixel electrode 221-1 and a second pixel electrode 221-2 are formed in the first area A1 and the second area A2, respectively. The first pixel electrode 221-1 can be electrically connected to the first transistor TR1 through the third contact hole CNT3, and the second pixel electrode 221-2 can be electrically connected to the second transistor TR2 through the third contact hole CNT3.

[0096] The first pixel electrode 221-1 and the second pixel electrode 221-2 can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO), or the like. In another embodiment, the first pixel electrode 221-1 and the second pixel electrode 221-2 can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof. In another embodiment, the first pixel electrode 221-1 and the second pixel electrode 221-2 can further include a layer including ITO, IZO, ZnO, and / or In2O3, or the like, on / under the reflective layer.

[0097] A pixel-defining layer 211 is formed over the first pixel electrode 221-1 and the second pixel electrode 221-2. The pixel-defining layer 211 can cover edges of each of the first pixel electrode 221-1 and the second pixel electrode 221-2 in the first area A1 and the second area A2. The pixel-defining layer 211 can include an organic insulating material and / or an inorganic insulating material. The pixel-defining layer 211 includes a first opening OP1 and a second opening OP2 which are superposed with the first pixel electrode 221-1 and the second pixel electrode 221-2, respectively.

[0098] The pixel-defining layer 211 can include a fourth hole (i.e., a fourth opening) H4 positioned in the third area A3. The fourth hole H4 can be formed during the same process as a process of forming the first opening OP1 and the second opening OP2. In some examples, the fourth hole H4 can be formed during a different process.

[0099] A first functional layer 222a is formed over the substrate 100 over which the pixel-defining layer 211 is formed. The first functional layer 222a can include a single layer or multiple layers. The first functional layer 222a can include a hole transport layer (HTL) having a single layer structure. In some embodiments, the first functional layer 222a can include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 222a can be provided in one body to cover the first area A1 and the second area A2.

[0100] Then, a first emission layer 222b1 is formed in the first area A1, and a second emission layer 222b2 is formed in the second area A2. The first emission layer 222b1 and the second emission layer 222b2 can include a polymer material or a low molecular weight material, and emit red light, green light, blue light, or white light. The first emission layer 222b1 and the second emission layer 222b2 can be patterned to be superposed with the first pixel electrode 221-1 and the second pixel electrode 221-2, respectively.

[0101] Next, a second functional layer 222c can be formed. In embodiments, the second functional layer 222c can be omitted. For example, in a case where the first functional layer 222a and the emission layer (e.g., the first emission layer 222b1 and the second emission layer 222b2) include a polymer material, it can be preferable to form the second functional layer 222c. The second functional layer 222c can include a single layer or multiple layers. The second functional layer 222c can include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 222c can be formed in one body to cover the first area A1 and the second area A2.

[0102] Then, a counter electrode 223 is formed. The counter electrode 223 can include a conductive material having a low work function. For example, the counter electrode 223 can include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. In some examples, the counter electrode 223 can further include a layer including ITO, IZO, ZnO, or In2O3, etc. on the (semi-)transparent layer including the above-described material. The counter electrode 223 can be formed in one body to cover the first region A1 and the second region A2.

[0103] Layers from the first pixel electrode 221-1 to the counter electrode 223 formed in the first region A1 can constitute a first organic light emitting diode OLED1. Layers from the second pixel electrode 221-2 to the counter electrode 223 formed in the second region A2 can constitute a second organic light emitting diode OLED2.

[0104] Referring to Figure 8 The first organic light emitting diode OLED1 and the second organic light emitting diode OLED2 can be covered by an encapsulation substrate 300A. The encapsulation substrate 300A can include a transparent material. For example, the encapsulation substrate 300A can include a glass material. In some examples, the encapsulation substrate 300A can include a polymer resin. The encapsulation substrate 300A can prevent or substantially prevent external moisture or foreign substances from penetrating into the first organic light emitting diode OLED1 and the second organic light emitting diode OLED2.

[0105] A sealing material such as a sealant can be disposed between the encapsulation substrate 300A and the substrate 100 on which the first organic light emitting diode OLED1 and the second organic light emitting diode OLED2 are formed. The sealing material can block external moisture or foreign substances that can penetrate a space between the substrate 100 and the encapsulation substrate 300A.

[0106] Before the encapsulation substrate 300A is disposed, a cap layer 250 can be formed on the counter electrode 223. The cap layer 250 can include LiF. In some examples, the cap layer 250 can include an inorganic insulating material such as silicon nitride and / or an organic insulating material. In some examples, the cap layer 250 can be omitted.

[0107] Referring to Figures 1-8 The described display panel 10A can display an image (e.g., a predetermined image) through the first organic light emitting diode OLED1 disposed in the first region A1 and the second organic light emitting diode OLED2 disposed in the second region A2. The third region A3 can include a transmissive region through which light can be transmitted. For example, in the case where the third region A3 includes a transmissive region, the display panel 10A can display an image through the first organic light emitting diode OLED1 and the second organic light emitting diode OLED2 and can transmit light through the third region A3. Figure 8In the embodiment, light generated from below the substrate 100 may travel through the third area A3 in the z direction, and light generated from above the encapsulation substrate 300A may travel through the third area A3 in the (-)z direction.

[0108] Figure 9 is a cross-sectional view of a display panel according to another embodiment. Figure 8 FIG. 1 shows that the display panel 10A may include a packaging substrate 300A as a packaging member, but in FIG. Figure 9 In another embodiment shown in , the display panel 10B may include a thin film encapsulation layer 300B as an encapsulation member.

[0109] Figure 9 Shown is a reference Figure 7 The process described above is followed by a process and shows a state in which the capping layer 250 is formed. Figure 9 , a thin film encapsulation layer 300B is formed on the capping layer 250. The thin film encapsulation layer 300B may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 9 3 shows that the thin film encapsulation layer 300B has a structure in which a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 are stacked. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be modified.

[0110] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one of inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride, and may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 may include a polymer material. The polymer material may include silicone resin, acrylic resin, epoxy resin, polyimide, and / or polyethylene, etc.

[0111] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be formed as a single body to cover the first area A1, the second area A2, and the third area A3. The organic encapsulation layer 320 may be formed as a single body to cover the first area A1 and the second area A2. The organic encapsulation layer 320 may not be present in the third area A3. In other words, the organic encapsulation layer 320 may include an opening corresponding to the third area A3. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contact each other in the third area A3. The first inorganic encapsulation layer 310 may contact the top surface of the substrate 100.

[0112] The substrate 100 may include multiple layers. For example, the substrate 100 may include a first base layer 101 , a first barrier layer 102 , a second base layer 103 , and a second barrier layer 104 .

[0113] Each of the first base layer 101 and the second base layer 103 can include a polymer resin. For example, each of the first base layer 101 and the second base layer 103 can include a polymer resin such as polyether sulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), or the like. The polymer resin can be transparent.

[0114] Each of the first barrier layer 102 and the second barrier layer 104 is a barrier layer that prevents or substantially prevents permeation of external foreign matter, and can include a single layer or multiple layers of an inorganic insulating material including silicon nitride (SiN x , x > 0) and silicon oxide (SiO x , x > 0). In a case in which the substrate 100 includes a polymer resin, flexibility of the substrate 100 can be relatively improved (e.g., increased) as compared to a case in which the substrate 100 includes a glass material.

[0115] Figure 10 is a cross-sectional view of a display panel 10B' according to another embodiment. As described with reference to Figure 9 , unlike a substrate including a glass material, in a substrate 100 including a polymer resin, a hole passing through the substrate 100 can be easily formed.

[0116] Referring to Figure 10 , as described with reference to Figure 9 , after the thin film encapsulation layer 300B is formed, a hole 100H passing through the substrate 100 can be formed. The hole 100H can be formed by a process such as laser, scribing, and polishing. During the process of forming the hole 100H, a hole 300BH in the thin film encapsulation layer 300B can also be formed, the hole 300BH corresponding to the third area A3. The hole 100H passing through the substrate 100 and the hole 300BH passing through the thin film encapsulation layer 300B can be superposed on each other and superposed on the first hole H1, the second hole H2, the third hole H3, and / or the fourth hole H4.

[0117] Since the display panel 10B' shown in Figure 10 includes the hole 10BH passing through the third area A3 of the display panel 10B', the display panel 10B' can have a relatively high transmittance in the third area A3 as compared to the display panel 10B shown in Figure 9 . Light and / or sound can be transmitted through the hole 10BH of the display panel 10B' shown in Figure 10 .

[0118] Figure 11is a cross-sectional view of the display panel 10C according to an embodiment. Since the structures of the first region Al and the second region A2 of the display panel 10C in Figure 11 are the same as those of the first region Al and the second region A2 of the display panel 10A described with reference to Figures 1-8 , the third region A3 will mainly be described below.

[0119] With reference to the third region A3 of the display panel 10C in Figure 11 , at least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 250 can be positioned in the third region A3. Figure 11 The transmittance of the third region A3 of the display panel 10C in Figure 8 may be relatively smaller than the transmittance of the third region A3 of the display panel 10A described with reference to Figure 8 . In an embodiment, in a case where the third region A3 of the display panel 10A described with reference to Figure 11 is used as a region through which light in a visible light wavelength band is transmitted, the third region A3 of the display panel 10C in

[0120] may be used as a region through which light in, for example, an infrared wavelength band is transmittable. Figure 12 is a cross-sectional view of the display panel 10D according to an embodiment. Since the structures of the first region Al and the second region A2 of the display panel 10D in Figure 12 are the same as those of the first region Al and the second region A2 of the display panel 10B described with reference to Figure 9 , the third region A3 will mainly be described below.

[0121] With reference to the third region A3 of the display panel 10D in Figure 12 , at least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 250 can be positioned in the third region A3. In addition, the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 can be positioned in the third region A3. Figure 12 The transmittance of the third region A3 of the display panel 10D in Figure 9 may be relatively smaller than the transmittance of the third region A3 of the display panel 10B described with reference to Figure 12 . In an embodiment, the third region A3 of the display panel 10D in

[0122] may be used as a region through which light in, for example, an infrared wavelength band is transmittable. Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 ​In the display panels 10A, 10B, 10B', 10C, and 10D described above, the first hole H1, the second hole H2, and the like are formed to improve (e.g., increase) the transmittance of the third region A3. In this case, the first hole H1 can be formed concurrently (e.g., simultaneously) with the first contact hole CNT1 during a process of forming the first contact hole CNT1. The second hole H2 can be formed concurrently (e.g., simultaneously) with the second contact hole CNT2 during a process of forming the second contact hole CNT2. Thus, since a separate process for improving (e.g., increasing) the transmittance of the third region A3 is not needed, manufacturing costs, time, and the like can be reduced.

[0123] Although the display panels 10A, 10B, 10B', 10C, and 10D described with reference to Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 , the first hole H1 and the first contact hole CNT1 are formed to pass through the first insulating layer IL1, and the first insulating layer IL1 includes the buffer layer 201 and the gate insulating layer 203, the present disclosure is not limited thereto. In an embodiment, as described below with reference to Figures 13-21 , the first hole H1 and the first contact hole CNT1 can be formed in a first insulating layer including a larger number of sub-layers than the sub-layers described with reference to Figure 8 .

[0124] Figure 13 is a cross-sectional view of a display panel 10E according to another embodiment.

[0125] With reference to Figure 13 , the first hole H1 and the first contact hole CNT1 can be formed to pass through the first insulating layer IL1'. The first insulating layer IL1' can include the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205.

[0126] The wiring GCL' electrically connected to the metal layer ML formed in the second region A2 can be formed during the same process as that of forming the second electrode layer CE2b. The process of forming the first contact hole CNT1 for connection between the wiring GCL' and the metal layer ML can be performed after the first interlayer insulating layer 205 is formed. The first hole H1 can be formed concurrently (e.g., simultaneously) with the first contact hole CNT1 during the process of forming the first contact hole CNT1.

[0127] The first contact hole CNT1 can be defined by side surfaces of the first insulating layer IL1' surrounding the first contact hole CNT1, and the first hole H1 can be defined by side surfaces of the first insulating layer IL1' surrounding the first hole H1. Since the first hole H1 and the first contact hole CNT1 are formed through the first insulating layer IL1' during the same process, the number of layers defining the first hole H1 can be the same as the number of layers defining the first contact hole CNT1, and / or the material variation of the layers defining the first contact hole CNT1 in the thickness (depth) direction can have the same manner as the material variation of the layers defining the first hole H1 in the thickness (depth) direction. Likewise, the material variation of the side surfaces of the first contact hole CNT1 in the depth (thickness) direction of the first contact hole CNT1 can be the same as the material variation of the side surfaces of the first hole H1 in the depth (thickness) direction of the first hole H1.

[0128] The wiring GCL' can apply a voltage (e.g., a predetermined voltage), such as a constant voltage (e.g., ELVDD, see Figure 21 ) to the metal layer ML. As a comparative example, in a case where the wiring is in a floating state, external static electricity can be introduced through the wiring in the floating state, and thus the second transistor TR2 can be damaged. In the present embodiment, in order to prevent or substantially prevent the introduction of external static electricity, a constant voltage can be applied to the metal layer ML.

[0129] The second hole H2 can be formed concurrently (e.g., simultaneously) with the second contact hole CNT2 during the process of forming the second contact hole CNT2. The second hole H2 can be formed in the second insulating layer IL2'. The second insulating layer IL2' can include the second interlayer insulating layer 207 positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2. That is, the number of layers defining the second hole H2 can be the same as the number of layers positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2. In an embodiment, in a case where the second interlayer insulating layer 207 includes a double layer of a silicon oxide layer and a silicon nitride layer, the number of layers defining the second hole H2 can be two. In this case, the number of layers positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2 is two. In another embodiment, in a case where the second interlayer insulating layer 207 includes a single layer of a silicon nitride layer, the number of layers defining the second hole H2 can be one, and the number of layers positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2 is one.

[0130] Although in the above-described embodiment, the first contact hole CNT1 is formed through the first insulating layer IL1', the first contact hole CNT1 can be formed through the first insulating layer IL1' and the first hole H1 can be formed through the first insulating layer IL1' and the first contact hole CNT1. In this case, the first contact hole CNT1 can be formed concurrently (e.g., simultaneously) with the first hole H1 during the process of forming the first hole H1. Figure 13The first hole H1 is shown to have a width greater than the width of the second hole H2, but embodiments are not limited thereto. In another embodiment, the width of the first hole H1 can be less than the width of the second hole H2, as described with reference to Figure 5B In some examples, the width of the first hole H1 can be the same as the width of the second hole H2.

[0131] Other elements not including the features described with reference to Figure 13 the embodiment described with reference to the same elements. Figure 8

[0132] Figure 14 and Figure 15 are cross-sectional views of display panels 10F and 10F' according to another embodiment.

[0133] In the display panels 10F and 10F' shown in Figure 14 and Figure 15 , the first hole H1 and the first contact hole CNT1 can be formed to pass through a first insulating layer IL1' including the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205, as described with reference to Figure 13 Unlike the display panel 10E shown in

[0134] and Figure 13 , in the display panels 10F and 10F' shown in Figure 14 and Figure 15 , the first organic light emitting diode OLED1 and the second organic light emitting diode OLED2 can be covered by a thin film encapsulation layer 300B. In addition, the substrate 100 can include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104. The specific configuration of the thin film encapsulation layer 300B and the substrate 100 is the same as that described with reference to Figure 9

[0135] Unlike the display panel 10F of Figure 14 , Figure 15 the display panel 10F' of can include a hole 100H passing through the substrate 100 and a hole 300BH passing through the thin film encapsulation layer 300B in the third area A3.

[0136] Figure 16 is a cross-sectional view of a display panel 10G according to another embodiment.

[0137] In the display panel 10G shown in Figure 16 , the first hole H1 and the first contact hole CNT1 can be formed to pass through a first insulating layer IL1' including the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205, as described with reference to Figure 13 ​​As described with reference to the display panel 10G, the first hole H1 and the first contact hole CNT1 can be formed to pass through the first insulating layer IL1' including the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205. The second hole H2 can be formed to pass through the second insulating layer IL2' including the second interlayer insulating layer 207.

[0138] Referring to Figure 16 the third region A3 of the display panel 10G, at least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 250 can be positioned in the third region A3, and the specific configuration thereof is the same as that described with reference to Figure 11 .

[0139] Figure 17 is a cross-sectional view of a display panel 10H according to another embodiment.

[0140] In the display panel 10H shown in Figure 17 , as described with reference to Figure 13 , the first hole H1 and the first contact hole CNT1 can be formed to pass through the first insulating layer IL1' including the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205. The second hole H2 can be formed to pass through the second insulating layer IL2' including the second interlayer insulating layer 207.

[0141] Referring to Figure 17 the third region A3 of the display panel 10H, at least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 250 can be positioned in the third region A3. In addition, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be positioned in the third region A3, and the specific structure including the above-described configuration is the same as that described with reference to Figure 12 .

[0142] Figure 18 is a perspective view of a display device 1 according to an embodiment.

[0143] Referring to Figure 18 , the display device 1 includes a display area DA surrounding a first component area RA1 and a second component area RA2. The first component area RA1 and the second component area RA2 can have different sizes (areas) and / or different shapes. In some examples, the first component area RA1 and the second component area RA2 can have the same size (area) and / or the same shape.

[0144] The display area DA can display an image (e.g., a predetermined image) by using light emitted from a plurality of pixels arranged in the display area DA. The intermediate area MA can be arranged between the first component area RA1 and the second component area RA2 and the display area DA. The display area DA can be surrounded by the peripheral area PA. The intermediate area MA and the peripheral area PA can be a kind of non-display area in which pixels are not arranged. The intermediate area MA can be completely surrounded by the display area DA, and the display area DA can be completely surrounded by the peripheral area PA.

[0145] Hereinafter, although the display device 1 according to an embodiment is described by using an organic light emitting display device as an example, the display device 1 of the present disclosure is not limited thereto. In another embodiment, various types of display devices such as inorganic light emitting displays and quantum dot light emitting displays can be used.

[0146] Figure 19 is a cross-sectional view of the display device 1 according to an embodiment. Figure 19 may correspond to a cross-section taken along a line XIX-XIX’ of Figure 18 .

[0147] Referring to Figure 19 , the display device 1 can include a display panel 10, an input sensing layer 40, and an optical functional layer 50 arranged on the display panel 10. These layers can be covered by a window 60. The display device 1 can include various suitable electronic devices such as mobile phones, notebook computers, and smart watches.

[0148] The display panel 10 can display an image. The display panel 10 includes pixels arranged in a display area DA. Each pixel can include a display element and a pixel circuit connected thereto. The display element can include an organic light emitting diode. In some examples, the display element can include an inorganic light emitting diode or a quantum dot light emitting diode.

[0149] The input sensing layer 40 acquires coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 can include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 can be arranged on the display panel 10. The input sensing layer 40 can sense an external input using a mutual capacitance method and / or a self-capacitance method.

[0150] The input sensing layer 40 can be directly formed on the display panel 10, or can be separately formed and then bonded to the display panel 10 by using an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 can be continuously formed after a process of forming the display panel 10. In this case, the adhesive layer can not be arranged between the input sensing layer 40 and the display panel 10. Although Figure 19It is shown that the input sensing layer 40 is disposed between the display panel 10 and the optical function layer 50, but in another embodiment, the input sensing layer 40 can be disposed on the optical function layer 50.

[0151] The optical function layer 50 can include an anti-reflection layer. The anti-reflection layer can reduce the reflectance of light (external light) incident from the outside toward the display panel 10 through the window 60. The anti-reflection layer can include a retarder and a polarizer. The retarder can include a film type retarder or a liquid crystal type retarder. The retarder can include a λ / 2 (half wavelength) retarder and / or a λ / 4 (quarter wavelength) retarder. The polarizer can include a film type polarizer or a liquid crystal type polarizer. The film type polarizer can include a stretchable synthetic resin film, and the liquid crystal type polarizer can include liquid crystals arranged in a set or predetermined arrangement. Each of the retarder and the polarizer can further include a protective film. The retarder and the polarizer themselves or the protective film can be defined as a base layer of the anti-reflection layer.

[0152] In another embodiment, the anti-reflection layer can include a black matrix and a color filter. The color filter can be disposed by considering the colors of light emitted from the pixels of the display panel 10, respectively. In another embodiment, the anti-reflection layer can include a destructive interference structure. The destructive interference structure can include a first reflection layer and a second reflection layer disposed on different layers, respectively. First reflected light and second reflected light reflected by the first reflection layer and the second reflection layer, respectively, can generate destructive interference, and thus can reduce the reflectance of the external light.

[0153] The optical function layer 50 can include a lens layer. The lens layer can improve (e.g., increase) the emission efficiency of light emitted from the display panel 10 or reduce the color deviation of light. The lens layer can include a layer having a concave lens or convex lens shape, and / or include a plurality of layers having different refractive indices, respectively. The optical function layer 50 can include both the anti-reflection layer and the lens layer, or include one of the anti-reflection layer and the lens layer.

[0154] Each of the display panel 10, the input sensing layer 40, and the optical function layer 50 can include an opening corresponding to one of the first component area RA1 and the second component area RA2. In this regard, it is shown in FIG. 1 that the display panel 10, the input sensing layer 40, and the optical function layer 50 include the first component opening 11, the second component opening 41, and the third component opening 51, respectively, and the first component opening 11, the second component opening 41, and the third component opening 51 overlap each other in the first component area RA1. Figure 19

[0155] ​Components for adding various functions to the display device 1 can be positioned in the first component area RA1 and the second component area RA2. Each of the first component area RA1 and the second component area RA2 can correspond to a sensor area, a camera area, or a speaker area according to the kind of components.

[0156] As shown in FIG. 1A, the first component 21 disposed in the first component area RA1 can be positioned inside the first component opening 11, the second component opening 41, and the third component opening 51. In some examples, like the second component 22, the first component 21 can be disposed under the display panel 10. Figure 19

[0157] The first component 21 and / or the second component 22 can include an electronic element. For example, the first component 21 and / or the second component 22 can include an electronic element using light or sound. For example, the electronic element can be a sensor (such as an infrared sensor that emits and / or receives light in an infrared waveband, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure a distance, or a sensor that recognizes a fingerprint), a small light that outputs light, or a speaker that outputs sound. The electronic element using light can use light in various suitable wavebands such as visible light, infrared light, and ultraviolet light. In an embodiment, the first component area RA1 and / or the second component area RA2 can be understood as a transmissive area through which light and / or sound propagating from the electronic element toward the outside or from the outside toward the electronic element can pass.

[0158] In an embodiment, in a case in which the display device 1 is used as a smart watch or an instrument panel for a car, the first component 21 can be a member including a pointer of a clock or a pointer indicating predetermined information (e.g., a speed of a vehicle, etc.) or the like. In a case in which the display device 1 includes a clock or a pointer of an instrument panel for a car, the pointer can be exposed to the outside through the window 60 which can include an opening. In some examples, even in a case in which the first component 21 includes a speaker, the window 60 can include an opening.

[0159] As described above, the first component 21 and the second component 22 can include an element(s) related to a function of the display device 1 or an element including an accessory such as increasing the aesthetic of the display device 1. A layer including an optically transparent adhesive or the like can be positioned between the window 60 and the optical functional layer 50.

[0160] Figure 20 is a plan view of the display panel 10 according to an embodiment.

[0161] Referring to Figure 20 , the display panel 10 can include a first component area RA1, a second component area RA2, a display area DA, a middle area MA, and a peripheral area PA. Figure 20 ​It may be a diagram of a substrate 100 of the display panel 10. For example, it may be understood that the substrate 100 includes a first assembly area RA1, a second assembly area RA2, a display area DA, a middle area MA, and a peripheral area PA.

[0162] The display panel 10 includes a plurality of pixels P arranged in a display area DA. Each pixel P may include a display element such as an organic light-emitting diode. Each pixel P may emit, for example, red light, green light, blue light, or white light via the organic light-emitting diode. In this specification, as described above, it is understood that a pixel P is a pixel that emits one of red light, green light, blue light, and white light. A first component area RA1 and a second component area RA2 are arranged within the display area DA, and an intermediate area MA is positioned between the first component area RA1 and the second component area RA2 and the display area DA.

[0163] The middle area MA may surround the first assembly area RA1 and the second assembly area RA2. The peripheral area PA may surround the display area DA. The middle area MA and the peripheral area PA are non-display areas where display elements, such as light-emitting organic light-emitting diodes, are not arranged. Signal traces and / or power lines that provide signals to the pixels P may be arranged in the middle area MA and the peripheral area PA.

[0164] The first outer driving circuit 110 , the second outer driving circuit 120 , the terminal 140 , the data driving circuit 150 , the first power line 160 , and the second power line 170 may be arranged in the peripheral area PA.

[0165] The first external driver circuit 110 may include a scan and control driver circuit. The first external driver circuit 110 may provide scan signals and emission control signals to the pixels P via scan lines SL and emission control lines EL. The second external driver circuit 120 may be arranged in parallel with the first external driver circuit 110, with the display area DA located between the first and second external driver circuits 110. The second external driver circuit 120 may also include a scan and control driver circuit. In another embodiment, the second external driver circuit 120 may be omitted.

[0166] The terminal 140 can be disposed on one side of the peripheral area PA. The terminal 140 can not be covered by the insulating layer and be exposed, and thus electrically connected to the printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB can be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits a signal or power of the controller to the display panel 10. A control signal generated by the controller can be transmitted to the first outer driving circuit 110 and the second outer driving circuit 120 through the printed circuit board PCB. The controller can provide a first power ELVDD (also referred to as a first power voltage) and a second power ELVSS (also referred to as a second power voltage, see Figure 21 ) to the first power supply line 160 and the second power supply line 170 through the first connection line 161 and the second connection line 171, respectively. The first power ELVDD can be provided to each pixel P through a driving voltage line PL connected to the first power supply line 160, and the second power ELVSS can be provided to the pixel P connected to the second power supply line 170.

[0167] The data driving circuit 150 is electrically connected to the data line DL. A data signal of the data driving circuit 150 can be provided to each pixel P through a connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Although it is shown that the data driving circuit 150 is disposed on the printed circuit board PCB in Figure 20 , in another embodiment, the data driving circuit 150 can be disposed on the substrate 100. For example, the data driving circuit 150 can be disposed between the terminal 140 and the first power supply line 160.

[0168] The first power supply line 160 can include a first sub-line 162 and a second sub-line 163 extending in parallel to the x-direction and having the display area DA therebetween. The second power supply line 170 can have a ring shape having one open side and partially surrounding the display area DA.

[0169] Figure 21 is an equivalent circuit diagram of one of the pixels of the display panel according to an embodiment.

[0170] Referring to Figure 21 , each pixel P includes a pixel circuit PC and an organic light emitting diode OLED as a display element, the display element being connected to the pixel circuit PC. The pixel circuit PC can include a driving transistor T1, a switching transistor T2, and a storage capacitor Cst. Each pixel P can emit, for example, red light, green light, or blue light or emit red light, green light, blue light, or white light through the organic light emitting diode OLED. The driving transistor T1 and the switching transistor T2 can be thin film transistors.

[0171] The switching transistor T2 is connected to the scan line SL and the data line DL. The switching transistor T2 can transmit a data voltage input from the data line DL to the driving transistor T1 in response to a switching voltage input from the scan line SL. The storage capacitor Cst can be connected to the switching transistor T2 and the driving voltage line PL, and can store a voltage corresponding to a difference between a voltage transmitted from the switching transistor T2 and a first power voltage ELVDD supplied through the driving voltage line PL.

[0172] The driving transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to a voltage stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light having a luminance (e.g., a predetermined luminance) by utilizing the driving current. An opposite electrode (e.g., a cathode) of the organic light emitting diode OLED can receive a second power voltage ELVSS.

[0173] Although the pixel circuit PC is shown to include two transistors and one storage capacitor in Figure 21 , embodiments are not limited thereto. The number of transistors and / or the number of storage capacitors can be variously modified according to the design of the pixel circuit PC.

[0174] Figure 22 is a plan view of a first assembly area RA1, a second assembly area RA2, and their vicinity of a display panel according to an example embodiment.

[0175] Referring to Figure 22 , the first assembly area RA1 and the second assembly area RA2 can be surrounded by a display area DA. A plurality of pixels P is arranged in the display area DA.

[0176] In an embodiment, the transmittance of the first assembly area RA1 and the transmittance of the second assembly area RA2 can be different from each other. For example, the first assembly area RA1 can have a relatively high transmittance, and the second assembly area RA2 can have a relatively low transmittance. A pixel Pa can be arranged in the second assembly area RA2. Hereinafter, in order to be distinguished from the pixels P arranged in the display area DA, each pixel Pa arranged in the second assembly area RA2 is referred to as a second pixel Pa. The second pixel Pa can emit red light, green light, blue light, or white light. The second pixel Pa can be substantially the same as the pixels P in the display area DA. For example, in a case in which the pixels P in the display area DA have the same structure as that of the equivalent circuit diagram described with reference to Figure 21 , the second pixel Pa can have the same structure as that of the pixels P.

[0177] The scan lines SL and the data lines DL, through which the scan signals and the data signals are respectively transmitted to the pixel P and the second pixel Pa, can bypass along an edge of the first component area RA1 in the middle area MA. The scan lines SL and the data lines DL can pass through the second component area RA2.

[0178] The second component area RA2 can include a first sub-area RA2-S1 in which the second pixel Pa is disposed and a second sub-area RA2-S2 in which no pixel is disposed. In Figure 22 The three second pixels Pa disposed in the first sub-area RA2-S1 illustrated in FIG. 10 can respectively emit red light, green light, and blue light. Since the second sub-area RA2-S2 does not include the second pixel Pa, the second sub-area RA2-S2 can be a transmissive area through which light emitted from or propagating toward the second component disposed in the second component area RA2 can pass. Although the second sub-area RA2-S2 corresponds to a kind of transmissive area, a wiring such as the data line DL can pass through the second sub-area RA2-S2. Accordingly, the transmittance of the second sub-area RA2-S2 can be relatively smaller than the transmittance of the first component area RA1 through which the data line DL does not pass.

[0179] As described above, the first component area RA1 and the second component area RA2 can have different transmittances. In this regard, the cross-sectional structures of the first component area RA1 and the second component area RA2 are described.

[0180] First, the cross-sectional structure of the first component area RA1 is described.

[0181] Figure 23 is a cross-sectional view of the display panel 10 according to an embodiment, and can correspond to a cross-section taken along the line XXIIa-XXIIa’ and the line XXIIb-XXIIb’ of Figure 22 FIG. 10.

[0182] Referring to the display area DA of Figure 23 FIG. 10, the first pixel circuit PC1 is positioned on the substrate 100 and electrically connected to the first organic light emitting diode OLED1. The first pixel circuit PC1 and the first organic light emitting diode OLED1 can constitute the pixel P described with reference to Figure 22 FIG. 9. The first pixel circuit PC1 can have the same structure as that of the pixel circuit PC described with reference to Figure 21 FIG. 9. The cross-sectional structures of the driving transistor T1 and the first storage capacitor Cst1 included in the first pixel circuit PC1 can be the same as those of the first transistor TR1 and the first storage capacitor Cst1 described with reference to Figures 1-8 FIG. 9. In an embodiment, the cross-sectional structure of the display area DA can be substantially the same as that of the first area A1 described with reference to Figure 8 FIG. 9.

[0183] Referring to Figure 23 the first component area RA1 on the base 100, the insulating layer can include a hole corresponding to the first component area RA1. For example, the first insulating layer IL1 can include a first hole H1, and the second insulating layer IL2 can include a second hole H2. Also, the planarization layer 209 can include a third hole H3, and the pixel definition layer 211 can include a fourth hole H4. The first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 can be stacked on each other. The detailed structure of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 and the process of forming the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 can be the same as those described with reference to Figures 1-8 the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4. In an embodiment, the cross-sectional structure of the first component area RA1 can be substantially the same as that of the third area A3 described with reference to Figure 8 .

[0184] Although the cross-sectional structures of the display area DA and the first component area RA1 are substantially the same as those of the first area A1 and the third area A3 described with reference to Figure 23 , Figure 8 respectively, embodiments are not limited thereto. In another embodiment, the cross-sectional structures of the display area DA and the first component area RA1 of the display panel 10 can be substantially the same as those of the first area A1 and the third area A3 of the display panel 10C, 10E, or 10G described with reference to Figure 11 , Figure 13 or Figure 16 respectively. In a case where it is desired that the first component area RA1 has a relatively high transmittance, preferably, the cross-sectional structures of the display area DA and the first component area RA1 of the display panel 10 are the same as those of the first area A1 and the third area A3 of the display panel 10E described with reference to Figure 13 .

[0185] Figure 24 is a cross-sectional view of a display panel according to another embodiment, and corresponds to a modified embodiment of Figure 23 . Since the display area DA of Figure 24 is the same as that of Figure 23 , the first component area RA1 is mainly described below.

[0186] Referring to Figure 24 the first component area RA1, the sealing material 340 can be disposed between the base 100 and the encapsulation base 300A. The sealing material 340 can prevent or substantially prevent external moisture from advancing toward the display elements between the base 100 and the encapsulation base 300A. As Figure 24As shown in FIG, in which the sealing material 340 surrounds the periphery of the first assembly area RA1, the substrate 100 and / or the package substrate 300A may include holes 100H and 300AH, respectively, located in the first assembly area RA1. In this case, as with reference Figure 23 Compared to the described embodiment, the transmittance of the first assembly area RA1 may be improved (eg, increased) even more.

[0187] Although Figure 24 , the first hole H1 is defined in the first insulating layer IL1 including the buffer layer 201 and the gate insulating layer 203, and the second hole H2 is defined in the second insulating layer IL2 including the first interlayer insulating layer 205 and the second interlayer insulating layer 207, but the embodiment is not limited thereto. In another embodiment, as shown in FIG. Figure 13 As described, the first hole H1 positioned in the first assembly region RA1 may be defined in the first insulating layer IL1 ′ including the buffer layer 201 , the gate insulating layer 203 , and the first interlayer insulating layer 205 , and the second hole H2 may be defined in the second insulating layer IL2 ′ including the second interlayer insulating layer 207 .

[0188] Although Figure 23 and Figure 24 3. The case where the package member includes a package substrate 300A is shown, but the embodiment is not limited thereto. Figure 9 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 15 and Figure 17 As shown in FIG, the encapsulation member may include a thin film encapsulation layer 300B. The first assembly area RA1 of the display panel 10 may have the same Figure 9 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 15 and Figure 17 For example, in the case where the first component area RA1 is expected to have a relatively high transmittance, the first component area RA1 of the display panel 10 preferably has the same structure as the reference area A3 or a structure derived therefrom. Figure 10 and / or Figure 15 The structure of the third area A3 is the same as described above.

[0189] Next, the cross-sectional structure of the second assembly area RA2 is described.

[0190] Figure 25 is a cross-sectional view of a display panel according to an embodiment, and may correspond to a cross-sectional view taken along Figure 22 A cross section taken along line XXIIc-XXIIc' and line XXIIa-XXIIa'.

[0191] As Figure 23 mentioned in Figure 8 , the cross-sectional structure of the first component region RA1 can have substantially the same structure as that of the display panel 10A shown in Figure 11 or the first region A1 of the display panel 10C shown in Figure 25 .

[0192] Referring to the first sub-region RA2-S1 of the second component region RA2 of Figure 22 , a second pixel circuit PC2 is positioned on the substrate 100 and electrically connected to the second organic light emitting diode OLED2. The second pixel circuit PC2 and the second organic light emitting diode OLED2 can constitute the second pixel Pa described with reference to Figure 11 . The second pixel circuit PC2 can have the same structure as that of the first pixel circuit PC1. The cross-sectional structures of the driving transistor T1a and the second storage capacitor Cst2 included in the second pixel circuit PC2 can be the same as those of the second transistor TR2 and the second storage capacitor Cst2 shown in Figure 11 , respectively. In an embodiment, the cross-sectional structure of the first sub-region RA2-S1 can be substantially the same as that of the second region A2 described with reference to Figure 21 . A metal layer ML is arranged under the second pixel circuit PC2. The metal layer ML can prevent or substantially prevent the second pixel circuit PC2 from being damaged due to light emitted from the second component 22 or prevent or substantially prevent the performance of the second pixel circuit PC2 from being deteriorated due to light emitted from the second component 22. In an embodiment, the metal layer ML can have the same voltage level as that of the driving voltage line PL (see Figure 25 ). In another embodiment, the metal layer ML can have the same voltage level as that of the gate electrode of the thin film transistor T1a.

[0193] Referring to the second sub-region RA2-S2 of the second component region RA2 of Figures 1-8 , the insulating layer on the substrate 100 can include a hole corresponding to the second component region RA2.

[0194] For example, the first insulating layer IL1 can include a first hole H1, and the second insulating layer IL2 can include a second hole H2. In addition, the planarization layer 209 can include a third hole H3, and the pixel definition layer 211 can include a fourth hole H4. The first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 can be stacked on each other. The specific structures of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 and the processes of forming the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 can be the same as those described with reference to Figure 11Those of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 described are the same. In an embodiment, the cross-sectional structure of the second sub-region RA2-S2 can be the same as that of the second sub-region RA2-S2 described with reference to FIG. 2B. Figure 25 The cross-sectional structure of the third region A3 described is substantially the same. At least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 250 can be formed in the first hole H1 of the second sub-region RA2-S2.

[0195] Although the cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second assembly region RA2 are described in Figure 11 , respectively, the embodiments are not limited thereto. In another embodiment, the cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second assembly region RA2 can be the same as those of the first sub-region RA2-S1 and the second sub-region RA2-S2 described with reference to Figure 16 , respectively. The cross-sectional structures of the second region A2 and the third region A3 described are substantially the same, but the embodiments are not limited thereto. In another embodiment, the cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second assembly region RA2 can be the same as those of the first sub-region RA2-S1 and the second sub-region RA2-S2 described with reference to Figure 25 The cross-sectional structures of the second region A2 and the third region A3 of the display panel 10G described are substantially the same.

[0196] Although the cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second assembly region RA2 are described in Figure 9 , respectively, the embodiments are not limited thereto. In another embodiment, the encapsulation member can include the thin film encapsulation layer 300B described with reference to Figure 9 , respectively. The cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second assembly region RA2 of the display panel 10 can have the same structures as those of the first sub-region RA2-S1 and the second sub-region RA2-S2 described with reference to Figure 10 , Figure 12 , Figure 14 , Figure 15 , Figure 17 or Figure 9 The structures of the second region A2 and the third region A3 described are the same structures or structures derived therefrom. For example, in a case in which the second assembly 22 does not require high transmittance like an infrared sensor, the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second assembly region RA2 of the display panel 10 can have the same structures as those of the first sub-region RA2-S1 and the second sub-region RA2-S2 described with reference to Figure 12 , Figure 14 , Figure 17 or ​ The structures of the second region A2 and the third region A3 described are the same structures or structures derived therefrom. For example, in a case in which the second assembly 22 does not require high transmittance like an infrared sensor, the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second assembly region RA2 of the display panel 10 can have the same structures as those of the first sub-region RA2-S1 and the second sub-region RA2-S2 described with reference to

[0197] The embodiments can provide a display panel and a display device that can provide various functions while simplifying a process.

[0198] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element, a first component, a first region, a first layer or a first section discussed herein could be named a second element, a second component, a second region, a second layer or a second section without departing from the spirit and scope of the inventive concept.

[0199] For ease of description, spatially relative terms, such as“under,”“below,”“lower,”“on,”“above,”“upper,” and the like, can be used herein for describing an element’s or feature’s relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as“below” or“under” other elements or features would then be oriented“above” the other elements or features. Thus, the example term“below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being“between” two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0200] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises” and / or“comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items.

[0201] For purposes of the present disclosure, “at least one of X, Y, and Z” and“at least one of X, Y, and Z selected from a group consisting of X, Y, and Z” can be interpreted to include one or more (e.g., one, two, three, four, or five or more) of X, Y, and Z, or any combination of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ.

[0202] Furthermore, the use of “may” when describing embodiments of the inventive concept refers to “one or more embodiments of the inventive concept.” Furthermore, the term “exemplary” is intended to indicate an example or illustration.

[0203] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, the element or layer can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or one or more intervening elements or layers may be present. When an element or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.

[0204] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations of measurements or calculations that would be recognized by one of ordinary skill in the art. Moreover, particular amounts or ranges recited in this written description or claims may also include the inherent deviations of measurements or calculations that would be recognized by one of ordinary skill in the art.

[0205] As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilize" and variations thereof, respectively.

[0206] The display panel and / or any other related apparatus or components according to embodiments of the present application described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or suitable combination of software, firmware, and hardware. For example, various components of the display panel can be formed on one integrated circuit (IC) chip or on separate IC chips. Further, various components of the display panel can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on the same substrate. Further, various components of the display panel can be various components of a process or thread running on one or more processors in one or more computing devices that execute computer program instructions to perform various functions described herein and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer readable media such as, for example, CD-ROM, flash drive, etc. Further, those skilled in the art should appreciate that functions of various computing devices can be combined or integrated into a single computing device, or functions of a particular computing device can be distributed across one or more other computing devices, without departing from the scope of exemplary embodiments of the present application.

[0207] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the attached drawings, it will be evident for those skilled in the art that various modifications in form and details can be made without departing from the spirit and scope of the claims and their equivalents.

Claims

1. A display device comprising: a substrate including a display region in which a plurality of first pixels are arranged, a first component region through which first light different from light emitted from the plurality of first pixels passes, and a second component region in which a plurality of second pixels are arranged, wherein the second component region includes a transmissive region through which second light different from light emitted from the plurality of first pixels and the plurality of second pixels passes; a first light-emitting diode corresponding to one of the plurality of first pixels and provided in the display region; a second light-emitting diode corresponding to one of the plurality of second pixels and provided in the second component region; and a plurality of insulating layers between the substrate and the second light-emitting diode, wherein the first component region and the second component region have different sizes or different shapes in a plan view.

2. The display device according to claim 1, wherein a transmittance of the first component region is different from a transmittance of the transmissive region of the second component region.

3. The display device according to claim 1, wherein at least one of the plurality of insulating layers has an opening corresponding to the transmissive region.

4. The display device according to claim 3, further comprising a transistor provided in the second component region and electrically connected to the second light-emitting diode, the at least one of the plurality of insulating layers includes a gate insulating layer interposed between a semiconductor layer of the transistor and a gate electrode of the transistor, and the gate insulating layer has a first opening corresponding to the transmissive region.

5. The display device of claim 4, wherein, the at least one of the plurality of insulating layers further includes a first interlayer insulating layer provided on an upper surface of the gate insulating layer such that the gate electrode is located between the gate insulating layer and the first interlayer insulating layer, and the first interlayer insulating layer has a second opening corresponding to the transmissive region.

6. The display device according to claim 4, wherein the at least one of the plurality of insulating layers further includes a lower insulating layer provided on a bottom surface of the gate insulating layer such that the semiconductor layer is located between the lower insulating layer and the gate insulating layer, and the lower insulating layer has a third opening corresponding to the transmissive region.

7. The display device according to claim 1, further comprising: a transistor provided in the second component region and electrically connected to the second light-emitting diode, the transistor including a semiconductor layer and a gate electrode; and a metal layer interposed between the substrate and the semiconductor layer in the second component region, wherein the semiconductor layer is stacked with the metal layer.

8. The display device according to claim 7, further comprising a wiring electrically connected to the metal layer, wherein the wiring has a constant voltage level.

9. The display device according to claim 1, further comprising a data line including: a first portion provided in the display region in a direction; and and a curved portion disposed in an intermediate region between the first component region and the display region, and bypassing the first component region along an edge of the first component region. 10.The display apparatus of claim 1, further comprising a data line passing through the second component region. 11.The display apparatus of claim 1, further comprising: a first component on a bottom surface of the base and corresponding to the first component region; and a second component on the bottom surface of the base and corresponding to the second component region, the first component including a camera and the second component including an infrared sensor. 12.A display panel, comprising: a base including a display region in which a plurality of first pixels are arranged, and a first region and a second region surrounded by the display region, wherein the second region includes a first sub-region in which a plurality of second pixels are arranged, and a second sub-region which is a transmissive region through which light different from light emitted from the plurality of first pixels and the plurality of second pixels passes; a first light emitting diode corresponding to one of the plurality of first pixels and disposed in the display region; a second light emitting diode corresponding to one of the plurality of second pixels and disposed in the first sub-region of the second region; a transistor disposed in the first sub-region of the second region and electrically connected to the second light emitting diode, wherein the transistor includes a semiconductor layer and a gate electrode; wherein the first region and the second region have different sizes or different shapes in a plan view. the semiconductor layer is stacked with the metal layer.

13. The display panel of claim 12, further comprising a metal layer disposed between the substrate and the semiconductor layer in the first sub-region of the second region, wherein, the metal layer has a constant voltage level.

14. The display panel of claim 13, wherein, 15.The display panel of claim 13, further comprising a wiring having a constant voltage level and electrically connected to the metal layer. the plurality of insulating layers include an inorganic insulating layer having an opening corresponding to the transmissive region.

16. The display panel of claim 12, further comprising a plurality of insulating layers between the substrate and the second light emitting diode, wherein, 17.A display panel, comprising: a base including a display region in which a plurality of first pixels are arranged, a first region surrounded by the display region, and a second region including a first sub-region in which a plurality of second pixels are arranged, and a second sub-region which is a transmissive region through which light different from light emitted from the plurality of first pixels and the plurality of second pixels passes; a first light emitting diode corresponding to one of the plurality of first pixels and disposed in the display region; a second light emitting diode corresponding to one of the plurality of second pixels and disposed in the first sub-region of the second region; and a plurality of insulating layers between the base and the second light emitting diode, wherein at least one of the plurality of insulating layers has an opening corresponding to the transmissive region, ​ In a plan view, the first region and the second region have different sizes or different shapes. 18.The display panel of claim 17, further comprising a transistor disposed in the first sub-region of the second region and electrically connected to the second light emitting diode, wherein, The transistor includes a semiconductor layer and a gate electrode.

19. The display panel of claim 18, further comprising a metal layer disposed between the substrate and the semiconductor layer in the first sub-region of the second region, wherein, The semiconductor layer is stacked with the metal layer, and wherein the metal layer has a constant voltage level.

20. The display panel of claim 18, wherein, The plurality of insulating layers includes: a gate insulating layer disposed between the semiconductor layer of the transistor and the gate electrode of the transistor; a first interlayer insulating layer disposed on an upper surface of the gate insulating layer; and a lower insulating layer disposed on a bottom surface of the gate insulating layer, wherein at least one selected from the gate insulating layer, the first interlayer insulating layer, and the lower insulating layer has the opening.

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