Miniature LED display and manufacturing method

Abstract

A micro light emitting diode (LED) display, an LED display, and a method for manufacturing an LED pixel pair are provided. A micro light emitting diode (LED) display includes a first pixel, a second pixel, and an opaque conductive element. The first pixel includes a first LED, a third LED, and a first common interconnect electrically connected to each of the first LED and the third LED. The second pixel includes a second LED, a fourth LED, and a second common interconnect electrically connected to each of the second LED and the fourth LED. The opaque conductive element is electrically connected with each of the first common interconnect and the second common interconnect.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of light emitting diodes (LEDs) and, in particular, to a micro light emitting diode (LED) display, an LED display, and a method for manufacturing a pair of LED pixels. BACKGROUND

[0002] Conventional micro light emitting diode (LED) display panels include an array of pixels covered by a transparent or semi-transparent conductive layer that acts as a common electrode for each pixel. Due to the sheet resistivity of this layer, the layer has a non-uniform voltage across the array of pixels, which reduces brightness uniformity and color accuracy. SUMMARY

[0003] Embodiments disclosed herein address the problems with conventional micro LED displays described above.

[0004] In a first aspect, a micro light emitting diode (LED) display is disclosed. The display includes a first pixel, a second pixel, and an opaque conductive element. The first pixel includes a first LED, a third LED, and a first common interconnect electrically connected to each of the first LED and the third LED. The second pixel includes a second LED, a fourth LED, and a second common interconnect electrically connected to each of the second LED and the fourth LED. The opaque conductive element is electrically connected to each of the first common interconnect and the second common interconnect.

[0005] In some embodiments, the LED display further includes a non-conductive transparent layer covering each of the first pixel and the second pixel.

[0006] In some embodiments, the LED display further includes a conductive transparent layer covering each of the first pixel and the second pixel, and the conductive transparent layer is electrically isolated from each of the first common interconnect and the second common interconnect.

[0007] In some embodiments, the opaque conductive element is a ground plane or a common voltage plane.

[0008] In some embodiments, the first pixel further includes a first drive circuit electrically connected to the first LED, the second pixel further includes a second drive circuit electrically connected to the second LED, and the LED display further includes a front plane layer including the first LED, the second LED, a first segment of the first common interconnect, and a first segment of the second common interconnect, and a back plane layer bonded to the front plane layer and including the first drive circuit and the second drive circuit, a bottom segment of the first common interconnect, and a bottom segment of the second common interconnect.

[0009] In some embodiments, the first pixel further includes a third driving circuit electrically connected with the third LED, the second pixel further includes a fourth driving circuit electrically connected with the fourth LED, the LED display further includes: a second front plane layer including the third LED, the fourth LED, a second segment of the first common interconnect, and a second segment of the second common interconnect; and the back plane layer further includes the third driving circuit and the fourth driving circuit, wherein the first front plane layer is located between the second front plane layer and the back plane layer.

[0010] In some embodiments, the first segment of the first common interconnect includes a first vertical subsection extending through the first front plane layer and a first lateral section extending from the first vertical subsection to the first LED; the second segment of the first common interconnect includes a third vertical subsection extending through the second front plane layer and a third lateral section extending from the third vertical subsection to the third LED; the first segment of the second common interconnect includes a second vertical subsection extending through the first front plane layer and a second lateral section extending from the second vertical subsection to the second LED; and the second segment of the second common interconnect includes a fourth vertical subsection extending through the second front plane layer and a fourth lateral section extending from the fourth vertical subsection to the fourth LED.

[0011] In some embodiments, the first pixel further includes a fifth LED electrically connected with the first common interconnect, the second pixel further includes a sixth LED electrically connected with the second common interconnect, the LED display further includes: a third front plane layer including the fifth LED, the sixth LED, a third segment of the first common interconnect, and a third segment of the second common interconnect, wherein the second front plane layer is located between the third front plane layer and the first front plane layer.

[0012] In some embodiments, the first segment of the first common interconnect includes a first vertical subsection extending through the first front planar layer and a first lateral section extending from the first vertical subsection to the first LED; the second segment of the first common interconnect includes a third vertical subsection extending through the second front planar layer and a third lateral section extending from the third vertical subsection to the third LED; the third segment of the first common interconnect includes a fifth vertical subsection extending through the third front planar layer and a fifth lateral section extending from the fifth vertical subsection to the fifth LED; the first segment of the second common interconnect includes a second vertical subsection extending through the first front planar layer and a second lateral section extending from the second vertical subsection to the second LED; the second segment of the second common interconnect includes a fourth vertical subsection extending through the second front planar layer and a fourth lateral section extending from the fourth vertical subsection to the fourth LED; and the third segment of the second common interconnect includes a sixth vertical subsection extending through the third front planar layer and a sixth lateral section extending from the sixth vertical subsection to the sixth LED.

[0013] In a second aspect, an LED display is disclosed. The LED display includes: a plurality of pixel pairs, each pixel pair of the plurality of pixel pairs including the first pixel and the second pixel described above, such that the plurality of pixel pairs includes a plurality of first common interconnects and a plurality of second common interconnects; wherein each of the plurality of first common interconnects is electrically isolated from (i) each other first common interconnect of the plurality of first common interconnects and (ii) each second common interconnect of the plurality of second common interconnects.

[0014] In a third aspect, a method for fabricating an LED pixel pair is disclosed. The method includes hybrid bonding a first front planar layer to a back planar layer. The first front planar layer includes (i) a first dielectric layer, (ii) a first LED and a second LED embedded in the first dielectric layer, (iii) a first common interconnect segment and a second common interconnect segment each spanning a thickness of the first dielectric layer. The method further includes hybrid bonding a second front planar layer to a first spacer dielectric layer located on the first front planar layer. The second front planar layer includes (i) a second dielectric layer, (ii) a third LED and a fourth LED embedded in the second dielectric layer, and (iii) a third common interconnect segment and a fourth common interconnect segment each spanning a thickness of the second dielectric layer.

[0015] In some embodiments, hybrid bonding the first front planar layer to the back planar layer includes: electrically connecting the lower first vertical subsection to a first back planar interconnect segment of the back planar layer; and electrically connecting the lower second vertical subsection to a second back planar interconnect segment of the back planar layer, wherein the second back planar interconnect segment is electrically isolated from the lower first vertical subsection.

[0016] In some embodiments, hybrid bonding the first front plane layer to the back plane layer further comprises: electrically connecting the first LED to a first driver circuit of the back plane layer; and electrically connecting the second LED to a second driver circuit of the back plane layer.

[0017] In some embodiments, hybrid bonding the second front plane layer to the first spacer dielectric layer includes: electrically connecting the third vertical subsegment to the lower first vertical subsegment; and electrically connecting the fourth vertical subsegment to the lower second vertical subsegment.

[0018] In some embodiments, the first, second, third and fourth LEDs are electrically connected to the first, second, third and fourth driving circuits of the back plane layer via corresponding first, second, third and fourth pixel driver interconnects (PDIs), respectively, and the method also includes forming the first front plane layer by the following steps: forming the first LED and the second LED on a first substrate; depositing the first dielectric layer on the first substrate; and forming a lower first vertical sub-segment, a lower second vertical sub-segment and corresponding segments of the first PDI, the second PDI, the third PDI and the fourth PDI in the first dielectric layer, each spanning the thickness of the first dielectric layer.

[0019] In some embodiments, after hybrid bonding the first front plane layer to the back plane layer, the method further includes: removing the first substrate to expose the surface of the first dielectric layer; and (i) electrically connecting the lower first vertical sub-segment to the first LED and (ii) electrically connecting the lower second vertical sub-segment to the second LED by depositing corresponding conductive elements on the surface.

[0020] In some embodiments, the method further includes: depositing the first spacer dielectric layer on the first dielectric layer; forming an upper first vertical sub-segment electrically connected to the lower first vertical sub-segment, an upper second vertical sub-segment electrically connected to the lower second vertical sub-segment, and corresponding segments of the third PDI and the fourth PDI, each of which spans the thickness of the first spacer dielectric layer, in the first spacer dielectric layer.

[0021] In some embodiments, the third and fourth LEDs are electrically connected to third and fourth drive circuits of the backplane layer via respective third and fourth pixel drive interconnects (PDIs), and the method further comprises forming the second frontplane layer by: forming the third and fourth LEDs on a second substrate; depositing the second dielectric layer on the second substrate; and forming in the second dielectric layer a lower third vertical subsection, a lower fourth vertical subsection, and respective segments of the third and fourth PDIs each spanning a thickness of the second dielectric layer.

[0022] In some embodiments, after hybrid bonding the second frontplane layer to the first spacer dielectric layer, the method further comprises: removing the second substrate to expose a surface of the second dielectric layer; and electrically connecting (i) the lower third vertical subsection to the third LED and (ii) the lower fourth vertical subsection to the fourth LED by depositing respective conductive elements on the surface.

[0023] In some embodiments, the method further comprises: hybrid bonding a third frontplane layer to a second spacer dielectric layer located on the second frontplane layer, wherein the third frontplane layer comprises (i) a third dielectric layer, (ii) fifth and sixth LEDs embedded in the third dielectric layer, and (iii) fifth and sixth vertical subsections each spanning a thickness of the third dielectric layer; wherein hybrid bonding the third frontplane layer comprises: electrically connecting the fifth vertical subsection to the lower third vertical subsection; and electrically connecting the sixth vertical subsection to the lower fourth vertical subsection.

[0024] In some embodiments, the fifth and sixth LEDs are electrically connected to fifth and sixth drive circuits of the backplane layer via respective fifth and sixth pixel drive interconnects (PDIs), wherein forming the second frontplane layer further comprises: forming in the second dielectric layer a lower fifth vertical subsection and a lower sixth vertical subsection, and respective segments of the fifth and sixth PDIs each spanning a thickness of the second dielectric layer.

[0025] In some embodiments, the method further comprises: depositing the second spacer dielectric layer on the second dielectric layer; forming in the second spacer dielectric layer an upper third vertical subsection electrically connected to the lower third vertical subsection, an upper fourth vertical subsection electrically connected to the lower fourth vertical subsection, and respective segments of the fifth and sixth PDIs each spanning a thickness of the second spacer dielectric layer.

[0026] In some embodiments, the fifth and sixth LEDs are electrically connected to fifth and sixth drive circuits of the backplane layer via respective fifth and sixth pixel drive interconnects (PDIs), and the method further comprises forming the third frontplane layer by: forming the fifth and sixth LEDs on a third substrate; depositing the third dielectric layer on the third substrate; and forming the fifth vertical subsection, the sixth vertical subsection, and respective segments of the fifth and sixth PDIs each spanning a thickness of the third dielectric layer in the third dielectric layer.

[0027] In some embodiments, after hybrid bonding the third frontplane layer to the second spacer dielectric layer, the method further comprises: removing the third substrate to expose a surface of the third dielectric layer; and electrically connecting (i) the fifth vertical subsection to the fifth LED and (ii) the sixth vertical subsection to the sixth LED by depositing respective electrically conductive elements on the surface. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic diagram of a light-emitting diode (LED) display comprising an array of pixels.

[0029] Figures 2 to 4 are respective schematic diagrams of a pixel in an embodiment, wherein the pixel is Figure 1 is an example of a pixel of the array of LEDs.

[0030] Figure 5A and Figure 5B are respective schematic diagrams of a pixel in an embodiment, wherein the pixel is Figure 1 is an example of a pixel of the array of LEDs.

[0031] Figure 6 illustrates a pixel of Figure 5A and Figure 5B in an embodiment surrounded by an opaque isolation wall.

[0032] Figure 7 is a connection diagram of a micro-LED display, wherein the micro-LED display is Figure 1 an embodiment of the LED display of

[0033] Figures 8 to 21 illustrates respective intermediate structures formed in an embodiment of a method for manufacturing Figure 7 the micro-LED display of

[0034] Figure 22 is a flowchart illustrating a method for manufacturing Figure 7 the micro-LED display of

[0035] Figure 23 is a flowchart of steps that can be included in an embodiment of the method of Figure 22 DETAILED DESCRIPTION

[0036] The drawings herein depict orthogonal axes Al, A2, and A3. Unless otherwise noted, the height and depth of an object herein refer to the extent of the object along axis A3. Also, herein, the horizontal plane is parallel to the Al-A2 plane, the width refers to the extent of the object along axis Al or axis A2, and the vertical direction is along axis A3.

[0037] Figure 1 is a schematic diagram of a light-emitting diode (LED) display 190 that includes an array of pixels 100. Each pixel 100 includes an LED 114, an LED 124, and an LED 134, each of which can be a micro-LED. The pixel 100 also includes a common interconnect 160 that is electrically connected with each of the LEDs 114, 124, and 134. For example, the common interconnect 160 can be electrically connected with respective anodes of the LEDs 114, 124, and 134 or with respective cathodes of the LEDs 114, 124, and 134.

[0038] Figures 2 to 4 is a respective schematic diagram of a pixel 200, where the pixel 200 is an example of the pixel 100. Each pixel 200 includes an LED 214, an LED 224, an LED 234, and a common interconnect 260, which are respective examples of the LEDs 114, 124, 134, and the common interconnect 160. The LEDs 214, 224, and 234 can be coplanar in a horizontal plane. Figure 3 is a plan view of the pixel 200. Figure 4 illustrates the pixel 200 surrounded by an opaque barrier 402 to prevent optical cross-talk between the pixel 200 and an adjacent pixel 200, such as between pixels 200 of the array of LEDs 100A. The LEDs 214, 224, and 234 can have different cross-sectional areas in the horizontal plane. In Figure 2 In an example of the pixel 200, the cross-sectional area of the LED 224 is greater than the cross-sectional area of the LED 234 and less than the cross-sectional area of the LED 214.

[0039] Figure 5A 、 Figure 5B and Figure 6 ​is a corresponding schematic diagram of pixel 500, where pixel 500 is an example of pixel 100. Each pixel 500 includes LED 514, LED 524, LED 534, and common interconnect 560, which are corresponding examples of LED 114, LED 124, LED 134, and common interconnect 160. In an embodiment, any two of LEDs 514, LED 524, and LED 534 in the same pixel 500 are not coplanar in a horizontal plane. Figure 6 The pixel 500 is shown surrounded by opaque isolation walls 602 to prevent optical crosstalk between the pixel 500 and an adjacent pixel 500 (eg, a pixel 500 and an adjacent pixel 500 of the LED array 100A).

[0040] Common interconnect 560 includes sections 561, 562, and 563, which respectively include transverse sections 553, 556, and 559. Portions of transverse sections 553, 556, and 559 can be in physical and / or electrical contact with LEDs 214, 224, and 234, respectively.

[0041] Figure 5B 1 represents axis A4, which is in a horizontal plane defined by axes A1 and A2, such that axis A4 is perpendicular to axis A3. A cross-sectional view of pixel 500 in a plane parallel to the A1-A3 plane includes the full length of transverse segment 559 along axis A1. A cross-sectional view of pixel 500 in a plane parallel to the A2-A3 plane includes the full length of transverse segment 556 along axis A2. A cross-sectional view of pixel 500 in a plane parallel to the A4-A3 plane includes the full length of transverse segment 553 along axis A4.

[0042] Figure 7 is a connection diagram of micro-LED display 700. Micro-LED display 700 includes pixels 702(1) and 702(2). In this document, elements indicated by reference numerals suffixed with numbers in parentheses are examples of the elements indicated by the reference numerals. For example, pixel 702(1) is an example (1) of pixel 702. A specific instance of an item can be referred to by using a number in parentheses (e.g., pixel 702(1)), while a number without parentheses refers to at least one of the enumerated items (e.g., one pixel 702 or a plurality of pixels 702).

[0043] Furthermore, in this document, unless otherwise indicated, elements having a (1) suffix are part of pixel 702(1), and elements having a (2) suffix are part of pixel 702(2). For example, pixel 702 includes LED 714 and LED 724, which means that pixel 702(1) includes LED 714(1) and LED 724(1), and pixel 702(2) includes LED 714(2) and LED 724(2).

[0044] Pixel 702 also includes LED 724 and common interconnect 760. Each common interconnect 760 is electrically connected with both a respective LED 714 and a respective LED 724. Pixel 702 can also include LED 734, in which case each common interconnect 760 is electrically connected with a respective LED 734.

[0045] Pixel 500, LED 214, LED 224, and LED 234 are respective examples of pixel 702, LED 714, LED 724, and LED 734. When pixel 702 is an instance of pixel 500, Figure 7 A true cross-section of micro-LED display 700 is not illustrated. Rather, Figure 7 The connections of the intra- and inter-layer components of micro-LED display 700 are shown.

[0046] Pixel 702(1) can include a first opaque isolation wall 602 that surrounds pixel 702(1) but not pixel 702(2). Pixel 702(2) can include a second opaque isolation wall 602 that surrounds pixel 702(2) but not pixel 702(1). The first and second opaque isolation walls can share a common side that is between pixel 702(1) and 702(2).

[0047] Micro-LED display 700 also includes electrically conductive element 744 that is electrically connected with each common interconnect 760. In micro-LED display 700, electrically conductive element 744 can be opaque and can act as a ground plane or a common voltage plane that is held at a common positive or negative voltage. LED 714 and LED 724 are examples of LED 114 and LED 124, respectively. Each common interconnect 760 is an example of common interconnect 160.

[0048] Micro-LED display 700 can include a transparent layer 770 that covers each pixel 702. Transparent layer 770 can be an electrically conductive transparent layer or an electrically non-conductive transparent layer. When transparent layer 770 is electrically conductive, it is electrically isolated from each common interconnect 760.

[0049] In an embodiment, the pixel 702 includes at least one of a drive circuit 741 electrically connected to the LED 714, a drive circuit 742 electrically connected to the LED 724, and a drive circuit 743 electrically connected to the LED 734. The micro-LED display 700 can include (i) a pixel drive interconnect (PDI) 771 electrically connecting the LED 714 to the drive circuit 741, (ii) a PDI 772 electrically connecting the LED 724 to the drive circuit 742, and (iii) a PDI 773 electrically connecting the LED 734 to the drive circuit 743.

[0050] The drive circuit 741 and the common interconnect 760 can be electrically connected to (a) an anode and a cathode of the LED 714 or (b) a first cathode and an anode of the LED 714, respectively. The drive circuit 742 and the common interconnect 760 can be electrically connected to (a) an anode and a cathode of the LED 724 or (b) a first cathode and an anode of the LED 724, respectively. The drive circuit 743 and the common interconnect 760 can be electrically connected to (a) an anode and a cathode of the LED 734 or (b) a first cathode and an anode of the LED 734, respectively.

[0051] The micro-LED display 700 can include a front plane layer 710 and a back plane layer 740. The front plane layer 710 includes the LED 714 and a segment 761 of the common interconnect 760. The back plane layer 740 is bonded to the front plane layer 710 and includes the drive circuit 741, a bottom segment 751 of the common interconnect 760, and a bottom segment 751 of the common interconnect 760. The back plane layer 740 can be bonded to a planar surface 711 of the front plane layer 710. The micro-LED display 700 can include a back plane substrate 709 that supports the back plane layer 740.

[0052] In an embodiment, the micro-LED display 700 includes a front plane layer 720 that includes the LED 724 and a second segment 762 of the common interconnect 760. In such an embodiment, the back plane layer 740 includes the drive circuit 743. The front plane layer 710 is between the front plane layer 720 and the back plane layer 740. The micro-LED display 700 can also include a front plane layer 730 that includes the LED 734 and a third segment 763 of the common interconnect 760. The front plane layer 720 is between the front plane layer 710 and the front plane layer 730.

[0053] The front plane layers 710, 720, and 730 include respective dielectric layers 718, 728, and 738. The back plane layer 740 includes a dielectric layer 748. Any two of the dielectric layers 718, 728, 738, and 748 can have the same material composition or different material compositions. Herein, when a component of the micro-LED display 700 is said to be part of the front plane layer 710, 720, or 730, the component can be partially or completely embedded in the dielectric layer of that front plane layer. For example: each LED 714 and each segment 761 can be at least partially embedded in the dielectric layer 718; each LED 724 and each segment 762 can be at least partially embedded in the dielectric layer 728; and each LED 734 and each segment 763 can be at least partially embedded in the dielectric layer 738. Similarly, each bottom segment 751 and each of the drive circuits 741-743 can be at least partially embedded in the dielectric layer 748. In Figure 7 In the example of FIG. 7, the conductive element 744 is embedded in the back plane layer 740. Without departing from the scope of the embodiments presented herein, the conductive element 744 can be embedded in any of the front plane layers 718, 728, or 738.

[0054] Embodiments of the micro-LED display 700 include (i) a conductive lateral segment 753 extending between and electrically connecting the common interconnect 760 and the LEDs 714, and (ii) a conductive lateral segment 756 extending between and electrically connecting the common interconnect 760 and the LEDs 724. The following description applies to such embodiments. The segment 761 of the common interconnect 760 includes a first vertical sub-segment extending through the front plane layer 710 and the lateral segment 753 extending from the first vertical sub-segment to the LEDs 714. The first vertical sub-segment includes the vertical sub-segments 752 and 754. The segment 762 of the common interconnect 760 includes a second vertical sub-segment extending through the front plane layer 720 and the lateral segment 756 extending from the third vertical sub-segment to the LEDs 724. The second vertical sub-segment includes the vertical sub-segments 755 and 757. When the micro-LED display 700 includes the LEDs 734, the segment 763 of the common interconnect 760 includes a vertical sub-segment 758 extending through the front plane layer 730 and a lateral segment 759 extending from the vertical sub-segment 758 to the LEDs 734. The lateral segment 759 electrically connects the LEDs 734 to the common interconnect 760.

[0055] In an embodiment, the display 190 includes a plurality of pixel pairs. Each pixel pair of the plurality of pixel pairs includes one pixel 702(1) and one pixel 702(2) such that the plurality of pixel pairs includes a plurality of common interconnects 760(1) and a plurality of common interconnects 760(2). In an embodiment, each of the plurality of common interconnects 760(1) is electrically isolated from (i) each other common interconnect 760(1) of the plurality of common interconnects 760(1) and (ii) each second common interconnect 760(2) of the plurality of common interconnects 760(2). In other embodiments, each common interconnect 760 is electrically connected with the conductive element 744.

[0056] Figures 8 to 21 Portions of results of manufacturing steps of a method for manufacturing the micro-LED display 700 are depicted. Figure 22 is a flowchart illustrating a method 2200 that is an example of such a method.

[0057] Figure 8 A backplane layer 740 on the backplane substrate 709 is shown. Figure 9 An intermediate structure 900 is illustrated that includes the LEDs 714 on the substrate 909. Figure 10 An intermediate structure 1000 is depicted that includes a frontplane layer 1010 on the intermediate structure 900. The frontplane layer 1010 includes a dielectric layer 1018 and the lower first vertical subsections 752 each spanning a thickness 1013 of the dielectric layer 1018. The frontplane layer 1010 also includes the PDI sections 1014, 1024, and 1034 that are partially embedded in the dielectric layer 1018. The PDI sections 1014, 1024, and 1034 are respective sections of the PDI 771, the PDI 772, and the PDI 773. The dielectric layer 1018 has a surface 1019 proximate to the substrate 909 and a surface 1011 opposite the surface 1019.

[0058] Figure 11 An intermediate structure 1100 is depicted that is the intermediate structure 1000 on the backplane layer 740. Figure 12 An intermediate structure 1200 is depicted that is the intermediate structure 1100 after removal of the substrate 909. Figure 12 A conductive lateral section 753 on the intermediate structure 1200 is illustrated as an embodiment of a method for manufacturing the micro-LED display 700 that includes depositing the section 753 on the surface 1019. Figure 13 An intermediate structure 1300 is depicted that is the intermediate structure 1200 with a spacer layer 1310 added on the dielectric layer 1018 to produce the frontplane layer 710.

[0059] Figure 14 An intermediate structure 1400 is depicted that includes the LEDs 724 on a substrate 1409.Figure 15 An intermediate structure 1500 is depicted that includes a front planar layer 1520 on the intermediate structure 1400. The front planar layer 1520 includes a dielectric layer 1528 and vertical subsections 755 each spanning a thickness 1523 of the dielectric layer 1528. The front planar layer 1520 also includes PDI segments 1524, each PDI segment 1524 being a segment of a respective PDI 772. The LEDs 724 are embedded in the dielectric layer 1528. In embodiments, the front planar layer 1520 is part of the front planar layer 720. The dielectric layer 1528 has a surface 1529 proximate to the substrate 1409 and a surface 1521 opposite the surface 1529.

[0060] Figure 16 An intermediate structure 1600 is depicted that is the intermediate structure 1300 with the intermediate structure 1500 on the intermediate structure 1300. Figure 17 An intermediate structure 1700 is depicted that is the intermediate structure 1600 with the substrate 1409 removed. Figure 17 Conductive lateral segments 756 on the intermediate structure 1700 are illustrated as an embodiment of a method for fabricating the micro-LED display 700 that includes depositing the segments 756 on the surface 1529.

[0061] Figure 18 An intermediate structure 1800 is depicted that is the intermediate structure 1700 with a spacer layer 1820 added to the intermediate structure 1700. The spacer layer 1820 includes a dielectric layer 1828, the conductive lateral segments 756, the vertical subsections 757, and segments 1834 of the PDIs 773. In embodiments, the spacer layer 1820 is part of the front planar layer 720 and the dielectric layer 1828 is part of the dielectric layer 728.

[0062] Figure 19 An intermediate structure 1900 is depicted that includes the LEDs 734 on a substrate 1909. Figure 20 An intermediate structure 2000 is depicted that includes the front planar layer 730 on the substrate 1909. The front planar layer 730 includes a dielectric layer 738 and vertical subsections 758 each spanning a thickness 733 of the dielectric layer 738. The front planar layer 730 also includes PDI segments 2034, each PDI segment 2034 being a segment of a respective PDI 773. The LEDs 734 are embedded in the dielectric layer 738. The dielectric layer 738 has a surface 739 proximate to the substrate 1909 and a surface 731 opposite the surface 739. Figure 21 An intermediate structure 2100 is depicted that is the intermediate structure 1800 with the intermediate structure 2000 on the intermediate structure 1800.

[0063] Figure 22 is a flowchart illustrating a method 2200 for fabricating a pair of LED pixels. The pair of pixels can includeFigure 7 The pixels 702(1) and 702(2) described or comprised by the intermediate structure. Figures 8 to 21 comprise the intermediate structure produced by the steps of the method 2200. Figures 8 to 21 and Figure 22 The following description in the best mode is best viewed together. The method 2200 includes at least one of steps 2230, 2240, and 2260.

[0064] The following description of the method 2200 includes numbers in parentheses following terms used in the steps of the method. The numbers in parentheses indicate that the element associated with the number in the parentheses is an example of the term. For example, the following description of step 2230 lists “first frontplane layer (1010),” which means that Figure 10 the frontplane layer 1010 of the structure of FIG. 7A is an example of the first frontplane layer introduced in step 2230.

[0065] Step 2230 includes hybrid bonding the first frontplane layer (1010) to the backplane layer (740). The first frontplane layer includes (i) a first dielectric layer (1018), (ii) a first LED (714(1)) and a second LED (714(2)) embedded in the first dielectric layer, (iii) a lower first vertical subsection 752(1) and a lower second vertical subsection 752(2) each spanning a thickness of the first dielectric layer. In an embodiment, step 2230 produces the intermediate structure 1100 of FIG. 11A. Figure 11

[0066] Step 2230 can include at least one of steps 2231, 2232, 2235, and 2236. Step 2231 includes electrically connecting the lower first vertical subsection (752(1)) to a first backplane interconnect subsection (751(1)) of the backplane layer (740).

[0067] Step 2232 includes electrically connecting the lower second vertical subsection (752(2)) to a second backplane interconnect subsection (751(2)) of the backplane layer (740). The second backplane interconnect subsection (751(2)) is electrically isolated from the lower first vertical subsection (752(1)).

[0068] ​Step 2235 includes electrically connecting the first LED (714(1)) to a first driver circuit (741(1)) of the back plane layer (740). Step 2236 includes electrically connecting the second LED (714(2)) to a second driver circuit (741(2)) of the back plane layer (740). In an embodiment, the first front plane layer (1010) includes a first driver circuit segment (1014(1,2)) electrically connected to the first and second LEDs (714(1,2)), respectively, and spanning between (i) the first LED or the second LED and (ii) a first dielectric surface (1011) of the first dielectric layer (1018) proximate to the back plane layer (740). In such an embodiment, step 2235 includes electrically connecting the first driver circuit segment (1014(1)) to the first driver circuit (741(1)). Additionally, in such an embodiment, step 2236 includes electrically connecting the second driver circuit segment (1014(2)) to the second driver circuit (741(2)).

[0069] Method 2200 may include step 2240 after step 2230. Step 2240 includes at least steps 2242 and 2244. In an embodiment, steps 2242 and 2244 produce Figure 12 The intermediate structure 1200.

[0070] Step 2242 includes removing the first substrate (909) to expose the surface (1019) of the first dielectric layer (1018). Step 2244 includes (i) electrically connecting the lower first vertical subsegment (752(1)) to the first LED (714(1)) and (ii) electrically connecting the lower second vertical subsegment (752(2)) to the second LED (714(2)) by depositing corresponding conductive elements (753(1,2)) on the surface (1019), as shown in FIG. Figure 12 shown.

[0071] Step 2240 may also include at least one of steps 2246 and 2248. In an embodiment, steps 2246 and 2248 produce Figure 13 The intermediate structure 1300 is formed by depositing a first spacer dielectric layer (1318) on the first dielectric layer (1018). Step 2248 includes forming in the first spacer dielectric layer (1318) an upper first vertical subsegment (754(1)) electrically connected to the lower first vertical subsegment (752(1)), an upper second vertical subsegment (754(2)) electrically connected to the lower second vertical subsegment (752(2)), and respective segments (1324(1,2), 1334(1,2)) of a third PDI and a fourth PDI, each spanning the thickness of the first spacer dielectric layer (1318).

[0072] Step 2260 includes hybrid-bonding a second front planar layer (1520) to the first spacer dielectric layer (1318) on the first front planar layer (710). In embodiments, step 2260 results in an intermediate structure 1600 of Figure 16 The second front planar layer includes (i) a second dielectric layer (1528), (ii) a third LED (724(1)) and a fourth LED (724(2)) embedded in the second dielectric layer, and (iii) a third common interconnect segment (762(1)) and a fourth common interconnect segment (762(2)) each spanning a thickness (723) of the second dielectric layer. Step 2260 can include abutting the second front planar layer (1520) to the first spacer dielectric layer (1318).

[0073] Step 2260 can include at least one of steps 2261 and 2262. Step 2261 includes electrically connecting the lower third vertical subsection (755(1)) to the first common interconnect segment (761(1)) including vertical subsection 752(1). Step 2262 includes electrically connecting the lower fourth vertical subsection (755(2)) to the second common interconnect segment (761(2)), vertical subsection 752(2).

[0074] In embodiments, the first, second, third, and fourth LEDs are electrically connected to the first, second, third, and fourth drive circuits of the back planar layer via respective first, second, third, and fourth pixel drive interconnects (PDIs). PDI 771 is an example of the first and second PDIs. PDI 772 is an example of the third and fourth PDIs. In such embodiments, method 2200 can include step 2210 of forming the first front planar layer (710).

[0075] Step 2210 includes steps 2212, 2214, and 2216. Step 2212 includes forming a first LED (714(1)) and a second LED (714(2)) on a first substrate (909). In embodiments, step 2212 results in an intermediate structure 900 of Figure 9 Step 2214 includes depositing a first dielectric layer (1018) on the first substrate.

[0076] Step 2216 includes forming in the first dielectric layer (1018) a lower first vertical subsection (752(1)), a lower second vertical subsection (752(2)), and respective segments of a first PDI (1014(1)), a second PDI (1014(2)), a third PDI (1024(1)), and a fourth PDI (1024(2)) each spanning a thickness (1013) of the first dielectric layer (1018). In embodiments, step 2216 results in an intermediate structure 1000 of Figure 10

[0077] ​In an embodiment, the third and fourth LEDs are electrically connected to the third and fourth drive circuits of the backplane layer via respective third and fourth pixel drive interconnects. LED 724 is an example of a third and fourth LED. PDI 772 is an example of a third and fourth pixel drive interconnect. In such embodiments, method 2200 can include step 2220 of forming a second frontplane layer, an example of which is frontplane layer 720.

[0078] Step 2220 includes steps 2222, 2224, and 2226. Step 2222 includes forming a third LED (724(1)) and a fourth LED (724(2)) on a second substrate (1409). In an embodiment, step 2222 results in intermediate structure 1400 of Figure 14 Step 2224 includes depositing a second dielectric layer (1528) on the second substrate.

[0079] Step 2226 includes forming a lower third vertical subsection (755(1)), a lower fourth vertical subsection (755(2)), and respective segments (1524(1,2)) of third and fourth PDIs that each span a thickness of the second dielectric layer in the second dielectric layer. In an embodiment, step 2226 results in intermediate structure 1500 of Figure 15 Step 2226 includes forming a lower third vertical subsection (755(1)), a lower fourth vertical subsection (755(2)), and respective segments (1524(1,2)) of third and fourth PDIs that each span a thickness of the second dielectric layer in the second dielectric layer. In an embodiment, step 2226 results in intermediate structure 1500 of

[0080] Method 2200 can include step 2272, which is performed after step 2260. Step 2272 includes removing the second substrate (1409) to expose a surface (1529) of the second dielectric layer (1528). In an embodiment, step 2272 results in intermediate structure 1700 of Figure 17 When method 2200 includes step 2272, it can also include step 2274. Step 2274 includes electrically connecting (i) the lower third vertical subsection (755(1)) to the third LED and (ii) the lower fourth vertical subsection (755(2)) to the fourth LED by depositing respective conductive elements (756(1,2)) on the surface (1529), as shown in Figure 17 Step 2274 results in intermediate structure 1800 of Figure 18 but without dielectric layer 1828, vertical subsections 757, and segments 1834.

[0081] Method 2200 can include additional steps 2300, which are shown in Figure 23 Step 2300 includes at least one of steps 2316, 2318, 2320, 2350, and 2360.

[0082] Step 2316 includes depositing a second spacer dielectric layer (1828) on the second dielectric layer (1528). Step 2318 includes forming in the second spacer dielectric layer (1828) an upper third vertical subsection (757(1)) in electrical connection with a lower third vertical subsection (755(1)), an upper fourth vertical subsection (757(2)) in electrical connection with a lower fourth vertical subsection (755(2)), and respective segments (1834(1,2)) of the fifth and sixth PDIs that each span a thickness of the second spacer dielectric layer (1828). In embodiments, steps 2316 and 2318 produce the intermediate structure 1800 of Figure 18 .

[0083] In embodiments, the fifth and sixth LEDs are electrically connected to fifth and sixth drive circuits of the backplane layer via respective fifth and sixth PDIs (773(1,2)). In such embodiments, step 2300 can include step 2320 of forming a third frontplane layer (730). Step 2320 includes at least one of steps 2322, 2324, and 2326. Step 2322 includes forming the fifth LED (734(1)) and the sixth LED (734(2)) on a third substrate (1909). In embodiments, step 2322 produces the intermediate structure 1900 of Figure 19 .

[0084] Step 2324 includes depositing a third dielectric layer (738) on the third substrate. Step 2326 includes forming in the third dielectric layer a fifth vertical subsection (758(1)), a sixth vertical subsection (758(2)), and respective segments (2034(1,2)) of the fifth and sixth PDIs that each span a thickness of the third dielectric layer. In embodiments, steps 2324 and 2326 produce the intermediate structure 2000 of Figure 20 .

[0085] Step 2350 includes hybrid bonding the third frontplane layer (730) to the second spacer dielectric layer (1828) that is located on the second frontplane layer (720). The third frontplane layer includes (i) the third dielectric layer (738), (ii) the fifth LED (734(1)) and the sixth LED (734(2)) embedded in the third dielectric layer, and (iii) the fifth vertical subsection (758(1)) and the sixth vertical subsection (758(2)) that each span a thickness (733) of the third dielectric layer. In step 2350, hybrid bonding the third frontplane layer includes electrically connecting the fifth vertical subsection (758(1)) to the lower third vertical subsection 755(1). The hybrid bonding of step 2350 also includes electrically connecting the sixth vertical subsection (758(2)) to the lower fourth vertical subsection 755(2).

[0086] In an embodiment, the third, fourth, fifth, and sixth LEDs are electrically connected to the third, fourth, fifth, and sixth drive circuits of the backplane layer via respective third, fourth, fifth, and sixth pixel drive interconnects (PDIs) (772(1,2), 773(1,2)). In such embodiments, the forming the second frontplane layer of step 2220 can include step 2228. Step 2228 includes forming a lower fifth vertical subsection (1534(1)) and a lower sixth vertical subsection (1534(2)) in the second dielectric layer (1528). Respective segments (1534(1,2)) of the fifth PDI (773(1)) and the sixth PDI (773(2)) each span a thickness of the second dielectric layer. In an embodiment, step 2228 results in the intermediate structure 1500 of Figure 15

[0087] Step 2360 is after step 2350 and includes 2362 and 2364, which are respectively similar to steps 2242 and 2244. Step 2362 includes removing the third substrate (1909) to expose a surface (739) of the third dielectric layer (738). Step 2364 includes electrically connecting (i) the fifth vertical subsection (758(1)) to the fifth LED (734(1)) and (ii) the sixth vertical subsection (758(2)) to the sixth LED (734(2)) by depositing respective conductive elements (759(1,2)) on the surface (739). Figure 7 FIGURE illustrates the lateral segments 759 on the surface 739.

[0088] Combinations of features

[0089] The above-mentioned features, as well as the features claimed below, can be combined in a variety of ways without departing from the scope of the invention. The following enumerated examples illustrate some possible non-limiting combinations.

[0090] Embodiment 1. A micro light emitting diode (LED) display (700) comprising: a first pixel comprising a first LED (714(1)), a third LED (724(1)), and a first common interconnect (760(1)) electrically connected with each of the first LED and the third LED; a second pixel comprising a second LED (714(2)), a fourth LED (724(2)), and a second common interconnect (760(2)) electrically connected with the second LED and the fourth LED; and an opaque conductive element (744) electrically connected with each of the first common interconnect and the second common interconnect.

[0091] Embodiment 2. The LED display of embodiment 1, further comprising a non- conductive transparent layer (770) covering each of the first pixel and the second pixel.

[0092] ​Embodiment 3. The LED display of embodiment 1, further comprising a conductive transparent layer covering each of the first pixel and the second pixel, and the conductive transparent layer is electrically isolated from each of the first common interconnect and the second common interconnect.

[0093] Embodiment 4. The LED display of embodiment 1, wherein the non-transparent conductive element is a ground plane or a common voltage plane.

[0094] Embodiment 5. The LED display of embodiment 1, wherein the first pixel further comprises a first drive circuit (741(1)) electrically connected with the first LED, the second pixel further comprises a second drive circuit (741(2)) electrically connected with the second LED, and the LED display further comprises: a front plane layer (710) comprising the first LED, the second LED, a first segment (761(1)) of the first common interconnect (760(1)), and a first segment (761(2)) of the second common interconnect (760(2)); and a back plane layer (740) bonded with the front plane layer and comprising the first drive circuit and the second drive circuit, a bottom segment (751(1)) of the first common interconnect, and a bottom segment (751(2)) of the second common interconnect.

[0095] Embodiment 6. The LED display of embodiment 5, wherein the first pixel further comprises a third drive circuit (742(1)) electrically connected with a third LED, the second pixel further comprises a fourth drive circuit (742(2)) electrically connected with a fourth LED, and the LED display further comprises: a second front plane layer (720) comprising the third LED, the fourth LED, a second segment (762(1)) of the first common interconnect, and a second segment (762(2)) of the second common interconnect; and the back plane layer (740) further comprises the third drive circuit and the fourth drive circuit, wherein the first front plane layer is between the second front plane layer and the back plane layer.

[0096] Example 7. The LED display of Example 6, wherein a first segment (761(1)) of the first common interconnect (760(1)) includes a first vertical subsegment (752(1)) / 754(1)) that extends through the first front planar layer and a first lateral segment (753(1)) that extends from the first vertical subsegment to the first LED; a second segment (762(1)) of the first common interconnect (760(1)) includes a third vertical subsegment (755(1)) / 757(1)) that extends through the second front planar layer and a third lateral segment (756(1)) that extends from the third vertical subsegment to the third LED; a first segment (761(2)) of the second common interconnect (760(2)) includes a second vertical subsegment (752(2)) / 754(2)) that extends through the first front planar layer and a second lateral segment (753(2)) that extends from the second vertical subsegment to the second LED; and a second segment (762(1)) of the second common interconnect (760(2)) includes a fourth vertical subsegment (755(2)) / 757(2)) that extends through the second front planar layer and a fourth lateral segment (756(2)) that extends from the fourth vertical subsegment to the fourth LED.

[0097] Example 8. The LED display of Example 1, wherein the first pixel further includes a fifth LED (734(1)) in electrical connection with the first common interconnect, the second pixel further includes a sixth LED (734(2)) in electrical connection with the second common interconnect, and the LED display further includes: a third front planar layer that includes the fifth LED, the sixth LED, a third segment of the first common interconnect, and a third segment of the second common interconnect, wherein the second front planar layer is between the third front planar layer and the first front planar layer.

[0098] Embodiment 9. The LED display of embodiment 8, wherein a first segment (761(1)) of the first common interconnect includes a first vertical subsection (752(1)) extending through the first front planar layer and a first lateral section (753(1)) extending from the first vertical subsection to the first LED; a second segment of the first common interconnect includes a third vertical subsection (755(1), 1657(1)) extending through the second front planar layer and a third lateral section (756(1)) extending from the third vertical subsection to the third LED; a third segment (763(1)) of the first common interconnect includes a fifth vertical subsection (758(1)) extending through the third front planar layer and a fifth lateral section (759(1)) extending from the fifth vertical subsection to the fifth LED; a first segment of the second common interconnect includes a second vertical subsection extending through the first front planar layer and a second lateral section extending from the second vertical subsection to the second LED; a second segment of the second common interconnect includes a fourth vertical subsection extending through the second front planar layer and a fourth lateral section extending from the fourth vertical subsection to the fourth LED; and a third segment (763(2)) of the second common interconnect includes a sixth vertical subsection (758(2)) extending through the third front planar layer and a sixth lateral section extending from the sixth vertical subsection to the sixth LED.

[0099] Embodiment 10. An LED display comprising: a plurality of pixel pairs, each pixel pair of the plurality of pixel pairs comprising a first pixel according to embodiment 1 and a second pixel according to embodiment 1, such that the plurality of pixel pairs comprises a plurality of first common interconnects and a plurality of second common interconnects; each of the plurality of first common interconnects is electrically isolated from (i) each other first common interconnect of the plurality of first common interconnects and (ii) each second common interconnect of the plurality of second common interconnects.

[0100] Embodiment 11. A method for fabricating a pair of LED pixels, comprising: hybrid bonding a first front planar layer (1010) to a back planar layer (740), the first front planar layer comprising (i) a first dielectric layer (1018), (ii) a first LED (714(1)) and a second LED (714(2)) embedded in the first dielectric layer, (iii) a lower first vertical subsection (752(1)) and a lower second vertical subsection (752(2)) each spanning a thickness (713) of the first dielectric layer; and hybrid bonding (2260) a second front planar layer (1520) to a first spacer dielectric layer (1318) positioned on the first front planar layer (710), the second front planar layer comprising (i) a second dielectric layer (1528), (ii) a third LED (724(1)) and a fourth LED (724(2)) embedded in the second dielectric layer, and (iii) a third vertical subsection (755(1)) and a fourth vertical subsection (755(2)) each spanning a thickness (1523) of the second dielectric layer.

[0101] Embodiment 12. The method of embodiment 11, bonding the first frontplane layer hybrid to the backplane layer comprises: electrically connecting (2231) the lower first vertical subsection (752(1)) to a first backplane interconnect subsection of the backplane layer; electrically connecting (2232) the lower second vertical subsection (752(2)) to a second backplane interconnect subsection of the backplane layer, wherein the second backplane interconnect subsection is electrically isolated from the lower first vertical subsection (752(1)).

[0102] Embodiment 13. The method of embodiment 11, bonding the first frontplane layer hybrid to the backplane layer further comprises: electrically connecting (2235) the first LED (714(1)) to a first drive circuit (741(1)) of the backplane layer; and electrically connecting (2236) the second LED (714(2)) to a second drive circuit (741(2)) of the backplane layer.

[0103] Embodiment 14. The method of embodiment 11, hybrid bonding the second frontplane layer to the first spacer dielectric layer comprises: electrically connecting (2261) the third vertical subsection (755(1)) to the lower first vertical subsection (752(1)); and electrically connecting (2262) the fourth vertical subsection (755(2)) to the lower second vertical subsection (752(2)).

[0104] Embodiment 15. The method of embodiment 11, the first, second, third, and fourth LEDs are electrically connected to the first, second, third, and fourth drive circuits of the backplane layer via respective first, second, third, and fourth pixel drive interconnects (PDIs) (771, 772), and the method further comprises forming the first frontplane layer (710) by: forming (2212) the first and second LEDs on a first substrate (909); depositing (2214) a first dielectric layer (1018) on the first substrate; and forming (2216) the lower first vertical subsection (752(1)), the lower second vertical subsection (752(2)), and respective segments (1014(1,2), 1024(1,2)) of the first, second, third, and fourth PDIs spanning a thickness of the first dielectric layer in the first dielectric layer.

[0105] Embodiment 16. The method of embodiment 15, further comprising, after hybrid bonding (2230, step 4) the first frontplane layer (1010) to the backplane layer (740): removing (2242) the first substrate (909) to expose a surface of the first dielectric layer; and electrically connecting (2244) (i) the lower first vertical subsection (752(1)) to the first LED and (ii) the lower second vertical subsection (752(2)) to the second LED by depositing respective conductive elements (753(1,2)) on the surface.

[0106] Embodiment 17. The method of embodiment 16, further comprising: depositing (2246) a first spacer dielectric layer (1318) on the first dielectric layer (1018); forming (2248) in the first spacer dielectric layer (1318) the upper first vertical subsection (754(1)) in electrical connection with the lower first vertical subsection (752(1)), the upper second vertical subsection (754(2)) in electrical connection with the lower second vertical subsection (752(2)), and respective segments (1324(1,2), 1334(1,2)) of the third and fourth PDIs each spanning a thickness of the first spacer dielectric layer (1318).

[0107] Embodiment 18. The method of embodiment 11, the third and fourth LEDs being electrically connected to third and fourth drive circuits of the backplane layer via respective third and fourth pixel drive interconnects (PDIs) (772(1,2)), and the method further comprising forming the second frontplane layer (720) by: forming (2222) the third and fourth LEDs on a second substrate (1409); depositing (2224) a second dielectric layer (1528) on the second substrate; and forming (2226) in the second dielectric layer the lower third vertical subsection (755(1)), the lower fourth vertical subsection (755(2)), and respective segments (1524(1,2)) of the third and fourth PDIs each spanning a thickness of the second dielectric layer.

[0108] Embodiment 19. The method of embodiment 18, further comprising, after hybrid bonding (step 10, 2260) the second frontplane layer (1520) to the first spacer dielectric layer (1318): removing (2272) the second substrate to expose a surface of the second dielectric layer; and electrically connecting (2274) (i) the lower third vertical subsection (755(1)) to the third LED and (ii) the lower fourth vertical subsection (755(2)) to the fourth LED by depositing respective conductive elements (756(1,2)) on the surface.

[0109] Embodiment 20. The method of embodiment 18, further comprising: hybrid-bonding a third front planar layer (730) to a second spacer dielectric layer (1828) on the second front planar layer (720), wherein the third front planar layer comprises (i) a third dielectric layer (738), (ii) a fifth LED (734(1)) and a sixth LED (734(2)) embedded in the third dielectric layer, and (iii) a fifth vertical subsection (758(1)) and a sixth vertical subsection (758(2)) each spanning a thickness (733) of the third dielectric layer; wherein hybrid-bonding the third front planar layer comprises: electrically connecting the fifth vertical subsection (758(1)) to the lower third vertical subsection (755(1)); and electrically connecting the sixth vertical subsection (758(2)) to the lower fourth vertical subsection (755(2)).

[0110] Embodiment 21. The method of embodiment 20, the fifth and sixth LEDs are electrically connected to fifth and sixth drive circuits of the back planar layer via respective fifth and sixth pixel drive interconnects (PDI) (772(1,2), 773(1,2)), wherein forming the second front planar layer (1010) further comprises: forming (2228) in the second dielectric layer (1528) the lower fifth vertical subsection (1534(1)) and the lower sixth vertical subsection (1534(2)), and respective segments (1534(1,2)) of the fifth and sixth PDIs each spanning a thickness of the second dielectric layer.

[0111] Embodiment 22. The method of embodiment 21, further comprising: depositing (2316) a second spacer dielectric layer (1828) on the second dielectric layer (1528); forming (2318) in the second spacer dielectric layer (1828) an upper third vertical subsection (757(1)) electrically connected to the lower third vertical subsection (755(1)), an upper fourth vertical subsection (757(2)) electrically connected to the lower fourth vertical subsection (755(2)), and respective segments (1834(1,2)) of the fifth and sixth PDIs each spanning a thickness of the second spacer dielectric layer (1828).

[0112] Example 23. The method of Example 20, the fifth and sixth LEDs are electrically connected to the fifth and sixth drive circuits of the backplane layer via respective fifth and sixth pixel drive interconnects (PDIs) (773(1,2)), and the method further comprises forming the third frontplane layer (730) by: forming the fifth and sixth LEDs on a third substrate (1909); depositing a third dielectric layer (738) on the third substrate; and forming the fifth vertical subsection (758(1)), the sixth vertical subsection (758(2)), and respective segments (2034(1,2)) of the fifth and sixth PDIs each spanning a thickness of the third dielectric layer in the third dielectric layer.

[0113] Example 24. The method of Example 23, further comprising, after hybrid bonding the third frontplane layer (730) to the second spacer dielectric layer (1828): removing the third substrate (1909) to expose a surface of the third dielectric layer (738); and electrically connecting (i) the fifth vertical subsection (758(1)) to the fifth LED and (ii) the sixth vertical subsection (758(2)) to the sixth LED by depositing respective electrically conductive elements (759(1,2)) on the surface.

[0114] Modifications can be made to the methods and systems described above without departing from the scope of the present embodiments. Therefore, it should be understood that the contents of the above description and the drawings included herein are to be construed as illustrative and not restrictive. In this document, the recitation of “in an embodiment” or similar phrases does not mean that all embodiments are identical. The appended claims are intended to cover all generic and specific features of the methods and systems described herein, and all statements of the scope of the methods and systems that, as a matter of language, might be said to fall therebetween.

Claims

1. A micro light emitting diode (LED) display comprising: a first pixel including a first LED, a third LED, and a first common interconnect electrically connected to each of the first LED and the third LED; a second pixel including a second LED, a fourth LED, and a second common interconnect electrically connected to each of the second LED and the fourth LED; and an opaque conductive element electrically connected to each of the first common interconnect and the second common interconnect.

2. The LED display of claim 1, further comprising a non-conductive transparent layer covering each of the first pixel and the second pixel.

3. The LED display of claim 1, further comprising a conductive transparent layer covering each of the first pixel and the second pixel, and the conductive transparent layer is electrically isolated from each of the first common interconnect and the second common interconnect.

4. The LED display of claim 1, wherein the opaque conductive element is a ground plane or a common voltage plane.

5. The LED display of claim 1, wherein the first pixel further includes a first drive circuit electrically connected to the first LED, the second pixel further includes a second drive circuit electrically connected to the second LED, the LED display further comprising: a front plane layer including the first LED, the second LED, a first segment of the first common interconnect, and a first segment of the second common interconnect; and a back plane layer bonded to the front plane layer and including the first drive circuit and the second drive circuit, a bottom segment of the first common interconnect, and a bottom segment of the second common interconnect.

6. The LED display of claim 5, wherein the first pixel further includes a third drive circuit electrically connected to the third LED, the second pixel further includes a fourth drive circuit electrically connected to the fourth LED, the LED display further comprising: a second front plane layer including the third LED, the fourth LED, a second segment of the first common interconnect, and a second segment of the second common interconnect; and the back plane layer further including the third drive circuit and the fourth drive circuit, wherein the first front plane layer is between the second front plane layer and the back plane layer.

7. The LED display of claim 6, wherein: the first segment of the first common interconnect includes a first vertical sub-segment extending through the first front plane layer and a first lateral segment extending from the first vertical sub-segment to the first LED; the second segment of the first common interconnect includes a third vertical sub-segment extending through the second front plane layer and a third lateral segment extending from the third vertical sub-segment to the third LED; the first segment of the second common interconnect includes a second vertical sub-segment extending through the first front plane layer and a second lateral segment extending from the second vertical sub-segment to the second LED; and the second segment of the second common interconnect includes a fourth vertical sub-segment extending through the second front plane layer and a fourth lateral segment extending from the fourth vertical sub-segment to the fourth LED. ​ ​ The second segment of the second common interconnect includes a fourth vertical subsection extending through the second front planar layer and a fourth lateral section extending from the fourth vertical subsection to the fourth LED.

8. The LED display of claim 1, wherein the first pixel further comprises a fifth LED in electrical connection with the first common interconnect, the second pixel further comprises a sixth LED in electrical connection with the second common interconnect, the LED display further comprising: a third front planar layer comprising the fifth LED, the sixth LED, a third segment of the first common interconnect, and a third segment of the second common interconnect, wherein a second front planar layer is positioned between the third front planar layer and the first front planar layer.

9. The LED display of claim 8, wherein: the first segment of the first common interconnect includes a first vertical subsection extending through the first front planar layer and a first lateral section extending from the first vertical subsection to the first LED; the second segment of the first common interconnect includes a third vertical subsection extending through the second front planar layer and a third lateral section extending from the third vertical subsection to the third LED; the third segment of the first common interconnect includes a fifth vertical subsection extending through the third front planar layer and a fifth lateral section extending from the fifth vertical subsection to the fifth LED; the first segment of the second common interconnect includes a second vertical subsection extending through the first front planar layer and a second lateral section extending from the second vertical subsection to the second LED; the second segment of the second common interconnect includes a fourth vertical subsection extending through the second front planar layer and a fourth lateral section extending from the fourth vertical subsection to the fourth LED; and the third segment of the second common interconnect includes a sixth vertical subsection extending through the third front planar layer and a sixth lateral section extending from the sixth vertical subsection to the sixth LED.

10. An LED display comprising: a plurality of pixel pairs, each pixel pair of the plurality of pixel pairs comprising a first pixel according to claim 1 and a second pixel according to claim 1, such that the plurality of pixel pairs comprises a plurality of first common interconnects and a plurality of second common interconnects; wherein each of the plurality of first common interconnects is electrically isolated from (i) each other first common interconnect of the plurality of first common interconnects and (ii) each second common interconnect of the plurality of second common interconnects.

11. A method for fabricating a pair of LED pixels, comprising: anisotropic conductive film (ACF) bonding a first front planar layer to a back planar layer, wherein the first front planar layer comprises (i) a first dielectric layer, (ii) a first LED and a second LED embedded in the first dielectric layer, (iii) a lower first vertical subsection and a lower second vertical subsection each spanning a thickness of the first dielectric layer; and bonding a second front planar layer hybrid-bonded to a first spacer dielectric layer located on the first front planar layer, wherein the second front planar layer includes (i) a second dielectric layer, (ii) a third LED and a fourth LED embedded in the second dielectric layer, and (iii) a third vertical subsection and a fourth vertical subsection each spanning a thickness of the second dielectric layer.

12. The method of claim 11, hybrid-bonding the first front planar layer to the back planar layer includes: electrically connecting the lower first vertical subsection to a first back planar interconnect subsection of the back planar layer; and electrically connecting the lower second vertical subsection to a second back planar interconnect subsection of the back planar layer, wherein the second back planar interconnect subsection is electrically isolated from the lower first vertical subsection.

13. The method of claim 11, wherein hybrid-bonding the first front planar layer to the back planar layer further includes: electrically connecting the first LED to a first drive circuit of the back planar layer; and electrically connecting the second LED to a second drive circuit of the back planar layer.

14. The method of claim 11, wherein hybrid-bonding the second front planar layer to the first spacer dielectric layer includes: electrically connecting the third vertical subsection to the lower first vertical subsection; and electrically connecting the fourth vertical subsection to the lower second vertical subsection.

15. The method of claim 11, wherein the first, second, third, and fourth LEDs are electrically connected to first, second, third, and fourth drive circuits of the back planar layer via respective first, second, third, and fourth pixel drive interconnects (PDIs), and the method further includes forming the first front planar layer by: forming the first LED and the second LED on a first substrate; depositing the first dielectric layer on the first substrate; and forming a lower first vertical subsection, a lower second vertical subsection, and respective sections of the first PDI, the second PDI, the third PDI, and the fourth PDI each spanning a thickness of the first dielectric layer in the first dielectric layer.

16. The method of claim 15, further including, after hybrid-bonding the first front planar layer to the back planar layer: removing the first substrate to expose a surface of the first dielectric layer; and electrically connecting (i) the lower first vertical subsection to the first LED and (ii) the lower second vertical subsection to the second LED by depositing respective conductive elements on the surface.

17. The method of claim 16, further including: depositing the first spacer dielectric layer on the first dielectric layer; forming an upper first vertical subsection electrically connected to the lower first vertical subsection, an upper second vertical subsection electrically connected to the lower second vertical subsection, and respective sections of the third PDI and the fourth PDI each spanning a thickness of the first spacer dielectric layer in the first spacer dielectric layer.

18. The method of claim 11, wherein the third and fourth LEDs are electrically connected to third and fourth drive circuits of the backplane layer via respective third and fourth pixel drive interconnects (PDIs), and the method further comprises forming the second frontplane layer by: forming the third LED and the fourth LED on a second substrate; depositing the second dielectric layer on the second substrate; and forming a lower third vertical subsection, a lower fourth vertical subsection, and respective segments of the third and fourth PDIs that each span a thickness of the second dielectric layer in the second dielectric layer.

19. The method of claim 18, further comprising, after hybrid bonding the second frontplane layer to the first spacer dielectric layer: removing the second substrate to expose a surface of the second dielectric layer; and electrically connecting (i) the lower third vertical subsection to the third LED and (ii) the lower fourth vertical subsection to the fourth LED by depositing respective conductive elements on the surface.

20. The method of claim 18, further comprising: hybrid bonding a third frontplane layer to a second spacer dielectric layer that is positioned on the second frontplane layer, wherein the third frontplane layer comprises (i) a third dielectric layer, (ii) fifth and sixth LEDs embedded in the third dielectric layer, and (iii) fifth and sixth vertical subsections that each span a thickness of the third dielectric layer; wherein hybrid bonding the third frontplane layer comprises: electrically connecting the fifth vertical subsection to the lower third vertical subsection; and electrically connecting the sixth vertical subsection to the lower fourth vertical subsection.

21. The method of claim 20, wherein the fifth and sixth LEDs are electrically connected to fifth and sixth drive circuits of the backplane layer via respective fifth and sixth pixel drive interconnects (PDIs), wherein forming the second frontplane layer further comprises: forming a lower fifth vertical subsection and a lower sixth vertical subsection in the second dielectric layer, and respective segments of the fifth and sixth PDIs that each span a thickness of the second dielectric layer.

22. The method of claim 21, further comprising: depositing the second spacer dielectric layer on the second dielectric layer; forming an upper third vertical subsection electrically connected to the lower third vertical subsection, an upper fourth vertical subsection electrically connected to the lower fourth vertical subsection, and respective segments of the fifth and sixth PDIs that each span a thickness of the second spacer dielectric layer in the second spacer dielectric layer.

23. The method of claim 20, wherein the fifth and sixth LEDs are electrically connected to fifth and sixth drive circuits of the backplane layer via respective fifth and sixth pixel drive interconnects (PDIs), and the method further comprises forming the third frontplane layer by: forming the fifth LED and the sixth LED on a third substrate; depositing the third dielectric layer on the third substrate; and forming a lower fifth vertical subsection, a lower sixth vertical subsection, and respective segments of the fifth and sixth PDIs that each span a thickness of the third dielectric layer in the third dielectric layer. forming the fifth vertical subsection, the sixth vertical subsection, and respective segments of the fifth PDI and the sixth PDI each spanning a thickness of the third dielectric layer in the third dielectric layer.

24. The method of claim 23, further comprising, after hybrid-bonding the third front planar layer to the second spacer dielectric layer: removing the third substrate to expose a surface of the third dielectric layer; and electrically connecting (i) the fifth vertical subsection to the fifth LED and (ii) the sixth vertical subsection to the sixth LED by depositing respective conductive elements on the surface.

25. The method of claim 23, wherein the third front planar layer is hybrid-bonded to the second spacer dielectric layer by: forming a plurality of openings in the third front planar layer, each of the plurality of openings exposing a respective one of the plurality of LEDs; forming a plurality of conductive elements in the plurality of openings, each of the plurality of conductive elements electrically connecting a respective one of the plurality of LEDs to the third front planar layer.

26. The method of claim 23, wherein the third front planar layer is hybrid-bonded to the second spacer dielectric layer by: forming a plurality of openings in the third front planar layer, each of the plurality of openings exposing a respective one of the plurality of LEDs; forming a plurality of conductive elements in the plurality of openings, each of the plurality of conductive elements electrically connecting a respective one of the plurality of LEDs to the third front planar layer.

27. The method of claim 23, wherein the third front planar layer is hybrid-bonded to the second spacer dielectric layer by: forming a plurality of openings

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