LED display device and preparation method

Abstract

The invention relates to an LED display device and a preparation method, the LED display device comprises a substrate and a pixel layer, the pixel layer comprises pixel units, the periphery of each pixel unit is at least surrounded by an annular partition groove, the bottom of each pixel unit is electrically connected with a corresponding first-class electrode contact, and the first-class electrode contact is electrically connected with a corresponding second-class electrode contact. The tops of the pixel units are electrically connected with the corresponding second type of electrode contacts through interconnection conductive pieces, the interconnection conductive pieces are located at the edges of the corresponding pixel units, and at least part of the interconnection conductive pieces are located in the nearest annular partition grooves of the corresponding pixel units. The invention further discloses a preparation method of the LED display device. The photoelectric performance and the reliability of the LED display device can be better guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an LED display device and a preparation method thereof. BACKGROUND

[0002] The LED display chip usually comprises a plurality of pixel units (i.e. light emitting units). With the development of semiconductor display technology, the size of the display chip is increasingly reduced, and the pixel density is also increasingly high, which also leads to the increasing heat density of the chip, and the heat is more easily concentrated. The source of the heat of the LED chip is mainly the conversion efficiency problem of the electrons and the outgoing photons. Most of the electric energy that is not converted into outgoing light energy will be converted into heat energy. These heat energy will cause the temperature of the LED chip to rise. The excessively high temperature of the LED chip will lead to the problems of low light efficiency, wavelength shift and low service life of the LED photoelectric device, and even will seriously affect the stability and reliability of the LED display device, and cannot meet the use requirements. SUMMARY

[0003] Therefore, the technical problem to be solved by the present application is to improve the heat dissipation capacity of the LED display device in the prior art, so that the LED display device can stably emit light, and the photoelectric performance and reliable performance of the LED display device are ensured.

[0004] To solve the above technical problems, the present application provides an LED display device, comprising,

[0005] a substrate, the substrate is a driving wafer, the driving wafer is provided with a first type of electrode contact and a second type of electrode contact, and the polarities of the first type of electrode contact and the second type of electrode contact are opposite;

[0006] a pixel layer, the pixel layer is a compound semiconductor layer, the pixel layer is located on the upper part of the substrate, the pixel layer comprises pixel units, the periphery of each pixel unit is at least surrounded by an annular isolation groove, the annular isolation groove at the outermost periphery of each pixel unit and the annular isolation groove at the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with the compound semiconductor; or, the compound semiconductor is reserved between the annular isolation groove at the outermost periphery of each pixel unit and the annular isolation groove at the outermost periphery of the adjacent pixel unit to completely separate each other;

[0007] wherein the bottom of each pixel unit is electrically connected with the corresponding first type of electrode contact, the top of each pixel unit is electrically connected with the corresponding second type of electrode contact through an interconnection conductive piece, the interconnection conductive piece is located at the edge of each corresponding pixel unit, and the interconnection conductive piece is at least partially located inside the annular isolation groove closest to the corresponding pixel unit.

[0008] In one embodiment of the present application, the projection area of each pixel unit on the substrate is defined as a first projection area, and the second type of electrode contact is located at the edge of the first projection area of the corresponding pixel unit, and the second type of electrode contact is at least partially located inside the first projection area where the corresponding pixel unit is located.

[0009] In one embodiment of the present application, the projection area of the annular isolation groove in the periphery of the pixel unit on the substrate is defined as a second projection area, and the second type of electrode contact is partially located inside the first projection area where the corresponding pixel unit is located, and the rest is at least extended to the inside of the nearest second projection area. In one embodiment of the present application, a plurality of second type of electrode contacts are arranged at the edge of each first projection area, and the plurality of second type of electrode contacts are annularly distributed.

[0010] In one embodiment of the present application, the first type of electrode contact is arranged inside each first projection area, and the first type of electrode contact is surrounded by the plurality of second type of electrode contacts arranged at the edge of the first projection area.

[0011] In one embodiment of the present application, the interconnection conductive part is located inside the corresponding pixel unit, and the rest is at least extended to the inside of the nearest annular isolation groove.

[0012] In one embodiment of the present application, the inner wall of the annular isolation groove is covered with a first insulating layer, the inside of the annular isolation groove has a filling area, the periphery of the filling area is surrounded by the first insulating layer at the inner wall of the annular isolation groove, and the inside of the filling area is filled with air to form an air isolation layer, or the filling area is filled with a first filler to form a solid structure.

[0013] In one embodiment of the present application, the upper part of the pixel unit is at least partially covered with a first insulating layer, and the area not covered with the first insulating layer forms the electrical contact area.

[0014] In one embodiment of the present application, the upper part of the pixel unit is further covered with a first conductive layer, the first insulating layer of the upper part of the pixel unit is at least partially covered with the first conductive layer, the middle part of the top surface of the pixel unit forms the electrical contact area, and the electrical contact area of the pixel unit and the interconnection conductive part at the edge of the pixel unit are both in contact with the same first conductive layer.

[0015] In one embodiment of the present application, the top of each interconnection conductive part at the edge of the pixel unit is respectively connected with a second conductive layer, and all the second conductive layers of each pixel unit are separated from each other and arranged discontinuously, and each interconnection conductive part at the edge of the pixel unit is in contact with the corresponding electrical contact area through the respective second conductive layer.

[0016] In one embodiment of the present application, a second conductive layer is arranged on the upper portion of the pixel unit, the second conductive layer is arranged in a ring shape, and all the interconnecting conductive members at the edge of the pixel unit are in contact with the same second conductive layer.

[0017] In one embodiment of the present application, an arc-shaped covering area is formed at the contact area between the second conductive layer and the interconnecting conductive member, and the arc-shaped covering area covers at least the top surface area of the interconnecting conductive member inside the pixel unit.

[0018] In one embodiment of the present application, the upper portion of the pixel layer is further covered by a thin film covering layer, and the upper portion of the filling area is enclosed by the thin film covering layer.

[0019] In one embodiment of the present application, the thin film covering layer comprises a downwardly protruding extension, the extension extends into the filling area, the extension only extends to the upper portion of the filling area, and the lower portion of the filling area forms the air gap.

[0020] Alternatively, the extension serves as the first filler, and the filling area is filled with the first filler to form a solid structure.

[0021] In one embodiment of the present application, the filling area contains air to form an air gap, and the air gap is surrounded by the first reflective layer.

[0022] Alternatively, the first reflective layer serves as the first filler, and the filling area is filled with the first filler to form a solid structure.

[0023] In one embodiment of the present application, the pixel layer and the substrate are bonded by a bonding layer, and the bottom surface of the ring-shaped isolation groove is not lower than the upper surface of the bonding layer.

[0024] In one embodiment of the present application, the interconnecting conductive member is a metal member.

[0025] In one embodiment of the present application, the periphery of each pixel unit is surrounded by at least two ring-shaped isolation grooves, and a compound semiconductor is retained between the adjacent ring-shaped isolation grooves of the periphery of each pixel unit to form a partition wall.

[0026] In one embodiment of the present application, the upper surface of the driving wafer is divided into at least one display area, each display area is covered by at least one pixel unit, and the bonding layer above each display area is arranged continuously.

[0027] In one embodiment of the present application, the bottom portion of each pixel unit is electrically connected to the corresponding first electrode contact, and the first electrode contact is located at the periphery of the display area where the corresponding pixel unit is located.

[0028] In one embodiment of the present application, the pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the second type of electrode contact is used to electrically connect with the first semiconductor layer in the corresponding pixel unit, and the first type of electrode contact is used to electrically connect with the second semiconductor layer in the corresponding pixel unit; the lower end of the annular groove extends between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the annular groove extends at least to the upper surface of the first semiconductor layer.

[0029] In one embodiment of the present application, an ohmic contact layer is further arranged between the pixel layer and the substrate, and the lower end of the annular groove extends between the lower surface of the active layer and the lower surface of the ohmic contact layer.

[0030] In one embodiment of the present application, the maximum dimension of the annular groove in the width direction is L2, then L2, and L2 is 0.02 um to 10 um.

[0031] The present application discloses a preparation method of an LED display device, comprising the following steps:

[0032] A driving wafer is selected as the substrate, and the driving wafer is provided with a first type of electrode contact and a second type of electrode contact with opposite polarities; and a compound semiconductor layer is selected as the pixel layer;

[0033] The pixel layer is connected to the upper part of the substrate;

[0034] The pixel layer is etched to obtain at least one pixel unit, and the periphery of each pixel unit obtained by etching is surrounded by at least one annular groove, so that the annular groove at the outermost periphery of each pixel unit and the annular groove at the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with the compound semiconductor; or the compound semiconductor is reserved between the annular groove at the outermost periphery of each pixel unit and the annular groove at the outermost periphery of the adjacent pixel unit to completely separate each other;

[0035] An interconnecting conductive member is prepared in the pixel layer, so that the interconnecting conductive member is located at the edge of the corresponding pixel unit, and so that the interconnecting conductive member is at least partially located inside the annular groove closest to the corresponding pixel unit;

[0036] The bottom of the pixel unit is electrically connected with the corresponding first type of electrode contact, and the top of the pixel unit is electrically connected with the corresponding second type of electrode contact through the interconnecting conductive member.

[0037] In one embodiment of the present application, when the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

[0038] In one embodiment of the present application, when the top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnection conductive member, the method comprises,

[0039] A second electrode filling hole is formed in the compound semiconductor layer, and the second electrode filling hole penetrates through the bonding layer;

[0040] A metal is filled in the second electrode filling hole to form an interconnection conductive member, the interconnection conductive member is located at the edge of each corresponding pixel unit, and the interconnection conductive member is at least partially located inside the annular groove closest to the corresponding pixel unit;

[0041] The top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnection conductive member.

[0042] The above technical solutions of the present application have the following advantages compared with the prior art:

[0043] The LED display device provided by the present application has good heat dissipation capacity, can make the LED display device emit light stably, better guarantees the photoelectric performance and reliability of the LED display device, and prolongs the working life of the LED display device. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in combination with the accompanying drawings.

[0045] Figure 1 is a structural schematic diagram of an LED display device in the prior art;

[0046] Figure 2 is a top view schematic diagram of an LED display device in the present application;

[0047] Figure 3 is Figure 2 is a partial enlarged view of FF in

[0048] Figure 4 is a partial cross-sectional view taken along Figure 2 in F2-F2;

[0049] Figure 5 is a partial cross-sectional view taken along Figure 2 in F1-F1;

[0050] Figure 6 is Figure 5 is a partial enlarged view of M1 in

[0051] Figure 7It is a schematic diagram of the structure of the second type of annular partition;

[0052] Figure 8 It is a structural diagram of the third type of annular partition groove;

[0053] Figure 9 It is a structural diagram of the fourth type of annular partition groove;

[0054] Figure 10 is a schematic structural diagram of the compound semiconductor layer in the present invention;

[0055] Figure 11 This is a bonding flow chart of the pixel layer and the driver wafer in the present invention;

[0056] Figure 12 yes Figure 2 The preparation flow chart of the LED display device shown;

[0057] Figure 13 It is a structural schematic diagram of the second LED display device in the present invention;

[0058] Figure 14 yes Figure 13 A schematic top view of the structure shown;

[0059] Figure 15 This is a schematic structural diagram of a third LED display device in the present invention;

[0060] Figure 16 yes Figure 15 A schematic top view of the structure shown;

[0061] Figure 17 This is a schematic structural diagram of a fourth LED display device in the present invention;

[0062] Figure 18 The present invention is Figure 17 The cross-sectional view obtained at G2-G2;

[0063] Figure 19 This is a schematic structural diagram of an LED display device having an annular partition groove with a certain etching depth in the present invention;

[0064] Figure 20 yes Figure 19 Schematic diagram of the internal structure at M3;

[0065] Figure 21 This is a schematic diagram of the structure of another LED display device in the form of an annular partition groove;

[0066] Figure 22 This is a schematic structural diagram of an LED display device in the present invention in which the display area is not provided with first-type electrode contacts;

[0067] Figure 23 is Figure 22 a top view layout of the LED display device shown in FIG. 1;

[0068] Figure 24 is a layout (top view) of driving display area on wafer in the present application;

[0069] Explanation of the drawing marks in the description:

[0070] 100, pixel unit; 101, first semiconductor layer; 102, active layer; 103, second semiconductor layer; 1031, electrical contact area;

[0071] 200, substrate; 201, display area; 202, first type of electrode contact; 203, second type of electrode contact;

[0072] 300, bonding layer; 301, first peripheral bar;

[0073] 400, pixel layer; 401, annular isolation groove; 4011, filling area; 40111, first filler; 40112, air isolation layer; 402, isolation wall; 403, etching barrier layer; 404, first insulating layer; 405, thin film cover layer; 4051, extension; 406, first reflective layer; 407, second type of electrode filling hole; 408, second insulating layer;

[0074] 500, ohmic contact layer;

[0075] 600, interconnection conductive piece;

[0076] 700, first conductive layer;

[0077] 800, peripheral electrode contact area; 900, interface;

[0078] 1000, second conductive layer; 10001, arc-shaped cover area; DETAILED DESCRIPTION

[0079] The present application will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present application and implement it. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present disclosure and its application or use.

[0080] In the description of the present application, it needs to be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0081] In the description of the present application, it needs to be understood that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0082] The LED display device in the prior art has the problem of poor heat dissipation effect. Therefore, the present application provides an LED display device to improve its heat dissipation capacity, so as to better ensure the photoelectric performance and reliability of the LED display device.

[0083] It should be noted that the compound semiconductor layer in the present application refers to a layer structure with a certain thickness prepared from a compound semiconductor material. Compound semiconductors generally refer to compounds formed by two or more elements, including crystalline inorganic compounds (such as III-V, II-VI compound semiconductors) and oxide semiconductors. The compound semiconductors involved in the present application are mainly light emitting diode epitaxial materials, such as InGaN ternary material system or AlGaInP quaternary material system, etc., which can cover the full wavelength range from ultraviolet, visible light and infrared, and the substrate material can be GaN, Si, SiC, Sapphire, GaAs, InP, etc.

[0084] Taking the field of Micro-LED as an example, some compound semiconductor materials involved in the present application are shown in Table 1. In some practical applications, the film layer of the compound semiconductor will be more complex, or there will be a situation of cross use of materials. Typical compound semiconductors mainly include P-type semiconductor material, N-type semiconductor material and MQW active quantum well sandwiched between them and other functional layers (barrier layer, confinement layer, waveguide layer, buffer layer, etc.):

[0085] Table 1 Compound Semiconductor Film Layer Material Table

[0086]

[0087] The related structure of the LED display device of the present application will be further described below in combination with the following specific embodiments.

[0088] Embodiment One

[0089] Referring to Figures 2-12 , the embodiment discloses an LED display device, comprising a substrate 200 and a pixel layer 400,

[0090] The substrate 200 is a driving wafer, and the driving wafer is provided with a first type of electrode contact 202 and a second type of electrode contact 203, the polarities of the first type of electrode contact 202 and the second type of electrode contact 203 are opposite, one of which is positive and the other of which is negative; it can be understood that the first type of electrode contact 202 and the second type of electrode contact 203 need to be insulated and isolated to prevent short circuit caused by direct contact between the two.

[0091] The pixel layer 400 is a compound semiconductor layer, and it can be understood that the above-mentioned compound semiconductor layer refers to a layer body with a certain thickness prepared from a compound semiconductor material.

[0092] Among them, the outermost peripheral annular isolation groove of each pixel unit and the outermost peripheral annular isolation groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area retains a compound semiconductor material area, that is, the outermost peripheral annular isolation groove of each pixel unit and the outermost peripheral annular isolation groove 401 of the adjacent pixel unit can share a part of the annular isolation groove, for example, as shown in Figure 2 , only one annular isolation groove 401 is arranged at the periphery of the pixel unit 100, and the annular isolation grooves of the adjacent two pixel units share a part;

[0093] Or, the outermost peripheral annular isolation groove of each pixel unit and the outermost peripheral annular isolation groove of the adjacent pixel unit can also be completely separated from each other by retaining a compound semiconductor, that is, the outermost peripheral annular isolation grooves of the adjacent two pixel units are completely non-overlapping and separated from each other, and the separated area retains the original compound semiconductor material area. For example, as shown in Figure 17 , the outermost peripheral annular isolation grooves of the adjacent two pixel units are completely non-overlapping and separated from each other, and the separated area retains the original compound semiconductor material area Q1.

[0094] Among them, the top of each pixel unit 100 is electrically connected to the corresponding second type of electrode contact 203, and the bottom of the pixel unit 100 is electrically connected to the corresponding first type of electrode contact 202;

[0095] like Figure 4 As shown, the above-mentioned LED display device also includes an interconnecting conductive member 600. The top of each pixel unit 100 is electrically connected to the corresponding second-type electrode contact 203 through the interconnecting conductive member 600. The interconnecting conductive member 600 is located at the edge of each corresponding pixel unit 100, and the interconnecting conductive member 600 is at least partially located inside the annular partition 401 closest to the corresponding pixel unit.

[0096] It is understandable that the top and bottom of the pixel unit 100 are two ends of opposite polarity. For example, the top is the end where the N-type semiconductor is located (or the end where the P-type semiconductor is located), and the bottom is the end where the P-type semiconductor is located (or the end where the N-type semiconductor is located), and they need to be connected to electrode contacts of different polarities. Among them, the correspondence between the pixel unit and the electrode contact (first type electrode contact or second type electrode contact) can be one-to-one or one-to-many. For example, one second type electrode contact can correspond to one pixel unit, or multiple second type electrode contacts can correspond to one pixel unit. Similarly, the same applies to the first type electrode contact.

[0097] The interconnecting conductive member 600 is arranged at the edge of the corresponding pixel unit 100 so that the interconnecting conductive member 600 is at least partially located inside the annular partition 401 closest to the corresponding pixel unit. This is particularly suitable for the preparation of display chips with relatively large pixel sizes and is conducive to enhancing the current transmission effect.

[0098] The above-mentioned driving wafer is an element with a driving circuit. The first type of electrode contact 202 and the second type of electrode contact 203 are the lead-out terminals of the driving circuit, which are used to electrically connect the driving circuit and the pixel unit. The pixel unit 100 is a light-emitting element. The pixel unit 100 can be controlled to emit light through the electrical connection between the driving wafer and the pixel unit 100.

[0099] The aforementioned driver wafer includes but is not limited to a CMOS (Complementary Metal Oxide Semiconductor) driver backplane or a TFT glass substrate.

[0100] The above structure can electrically connect the driver wafer to the pixel unit 100 by disposing the first type electrode contact 202 and the second type electrode contact 203 , so as to control each pixel unit 100 to emit light by using the driver wafer.

[0101] The shapes of the first type electrode contact 202 and the second type electrode contact 203 are not limited and may be circular, elongated or other shapes.

[0102] In some preferred embodiments, each pixel unit 100 in the pixel layer 400 can emit light independently.

[0103] As shown in FIG. 1, in the prior art, when the pixel unit 100 is prepared, a large amount of compound semiconductor material around the pixel unit 100 needs to be etched and removed, and then the insulating medium material G1 is filled to realize the independence of the pixel unit 100. However, the thermal conductivity of the insulating medium material is lower than that of the original compound semiconductor, so that the heat generated by the device cannot be timely transmitted, resulting in an increase in the temperature of the device, thereby greatly reducing the photoelectric performance and reliability of the device. Figure 1 As shown in FIG. 1, in the prior art, when the pixel unit 100 is prepared, a large amount of compound semiconductor material around the pixel unit 100 needs to be etched and removed, and then the insulating medium material G1 is filled to realize the independence of the pixel unit 100. However, the thermal conductivity of the insulating medium material is lower than that of the original compound semiconductor, so that the heat generated by the device cannot be timely transmitted, resulting in an increase in the temperature of the device, thereby greatly reducing the photoelectric performance and reliability of the device.

[0104] Table 2: Comparison table of thermal conductivities of different materials

[0105]

[0106] As shown in Table 2, among the three materials of insulating medium, compound semiconductor and metal, the thermal conductivity of the metal material is higher than that of the compound semiconductor material, and the thermal conductivity of the compound semiconductor material is higher than that of the insulating medium material.

[0107] As shown in FIG. 1, in the prior art, when the pixel unit 100 is prepared, a large amount of compound semiconductor material around the pixel unit 100 needs to be etched and removed, and then the insulating medium material G1 is filled to realize the independence of the pixel unit 100. However, the thermal conductivity of the insulating medium material is lower than that of the original compound semiconductor, so that the heat generated by the device cannot be timely transmitted, resulting in an increase in the temperature of the device, thereby greatly reducing the photoelectric performance and reliability of the device. Figures 2-5 As shown in FIG. 1, in the prior art, when the pixel unit 100 is prepared, a large amount of compound semiconductor material around the pixel unit 100 needs to be etched and removed, and then the insulating medium material G1 is filled to realize the independence of the pixel unit 100. However, the thermal conductivity of the insulating medium material is lower than that of the original compound semiconductor, so that the heat generated by the device cannot be timely transmitted, resulting in an increase in the temperature of the device, thereby greatly reducing the photoelectric performance and reliability of the device.

[0108] It should be noted that, Figure 4 only when arranged in the form shown in FIG. 1, a cross-sectional view of one pixel unit and its peripheral structure obtained along the F2-F2 section. Figure 2 only when arranged in the form shown in FIG. 1, a cross-sectional view of one pixel unit and its peripheral structure obtained along the F2-F2 section. Figure 2 only when arranged in the form shown in FIG. 1, a cross-sectional view of one pixel unit and its peripheral structure obtained along the F2-F2 section. Figure 5 only when arranged in the form shown in FIG. 1, a cross-sectional view of one pixel unit and its peripheral structure obtained along the F2-F2 section. Figure 2 only when arranged in the form shown in FIG. 1, a cross-sectional view of one pixel unit and its peripheral structure obtained along the F2-F2 section. Figure 2 only when arranged in the form shown in FIG. 1, a cross-sectional view of one pixel unit and its peripheral structure obtained along the F2-F2 section.

[0109] In the present application, the "width" direction is the X direction, the "height" or "up-down" direction is the Z direction, and there is also a Y direction, wherein the X direction, the Y direction, and the Z direction are perpendicular to each other. The pixel layer 400 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom. The Z direction is the stacking direction of the first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103.

[0110] In some embodiments, a portion of the interconnection conductive member 600 is located inside each corresponding pixel unit 100, and the remaining portion extends at least to the annular groove 401 closest to the pixel unit. For example, when the pixel unit 100 has two annular grooves 401 on the periphery, a portion of the interconnection conductive member 600 is located inside the corresponding pixel unit 100, and the remaining portion is at least partially located in the annular groove 401 closest to the pixel unit 100 on the periphery of the pixel unit 100, and can further extend into the second annular groove 401.

[0111] In the present application, the "width" direction is the X direction, the "height" or "up-down" direction is the Z direction, and there is also a Y direction, wherein the X direction, the Y direction, and the Z direction are perpendicular to each other. The pixel layer 400 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom. The Z direction is the stacking direction of the first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103.

[0112] Further, in the specific arrangement, each pixel unit 100 and the corresponding second electrode contact 203 can adopt the following arrangement:

[0113] The second electrode contact 203 is located at the edge of the first projection area of the corresponding pixel unit 100, and at least part of the second electrode contact is located inside the second projection area closest to the periphery of the corresponding pixel unit, i.e., at least part of the second electrode contact is located inside the second projection area closest to the first projection area of the corresponding pixel unit.

[0114] Further, a portion of the second electrode contact 203 is located inside the first projection area of the corresponding pixel unit, and the remaining portion extends at least to the inside of the second projection area closest to the first projection area.

[0115] For example, Figures 2-3As shown in FIG. 1, each pixel unit 100 corresponds to 4 second-type electrode contacts 203, and each pixel unit 100 has a ring-shaped isolation groove 401 in the periphery, so that each pixel unit 100 corresponds to a first projection area and a second projection area. At this time, each of the 4 second-type electrode contacts 203 only has a part inside the first projection area of the corresponding pixel unit, and the remaining part is in the second projection area in the periphery of the pixel unit.

[0116] In other cases, as shown in FIG. 2, each pixel unit 100 has two ring-shaped isolation grooves 401 in the periphery, so that each pixel unit 100 corresponds to a first projection area and two second projection areas. At this time, each of the 4 second-type electrode contacts 203 only has a part inside the first projection area of the corresponding pixel unit, and at least one part of the remaining part is in the second projection area in the periphery of the pixel unit and closest to (adjacent to) the pixel unit. Figure 17

[0117] In other ways, the second-type electrode contacts 203 are located at the edge of the first projection area of the corresponding pixel unit 100 and completely inside the first projection area or inside the second projection area.

[0118] In some embodiments, a plurality of second-type electrode contacts 203 are arranged at the edge of each first projection area, and the plurality of second-type electrode contacts 203 are arranged in a ring shape. For example, as shown in FIG. 3, each pixel unit 100 corresponds to 4 second-type electrode contacts 203, which are electrically connected to the top of the pixel unit 100. The 4 second-type electrode contacts 203 are arranged in a ring shape around the center of the pixel unit 100, and each of the 4 second-type electrode contacts is located at the edge of the projection area (the first projection area) of the pixel unit on the substrate 200. Figures 2-3

[0119] Through the arrangement of the plurality of second-type electrode contacts 203, the current spreading can be better realized, and the current intensity can be improved.

[0120] In some embodiments, a first-type electrode contact 202 is arranged inside each first projection area, and the first-type electrode contact 202 is surrounded by a plurality of second-type electrode contacts 203 arranged at the edge of the first projection area. For example, as shown in FIG. 4, a first-type electrode contact 202 is located at the center of the pixel, and the first-type electrode contact 202 is surrounded by a plurality of second-type electrode contacts 203 in the periphery. Figures 2-3

[0121] In some embodiments, as shown in FIG. 5, a first-type electrode contact 202 is arranged at the center of each pixel unit 100, and the first-type electrode contact 202 is surrounded by a plurality of second-type electrode contacts 203 in the periphery. Figure 4 and​​​Figure 5 As shown, the inner wall of the annular isolation groove 401 is covered with a first insulating layer 404, and the interior of the annular isolation groove 401 has a filling area 4011, the periphery of which is surrounded by the first insulating layer 404 at the inner wall of the annular isolation groove, and the filling area 4011 contains an air isolation layer 40112 composed of air, or the filling area 4011 is filled with a first filler 40111 to form a solid structure.

[0122] The first filler 40111 can be an insulating medium or metal, etc.

[0123] The first insulating layer 404 covering the inner wall of the annular isolation groove 401 can better isolate the pixel unit 100 and prevent the phenomenon of electric leakage.

[0124] It should be noted that the inner wall of the annular isolation groove 401 includes a side wall and a bottom surface, both of which are covered with the first insulating layer 404, and when the air isolation layer 40112 in the interior of the filling area 4011 has an air isolation layer 40112, the bottom surface position of the air isolation layer 40112 is not lower than the bottom surface of the annular isolation groove 401.

[0125] It can be understood that in some ways, the pixel unit 100 and the annular isolation groove 401 adjacent to the periphery share a side wall, and the first insulating layer 404 at the side wall is also shared by both.

[0126] The first insulating layer 404 can be a transparent material.

[0127] For example, the first insulating layer 404 can be one or more of a silicon oxide, an aluminum oxide, a silicon nitride, a titanium oxide, a hafnium oxide, a tantalum oxide, a niobium oxide, an aluminum nitride, a gallium nitride, etc. medium layer, constituting a single-layer structure or a laminated structure composed of multiple.

[0128] For example, the first insulating layer 404 can be a laminated structure of silicon oxide and titanium oxide, and a DBR (distributed Bragg reflector) Bragg reflection structure is constructed by using the refractive index difference of the two materials.

[0129] In some embodiments, the thickness of the first insulating layer 404 is 5nm-2um.

[0130] Further, the thickness of the first insulating layer 404 is 5nm-1um, and when the filler has an air isolation layer 40112, the maximum size L3 of the air isolation layer 40112 in the width direction (X direction) can be 0.01um-8um.

[0131] In some embodiments, as Figure 20As shown, the width L1 of the pixel unit 100 is 0.2 um to 80 um. The width of the pixel unit 100 can be understood as the maximum dimension of the pixel unit 100 along the width direction (X direction).

[0132] Further, the height h1 of the pixel unit 100 is 0.1 um to 5 um. The height of the pixel unit 100 refers to the distance between the upper surface of the first semiconductor layer 101 and the lower surface of the second semiconductor layer 103 in the pixel unit.

[0133] The shape of the pixel unit 100 described above includes but is not limited to a circle, an ellipse, a polygon, and other shapes, and is preferably a circle, a quadrilateral, and a hexagon.

[0134] In some embodiments, as shown, the top of each pixel unit 100 has an electrical contact area 1031, and the top of the pixel unit 100 is electrically connected through the electrical contact area 1031 and the upper end of the interconnection conductive member 600. Figure 4

[0135] For example, the electrical contact area 1031 and the upper end of the interconnection conductive member 600 can be connected through a conductive structure, and the electrical contact area 1031 and the interconnection conductive member 600 are both in contact with the conductive structure to achieve electrical connection. The conductive structure can be the first conductive layer 700, the second conductive layer 1000, or other conductive structures described in the present application.

[0136] In some embodiments, the upper part of the pixel unit 100 is at least partially covered by the first insulating layer 404, and the area not covered by the first insulating layer 404 forms the electrical contact area 1031.

[0137] For example, the upper part of the pixel unit 100 is further covered by the first conductive layer 700, and the first insulating layer 404 on the upper part of the pixel unit 100 is at least partially covered by the first conductive layer 700 above; wherein the middle area of the top surface of the pixel unit 100 forms the electrical contact area 1031, and the top of the electrical contact area 1031 of the pixel unit 100 and the top of the interconnection conductive member 600 are both in contact with the same first conductive layer 700.

[0138] The first conductive layer 700 described above can be a transparent conductive layer.

[0139] For example, the transparent conductive layer described above can use one or more of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, or gold-doped indium tin oxide.

[0140] Further, as shown, Figure 2 and Figure 17 ​As shown (the oblique hatched area in the figure is the region of the first conductive layer 700), the pixel unit 100 and the first conductive layer 700 can be one-to-one corresponding, and the first conductive layers 700 of adjacent pixel units 100 are mutually spaced apart.

[0141] In this embodiment, the pixel layer 400 and the substrate 200 are bonded through the bonding layer 300, and the bottom surface of the annular groove 401 is not lower than the upper surface of the bonding layer 300.

[0142] For example, as shown, the bonding layer 300 adopts a conductive metal layer, and the upper part of the bonding layer 300 is formed with a first peripheral fence 301, and the inside of the first peripheral fence 301 is provided with an interconnection conductive piece 600, and the first peripheral fence 301 and the interconnection conductive piece 600 inside are isolated by a second insulating layer 408. The second insulating layer 408 can be arranged at the inner wall of the first peripheral fence 301. Figure 4

[0143] In addition, since the first type of electrode contact 202 can also be connected on the bonding layer 300, through the arrangement of the second insulating layer 408, the second type of electrode contact 203 and the first type of electrode contact 202 are insulated and isolated, so as to avoid short circuit.

[0144] Further, the outer wall of the first peripheral fence 301 can also be coated with a first insulating layer 404.

[0145] The bonding layer 300 can be one or more of Ni, Sn combination, Au, Sn combination, Cu, Sn combination, Au, In combination, Au, Au combination, Al, Al combination, Cu, Cu combination or ITO, ITO combination. The bonding layer 300 and the driving wafer can also be provided with an adhesion layer (such as Cr, Ti, Ni, etc.) and a barrier depletion layer (such as Ni, Pt, Cu, etc.).

[0146] In some preferred modes, the bonding layer 300 can be a multi-layer structure stacked in the height direction, and the layers from bottom to top are Cr layer (adhesion layer), Pt layer (barrier depletion layer), Au layer, Sn layer, Au layer, and the thicknesses are 10 nm, 50 nm, 100 nm, 150 nm and 50 nm respectively.

[0147] For example, the second insulating layer 408 can be one or more of a medium layer such as silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, aluminum nitride, gallium nitride, etc., constituting a single-layer structure or a stacked structure composed of multiple layers.

[0148] In some embodiments, the thickness of the second insulating layer 408 can be 5 nm to 2 um to ensure the insulation and isolation effect.

[0149] ​In some embodiments, the interconnection conductive member 600 is made of a metal member.

[0150] Since the metal member has a high thermal conductivity, the interconnection conductive member 600 of the above structure can further improve the heat dissipation effect of the LED display device.

[0151] In the embodiment, as shown in FIG. 1, the pixel layer 400 includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom. It can be understood that the pixel unit 100 is obtained by etching on the pixel layer 400, and each pixel unit 100 also includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom. Figure 10

[0152] The second type of electrode contact 203 is used to electrically connect with the first semiconductor layer 101 in the corresponding pixel unit 100, and the first type of electrode contact 202 is used to electrically connect with the second semiconductor layer 103 in the corresponding pixel unit 100.

[0153] In the embodiment, one of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. The active layer 102 is used for light emission and can be an MQW active quantum well.

[0154] In some embodiments, the lower end of the annular groove 401 extends between the lower surface of the active layer 102 and the upper surface of the substrate 200, and the upper end of the annular groove 401 extends at least to the upper surface of the first semiconductor layer 101.

[0155] Further, the minimum size of the annular groove 401 along the width direction (X direction) is greater than 0, and the maximum size of the annular groove 401 along the width direction (X direction) is L2, and L2 is 0.02um-10um. The width should not be too large in order to maximize the retention of semiconductor materials in the compound semiconductor layer and improve the heat dissipation effect. Also, the width should not be too small, otherwise it will be not conducive to processing and ensuring effective separation between the pixel units 100, and the light emission effect will also be affected by the too small width.

[0156] In some embodiments, the top of the pixel layer 400 is provided with a lens, and the lens covers at least one pixel unit 100. That is, the lens can correspond to one-to-one pixel units 100, or multiple pixel units 100 can correspond to one lens.

[0157] The material of the lens can be an insulating material. For example, the lens can be made of materials such as silicon oxide, silicon nitride, aluminum oxide, silicate glass, PMMA, silicone substance or SU8.

[0158] ​The LED display device of the above embodiment is controllable in addressing the top of each pixel unit, and can be addressed and lighted.

[0159] The embodiment also discloses a preparation method of the LED display device, comprising the following steps:

[0160] Step S1: selecting a driving wafer as the substrate 200, the driving wafer being provided with opposite first electrode contacts 202 and second electrode contacts 203; and selecting a compound semiconductor layer as the pixel layer 400, the structure of the compound semiconductor layer referring to Figure 10 , the compound semiconductor layer comprising a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom;

[0161] Step S2: connecting the pixel layer 400 to the upper part of the substrate 200 as shown in Figure 11 .

[0162] Step S3: etching the pixel layer 400 to obtain at least one pixel unit 100 as shown in Figure 12 , each pixel unit 100 obtained by etching being surrounded by at least one annular isolation groove 401, so that the annular isolation groove 401 at the outermost periphery of each pixel unit and the annular isolation groove 401 at the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with the compound semiconductor; or, the annular isolation groove 401 at the outermost periphery of each pixel unit and the annular isolation groove 401 at the outermost periphery of the adjacent pixel unit are reserved with the compound semiconductor to be completely separated from each other.

[0163] The interconnection conductive member 600 is prepared in the pixel layer 400, so that the interconnection conductive member 600 is located at the edge of the corresponding pixel unit 100, and so that the interconnection conductive member 600 is at least partially located inside the outermost adjacent annular isolation groove 401 of the corresponding pixel unit 100.

[0164] So that the bottom of each pixel unit 100 is electrically connected with the corresponding first electrode contact 202, and so that the top of each pixel unit 100 is electrically connected with the corresponding second electrode contact 203 through the interconnection conductive member 600.

[0165] Further, when the pixel layer 400 is connected to the upper part of the substrate 200 in step S2, the pixel layer 400 is connected to the substrate 200 through the bonding layer 300.

[0166] When the pixel layer 400 and the substrate 200 are connected through the bonding layer 300, a hot-press bonding method can be used.

[0167] In some embodiments, when the top of each pixel unit 100 is electrically connected to the interconnection conductive member 600 and the corresponding second-type electrode contact 203 in step S3, a second-type electrode filling hole 407 is formed in the compound semiconductor layer, so that the second-type electrode filling hole 407 penetrates the bonding layer 300; and the interconnection conductive member 600 is formed by filling metal in the second-type electrode filling hole 407, so that the interconnection conductive member 600 is located at the edge of each corresponding pixel unit 100, part of the interconnection conductive member 600 is located inside each corresponding pixel unit 100, and the remaining part at least extends into the nearest annular isolation groove 401; after the interconnection conductive member 600 is prepared, the top of each pixel unit 100 is electrically connected to the top of the interconnection conductive member 600, so that the top of the pixel unit 100 can be electrically connected through the interconnection conductive member 600 and the corresponding second-type electrode contact 203.

[0168] In some embodiments, step S3 can specifically include the following steps:

[0169] Step S31: An etching stop layer 403 is arranged on the upper surface of the pixel layer 400, and the etching stop layer 403 is etched to obtain a patterned mask layer;

[0170] Step S32: As Figure 12 in stage c, the pixel layer 400 is etched by the mask layer to obtain at least one pixel unit 100, and at least one annular isolation groove 401 is formed at the periphery of each pixel unit 100, so that the outermost annular isolation groove 401 of each pixel unit at least partially overlaps with the outermost annular isolation groove 401 of the adjacent pixel unit, and the non-overlapping area is reserved with the compound semiconductor; or,

[0171] so that the outermost annular isolation groove 401 of each pixel unit and the outermost annular isolation groove 401 of the adjacent pixel unit are completely separated from each other by the compound semiconductor;

[0172] When the pixel layer 400 is etched by the mask layer, the second-type electrode filling hole 407 can also be etched above the second-type electrode contact 203, that is, the second-type electrode filling hole 407 is directly etched in the compound semiconductor layer at this time;

[0173] For example, the angle a of the pixel unit 100 obtained by etching can be 90°±45°, and preferably, the angle a of the pixel unit 100 can be 90°±20°. Wherein, the angle a of the pixel unit 100 is the maximum angle between the side wall of the pixel unit 100 and the upper surface of the substrate 200.

[0174] Step S33: As Figure 12In the middle d stage, the first insulating layer 404 is deposited on the surface of the pixel layer 400, so that the first insulating layer 404 covers the inner wall of the annular isolation groove 401 and the sidewall of the pixel unit 100, and the inside of the annular isolation groove 401 forms a filling area 4011 surrounded by the first insulating layer 404;

[0175] At this time, the inner wall of the second electrode filling hole 407 and the upper surface of the pixel layer 400 are also covered with the first insulating layer 404;

[0176] Step S34: as Figure 12 In the middle e stage, the material at the bottom of the second electrode filling hole 407 is removed, so that the second electrode filling hole 407 penetrates through the bonding layer 300 to expose the second electrode contact 203; it can be understood that this step is to remove all the material between the second electrode filling hole 407 and the bottom second electrode contact 203 to expose the second electrode contact 203;

[0177] Step S35: as Figure 12 In the middle f stage, the second insulating layer 408 is deposited on the inner wall of the second electrode filling hole 407;

[0178] Step S36: as Figure 12 In the middle g stage, the metal is filled in the second electrode filling hole 407 to form the interconnection conductive piece 600, so that the interconnection conductive piece 600 is located at the edge of the corresponding pixel unit 100; specifically, the interconnection conductive piece 600 can be partially located inside each corresponding pixel unit 100, and the remaining part at least extends into the adjacent annular isolation groove 401;

[0179] The interconnection conductive piece 600 obtained in this way is a metal piece;

[0180] Step S37: as Figure 12 In the middle h stage, the top of each pixel unit 100 is electrically connected through the interconnection conductive piece 600 and the corresponding second electrode contact 203. For example, the top of the pixel unit 100 is connected to the top of the interconnection conductive piece 600 through the first conductive layer 700.

[0181] After step S37, step S38 is further performed: a lens is prepared on the top of the pixel layer 400, and the lens corresponds to one pixel unit 100 or one lens corresponds to multiple pixel units 100.

[0182] When the lens is prepared: the insulating medium layer can be backfilled first, and then the backfilled insulating medium layer is patterned and etched to form the lens; or after the insulating medium layer is backfilled, CMP planarization is performed first, and then the lens material is coated and patterned to form the lens.

[0183] In some embodiments, an ohmic contact layer 500 is further arranged between the pixel layer 400 and the bonding layer 300. When the pixel layer 400 is etched with a mask layer in step S32, the ohmic contact layer 500 can be etched to the inside of the ohmic contact layer but above the lower surface of the ohmic contact layer.

[0184] In some embodiments, the width of the second electrode filling hole 407 can be 0.1 um to 10 um. Here, the width of the second electrode filling hole 407 can be understood as the maximum dimension of the second electrode filling hole 407 in the width direction (X direction).

[0185] In some embodiments, after the filling area 4011 is formed inside the annular groove 401 and surrounded by the first insulating layer 404 in step S33, air is retained in the filling area 4011 to form an air isolation layer 40112, that is, the filling area 4011 has a hollow structure, or the filling area 4011 is filled with a first filler 40111 to form a solid structure.

[0186] In some embodiments, the bonding layer 300 can be made of metal. When the second electrode filling hole 407 is formed to expose the second electrode contact 203 by removing the material at the bottom of the second electrode filling hole 407 in step S34, a metal fence, i.e., a first peripheral fence 301, is formed on the upper part of the bonding layer 300. The second insulating layer 408 deposited in step S35 is located on the inner wall of the first peripheral fence 301, and the interconnection conductive member 600 is located inside the first peripheral fence 301, so that the first peripheral fence 301 and the interconnection conductive member 600 are insulated and separated by the second insulating layer 408.

[0187] Further, the top surface of the interconnection conductive member 600 can be higher than the first peripheral fence 301, and the height of the second insulating layer 408 can be the same as that of the interconnection conductive member 600, so as to better ensure the insulation and separation effect.

[0188] In some embodiments, the bonding layer 300 is made of a metal layer, and a first dielectric layer is further arranged between the pixel layer 400 and the bonding layer 300. The first dielectric layer is a low refractive index layer, and the bonding layer 300 can be made of a high reflectivity metal layer to form an ODR (Omni Directional Reflector) structure, thereby better improving the brightness of the device.

[0189] In some embodiments, the thickness of the first dielectric layer is 0.01 um to 0.5 um.

[0190] For example, the first dielectric layer can include one or more of silicon oxide, silicon nitride, aluminum oxide, or magnesium fluoride, which all have a low refractive index. Of course, other materials with a low refractive index can also be used.

[0191] The above-mentioned LED display devices include but are not limited to Micro-LED, Micro-Laser and other display devices.

[0192] The LED display device obtained in the above embodiment realizes the independence of the pixel unit by means of annular partition grooves, and directly prepares the interconnecting conductive parts on the compound semiconductor layer, thereby retaining the compound semiconductor material to the greatest extent, thereby greatly increasing the heat conduction area of ​​the entire device, thereby effectively reducing the heat accumulation problem of the pixel unit, greatly reducing the operating temperature of the LED display device, and better ensuring the optoelectronic performance and reliability of the LED device.

[0193] Example 2

[0194] This embodiment will combine Figure 4 , Figures 13-16 , further describes the relevant structure of the LED display device of this application.

[0195] In this embodiment, each pixel unit 100 has an electrical contact region 1031 on the top thereof, so as to achieve electrical connection through the electrical contact region 1031 and the upper end of the interconnection conductive member 600 .

[0196] Exemplarily, the electrical contact region 1031 and the upper end of the interconnecting conductive member 600 are connected via a conductive structure. Both the electrical contact region 1031 and the interconnecting conductive member 600 are in contact with the conductive structure to achieve electrical connection. The conductive structure may be arranged in the following manners:

[0197] First way:

[0198] The upper portion of the pixel unit 100 is at least partially covered by the first insulating layer 404 , and the area not covered by the first insulating layer 404 forms an electrical contact region 1031 .

[0199] Among them, Figure 4 As shown, the upper portion of the pixel unit 100 is also covered with a first conductive layer 700, the first insulating layer 404 on the upper portion of the pixel unit 100 is at least partially covered by the first conductive layer 700, an electrical contact region 1031 is formed in the middle portion of the top surface of the pixel unit 100, and the electrical contact region 1031 of the pixel unit 100 and the interconnected conductive member 600 at the edge of the pixel unit 100 are both in contact with the same first conductive layer 700 to achieve electrical connection.

[0200] Preferably, the first conductive layer 700 may be a transparent conductive layer.

[0201] It is understandable that a thin film cover layer 405 or other layers may be further provided between the first conductive layer 700 and the first insulating layer 404 on the upper portion of the pixel unit 100 .

[0202] Second way:

[0203] The upper portion of the pixel unit 100 is at least partially covered by the first insulating layer 404 , and the area not covered by the first insulating layer 404 forms an electrical contact region 1031 .

[0204] in, Figure 14 yes Figure 13 A top view of the structure shown, Figure 13 It is along Figure 14 The cross-sectional view at O1-O1 is as follows: Figures 13-14 As shown, in this method, the top of each interconnected conductive member 600 at the edge of the pixel unit 100 is respectively connected to the second conductive layer 1000, all the second conductive layers 1000 corresponding to each pixel unit are separated from each other and arranged non-continuously, and each interconnected conductive member 600 at the edge of the pixel unit is in contact with the corresponding electrical contact area 1031 through its own second conductive layer 1000.

[0205] That is, in this manner, each pixel unit 100 corresponds to a plurality of second conductive layers 1000 , and the second conductive layers 1000 and the electrical contact regions 1031 may correspond one to one.

[0206] In some embodiments, the second conductive layer 1000 can be made of one or more materials selected from the group consisting of Cr, Pt, Ni, Al, Ti, and Au.

[0207] Furthermore, arc-shaped covering areas 10001 are formed at the contact areas between the second conductive layer 1000 and the interconnecting conductive element 600 . The arc-shaped covering areas 10001 at least cover the top surface area of ​​the interconnecting conductive element 600 inside the pixel unit 100 to better ensure the reliability of the electrical connection.

[0208] The third way:

[0209] Figure 16 yes Figure 15 A top view of the structure shown, Figure 15 It is along Figure 16 The cross-sectional view at O2-O2 in the figure is as follows: Figures 15-16 As shown, in this method, a second conductive layer 1000 is provided on the upper part of the pixel unit 100, and the second conductive layer 1000 is arranged in a ring shape. The top surfaces of all interconnected conductive members 600 at the edge of the pixel unit are in contact with the same second conductive layer 1000. This method can better enhance the current expansion capability and increase the current intensity.

[0210] It can be understood that the second conductive layer 1000 can be in the shape of a circular ring, a rectangular ring or other forms of ring structures.

[0211] Furthermore, arc-shaped covering areas 10001 are formed at the contact areas between the second conductive layer 1000 and the interconnecting conductive element 600 . The arc-shaped covering areas 10001 at least cover the top surface area of ​​the interconnecting conductive element 600 inside the pixel unit 100 to better ensure the reliability of the electrical connection.

[0212] It is understandable that in the above methods, the top surface of the pixel unit 100 can be roughened to form an uneven surface, thereby reducing total reflection and increasing light extraction rate, thereby improving the brightness of the LED display device.

[0213] In all of the above methods, a metal grid can be provided on the upper portion of the first conductive layer 700 or the second conductive layer 1000 to achieve better current expansion, and can also further increase the heat conduction capability and improve the reliability of the LED display device.

[0214] The metal grid can be made of one or more materials selected from the group consisting of Pt, Ni, Al, Ti and Au.

[0215] Example 3

[0216] This embodiment will combine Figures 5-9 , the relevant structure of the LED display device of this application is further described. Among them, Figures 6-9 for Figure 5 Schematic diagram of different configurations of the annular partition 401 at M1.

[0217] In the present application, each pixel unit 100 is provided with an annular partition groove 401 on its periphery, and a filling area 4011 is provided inside the annular partition groove 401. The periphery of the filling area 4011 is surrounded by a first insulating layer 404 on the inner wall of the annular partition groove 401. Air can be contained in the filling area 4011 to form an air barrier 40112, or the filling area 4011 can be filled with a first filler 40111 to form a solid structure. The structural forms can be as follows.

[0218] The first structural form:

[0219] A first insulating layer 404 is provided on the upper portion of the pixel layer 400. The first insulating layer 404 covers the upper surface of each light emitting area of ​​the pixel unit 100 and the inner wall of the annular partition 401. Figures 5-6 As shown, a thin film cover layer 405 is also covered on the upper part of the pixel layer 400 , the upper part of the filling area 4011 is enclosed by the thin film cover layer 405 , and the first insulating layer 404 at the upper surface of the pixel unit 100 is located below the thin film cover layer 405 .

[0220] Preferably, the thin film covering layer 405 may be an insulating medium.

[0221] In some embodiments, the thin film covering layer 405 further includes a downwardly protruding extension portion 4051 , wherein the extension portion 4051 extends into the filling region 4011 ;

[0222] Among them, such as Figure 6 As shown, the extension portion 4051 may only extend into the upper portion of the filling area 4011 , so that a hollow portion remains at the lower portion of the filling area 4011 , thereby forming the above-mentioned air barrier 40112 at the lower portion of the filling area 4011 .

[0223] Or, as Figure 7 As shown, the extension portion 4051 serves as the first filler 40111, and the filling area 4011 is filled with the first filler 40111 to form a solid structure. The material of the first filler 40111 is the same as that of the thin film covering layer 405, both of which are insulating media.

[0224] Furthermore, when the filler has an air barrier layer 40112 inside, the minimum dimension of the air barrier layer 40112 along the width direction needs to be greater than 0, and the maximum dimension L3 of the air barrier layer 40112 along the width direction can be 0.01um to 8um.

[0225] The thin film cover layer 405 may be made of one or more insulating materials such as silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, and polyimide.

[0226] In some embodiments, the sidewalls of the pixel unit 100 are also covered with a first insulating layer 404 to ensure insulation between the first semiconductor layer 101 and the second semiconductor layer 103 in the pixel unit 100. The upper portion of the pixel unit 100 is at least partially covered with the first insulating layer 404. The first insulating layer 404 on the upper portion of the pixel unit 100 is located below the thin film covering layer 405.

[0227] In some embodiments, the thickness of the thin film cover layer 405 is 0.05 μm to 8 μm. It is understood that the thickness of the thin film cover layer 405 here refers to the thickness of the thin film cover layer 405 on the top of the pixel unit 100 , excluding the extension portion 4051 .

[0228] The first insulating layer 404 and the thin film cover layer 405 may both be transparent material layers.

[0229] The second structural form:

[0230] like Figure 9As shown, this method does not require the thin film covering layer 405, and only the first insulating layer 404 is provided on the upper part of the pixel layer 400. A gap is retained in the filling area 4011 inside the annular partition 401 to accommodate air to form an air partition layer 40112, that is, a filling area 4011 with a hollow structure is formed; or, the filling area 4011 is filled with a first filler 40111 to form a solid structure.

[0231] The first filler 40111 may be an insulating medium or metal.

[0232] For example, the filling area 4011 may be directly filled with the material of the first insulating layer 404 ; of course, a filler made of a material different from that of the first insulating layer 404 may also be used to fill the filling area 4011 .

[0233] The third structural form:

[0234] like Figure 8 As shown, in this method, the inner wall of the annular groove 401 is sequentially covered with a first insulating layer 404 and a first reflective layer 406. That is, the first reflective layer 406 is further provided outside the first insulating layer 404 on the inner wall of the annular groove 401, so that air is placed in the filling area 4011 to form an air barrier layer 40112, and the first reflective layer 406 surrounds the outer periphery of the air barrier layer 40112.

[0235] Alternatively, the first reflective layer 406 serves as the first filler 40111 , and the filling area 4011 is filled with the first filler 40111 to form a solid structure.

[0236] The first reflective layer 406 may be a reflective metal layer, for example, a single layer or stacked layers of highly reflective metals such as Al, Ag and Au, to form an omnidirectional reflector (ODR) structure, thereby better preventing optical crosstalk between pixels.

[0237] In the various structural forms described above, an etching stop layer 403 may be provided on the upper surface of each pixel unit 100 . When a first insulating layer 404 is provided on the top of the pixel unit 100 , the first insulating layer 404 is located above the etching stop layer 403 .

[0238] The etching stop layer 403 may be a transparent material layer.

[0239] Exemplarily, the above-mentioned etching stop layer 403 can be a mask made of materials such as silicon oxide and silicon nitride, or a contact layer made of materials such as ITO and metal, or a stack on the dielectric layer below the contact layer. In addition to forming contact with the first semiconductor layer 101 (such as ohmic contact), this film layer is mainly used as a mask for graphical etching.

[0240] Example 4

[0241] This embodiment will combine Figures 19-21 , further describes the relevant structure of the LED display device of this application.

[0242] The pixel layer 400 includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom. The second type of electrode contact 203 is used to electrically connect to the first semiconductor layer 101 in the corresponding pixel unit 100, and the first type of electrode contact 202 is used to electrically connect to the second semiconductor layer 103 in the corresponding pixel unit 100.

[0243] One of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.

[0244] Among them, the pixel layer 400 and the substrate 200 are bonded through the bonding layer 300, and an ohmic contact layer 500 is also provided between the pixel layer 400 and the substrate 200. The ohmic contact layer 500 is located between the second semiconductor layer 103 and the bonding layer 300, and is used to better achieve ohmic contact between the second conductor layer and the bonding layer 300.

[0245] The lower end of the annular partition groove 401 extends between the lower surface of the active layer 102 and the lower surface of the ohmic contact layer 500 .

[0246] When etching the annular groove 401, the annular groove 401 may have the following forms depending on the etching depth of the annular groove 401:

[0247] The first form: Figure 21 As shown, Figure 21 yes Figure 19 Schematic diagram of another structural form at M3 in the figure; the lower end of the annular groove 401 extends directly to the ohmic contact layer 500, and can extend into the interior thereof and be located above the lower surface of the ohmic contact layer, and the upper end of the annular groove 401 extends at least to the upper surface of the first semiconductor layer 101, for example, can directly extend to the upper surface of the first semiconductor layer 101 or continue to extend above the etch stop layer 403.

[0248] The second form: Figures 19-20 As shown, the lower end of the annular groove 401 is higher than the upper surface of the ohmic contact layer 500 and lower than the lower surface of the active layer 102, that is, the lower end of the annular groove 401 is located in the area between the lower surface of the active layer 102 and the upper surface of the ohmic contact layer 500.

[0249] Exemplarily, the ohmic contact layer 500 may be a transparent conductive film made of one or more of ITO, IZO, IGZO, or AZO, or may be a metal layer made of one or more of Ni, Cr, Au, Ag, Zn, Rh, Be, or Al, or may be an alloy layer, or may be a laminate of a transparent metal oxide and a metal;

[0250] The thickness of the ohmic contact layer 500 is 1 nm to 500 nm. If the thickness is too large, it will cause material waste, while if the thickness is too small, it will be difficult to achieve a good ohmic contact effect.

[0251] In some embodiments, the minimum dimension of the annular groove 401 along the width direction (X direction) needs to be greater than 0, and the maximum dimension L2 of the annular groove 401 along the width direction (X direction) is 0.02 um to 10 um.

[0252] Example 5

[0253] This embodiment will combine Figures 17-18 , further describes the relevant structure of the LED display device of this application.

[0254] in, Figure 18 Only shows the Figure 17 When arranged in the form shown, a Figure 17 A schematic cross-sectional view of a pixel unit and its surrounding structures obtained at the G2-G2 section.

[0255] The main difference between this embodiment and the above embodiment is that each pixel unit 100 is surrounded by at least two annular partitions 401, and compound semiconductors are retained between adjacent annular partitions 401 on the periphery of each pixel unit 100 to form partition walls 402, that is, the partition walls 402 themselves are also made of compound semiconductor material.

[0256] The manufacturing method of the display device in this embodiment is substantially the same as that in the first embodiment, except that when etching the pixel layer 400 using the mask layer to obtain at least one pixel unit 100, the etching is performed so as to form at least two annular partitions 401 around the periphery of each pixel unit 100, so that the compound semiconductor between adjacent annular partitions 401 around the periphery of each pixel unit 100 is retained to form partition walls 402.

[0257] In this embodiment, each pixel unit 100 is surrounded by at least two annular partition grooves 401. While improving the heat dissipation effect, the partition wall 402 structure can also better prevent metal atoms from diffusing to the side walls of the pixel unit 100, thereby better reducing the leakage risk of the device and improving the reliability of the device.

[0258] Example 6

[0259] This embodiment will further describe the related structure of the LED display device of the present application in combination with Figure 4 , Figure 22 , Figure 23 and Figure 24 .

[0260] The upper surface of the driving wafer in this embodiment is divided into at least one display area 201, and each display area 201 is covered by at least one pixel unit 100, that is, the display area 201 is the area covered by the pixel unit 100 (at least one pixel unit 100) to form an image display area 201.

[0261] Among them, the bonding layer 300 above each display area 201 is continuously arranged to further retain the bonding layer 300 material, improve the heat dissipation area, and thus improve the heat dissipation effect of the device; at the same time, it is more conducive to the connection of the bonding layer 300 and the electrode contact, and the bonding can be performed in a non-alignment manner.

[0262] For example, each display area 201 has a pixel array composed of a plurality of pixel units 100 above it, that is, each display area 201 is covered by a corresponding pixel array, and the projection of the pixel array on the driving wafer is located within the corresponding display area 201. The "bonding layer 300 above each display area 201" can be understood as the bonding layer whose projection on the driving wafer can fall within the display area. Therefore, the bonding layer above each display area needs to be at least continuously arranged within the corresponding area of the display area. When specifically arranged, the bonding layer above the display area can be continuously arranged within the corresponding area above the display area 201, while the bonding layer between the display areas is discontinuous (such as the K1 area in Figure 24 ); or a plurality of display areas 201 can share a continuous bonding layer 300, for example, two display areas 201 share a continuous bonding layer 300 (such as the K2 area in Figure 24 ), or four display areas 201 share a continuous bonding layer 300 (such as the K3 area in Figure 24 ), or nine display areas 201 share a continuous bonding layer 300 (such as the K4 area in Figure 24 ), and so on, while the non-display area 201 (which has no pixel unit 100 above it) can be filled with a dielectric layer for support.

[0263] When arranging the first type of electrode contact 202, the following forms can be used:

[0264] In one way: as shown in Figure 4As shown, the bottom of each pixel unit 100 is electrically connected to a corresponding first electrode contact 202, which is located inside the display area 201 where the corresponding pixel unit 100 is located. For example, the first electrode contact 202 can be arranged inside the display area 201 directly below each pixel unit 100.

[0265] In another way, the bottom of each pixel unit 100 is electrically connected to a corresponding first electrode contact 202, which is located at the periphery of the display area 201 where the corresponding pixel unit 100 is located, i.e. the first electrode contact 202 is no longer arranged inside the display area 201.

[0266] For example, as shown, a peripheral electrode contact area 800 can be arranged at the periphery of the display area 201 on the driving wafer, and the first electrode contact 202 is arranged at the peripheral electrode contact area 800. Figures 22-23

[0267] The driving wafer is also provided with a plurality of interfaces 900 to connect external circuit (signal source or power supply, etc.) devices. The peripheral electrode contact area 800 can be connected / disconnected to the interfaces 900 as needed.

[0268] All the optional technical solutions described above can be combined to form optional embodiments of the present application, i.e. any number of embodiments can be combined to meet the needs of different application scenarios, which are all within the protection scope of the present application and will not be described one by one here.

[0269] It should be noted that the above embodiments are only examples for clear illustration and do not limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those of ordinary skill in the art. Here, it is not necessary and impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.​

Claims

1. An LED display device, characterized by: The compound semiconductor device comprises: a substrate, which is a driving wafer, and first and second electrode contacts arranged on the substrate, the first and second electrode contacts having opposite polarities; a pixel layer, which is a compound semiconductor layer, and is arranged on the substrate, the pixel layer comprising pixel units, each of the pixel units being surrounded by at least one annular isolation groove, and the outermost annular isolation groove of each of the pixel units and the outermost annular isolation groove of an adjacent pixel unit at least partially overlapping, and the non-overlapping area being filled with the compound semiconductor; or, the outermost annular isolation groove of each of the pixel units and the outermost annular isolation groove of an adjacent pixel unit being completely separated from each other by the compound semiconductor filled therebetween; wherein the bottom of each of the pixel units is electrically connected to the corresponding first electrode contact, and the top of each of the pixel units is electrically connected to the corresponding second electrode contact through an interconnection conductive member, the interconnection conductive member being arranged at the edge of each of the pixel units, and the interconnection conductive member being at least partially arranged inside the nearest annular isolation groove of the corresponding pixel unit.

2. The LED display device of claim 1, wherein: The projection area of each of the pixel units on the substrate is defined as a first projection area, and the second electrode contact is arranged at the edge of the first projection area of the corresponding pixel unit, and the second electrode contact is at least partially arranged inside the first projection area where the corresponding pixel unit is located.

3. The LED display device of claim 2, wherein: The projection area of the annular isolation groove surrounding each of the pixel units on the substrate is defined as a second projection area, and the second electrode contact is partially arranged inside the first projection area where the corresponding pixel unit is located, and the remaining part of the second electrode contact is at least extended to the inside of the nearest second projection area.

4. The LED display device of claim 1, wherein: A plurality of second electrode contacts are arranged at the edge of each of the first projection areas, and the plurality of second electrode contacts are arranged in an annular manner.

5. The LED display device of claim 4, wherein: The first electrode contact is arranged inside each of the first projection areas, and the first electrode contact is surrounded by the plurality of second electrode contacts arranged at the edge of the first projection area.

6. The LED display device of claim 1, wherein: The interconnection conductive member is partially arranged inside the corresponding pixel unit, and the remaining part of the interconnection conductive member is at least extended to the inside of the nearest annular isolation groove.

7. The LED display device of claim 1, wherein: The inner wall of the annular isolation groove is covered with a first insulating layer, and the inside of the annular isolation groove has a filling area, the periphery of the filling area is surrounded by the first insulating layer on the inner wall of the annular isolation groove, and the filling area contains air to form an air isolation layer, or the filling area is filled with a first filler to form a solid structure.

8. The LED display device of claim 7, wherein: The upper part of the pixel unit is at least partially covered with the first insulating layer, and the area not covered with the first insulating layer forms the electrical contact area.

9. The LED display device of claim 8, wherein: The upper part of the pixel unit is further covered with a first conductive layer, the first insulating layer on the upper part of the pixel unit is at least partially covered with the first conductive layer, the middle part of the top surface of the pixel unit forms the electrical contact area, and the electrical contact area of the pixel unit and the interconnection conductive member at the edge of the pixel unit are both in contact with the same first conductive layer.

10. The LED display device of claim 8, wherein: The top of each of the interconnection conductive members at the edge of the pixel unit is connected with a second conductive layer, and all the second conductive layers of each pixel unit are discontinuously arranged by being separated from each other, and each of the interconnection conductive members at the edge of the pixel unit is contacted through the corresponding second conductive layer and the corresponding electrical contact area.

11. The LED display device of claim 8, wherein: The upper portion of the pixel unit is provided with a second conductive layer, the second conductive layer is arranged in a ring shape, and all the interconnection conductive members at the edge of the pixel unit are contacted with the same second conductive layer.

12. The LED display device according to claim 10 or 11, characterized in that: An arc-shaped covering area is formed at the contact area between the second conductive layer and the interconnection conductive member, and the arc-shaped covering area covers at least the top surface area of the interconnection conductive member inside the pixel unit.

13. The LED display device of claim 7, wherein: The upper portion of the pixel layer is further covered with a thin film covering layer, and the upper portion of the filling area is closed by the thin film covering layer.

14. The LED display device of claim 12, wherein: The thin film covering layer comprises a downwardly protruding extension portion, the extension portion extends into the filling area, the extension portion only extends to the upper portion of the filling area, and the lower portion of the filling area forms the air separation layer. Alternatively, the extension portion serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

15. The LED display device of claim 7, wherein: The filling area is filled with air to form an air separation layer, and the periphery of the air separation layer is surrounded by the first reflective layer. Alternatively, the first reflective layer serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

16. The LED display device of claim 1, wherein: The pixel layer and the substrate are bonded through a bonding layer, and the bottom surface of the ring-shaped separation groove is not lower than the upper surface of the bonding layer.

17. The LED display device of claim 1, wherein: The interconnection conductive member is a metal member.

18. The LED display device of claim 1, wherein: The periphery of each pixel unit is surrounded by at least two ring-shaped separation grooves, and a compound semiconductor is also reserved between adjacent ring-shaped separation grooves of the periphery of each pixel unit to form a partition wall.

19. The LED display device of claim 16, wherein: The upper surface of the driving wafer is divided into at least one display area, each display area is covered by at least one pixel unit, and the bonding layer above each display area is continuously arranged.

20. The LED display device of claim 19, wherein: The bottom of each pixel unit is electrically connected with the corresponding first electrode contact, and the first electrode contact is located at the periphery of the display area where the corresponding pixel unit is located.

21. The LED display device of claim 1, wherein: The pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the second electrode contact is used for electrically connecting with the first semiconductor layer in the corresponding pixel unit, the first electrode contact is used for electrically connecting with the second semiconductor layer in the corresponding pixel unit, the lower end of the ring-shaped separation groove extends between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the ring-shaped separation groove extends at least to the upper surface of the first semiconductor layer.

22. The LED display device of claim 21, wherein: An ohmic contact layer is further arranged between the pixel layer and the substrate, and the lower end of the ring-shaped separation groove extends between the lower surface of the active layer and the lower surface of the ohmic contact layer.

23. The LED display device of claim 1, wherein: The maximum size of the ring-shaped separation groove in the width direction is L2, L2, and L2 is 0.02 um to 10 um.

24. A method of fabricating an LED display device, the method comprising: The method comprises the following steps: ​ selecting a driving wafer as a substrate, the driving wafer being provided with first electrode contacts and second electrode contacts with opposite polarities; and selecting a compound semiconductor layer as a pixel layer; connecting the pixel layer to the upper portion of the substrate; and bonding the pixel layer to the substrate. The pixel layer is etched to obtain at least one pixel unit. The periphery of each pixel unit obtained by etching is surrounded by at least one annular isolation groove, so that the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved for the compound semiconductor; or the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit are reserved for the compound semiconductor to be completely separated from each other. An interconnecting conductive member is prepared in the pixel layer, so that the interconnecting conductive member is located at the edge of the corresponding pixel unit, and the interconnecting conductive member is at least partially located inside the annular isolation groove closest to the corresponding pixel unit; The bottom of each pixel unit is electrically connected to the corresponding first electrode contact, and the top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnecting conductive member.

25. The method of claim 24, wherein: When the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

26. The method of claim 25, wherein: When the top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnecting conductive member, the method comprises, A second electrode filling hole is formed in the compound semiconductor layer, and the second electrode filling hole penetrates the bonding layer; A metal is filled in the second electrode filling hole to form an interconnecting conductive member, which is located at the edge of each corresponding pixel unit and at least partially located inside the annular isolation groove closest to the corresponding pixel unit; The top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnecting conductive member.

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