Semiconductor device, LED display device and preparation method
By opening an annular partition groove in the compound semiconductor layer, the independence of the pixel unit is achieved, the heat dissipation problem of the LED display device is solved, and the optoelectronic performance and reliability are improved.
Patent Information
- Application Number
- CN202510870258.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-26
- Publication Date
- 2025-10-24
AI Technical Summary
Existing LED display devices have poor heat dissipation, leading to increased temperature and affecting photoelectric performance and reliability.
By creating annular slots in the compound semiconductor layer, pixel units can be made independent while retaining the compound semiconductor material. The design of the annular slots maximizes the retention of the compound semiconductor material and improves heat dissipation.
It improves the heat dissipation capacity of LED display devices, ensures photoelectric performance and reliability, and extends service life.
Smart Images
Figure CN120835656A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device, an LED display device and a preparation method. BACKGROUND
[0002] The LED display chip usually comprises a plurality of pixel units (i.e. light emitting units). With the development of semiconductor display technology, the size of the display chip is increasingly reduced. Taking the micro-LED micro display chip as an example, the pixel size is gradually reduced to 1um-5um, or even to nanometer level. The smaller the size, the higher the thermal density, and the heat is more easily concentrated. The main source of heat of the LED chip is the conversion efficiency problem of electrons and outgoing photons. Most of the electric energy that is not converted into outgoing light energy is converted into heat energy. These heat energy will cause the temperature of the LED chip to rise. If the temperature of the LED chip is too high, it will cause the light efficiency of the LED photoelectric device to decrease, the wavelength to shift, the service life to be low, and even seriously affect the stability and reliability of the LED display device, which cannot meet the use requirements. SUMMARY
[0003] Therefore, the technical problem to be solved by the present application is to improve the heat dissipation capacity of the LED display device in the prior art, so as to better guarantee the photoelectric performance and reliable performance of the LED display device.
[0004] To solve the above technical problems, the present application provides a semiconductor device, comprising,
[0005] The pixel layer is a compound semiconductor layer, and the pixel layer comprises pixel units. The periphery of each pixel unit is surrounded by at least one annular isolation groove. The outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with compound semiconductor; or,
[0006] The outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit are completely separated from each other by reserving compound semiconductor therebetween.
[0007] The periphery of each pixel unit of the semiconductor device is surrounded by at least two annular isolation grooves, and the adjacent annular isolation grooves of the periphery of each pixel unit are also reserved with compound semiconductor to form a partition wall.
[0008] In an embodiment of the present application, the maximum size of the annular isolation groove in the width direction is L2, and L2 is 0.02um-10um.
[0009] In one embodiment of the present application, the semiconductor device further comprises a substrate, the pixel layer is located on the upper portion of the substrate, the pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the lower end of the ring-shaped isolation groove extends between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the ring-shaped isolation groove extends at least to the upper surface of the first semiconductor layer.
[0010] In one embodiment of the present application, the upper portion of the first semiconductor layer is further provided with an etching stop layer, and the upper end of the ring-shaped isolation groove extends at least to the upper surface of the etching stop layer.
[0011] In one embodiment of the present application, the inner wall of the ring-shaped isolation groove is covered with a first insulating layer, the interior of the ring-shaped isolation groove has a filling area, the periphery of the filling area is surrounded by the first insulating layer, and the filling area contains air to form an air isolation layer, or the filling area is filled with a first filler to form a solid structure.
[0012] In one embodiment of the present application, the upper portion of the pixel layer is covered with a thin film cover layer, and the upper portion of the filling area is closed by the thin film cover layer.
[0013] In one embodiment of the present application, the thin film cover layer comprises an extension protruding downward, the extension extends into the interior of the filling area, the extension only extends to the upper portion of the filling area, and the lower portion of the filling area forms the air isolation layer.
[0014] Alternatively, the extension serves as a first filler, and the filling area is filled with the first filler to form a solid structure.
[0015] In one embodiment of the present application, the sidewall of the pixel unit is covered with the first insulating layer, at least a part of the upper portion of the pixel unit is covered with the first insulating layer, and the first insulating layer of the upper portion of the pixel unit is located below the thin film cover layer.
[0016] In one embodiment of the present application, the thickness of the thin film cover layer is 0.05um-8um.
[0017] In one embodiment of the present application, the inner wall of the ring-shaped isolation groove is covered with a first insulating layer and a first reflective layer in sequence.
[0018] In one embodiment of the present application, the filling area contains air to form an air isolation layer, and the periphery of the air isolation layer is surrounded by the first reflective layer, or
[0019] The first reflective layer serves as a first filler, and the filling area is filled with the first filler to form a solid structure.
[0020] In one embodiment of the present application, the first insulating layer has a thickness of 5 nm to 2 um.
[0021] In one embodiment of the present application, the pixel unit has a height of 0.1 um to 5 um.
[0022] The present application discloses a method for preparing a semiconductor device, comprising the following steps,
[0023] The compound semiconductor layer is selected as the pixel layer.
[0024] The pixel layer is etched to obtain at least one pixel unit, and each pixel unit obtained by etching has at least one annular isolation groove around the periphery, so that the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area retains the compound semiconductor; or,
[0025] The outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit retain the compound semiconductor to completely separate each other.
[0026] In one embodiment of the present application, before the pixel layer is etched to obtain at least one pixel unit, the method further comprises,
[0027] The pixel layer is connected to the substrate, so that the pixel layer is located on the upper part of the substrate.
[0028] The pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom.
[0029] In one embodiment of the present application, when the pixel layer is etched to obtain at least one pixel unit, the method comprises,
[0030] An etching stop layer is arranged on the upper surface of the pixel layer, and the etching stop layer is etched to obtain a patterned mask layer.
[0031] The pixel layer is etched by the mask layer to obtain at least one pixel unit, and at least one annular isolation groove is formed around each pixel unit.
[0032] In one embodiment of the present application, the pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, and when the pixel layer is etched by the mask layer to obtain at least one pixel unit and at least one annular isolation groove is formed around each pixel unit, the method comprises,
[0033] After etching, the lower end of the annular groove is located between the lower surface of the active layer and the upper surface of the substrate, and the upper end extends at least to the upper surface of the first semiconductor layer.
[0034] In one embodiment of the present application, in the above preparation method, when the pixel layer is etched by the mask layer to obtain at least one pixel unit, the periphery of each pixel unit forms at least two annular grooves, so that the compound semiconductor between the adjacent annular grooves of the periphery of each pixel unit is reserved to form a partition wall.
[0035] In one embodiment of the present application, in the above preparation method, after the pixel layer is etched by the mask layer to obtain at least one pixel unit, the method further comprises,
[0036] A first insulating layer is deposited on the surface of the pixel layer, so that the first insulating layer covers at least the inner wall of the annular groove and the sidewall of the pixel unit, and the inside of the annular groove forms a filling area surrounded by the first insulating layer.
[0037] In one embodiment of the present application, in the above preparation method, when the filling area is formed in the annular groove or after the filling area is formed, a first filler is filled in the filling area to fill the filling area to form a solid structure.
[0038] In one embodiment of the present application, in the above preparation method, the first filler is an insulating medium or a metal.
[0039] In one embodiment of the present application, in the above preparation method, after the filling area is formed in the annular groove, a thin film cover layer is deposited on the upper part of the pixel layer, so that the upper part of the filling area is closed by the thin film cover layer.
[0040] In one embodiment of the present application, when the thin film cover layer is deposited on the upper part of the pixel layer, the method further comprises,
[0041] At least one downwardly protruding extension is formed on the thin film cover layer, and each of the extensions extends into the corresponding filling area, so that the extension only extends to the upper part of the filling area, so that the lower part of the filling area forms an air partition, or
[0042] The extension penetrates the filling area, so that the filling area is filled by the extension to form a solid structure.
[0043] In one embodiment of the present application, in the above preparation method, after the filling area is formed inside the annular groove, a first reflective layer is deposited on the pixel layer, so that the outer part of the first insulating layer on the inner wall of the annular groove is covered with the first reflective layer, and so that the air in the filling area forms an air separation layer, the periphery of the air separation layer surrounding the first reflective layer, or,
[0044] The first reflective layer is used as a first filler, so that the filling area is filled with the first filler to form a solid structure.
[0045] In one embodiment of the present application, the first reflective layer is metal.
[0046] The present application also discloses an LED display device, comprising a substrate and the semiconductor device described in any one of the above, the substrate being a driving wafer, the pixel layer being located on the upper part of the substrate, the pixel layer and the driving wafer being bonded by a bonding layer, the bottom surface of the annular groove being not lower than the upper surface of the bonding layer.
[0047] In one embodiment of the present application, the upper surface of the driving wafer is divided into at least one display area, and at least one pixel unit exists above each display area, and the bonding layer above each display area is continuously arranged.
[0048] The above technical solution of the present application has the following advantages compared with the prior art:
[0049] The semiconductor device and the preparation method thereof disclosed by the present application can maximize the retention of the original compound semiconductor material by forming an annular groove in the compound semiconductor layer to realize the independence of the pixel units, so that the annular groove at the outermost periphery of each pixel unit and the annular groove at the outermost periphery of the adjacent pixel unit at least partially overlap, or the compound semiconductor material area is retained in the non-overlapping area, or the compound semiconductor is retained between the annular groove at the outermost periphery of each pixel unit and the annular groove at the outermost periphery of the adjacent pixel unit to completely separate each other, thereby better guaranteeing the photoelectric performance and reliability of the LED display device. BRIEF DESCRIPTION OF DRAWINGS
[0050] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the accompanying drawings.
[0051] Figure 1 is a structure schematic diagram of a semiconductor device in the prior art;
[0052] Figure 2 is a structure schematic diagram of a semiconductor device in one embodiment of the present application;
[0053] Figure 3 is Figure 2 Fig. 2 is a schematic diagram of the structure after removing the first insulating layer in the semiconductor device shown in Fig. 1;
[0054] Figure 4 is Figure 3 Fig. 4 is a schematic diagram of a first arrangement of the semiconductor device shown in Fig. 3 (top view);
[0055] Figure 5 is Figure 3 Fig. 5 is a schematic diagram of a second arrangement of the semiconductor device shown in Fig. 3 (top view);
[0056] Figure 6 is Figure 3 Fig. 6 is a schematic diagram of a third arrangement of the semiconductor device shown in Fig. 3 (top view);
[0057] Figure 7 is a schematic diagram of another semiconductor device in the first embodiment of the present application;
[0058] Figure 8 is a flow chart of the preparation of a semiconductor device in an embodiment of the present application;
[0059] Figure 9 is a schematic diagram of a semiconductor device in the second embodiment of the present application;
[0060] Figure 10 is a schematic diagram of another semiconductor device in the second embodiment of the present application;
[0061] Figure 11 is a schematic diagram of a semiconductor device in the third embodiment of the present application;
[0062] Figure 12 is a schematic diagram of another semiconductor device in the third embodiment of the present application;
[0063] Figure 13 is a schematic diagram of a semiconductor device in the fourth embodiment of the present application;
[0064] Figure 14 is a schematic diagram of another semiconductor device in the fourth embodiment of the present application; Figure 11
[0065] Figure 15 is a schematic diagram of an embodiment of the LED display device in the present application;
[0066] Figure 16 is a schematic diagram of an arrangement of the display area on the wafer driven in the present application (top view);
[0067] Explanation of the reference signs in the attached drawings:
[0068] 100, pixel unit; 101, first semiconductor layer; 102, active layer; 103, second semiconductor layer;
[0069] 200, substrate; 201, display area;
[0070] 300, bonding layer;
[0071] 400, pixel layer; 401, annular isolation groove; 4011, filling area; 40112, air isolation layer; 40113, first filler; 402, isolation wall; 403, etching stop layer; 404, first insulating layer; 405, thin film cover layer; 4051, extension; 406, first reflective layer; DETAILED DESCRIPTION
[0072] The present application will be further described below with reference to the drawings and specific embodiments, so that those skilled in the art can better understand the present application and implement it. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present disclosure and its application or use.
[0073] In the description of the present application, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited by "first", "second" can be explicitly or implicitly included one or more features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.
[0074] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0075] The LED display device in the prior art has the problem of poor heat dissipation effect. In view of this, the semiconductor device and the display device are provided to improve the heat dissipation capacity, so as to better ensure the photoelectric performance and reliability of the LED display device.
[0076] It should be noted that the compound semiconductor layer in the present application refers to a layer structure with a certain thickness prepared from a compound semiconductor material. The compound semiconductor generally refers to a compound formed by two or more elements, including crystalline inorganic compounds (such as III-V, II-VI compound semiconductors) and oxide semiconductors. The compound semiconductor involved in the present application is mainly a light emitting diode epitaxial material, such as an InGaN ternary material system or an AlGaInP quaternary material system, etc., and its light emitting wavelength can cover the full wavelength band from ultraviolet, visible light and infrared, and its substrate material can be GaN, Si, SiC, sapphire, GaAs, InP, etc.
[0077] Taking the field of Micro-LED as an example, some compound semiconductor materials involved in the present application are shown in Table 1. In some practical applications, the film layer of the compound semiconductor will be more complex, or there will be a situation of cross use of materials. The typical compound semiconductor mainly includes P-type semiconductor material, N-type semiconductor material, and MQW active quantum well and other functional layers (barrier layer, confinement layer, waveguide layer, buffer layer, etc.) sandwiched between them:
[0078] Table 1: Compound semiconductor film layer material table
[0079]
[0080] The related structure of the semiconductor device and the display device of the present application will be further described below in combination with the following specific embodiments.
[0081] Embodiment one
[0082] Referring to Figures 2-4 The present embodiment discloses a semiconductor device, which comprises a pixel layer 400, the pixel layer 400 being a compound semiconductor layer, the pixel layer 400 comprising at least one pixel unit 100, the pixel unit 100 being a light emitting element, and the periphery of each pixel unit 100 being surrounded by at least one annular isolation groove 401 to realize pixel independence through the annular isolation groove 401 in the periphery.
[0083] It can be understood that the above-mentioned compound semiconductor layer refers to a layer body with a certain thickness prepared from a compound semiconductor material. The pixel unit 100 is a light emitting element.
[0084] Wherein, the outermost annular groove of each pixel unit and the outermost annular groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area retains a compound semiconductor material area Q1, that is, the outermost annular groove of each pixel unit and the outermost annular groove of the adjacent pixel unit can share a part of the annular groove, for example, as shown in Figure 3 The pixel unit 100 is provided with only one annular groove 401, and the annular grooves 401 of the adjacent two pixel units have an intersection W1 which is a shared part.
[0085] Alternatively,
[0086] The outermost annular groove of each pixel unit and the outermost annular groove of the adjacent pixel unit can also be completely separated from each other by retaining a compound semiconductor, that is, the outermost annular grooves of the adjacent two pixel units are completely non-overlapping and separated from each other, and the separated area retains the original compound semiconductor material area Q1. For details, please refer to Figure 12 .
[0087] It should be noted that Figure 3 Only one cross-sectional view of a pixel unit 100 and its peripheral structure obtained along the A1-A1 (or A2-A2) section in the following description is shown. Figure 4
[0088] The shape of the annular groove 401 can be adapted to the shape of the pixel unit 100, for example, as shown in Figure 4 The pixel unit and the annular groove can both be circular, as shown in Figure 5 The pixel unit and the annular groove can both be quadrilateral, as shown in Figure 6 The pixel unit and the annular groove can both be hexagonal.
[0089] As shown in Figure 1 In the conventional technology, when preparing the pixel unit, a large amount of compound semiconductor material around the pixel unit needs to be etched and removed, and then filled with an insulating dielectric material G1 to achieve the independence of the pixel unit. The thermal conductivity of the insulating dielectric material is lower than that of the original compound semiconductor, so that the heat generated by the device cannot be transmitted in time, resulting in an increase in the temperature of the device, thereby greatly reducing the photoelectric performance and reliability of the device.
[0090] Table 2 Comparison of thermal conductivities of different materials
[0091]
[0092] As shown in Table 2, among the three materials of insulating dielectric, compound semiconductor and metal, the thermal conductivity of the metal material is higher than that of the compound semiconductor material, and the thermal conductivity of the compound semiconductor material is higher than that of the insulating dielectric material.
[0093] The semiconductor device structure of the present embodiment can maximize the remaining compound semiconductor material, and the thermal conductivity of the compound semiconductor material is relatively high. Compared with the structure of removing most of the compound semiconductor material and filling it with an insulating dielectric material in the prior art, the heat dissipation effect of the semiconductor device can be effectively improved.
[0094] In the present application, the "width" direction is the X direction in Figure 2 , and the "height" or "up and down" direction is the Z direction in Figure 2 . In addition, there is also a Y direction, wherein the X direction, the Y direction and the Z direction are perpendicular to each other.
[0095] In some embodiments, the minimum size of the annular groove 401 in the width direction (X direction) is greater than 0, and the maximum size of the annular groove 401 in the width direction (X direction) is L2, L2 is 0.02um-10um. The width should not be too large, because the larger the width, the more compound semiconductor material is removed, which is not conducive to heat dissipation. If the width is too small, the effective separation of the pixel unit 100 cannot be achieved, and it is also not conducive to the subsequent process.
[0096] For example, the semiconductor device further includes a substrate 200, and the pixel layer 400 is located on the upper portion of the substrate 200. The pixel layer 400 includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom (Z direction). The Z direction is the stacking direction of the first semiconductor layer 101, the active layer 102 and the second semiconductor layer 103.
[0097] It can be understood that each pixel unit 100 is etched from the pixel layer 400, and each pixel unit 100 also corresponds to a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom (Z direction).
[0098] Among the above-mentioned first semiconductor layer 101 and second semiconductor layer 103, one is a P-type semiconductor layer and the other is an N-type semiconductor layer, that is, if the first semiconductor layer 101 is a P-type semiconductor layer, the second semiconductor layer 103 is an N-type semiconductor layer, or if the first semiconductor layer 101 is an N-type semiconductor layer, the second semiconductor layer 103 is a P-type semiconductor layer.
[0099] The active layer 102 is used for light emission, and can be an MQW active quantum well.
[0100] In some embodiments, the lower end of the annular groove 401 extends between the lower surface of the active layer 102 and the upper surface of the substrate 200, and the upper end of the annular groove 401 extends at least to the upper surface of the first semiconductor layer 101.
[0101] Further, the lower end of the annular groove 401 extends between the lower surface of the active layer 102 and the lower surface of the second semiconductor, and the upper end of the annular groove 401 extends to the upper surface of the first semiconductor layer 101 and above.
[0102] For example, the lower end of the annular groove 401 can directly extend to the upper surface of the substrate 200, or can extend to a position inside the second semiconductor beyond the lower surface of the active layer 102.
[0103] Further, the upper portion of the first semiconductor layer 101 is further provided with an etching stop layer 403, and the upper end of the annular groove 401 extends at least to the upper surface of the etching stop layer 403.
[0104] The etching stop layer 403 can be a transparent material layer.
[0105] In some embodiments, the inner wall of the annular groove 401 is covered with a first insulating layer 404, and the inside of the annular groove 401 has a filling area 4011, and the periphery of the filling area 4011 is surrounded by the first insulating layer 404, so as to better isolate the pixel unit 100 and prevent the phenomenon of electric leakage.
[0106] The filling area 4011 is filled with air to form an air separation layer 40112, i.e., the filling area 4011 has a hollow structure.
[0107] Alternatively, the filling area 4011 is filled with a first filler 40113 to form a solid structure.
[0108] The first filler 40113 can be an insulating medium or a metal, etc.
[0109] For example, the filling area 4011 can be filled with the material of the first insulating layer 404; of course, a filler different from the material of the first insulating layer 404 can also be used to fill the filling area 4011.
[0110] It should be noted that the inner wall of the annular groove 401 includes a side wall and a bottom surface, and the side wall and the bottom surface are both covered with the first insulating layer 404. When the filling area 4011 has the air separation layer 40112, the bottom surface position of the air separation layer 40112 is not lower than the bottom surface of the annular groove 401.
[0111] In some embodiments, the top surface of the air gap 40112 is not higher than the upper surface of the etching stop layer 403, and the bottom surface of the air gap 40112 is not lower than the bottom surface of the annular isolation groove 401.
[0112] Further, the top surface of the air gap 40112 is not higher than the upper surface of the first semiconductor layer, and the bottom surface of the air gap 40112 is not lower than the bottom surface of the annular isolation groove 401.
[0113] In some embodiments, the sidewall of the pixel unit 100 is covered by the first insulating layer 404, and the upper part of the pixel unit 100 is at least partially covered by the first insulating layer 404. The upper part of the pixel unit 100 can be completely covered by a whole layer of the first insulating layer 404, and then a part of the first insulating layer 404 is removed to expose part of the first semiconductor layer for subsequent electrical connection.
[0114] In some embodiments, the thickness of the first insulating layer 404 is 5 nm to 2 um.
[0115] Further, the thickness of the first insulating layer 404 is 5 nm to 1 um, so that when the air gap 40112 is inside the filler, the width L3 of the air gap 40112 can be 0.01 um to 8 um.
[0116] In some embodiments, as shown in FIG. 1, the width L1 of the pixel unit 100 is 0.2 um to 80 um. Here, the width of the pixel unit can be understood as the maximum dimension of the pixel unit along the X direction. Figure 3
[0117] Further, the height h1 of the pixel unit 100 is 0.1 um to 5 um. Here, the height of the pixel unit refers to the distance between the upper surface of the first semiconductor layer 101 and the lower surface of the second semiconductor layer 103 in the pixel unit.
[0118] The shape of the pixel unit 100 described above includes but is not limited to a circle, an ellipse, a polygon, and other shapes, and is preferably a circle, a quadrilateral, and a hexagon. For details, please refer to FIG. 1. Figures 4-6
[0119] Next, the preparation method of the semiconductor device described in the above embodiments is described.
[0120] As shown in FIG. 2, the preparation method of the semiconductor device described above can include the following steps: Figure 6
[0121] Step S1: selecting a compound semiconductor layer as the pixel layer 400;
[0122] It can be understood that the compound semiconductor layer includes the first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 arranged in order from top to bottom.
[0123] Step S2: etching the pixel layer 400 to obtain at least one pixel unit 100, and each pixel unit 100 obtained by etching is surrounded by at least one annular isolation groove 401, so that the outermost annular isolation groove 401 of each pixel unit and the outermost annular isolation groove 401 of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with a compound semiconductor; or,
[0124] so that the outermost annular isolation groove 401 of each pixel unit and the outermost annular isolation groove 401 of the adjacent pixel unit are completely separated from each other, that is, they are completely non-overlapping.
[0125] In the pixel layer 400 prepared by the above method, the area in the peripheral region of the pixel unit 100 except the annular isolation groove 401 is reserved with a compound semiconductor material.
[0126] Before the pixel layer 400 is etched to obtain at least one pixel unit 100, the above method further comprises: connecting the pixel layer 400 and the substrate 200, so that the pixel layer 400 is located on the upper part of the substrate 200;
[0127] The pixel layer 400 comprises a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom. One of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
[0128] The substrate 200 can be the substrate material in Table 1, and contains the corresponding remaining film layers, such as GaAs, Si substrate and the buffer layer or cutoff layer carried by the substrate;
[0129] The substrate 200 can also be a temporary or permanent support substrate transferred by bonding and its bonding structure, such as Si, CMOS backplane and its bonding structure, the bonding structure can include organic materials (such as PI), or metal materials (such as AuSn, NiSn, Al, Cu, Au and other metal alloys or single elements and the film layers formed by them, etc.), or dielectric materials (such as silicon oxide, aluminum oxide, SiCN, etc.), or a mixed structure of dielectric layer and metal (such as a mixed structure of Cu column arranged in silicon oxide, etc.).
[0130] In some embodiments, step S2 can comprise the following steps:
[0131] Step S21: as Figure 8 In stage a of the above method, an etching stop layer 403 is arranged on the upper surface of the pixel layer 400, and the etching stop layer 403 is etched to obtain a patterned mask layer;
[0132] Step S22: as Figure 8In the middle b stage, the pixel layer 400 is etched by a mask layer to obtain at least one pixel unit 100, and at least one annular groove 401 is formed in the periphery of each pixel unit 100, so that the annular groove 401 at the outermost periphery of each pixel unit and the annular groove 401 at the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with the compound semiconductor; or,
[0133] The annular groove 401 at the outermost periphery of each pixel unit and the annular groove 401 at the outermost periphery of the adjacent pixel unit are reserved with the compound semiconductor to separate each other.
[0134] Step S23: as Figure 8 In the middle c stage, a first insulating layer 404 is deposited on the surface of the pixel layer 400, so that the first insulating layer 404 covers at least the inner wall of the annular groove 401 and the side wall of the pixel unit 100, and the inside of the annular groove 401 forms a filling area 4011 surrounded by the first insulating layer 404;
[0135] And the filling area 4011 is filled with a first filler 40113 to make the filling area 4011 filled to form a solid structure, as Figure 2 As shown, the filling area 4011 can be directly filled with the material of the first insulating layer 404; of course, the filling area 4011 can also be filled with a filler different from the material of the first insulating layer 404; or, the filling area 4011 can be reserved with air to form an air separation layer 40112, that is, the filling area 4011 has a hollow structure.
[0136] In some embodiments, the first filler 40113 is an insulating medium or a metal.
[0137] It can be understood that when the above method is used for preparation, in step S23, when the first insulating layer 404 is deposited on the surface of the pixel layer 400, a whole layer of the first insulating layer 404 can be first deposited on the surface of the pixel layer 400, so that the upper surface of the etching stop layer 403, the inner wall of the annular groove 401 and the side wall of the pixel unit 100 are all covered by the first insulating layer 404, and then part of the etching stop layer 403 on the top of the pixel unit 100 and the first insulating layer 404 thereon can be removed to expose part of the first semiconductor for subsequent electrical connection.
[0138] Further, in the above preparation process, when the pixel layer 400 is etched by the mask layer, the etching depth needs to be controlled, that is, the etching depth is at least to the lower surface of the active layer 102 and at most to the upper surface of the substrate 200, so as to ensure that the lower end of the annular groove 401 extends between the lower surface of the active layer 102 and the upper surface of the substrate 200.
[0139] The etching stop layer 403 can be a mask layer made of silicon oxide, silicon nitride, etc., a contact layer made of ITO, metal, etc., or a stack layer on a medium layer below the contact layer. In addition to forming a contact (e.g., ohmic contact) with the first semiconductor layer 101, the etching stop layer 403 is mainly used as a mask and etching stop layer for patterning and subsequent sidewall etching.
[0140] The etching method used for etching the pixel layer 400 to form the pixel unit 100 can be dry etching, wet etching, or a combination of dry and wet etching. For example, the compound semiconductor layer can be patterned by ICP, RIE, KOH, HCl, or a combination of dry and wet etching, thereby obtaining a plurality of independent pixel units 100.
[0141] The angle a of the pixel unit 100 obtained by etching can be 90°±45°, and preferably, the angle a of the pixel unit 100 can be 90°±20°. The angle a of the pixel unit 100 is the maximum angle between the sidewall of the pixel unit and the upper surface of the substrate.
[0142] In some embodiments, the first insulating layer 404 can be a single-layer structure or a stack structure composed of one of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, aluminum nitride, gallium nitride, etc.
[0143] For example, the first insulating layer 404 can be a stack structure of silicon oxide and titanium oxide, and a DBR (distributed Bragg reflector) Bragg reflection structure can be constructed by using the difference in refractive index of the two materials.
[0144] In some embodiments, the first insulating layer 404 is a transparent material layer.
[0145] The semiconductor device and the preparation method thereof according to the above embodiments change the independent mode of the pixel light-emitting unit, and the independence of the pixel unit 100 is achieved by forming the annular isolation groove 401 in the compound semiconductor layer. The compound semiconductor material with high thermal conductivity is maximally reserved, thereby improving the heat dissipation effect of the semiconductor device, reducing the phenomenon of excessive temperature rise of the pixel unit 100 due to heat accumulation, and effectively improving the reliability and service life of the semiconductor device.
[0146] Embodiment Two
[0147] Referring to Figure 9 The main difference between the present embodiment and Embodiment One is that the upper part of the pixel layer 400 further covers a thin film cover layer 405, and the upper part of the filling area 4011 is closed by the thin film cover layer 405.
[0148] Preferably, the thin film covering layer 405 is an insulating medium.
[0149] Specifically, the inner wall of the annular groove 401 is covered with a first insulating layer 404 . The annular groove 401 has a filling area 4011 inside. The first insulating layer 404 surrounds the filling area 4011 . The upper part of the filling area 4011 is covered and sealed by a thin film covering layer 405 .
[0150] The thin film cover layer 405 may be a single-layer structure composed of one of the materials such as silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, polyimide, etc., or a multi-layer structure composed of multiple materials.
[0151] Furthermore, the thin film covering layer 405 includes a downwardly protruding extension portion 4051 , and the extension portion 4051 extends into the interior of the filling area 4011 ;
[0152] Exemplarily, the extension portion 4051 may only extend into the upper portion of the filling area 4011 , so that a hollow portion remains at the lower portion of the filling area 4011 , thereby forming the above-mentioned air barrier 40112 at the lower portion of the filling area 4011 .
[0153] Alternatively, the extension portion 4051 is used as the first filler 40113, so that the filling area 4011 is filled with the first filler 40113 to form a solid structure. In this case, the material of the first filler 40113 is the same as that of the thin film cover layer 405, that is, an insulating medium.
[0154] Furthermore, when the filler has an air barrier layer 40112 inside, the maximum dimension L3 of the air barrier layer 40112 along the width direction can be 0.01um to 8um.
[0155] In some embodiments, the sidewalls of the pixel unit 100 are also covered with a first insulating layer 404 to ensure insulation between the first semiconductor layer 101 and the second semiconductor layer 103 in the pixel unit 100. The upper portion of the pixel unit 100 is at least partially covered with the first insulating layer 404. The first insulating layer 404 on the upper portion of the pixel unit 100 is located below the thin film covering layer 405.
[0156] It can be understood that in some embodiments, the pixel unit 100 and the peripheral adjacent annular partition 401 share a side wall, and in this case, the first insulating layer 404 on the side wall is also shared by both.
[0157] In some embodiments, the thickness of the thin film cover layer 405 is 0.05 um to 8 um.
[0158] In some embodiments, the first insulating layer 404 and the thin film cover layer 405 are both transparent material layers.
[0159] Next, a preparation method corresponding to the semiconductor device described in the present embodiment is described.
[0160] The preparation method of the semiconductor device in the present embodiment can include the following steps:
[0161] Step S1: selecting a compound semiconductor layer as a pixel layer 400;
[0162] Step S2: etching the pixel layer 400 to obtain at least one pixel unit 100, each pixel unit 100 obtained by etching has at least one annular isolation groove 401 around the periphery, so that the outermost annular isolation groove 401 of each pixel unit 100 and the outermost annular isolation groove 401 of the adjacent pixel unit 100 at least partially overlap, and the non-overlapping area retains a compound semiconductor; or,
[0163] so that the outermost annular isolation groove 401 of each pixel unit 100 and the outermost annular isolation groove 401 of the adjacent pixel unit 100 retain a compound semiconductor to separate each other.
[0164] In some embodiments, the preparation method further includes: connecting the pixel layer 400 and the substrate 200, so that the pixel layer 400 is located on the upper part of the substrate 200, before etching the pixel layer 400 to obtain at least one pixel unit 100.
[0165] The pixel layer 400 includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in order from top to bottom. One of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
[0166] In some embodiments, step S2 can include the following steps:
[0167] Step S21: providing an etching stop layer 403 on the upper surface of the pixel layer 400, and etching the etching stop layer 403 to obtain a patterned mask layer;
[0168] Step S22: etching the pixel layer 400 with the mask layer to obtain at least one pixel unit 100, and forming at least one annular isolation groove 401 around the periphery of each pixel unit 100, so that the outermost annular isolation groove 401 of each pixel unit 100 and the outermost annular isolation groove 401 of the adjacent pixel unit 100 at least partially overlap, and the non-overlapping area retains a compound semiconductor; or,
[0169] so that the outermost annular isolation groove 401 of each pixel unit 100 and the outermost annular isolation groove 401 of the adjacent pixel unit 100 retain a compound semiconductor to separate each other.
[0170] Step S23: depositing a first insulating layer 404 on the surface of the pixel layer 400, so that the first insulating layer 404 covers at least the inner wall of the annular isolation groove 401 and the sidewall of the pixel unit 100, and the inner part of the annular isolation groove 401 forms a filling area 4011 surrounded by the first insulating layer 404;
[0171] Step S24: depositing a thin film cover layer 405 on the upper part of the pixel layer 400, the thin film cover layer 405 being an insulating medium, so that the upper part of the filling area 4011 is closed by the thin film cover layer 405.
[0172] When depositing the thin film cover layer 405, at least one downward protruding extension 4051 is formed on the thin film cover layer 405, and each extension 4051 extends into the corresponding filling area 4011, as shown in FIG. 10, the extension 4051 can extend only to the upper part of the filling area 4011, so that the lower part of the filling area 4011 forms an air isolation layer 40112, or, Figure 7
[0173] As shown in FIG. 10, the extension 4051 penetrates the filling area 4011, so that the filling area 4011 is filled with the extension 4051 to form a solid structure.
[0174] In some embodiments, the thin film cover layer 405 can be a single layer or a multi-layer structure of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, polyimide, etc.
[0175] In some embodiments, the thickness of the thin film cover layer 405 is 0.05um-8um. It can be understood that the thickness of the thin film cover layer 405 here refers to the thickness of the thin film cover layer 405 at the top of the pixel unit 100, excluding the extension 4051.
[0176] It can be understood that when using the above method for preparation, in step S23, when depositing the first insulating layer 404 on the surface of the pixel layer 400, a whole layer of the first insulating layer 404 can be first deposited on the surface of the pixel layer 400, so that the upper surface of the etching stop layer 403, the inner wall of the annular isolation groove 401, and the sidewall of the pixel unit 100 are all covered by the first insulating layer 404, and then the thin film cover layer 405 in the subsequent step S24 is deposited on the upper part of the first insulating layer 404 on the upper surface of the pixel layer 400, and then part of the etching stop layer 403 at the top of the pixel unit 100 and the first insulating layer 404 and the thin film cover layer 405 thereon can be removed to expose part of the first semiconductor for subsequent electrical connection.
[0177] The main difference between the semiconductor device of the embodiment and the semiconductor device of the embodiment one is that a thin film cover layer 405 is prepared after the first insulating layer 404 is deposited, and the air gap of the filling area 4011 and the forming method of the solid structure are different.
[0178] Embodiment three
[0179] Referring to Figure 11 The main difference between the embodiment and the embodiment one is that the inner wall of the annular isolation groove 401 is covered with the first insulating layer 404 and the first reflective layer 406 in sequence.
[0180] Specifically, the inner wall of the annular isolation groove 401 is covered with the first insulating layer 404, the annular isolation groove 401 has a filling area 4011, the periphery of the filling area 4011 is surrounded by the first insulating layer 404, and the outer part of the first insulating layer 404 further has the first reflective layer 406.
[0181] The first reflective layer 406 can be a reflective metal layer, for example, a high reflective layer metal of Al, Ag, Au, Rh and the like can be used to form an omnidirectional reflector structure (ODR), so as to better prevent the problem of light crosstalk between pixels.
[0182] Further, as shown in Figure 11 The filling area 4011 contains an air gap 40112 composed of air, and the periphery of the air gap 40112 is surrounded by the first reflective layer 406, or
[0183] As shown in Figure 12 The first reflective layer 406 is used as the first filling material 40113, and the filling area 4011 is filled with the first filling material 40113 to form a solid structure.
[0184] Next, the preparation method of the semiconductor device of the embodiment is described.
[0185] The preparation method of the semiconductor device of the embodiment can include the following steps:
[0186] Step S1: selecting a compound semiconductor layer as a pixel layer 400;
[0187] Step S2: etching the pixel layer 400 to obtain at least one pixel unit 100, and the periphery of each pixel unit 100 obtained by etching is surrounded by at least one annular isolation groove 401, so that the outermost annular isolation groove 401 of each pixel unit 100 and the outermost annular isolation groove 401 of the adjacent pixel unit 100 at least partially overlap, and the non-overlapping area is reserved for the compound semiconductor; or
[0188] The compound semiconductor is reserved between the outermost annular groove 401 of each pixel unit 100 and the outermost annular groove 401 of the adjacent pixel unit 100 to separate each other.
[0189] Before the pixel layer 400 is etched to obtain at least one pixel unit 100, the method further comprises: connecting the pixel layer 400 and the substrate 200, so that the pixel layer 400 is located on the upper part of the substrate 200.
[0190] The pixel layer 400 comprises a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom. One of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
[0191] In some embodiments, step S2 can comprise the following steps:
[0192] Step S21: An etching stop layer 403 is arranged on the upper surface of the pixel layer 400, and the etching stop layer 403 is etched to obtain a patterned mask layer.
[0193] Step S22: The pixel layer 400 is etched by the mask layer to obtain at least one pixel unit 100, and at least one annular groove 401 is formed on the periphery of each pixel unit 100, so that the outermost annular groove 401 of each pixel unit and the outermost annular groove 401 of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with a compound semiconductor; or,
[0194] The compound semiconductor is reserved between the outermost annular groove 401 of each pixel unit 100 and the outermost annular groove 401 of the adjacent pixel unit 100 to separate each other.
[0195] Step S23: A first insulating layer 404 is deposited on the surface of the pixel layer 400, so that the first insulating layer 404 covers at least the inner wall of the annular groove 401 and the sidewall of the pixel unit 100, and the inside of the annular groove 401 forms a filling area 4011 surrounded by the first insulating layer 404.
[0196] Step S24: A first reflective layer 406 is deposited on the pixel layer 400, so that the outside of the first insulating layer 404 on the inner wall of the annular groove 401 is covered with the first reflective layer 406, and the filling area 4011 is reserved with air to form an air separation layer 40112, the periphery of the air separation layer 40112 surrounds the first reflective layer 406, or,
[0197] The first reflective layer 406 is used as a first filler 40113, so that the filling area 4011 is filled with the first filler 40113 to form a solid structure.
[0198] It can be understood that, when prepared by the above method, in step S23, when the first insulating layer 404 is deposited on the surface of the pixel layer 400, a whole layer of the first insulating layer 404 can be first deposited on the surface of the pixel layer 400, so that the upper surface of the etching stop layer 403, the inner wall of the annular isolation groove 401, and the sidewall of the pixel unit 100 are all covered by the first insulating layer 404. Then, in the subsequent step S24, the first reflective layer 406 is deposited on the upper part of the first insulating layer 404 on the upper surface of the pixel layer 400. Subsequently, part of the etching stop layer 403 on the top of the pixel unit 100 and the first reflective layer 406 or the non-light-transmitting material layer on the top of the pixel unit 100 can be removed, so that the light emitted by the pixel unit 100 can be transmitted.
[0199] The main difference between the preparation method of the semiconductor device in this embodiment and that in Embodiment 1 is that the preparation of the first reflective layer 406 is additionally performed after the deposition of the first insulating layer 404, and the formation mode of the air isolation layer 40112 and the solid structure of the filling area 4011 is different.
[0200] Embodiment Four
[0201] Referring to Figures 13-14 The main difference between this embodiment and the above embodiments is that each pixel unit 100 is surrounded by at least two annular isolation grooves 401, and the compound semiconductor between the adjacent annular isolation grooves 401 around each pixel unit 100 is also reserved to form a partition wall 402, that is, the partition wall 402 itself is also a compound semiconductor material.
[0202] The preparation method of the semiconductor device in this embodiment is substantially the same as that in Embodiment 1, except that when the pixel layer 400 is etched by a mask layer to obtain at least one pixel unit 100, the etching is performed to form at least two annular isolation grooves 401 around each pixel unit 100, so that the compound semiconductor between the adjacent annular isolation grooves around each pixel unit 100 is reserved to form a partition wall 402.
[0203] For example, Figures 13-14 Each pixel unit is surrounded by two annular isolation grooves 401, wherein Figure 13 Only the internal structure schematic diagram of one pixel area (one pixel unit and the surrounding area) is shown, Figure 14 A top view arrangement schematic diagram of multiple pixel areas is shown.
[0204] In this embodiment, each pixel unit 100 is surrounded by at least two annular isolation grooves 401, which can improve the heat dissipation effect, and can also better prevent the diffusion of metal atoms to the sidewall of the pixel unit 100 through the partition wall 402 structure, so as to better reduce the risk of device leakage and improve the reliability of the device.
[0205] The technical solutions in the embodiments can be applied to the above-mentioned embodiments to meet the requirements of different application scenarios.
[0206] Embodiment Five
[0207] With reference to Figure 15 The embodiment discloses an LED display device, which comprises a substrate 200 and a pixel layer 400 in the semiconductor device described in the above-mentioned embodiments.
[0208] The substrate 200 is a driving wafer, the driving wafer has a driving circuit, the pixel unit 100 is a light-emitting element, and the driving wafer is electrically connected with the pixel unit 100 to control the pixel unit 100 to emit light.
[0209] The pixel layer 400 is located on the upper part of the substrate 200, the pixel layer 400 and the driving wafer are bonded through the bonding layer 300, the bottom surface of the annular isolation groove 401 is not lower than the upper surface of the bonding layer 300, so that the bonding layer 300 below the annular isolation groove 401 is not etched to maximize the retention of the bonding layer 300 material, the bonding layer 300 usually adopts a conductive metal material, and the metal material has a high thermal conductivity. In this way, the heat diffusion area can be increased, the heat dissipation capacity of the pixels in the display area 201 of the device is improved, and the heat aggregation phenomenon of the pixel unit 100 is reduced.
[0210] Further, the upper surface of the driving wafer is divided into at least one display area 201, and at least one pixel unit 100 exists above each display area 201, that is, the display area 201 is a region covered by the pixel unit 100 (at least one pixel unit 100) to form an image display area 201.
[0211] The bonding layer 300 above each display area 201 is continuously arranged to further retain the bonding layer 300 material and improve the heat dissipation area, so that the heat dissipation effect of the device is improved.
[0212] For example, each display area 201 has a pixel array composed of a plurality of pixel units 100 above the display area 201, that is, each display area 201 is covered by a corresponding pixel array, and the projection of the pixel array on the driving wafer is located in the corresponding display area 201. The bonding layer 300 above each display area 201 can be understood as the bonding layer whose projection on the driving wafer falls into the display area. Therefore, the bonding layer above each display area needs to be continuously arranged in the corresponding region of the display area. Specifically, the bonding layer above the display area can be continuously arranged in the corresponding upper region of the display area, and the bonding layer between the display areas is discontinuous (for example, Figure 16The plurality of display areas 201 can share one continuous bonding layer 300, for example, two display areas 201 share one continuous bonding layer 300 (as shown in K1 region), or four display areas 201 share one continuous bonding layer 300 (as shown in K2 region), or nine display areas 201 share one continuous bonding layer 300 (as shown in K3 region), or sixteen display areas 201 share one continuous bonding layer 300 (as shown in K4 region), and so on. Figure 16 The plurality of display areas 201 can share one continuous bonding layer 300, for example, two display areas 201 share one continuous bonding layer 300 (as shown in K1 region), or four display areas 201 share one continuous bonding layer 300 (as shown in K2 region), or nine display areas 201 share one continuous bonding layer 300 (as shown in K3 region), or sixteen display areas 201 share one continuous bonding layer 300 (as shown in K4 region), and so on. Figure 16 The plurality of display areas 201 can share one continuous bonding layer 300, for example, two display areas 201 share one continuous bonding layer 300 (as shown in K1 region), or four display areas 201 share one continuous bonding layer 300 (as shown in K2 region), or nine display areas 201 share one continuous bonding layer 300 (as shown in K3 region), or sixteen display areas 201 share one continuous bonding layer 300 (as shown in K4 region), and so on. Figure 16 The plurality of display areas 201 can share one continuous bonding layer 300, for example, two display areas 201 share one continuous bonding layer 300 (as shown in K1 region), or four display areas 201 share one continuous bonding layer 300 (as shown in K2 region), or nine display areas 201 share one continuous bonding layer 300 (as shown in K3 region), or sixteen display areas 201 share one continuous bonding layer 300 (as shown in K4 region), and so on.
[0213] The pixel unit 100 comprises, from top to bottom, a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103, one of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
[0214] In some modes, the driving wafer can be provided with a first type of electrode contact and a second type of electrode contact, the polarities of the first type of electrode contact and the second type of electrode contact are opposite, the second semiconductor layer 103 is electrically connected with the first type of electrode contact, and the first semiconductor layer 101 is electrically connected with the second type of electrode contact.
[0215] Further, the upper part of the pixel layer 400 can be provided with a conductive layer, the first semiconductor layer 101 of the pixel unit 100 is electrically connected with the second type of electrode contact through the conductive layer, and the second semiconductor layer 103 of the pixel unit 100 is electrically connected with the first type of electrode contact through the bonding layer 300.
[0216] The driving wafer described above includes but is not limited to a CMOS (Complementary Metal Oxide Semiconductor) driving backplane or a TFT glass substrate, etc.
[0217] The LED display device described above includes but is not limited to a Micro-LED, a Micro-Laser, and other display devices.
[0218] All the optional technical solutions described above can be combined to form optional embodiments of the present application, that is, any number of embodiments can be combined to meet the needs of different application scenarios, which are all within the protection scope of the present application and will not be described one by one here.
[0219] It should be noted that the above-mentioned embodiments are only examples for clearly illustrating the present application and are not intended to limit the present application. Based on the above-mentioned embodiments, other different forms of changes or modifications can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated. The obvious changes or modifications derived from the above-mentioned embodiments are still within the scope of the present application.
Claims
1. A semiconductor device, characterized by: comprises, the pixel layer is a compound semiconductor layer, the pixel layer comprises pixel units, each of the pixel units is surrounded by at least one annular isolation groove, and the outermost annular isolation groove of each of the pixel units and the outermost annular isolation groove of an adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with the compound semiconductor; or, the outermost annular isolation groove of each of the pixel units and the outermost annular isolation groove of an adjacent pixel unit are completely separated from each other by the compound semiconductor reserved therebetween.
2. The semiconductor device of claim 1, wherein: Each of the pixel units is surrounded by at least two annular isolation grooves, and the adjacent annular isolation grooves of each of the pixel units are also reserved with the compound semiconductor to form a partition wall.
3. The semiconductor device of claim 1, wherein: The maximum size of the annular isolation groove in the width direction is L2, and L2 is 0.02 um to 10 um.
4. The semiconductor device of claim 1, wherein: The pixel layer is located on the upper portion of the substrate, the pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the lower end of the annular isolation groove extends between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the annular isolation groove extends at least to the upper surface of the first semiconductor layer.
5. The semiconductor device of claim 4, wherein: The upper portion of the first semiconductor layer is further provided with an etching stop layer, and the upper end of the annular isolation groove extends at least to the upper surface of the etching stop layer.
6. The semiconductor device of claim 1, wherein: The inner wall of the annular isolation groove is covered with a first insulating layer, the annular isolation groove has a filling area, the periphery of the filling area is surrounded by the first insulating layer, the filling area contains air to form an air isolation layer, or the filling area is filled with a first filler to form a solid structure.
7. The semiconductor device of claim 6, wherein, The upper portion of the pixel layer is covered with a thin film cover layer, and the upper portion of the filling area is closed by the thin film cover layer.
8. The semiconductor device of claim 7, wherein, The thin film cover layer comprises an extension protruding downward, the extension extends into the filling area, the extension only extends to the upper portion of the filling area, and the lower portion of the filling area forms the air isolation layer. Or, the extension serves as a first filler, and the filling area is filled with the first filler to form a solid structure.
9. The semiconductor device of claim 7, wherein, The sidewall of the pixel unit is covered with the first insulating layer, and the upper portion of the pixel unit is at least partially covered with the first insulating layer, and the first insulating layer of the upper portion of the pixel unit is located below the thin film cover layer.
10. The semiconductor device of claim 7, wherein The thickness of the thin film cover layer is 0.05 um to 8 um.
11. The semiconductor device of claim 6, wherein The inner wall of the annular isolation groove is sequentially covered with a first insulating layer and a first reflective layer.
12. The semiconductor device of claim 11, wherein, The filling area contains air to form an air isolation layer, and the periphery of the air isolation layer is surrounded by the first reflective layer, or The first reflective layer serves as a first filler, and the filling area is filled with the first filler to form a solid structure.
13. The semiconductor device of claim 6, wherein The thickness of the first insulating layer is 5 nm to 2 um.
14. The semiconductor device of claim 1, wherein, The height of the pixel unit is 0.1 um to 5 um.
15. A method of fabricating a semiconductor device, characterized by: The method comprises the following steps: selecting a compound semiconductor layer as a pixel layer; The pixel layer is etched to obtain at least one pixel unit, and each pixel unit is surrounded by at least one annular groove, so that the outermost annular groove of each pixel unit and the outermost annular groove of the adjacent pixel unit at least partially overlap, and the compound semiconductor is reserved in the non-overlapping area; or, The outermost annular groove of each pixel unit and the outermost annular groove of the adjacent pixel unit are completely separated by the compound semiconductor reserved therebetween.
16. The method of claim 16, wherein: When the pixel layer is etched to obtain at least one pixel unit, the method comprises, An etching stop layer is arranged on the upper surface of the pixel layer, and the etching stop layer is etched to obtain a patterned mask layer; The pixel layer is etched by the mask layer to obtain at least one pixel unit, and at least one annular groove is formed in the periphery of each pixel unit.
17. The method of claim 16, wherein: The pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, and when the pixel layer is etched by the mask layer to obtain at least one pixel unit and at least one annular groove is formed in the periphery of each pixel unit, the method comprises, After etching, the lower end of the annular groove is located between the lower surface of the active layer and the upper surface of the substrate, and the upper end extends to at least the upper surface of the first semiconductor layer.
18. The method of claim 16, wherein: When the pixel layer is etched by the mask layer to obtain at least one pixel unit, at least two annular grooves are formed in the periphery of each pixel unit, so that the compound semiconductor between the adjacent annular grooves in the periphery of each pixel unit is reserved to form a partition wall.
19. The method of claim 16, wherein: After the pixel layer is etched by the mask layer to obtain at least one pixel unit, the method further comprises, A first insulating layer is deposited on the surface of the pixel layer, so that the first insulating layer covers at least the inner wall of the annular groove and the sidewall of the pixel unit, and the inside of the annular groove forms a filling area surrounded by the first insulating layer.
20. The method of claim 19, wherein: When the filling area is formed in the annular groove or after the filling area is formed, a first filler is filled in the filling area to fill the filling area to form a solid structure.
21. The method of claim 20, wherein: The first filler is an insulating medium or a metal.
22. The method of claim 19, wherein: After the filling area is formed in the annular groove, a thin film cover layer is deposited on the upper part of the pixel layer, so that the upper part of the filling area is closed by the thin film cover layer.
23. The method of claim 22, wherein: When the thin film cover layer is deposited on the upper part of the pixel layer, the method further comprises, At least one downward protruding extension is formed on the thin film cover layer, and each extension extends into the corresponding filling area, so that the extension only extends to the upper part of the filling area, so that the lower part of the filling area forms an air separation layer, or The extension penetrates the filling area, so that the filling area is filled by the extension to form a solid structure.
24. The method of claim 19, wherein: After forming the filling area inside the annular isolation groove, a first reflective layer is deposited on the pixel layer, so that the outer part of the first insulating layer on the inner wall of the annular isolation groove is covered by the first reflective layer, and so that the air inside the filling area forms an air isolation layer, the periphery of the air isolation layer surrounding the first reflective layer, or The first reflective layer is used as a first filling material, so that the filling area is filled with the first filling material to form a solid structure.
25. The method of claim 24, wherein: The first reflective layer is metal.
26. An LED display device, comprising: The semiconductor device of any one of claims 1-14, wherein the substrate is a driving wafer, the pixel layer is located on the upper part of the substrate, the pixel layer and the driving wafer are bonded by a bonding layer, and the bottom surface of the annular isolation groove is not lower than the upper surface of the bonding layer.
27. The LED display device according to claim 26, characterized in that: The upper surface of the driving wafer is divided into at least one display area, each display area being covered by at least one pixel unit, and the bonding layer above each display area is continuously arranged.