LED display device and preparation method

Abstract

The invention relates to an LED display device and a preparation method, the LED display device comprises a substrate and a pixel layer, the substrate is a driving wafer, the pixel layer is located on the upper portion of the substrate, pixel units and interconnection conductive parts are arranged in the pixel layer, the tops of the pixel units are electrically connected with corresponding second-class electrode contacts through the interconnection conductive parts, and the second-class electrode contacts are electrically connected with the substrate through the interconnection conductive parts. The bottoms of the pixel units are electrically connected with the corresponding first type of electrode contacts; wherein the interconnection conductive part comprises a core body, the core body is a compound semiconductor, the core body is located in the first inner fence, the first inner fence is a conductive part, and the tops of the pixel units are electrically connected with the corresponding second type of electrode contacts through the first inner fence of the interconnection conductive part. The invention further discloses a preparation method of the LED display device. According to the invention, the production cost of the LED display device is effectively reduced, and the stability and reliability of the LED display device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly to an LED display device and a preparation method thereof. BACKGROUND

[0002] The LED display chip generally comprises a driving wafer and a plurality of pixel units (i.e. light emitting units), the driving wafer is provided with corresponding electrode contacts, the pixel units need to be electrically connected with the corresponding electrode contacts through the interconnection conductive member to realize the conduction of the cathode (or anode), but the existing interconnection conductive member generally adopts a metal member, and the interconnection conductive member is formed by first opening a backfill hole and then filling metal in the backfill hole during preparation, the preparation process is relatively complex, a large amount of raw materials need to be removed, the production cost is high, and metal atoms are prone to diffuse to the surrounding, which may cause a risk of electric leakage, and cannot meet the production requirements. SUMMARY

[0003] Therefore, the main technical problem to be solved by the present application is to reduce the production cost of the LED display device in the prior art and improve the stability and reliability of the LED display device.

[0004] To solve the above technical problems, the present application provides an LED display device, comprising,

[0005] a substrate, the substrate is a driving wafer, the driving wafer is connected with a first type of electrode contact and a second type of electrode contact, and the polarities of the first type of electrode contact and the second type of electrode contact are opposite;

[0006] a pixel layer, the pixel layer is located on the upper part of the substrate, the pixel layer is provided with a pixel unit and an interconnection conductive member, the top of the pixel unit is electrically connected with the corresponding second type of electrode contact through the interconnection conductive member, and the bottom of the pixel unit is electrically connected with the corresponding first type of electrode contact;

[0007] wherein the interconnection conductive member comprises a core body, the core body is a compound semiconductor, the core body is located inside a first inner fence, the first inner fence is a conductive member, and the top of the pixel unit is electrically connected with the corresponding second type of electrode contact through the first inner fence of the interconnection conductive member.

[0008] In an embodiment of the present application, the top of the pixel unit is connected with a first conductive layer, the upper part of the first inner fence of the interconnection conductive member is electrically connected with the first conductive layer, and the lower part is electrically connected with the corresponding second type of electrode contact.

[0009] In an embodiment of the present application, the upper part of the first inner fence of the interconnection conductive member is electrically connected with the first conductive layer through a metal reinforcing member.

[0010] In one embodiment of the present application, the upper part of the first inner fence is covered by the metal reinforcing member.

[0011] In one embodiment of the present application, the substrate and the pixel layer are connected by a bonding layer, the bonding layer is a metal layer, and the first inner fence is formed on the bonding layer.

[0012] In one embodiment of the present application, the interconnection conductive members are located at the periphery of the pixel units.

[0013] In one embodiment of the present application, the pixel layer is provided with a first cut groove, the first cut groove is annular, the first cut groove penetrates the bonding layer, the periphery of the interconnection conductive members is surrounded by the first cut groove, a first outer fence is further formed on the bonding layer, the inner cavity of the first outer fence penetrates the bonding layer, the first outer fence is located in each of the first cut grooves, the first inner fence is arranged in the inner cavity of the first outer fence, the first inner fence has the core inside, and the first outer fence and the first inner fence are isolated by a second insulating layer.

[0014] In one embodiment of the present application, the interconnection conductive members at the periphery of the pixel units are separated by a non-light-emitting region, the non-light-emitting region is a compound semiconductor, and the non-light-emitting region is located between the first outer fence at the periphery of the pixel units and the interconnection conductive members.

[0015] In one embodiment of the present application, the interconnection conductive members at the periphery of the pixel units are separated by an insulating filling region, the insulating filling region is located between the first inner fence of the pixel units and the interconnection conductive members, and the insulating filling region is filled with an insulating material.

[0016] In one embodiment of the present application, the side wall of the first inner fence directly contacts the inner core, or an insulating deposition layer is arranged between the side wall of the first inner fence and the inner core.

[0017] In one embodiment of the present application, the periphery of the pixel units is surrounded by at least one annular separation groove, and the interconnection conductive members are located at the periphery of the outermost annular separation groove of the pixel units.

[0018] In one embodiment of the present application, the inner wall of the annular separation groove is covered with a first insulating layer, the annular separation groove has a filling region inside, the periphery of the filling region is surrounded by the first insulating layer on the inner wall of the annular separation groove, and the filling region is filled with air to form an air separation layer, or the filling region is filled with a first filler to form a solid structure.

[0019] In one embodiment of the present application, the pixel unit periphery further has a partition wall, the partition wall is a compound semiconductor, and a ring-shaped partition groove is formed between the pixel unit periphery and the partition wall closest to the periphery.

[0020] The present application also discloses a preparation method of an LED display device, comprising the following steps:

[0021] selecting a driving wafer as a substrate, the driving wafer being connected with a first type of electrode contact and a second type of electrode contact with opposite polarities; and selecting a compound semiconductor layer as a pixel layer;

[0022] connecting the pixel layer to the upper part of the substrate;

[0023] performing etching treatment on the pixel layer to obtain a core of the interconnection conductive member, the core being a compound semiconductor and being located inside a first inner fence, the first inner fence being a conductive member;

[0024] electrically connecting the top of the pixel unit to the first inner fence of the interconnection conductive member and the corresponding second type of electrode contact, and electrically connecting the bottom of the pixel unit to the corresponding first type of electrode contact.

[0025] In one embodiment of the present application, when the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

[0026] In one embodiment of the present application, when the core of the interconnection conductive member is obtained by performing etching treatment on the pixel layer and the core is located inside the first inner fence, the method comprises:

[0027] performing etching treatment on the pixel layer to obtain a first cut groove, the first cut groove being ring-shaped, so that the first cut groove penetrates through the bonding layer, and the area surrounded by the inner wall of the first cut groove is reserved to form an interconnection conductive member, the interconnection conductive member comprising a core, the core being a compound semiconductor, the bonding layer below the core being connected to the corresponding second type of electrode contact, and a first inner fence being formed on the bonding layer below the core, so that the core is covered inside the first inner fence, and a first outer fence being further formed on the bonding layer of the periphery of the interconnection conductive member, the inner cavity of the first outer fence penetrating through the bonding layer, the first outer fence being located in the first cut groove, and the first inner fence being located in the inner cavity of the first outer fence;

[0028] a second insulating layer is arranged between the first outer fence and the first inner fence inside to perform insulation and isolation.

[0029] In one embodiment of the present invention, in the above method, the interconnected conductive member is formed on the periphery of the corresponding pixel unit, and when the first groove is obtained by etching on the pixel layer, the compound semiconductor between the pixel unit and the peripheral interconnected conductive member is retained to form a non-luminous area, and the non-luminous area is located between the pixel unit and the first outer fence around the interconnected conductive member.

[0030] In one embodiment of the present invention, when the pixel layer is etched to obtain a core of an interconnected conductive member, the core is a compound semiconductor, and the core is located inside the first inner fence, the method further comprises:

[0031] The interconnected conductive member is formed at the periphery of the corresponding pixel unit, and an insulating filling area is constructed between the pixel unit and the first inner fence of the peripheral interconnected conductive member. The original material in the insulating filling area is removed and filled with insulating material.

[0032] The above technical solution of the present invention has the following advantages over the prior art:

[0033] The LED display device and preparation method thereof of the present invention effectively reduce production costs, simplify the preparation process, and make the interconnected conductive parts easier to prepare and have higher stability, thereby better ensuring the stability and reliability of the LED display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0035] Figure 1 It is a structural schematic diagram of a first LED display device of the present invention;

[0036] Figure 2 yes Figure 1 A partial enlarged view of M2 in the middle;

[0037] Figure 3 yes Figure 1 A partial enlarged view of M1 in the middle;

[0038] Figure 4 is a schematic structural diagram of a second LED display device of the present invention;

[0039] Figure 5 yes Figure 4 A partial enlarged view of M3 in the middle;

[0040] Figure 6 1 is a schematic structural diagram of a third LED display device of the present invention;

[0041] Figure 7is a structural schematic diagram of a compound semiconductor layer of the present application;

[0042] Figure 8 is a bonding flow chart of a pixel layer and a driving wafer in the present application;

[0043] Figure 9 is Figure 1 is a preparation flow chart of the LED display device shown in the figure;

[0044] Figure 10 is Figure 4 is a preparation flow chart of the LED display device shown in the figure;

[0045] Figure 11 is Figure 6 is a preparation flow chart of the LED display device shown in the figure;

[0046] Description of the drawings:

[0047] 100, pixel unit; 101, first semiconductor layer; 102, active layer; 103, second semiconductor layer;

[0048] 200, substrate; 201, first type of electrode contact; 202, second type of electrode contact;

[0049] 300, bonding layer; 301, first peripheral fence; 302, second peripheral fence;

[0050] 400, pixel layer; 401, annular isolation groove; 4011, filling area; 402, isolation wall; 403, etching barrier layer; 404, first insulating layer; 405, thin film cover layer; 406, second insulating layer; 407, first cutting groove; 408, non-light-emitting area; 409, first to-be-filled area; 410, insulating filling area; 411, insulating deposition layer;

[0051] 500, ohmic contact layer;

[0052] 600, interconnection conductive member; 601, core; 602, first inner fence;

[0053] 700, first conductive layer;

[0054] 800, metal reinforcement; DETAILED DESCRIPTION

[0055] The present application will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present application and implement it. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present disclosure and its application or use.

[0056] In the description of the present application, it needs to be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0057] In the description of the present application, it needs to be understood that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0058] The LED display device in the prior art has problems of complex preparation process, high production cost, poor reliability and the like. In view of this, the present application provides a display device to improve the above problems, so as to better ensure the photoelectric performance and reliability of the LED display device.

[0059] It should be noted that the compound semiconductor layer in the present application refers to a layer structure with a certain thickness prepared from a compound semiconductor material. Compound semiconductors generally refer to compounds formed by two or more elements, including crystalline inorganic compounds (such as III-V, II-VI compound semiconductors) and oxide semiconductors. The compound semiconductors involved in the present application are mainly light emitting diode epitaxial materials, such as InGaN ternary material system or AlGaInP quaternary material system, etc., which can cover the full wavelength range from ultraviolet, visible light and infrared, and the substrate material can be GaN, Si, SiC, sapphire, GaAs, InP, etc.

[0060] For example, in the field of Micro-LED, some compound semiconductor materials involved in the present application are shown in Table 1. In some practical applications, the film layer of the compound semiconductor is more complex, or there is a cross-use of materials. The typical compound semiconductor mainly includes P-type semiconductor material, N-type semiconductor material, and MQW active quantum well and other functional layers (barrier layer, confinement layer, waveguide layer, buffer layer, etc.) sandwiched therebetween:

[0061] Table 1: Film layer material table of compound semiconductor

[0062]

[0063] The related structure of the LED display device of the present application will be further described below in conjunction with the following specific embodiments.

[0064] Embodiment One

[0065] Referring to Figures 1-3 The present embodiment discloses an LED display device, which comprises a substrate 200 and a pixel layer 400,

[0066] The substrate 200 is a driving wafer, and the driving wafer is connected with a first type of electrode contact 201 and a second type of electrode contact 202. The polarities of the first type of electrode contact 201 and the second type of electrode contact 202 are opposite, one of which is positive and the other of which is negative. It can be understood that the first type of electrode contact 201 and the second type of electrode contact 202 need to be insulated and isolated to prevent short circuit caused by direct contact therebetween

[0067] The pixel layer 400 is located on the upper part of the substrate 200, and the pixel layer 400 is provided with a pixel unit 100 and an interconnection conductive member 600. The top of the pixel unit 100 is electrically connected to the corresponding second type of electrode contact 202 through the interconnection conductive member 600, and the bottom of the pixel unit 100 is electrically connected to the corresponding first type of electrode contact 201, so as to realize the electrical connection between the pixel unit 100 and the driving wafer.

[0068] The interconnection conductive member 600 comprises a core 601, and the core 601 is a compound semiconductor. The core 601 is located inside a first inner fence 602, and the first inner fence 602 is a conductive member. The top of the pixel unit 100 is electrically connected to the corresponding second type of electrode contact 202 through the first inner fence 602 of the interconnection conductive member 600.

[0069] Specifically, the upper part of the first inner fence 602 is electrically connected to the top of the pixel unit 100, and the lower part of the first inner fence 602 is electrically connected to the corresponding second type of electrode contact 202.

[0070] It can be understood that the top and bottom of the pixel unit 100 are respectively two ends of opposite polarity, for example, the top is the end where the N-type semiconductor (or the end where the P-type semiconductor) is located, and the bottom is the end where the P-type semiconductor (or the end where the N-type semiconductor) is located, and needs to be connected to electrode contacts of different polarities. Among them, the pixel unit and the electrode contact (the first type of electrode contact or the second type of electrode contact) can be one-to-one correspondence, or one-to-many form, for example, one second type of electrode contact can correspond to one pixel unit, or multiple second type of electrode contacts can correspond to one pixel unit, and similarly, the first type of electrode contact is the same.

[0071] Among them, the driving wafer is an element with a driving circuit, the first type of electrode contact 201 and the second type of electrode contact 202 are the lead terminals of the driving circuit, used to electrically connect the driving circuit and the pixel unit, and the pixel unit 100 is a light-emitting element. The electrical connection between the driving wafer and the pixel unit 100 can control the light-emitting of the pixel unit 100.

[0072] The driving wafer includes but is not limited to a CMOS (Complementary Metal Oxide Semiconductor) driving backplane or a TFT glass substrate, etc.

[0073] The above structure can electrically connect the driving wafer and the pixel unit 100 through the first type of electrode contact 201 and the second type of electrode contact 202, so as to control the light-emitting of each pixel unit 100 by the driving wafer.

[0074] In some preferred modes, each pixel unit 100 in the pixel layer 400 can independently emit light.

[0075] The above structure has a core structure of compound semiconductor material for the interconnection conductive member, instead of being completely prepared by metal material. This mode can directly retain and utilize the original compound semiconductor material in the pixel layer, thereby improving the utilization rate of the original preparation material-compound semiconductor material, reducing the production cost, simplifying the preparation process, and further, the core of the above compound semiconductor material has high stability and is not prone to metal atom diffusion to the periphery during preparation, which can greatly reduce the risk of electric leakage, improve the product yield, and better guarantee the stability and reliability of the LED display device.

[0076] It should be noted that the "width" direction in the present application is the X direction, the "height" or "up-down" direction is the Z direction, and there is also a Y direction, wherein the X direction, the Y direction, and the Z direction are perpendicular to each other. The pixel layer 400 (compound semiconductor layer) includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom. The Z direction is the stacking direction of the first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103.

[0077] In some embodiments, the top of the pixel unit 100 is connected with a first conductive layer 700, the upper part of the first inner fence 602 of the interconnection conductive member 600 is electrically connected with the first conductive layer 700, and the lower part is electrically connected with the corresponding second type of electrode contact 202.

[0078] The first conductive layer 700 described above can be a transparent conductive layer.

[0079] For example, the transparent conductive layer described above can be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, or gold-doped indium tin oxide.

[0080] In some preferred embodiments, the upper part of the first inner fence 602 of the interconnection conductive member 600 is electrically connected with the first conductive layer 700 through a conductive metal reinforcement 800.

[0081] For example, the metal reinforcement 800 can be arranged directly above the interconnection conductive member 600, and the electrical connection is achieved by the contact between the metal reinforcement 800 and the first conductive layer 700, which is more convenient for preparation.

[0082] The metal reinforcement 800 is made of a metal material, which can better achieve current spreading and enhance the conductive capacity.

[0083] Further, the upper part of the first inner fence 602 is covered by the metal reinforcement 800 to improve the stability of the electrical connection.

[0084] In some embodiments, the top surface of the core 601 of the interconnection conductive member 600 is higher than the top surface of the first inner fence 602, and to further ensure the stability of the connection, the part of the core 601 that protrudes out of the first inner fence 602 is also covered by the metal fence.

[0085] Further, the top surface of the metal reinforcement 800 has a recessed part or is a flat surface.

[0086] In the embodiment, the substrate 200 and the pixel layer 400 are connected through the bonding layer 300, the bonding layer 300 is a conductive metal layer, and the first inner fence 602 is formed on the bonding layer 300. It can be understood that the metal layer is conductive, and the first inner fence 602 is a metal fence sputtered by the bonding layer 300. It can be understood that the core 601 is connected to the second electrode contact 202 through the bonding layer 300 at the bottom of the core 601, and the bonding layer 300 at the bottom of the core 601 and the first inner fence 602 are integrally formed.

[0087] Further, the bonding layer 300 and the pixel layer 400 are further provided with an ohmic contact layer 500, a part of the ohmic contact layer 500 is contained in the first inner fence 602, and the ohmic contact layer 500 in the first inner fence 602 is located below the core 601.

[0088] The pixel unit 100 in the embodiment includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom, the second electrode contact 202 is used to electrically connect the first semiconductor layer 101 in the corresponding pixel unit 100, and the first electrode contact 201 is used to electrically connect the second semiconductor layer 103 in the corresponding pixel unit 100.

[0089] Among them, one of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. The active layer 102 described above is used for light emission and can be an MQW active quantum well.

[0090] The ohmic contact layer 500 described above is located between the second semiconductor layer 103 and the bonding layer 300, and is used to better realize the ohmic contact between the second semiconductor layer and the bonding layer 300.

[0091] For example, the ohmic contact layer 500 can be a transparent conductive film made of one or more of ITO, IZO, IGZO or AZO, or can be a metal layer made of one or more of Ni, Cr, Au, Ag, Zn, Rh, Be or Al, or can be an alloy layer, or can also be a stack of transparent metal oxide and metal;

[0092] The thickness of the ohmic contact layer 500 described above is 1nm-500nm, and the thickness is too large to cause waste of materials, and the thickness is too small to easily achieve better ohmic contact effect.

[0093] In some embodiments, the bonding layer 300 can be one or more of a Ni, Sn combination, an Au, Sn combination, a Cu, Sn combination, an Au, In combination, an Au, Au combination, an Al, Al combination, a Cu, Cu combination, or an ITO, ITO combination. An adhesion layer (such as Cr, Ti, Ni, etc.) and a barrier depletion layer (such as Ni, Pt, Cu, etc.) can also be provided between the bonding layer 300 and the driving wafer.

[0094] In some preferred embodiments, the bonding layer 300 can be a multi-layer structure stacked in the height direction, in which the layers from bottom to top are a Cr layer (adhesion layer), a Pt layer (barrier depletion layer), an Au layer, a Sn layer, and an Au layer, with thicknesses of 10 nm, 50 nm, 100 nm, 150 nm, and 50 nm, respectively.

[0095] In some embodiments, the interconnection conductive members 600 are located in the periphery of the pixel units 100.

[0096] In this embodiment, as shown in FIG. 4, the pixel layer 400 is provided with a first cut groove 407, which is annular, and the first cut groove 407 penetrates the bonding layer 300, and the periphery of each interconnection conductive member 600 is surrounded by the first cut groove 407. Figure 9

[0097] In this embodiment, as shown in FIG. 4, the pixel layer 400 is provided with a first cut groove 407, which is annular, and the first cut groove 407 penetrates the bonding layer 300, and the periphery of each interconnection conductive member 600 is surrounded by the first cut groove 407.

[0098] In the area surrounded by each first peripheral fence 301, the first peripheral fence 301 and the first inner fence 602 are separated by the second insulating layer 406.

[0099] Since the bonding layer 300 can also be connected to the first electrode contact, the second insulating layer 406 also insulates and separates the entire interconnection conductive member 600 and the second type of electrode contact 202 at the bottom from the first type of electrode contact 201, thereby avoiding short circuiting.

[0100] For example, the second insulating layer 406 can be one or more of a silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, aluminum nitride, gallium nitride, etc., in a single-layer structure or a stacked structure.

[0101] Further, as shown in FIG. 4, the pixel layer 400 is provided with a second cut groove 408, which is annular, and the second cut groove 408 penetrates the bonding layer 300, and the periphery of each interconnection conductive member 600 is surrounded by the second cut groove 408. Figure 1 ​As shown, the interconnection conductive member 600 is located at the periphery of the pixel unit 100, and the pixel unit 100 and the interconnection conductive member 600 at the periphery are separated by the non-light-emitting region 408, which is a compound semiconductor, between the pixel unit 100 and the first peripheral fence 301 at the periphery of the interconnection conductive member 600.

[0102] It can be understood that the above-mentioned "non-light-emitting region 408" refers to a region that is not used as a light-emitting unit, and only the "pixel unit 100" is required to be used as a light-emitting unit. The materials of the "non-light-emitting region 408" and the "pixel unit 100" are the same, and are both compound semiconductor materials.

[0103] By reserving the compound semiconductor material between the pixel unit and the interconnection conductive member at the periphery as a non-light-emitting region, the pixel unit and the interconnection conductive member can be sufficiently isolated, ensuring the isolation effect, so that the pixel unit is not easily failed due to the leakage phenomenon. In addition, the above-mentioned method can also reserve the compound semiconductor material to a large extent, and the compound semiconductor material has high thermal conductivity, which also effectively increases the heat dissipation performance of the LED device.

[0104] Further, the first inner fence 602 and the sidewall of the inner core 601 can be directly in contact.

[0105] In other ways, an insulating deposition layer 411 can also be provided between the first inner fence 602 and the sidewall of the inner core 601.

[0106] In some embodiments, the periphery of each pixel unit 100 is surrounded by at least one annular isolation groove 401, so as to realize the independence of the pixel unit 100 through the annular isolation groove 401.

[0107] Among them, the interconnection conductive member 600 is located at the periphery of the outermost annular isolation groove 401 of the pixel unit. Further, the above-mentioned non-light-emitting region 408 is located between the outermost annular isolation groove 401 of the pixel unit and the first peripheral fence 301 at the periphery of the interconnection conductive member.

[0108] In some embodiments, the minimum size of the annular isolation groove 401 in the width direction (X direction) is greater than 0, and the maximum size of the annular isolation groove 401 in the width direction (X direction) is L2, L2 is 0.02um-10um. The width should not be too large in order to maximize the reservation of semiconductor materials in the compound semiconductor layer and improve the heat dissipation effect. It should also not be too small, otherwise it will be not conducive to processing and ensuring the effective separation between the pixel units 100, and the light output effect will also be affected by too small width.

[0109] Further, as shown in FIG. 4, the first inner fence 602 and the sidewall of the inner core 601 can be directly in contact. Figure 3As shown, the inner wall of the annular isolation groove 401 is covered with a first insulating layer 404, and the inner part of the annular isolation groove 401 has a filling area 4011, which is surrounded by the first insulating layer 404 on the inner wall of the annular isolation groove 401, and the filling area 4011 contains air to form an air isolation layer, or the filling area 4011 is filled with a first filler to form a solid structure.

[0110] The first filler can be an insulating medium or metal, etc.

[0111] The first insulating layer 404 on the inner wall of the annular isolation groove 401 can better isolate the pixel unit 100 and prevent the phenomenon of electric leakage.

[0112] It should be noted that the inner wall of the annular isolation groove 401 includes a side wall and a bottom surface, and the side wall and the bottom surface are both covered with the first insulating layer 404. When the inner part of the filling area 4011 has an air isolation layer, the bottom surface of the air isolation layer is not lower than the bottom surface of the annular isolation groove 401.

[0113] It can be understood that in some modes, the pixel unit 100 and the peripherally adjacent (closest) annular isolation groove 401 share a side wall, and the first insulating layer 404 at the side wall is also shared by the two.

[0114] Further, the upper part of the pixel layer 400 is also deposited with the first insulating layer 404, and the upper part of the pixel unit 100 is at least partially covered with the first insulating layer 404, and the area not covered with the first insulating layer 404 forms an electrical contact area for contacting the first conductive layer 700. At this time, the upper surface of the non-light-emitting area 408 is also covered with the first insulating layer 404 to cover the upper surface of the non-light-emitting area 408.

[0115] For example, the first insulating layer 404 can be one or more of a silicon oxide, an aluminum oxide, a silicon nitride, a titanium oxide, a hafnium oxide, a tantalum oxide, a niobium oxide, an aluminum nitride, a gallium nitride, etc., to form a single-layer structure or a stacked-layer structure.

[0116] For example, the first insulating layer 404 can be a stacked-layer structure of silicon oxide and titanium oxide, and a DBR (distributed Bragg reflector) Bragg reflection structure is constructed by using the difference in refractive index of the two materials.

[0117] In some embodiments, a thin film cover layer 405 is further deposited on the upper portion of the pixel layer 400 to seal the upper portion of the filling region 4011 with the thin film cover layer 405; the thin film cover layer 405 is located above the first insulating layer 404 of the upper portion of the pixel layer 400; a second insulating layer 406 is further deposited on the thin film cover layer 405. The upper portion of the second insulating layer 406 above the pixel layer 400 is provided with a first conductive layer 700, so that a portion of the first conductive layer 700 is in contact with the top of the pixel unit 100 and a portion is connected to the top surface of the interconnection conductive member 600.

[0118] The thin film cover layer 405 described above can be an insulating material layer.

[0119] In some embodiments, the top surface of the non-light emitting region 408 in the pixel layer 400 is further provided with an etching stop layer 403 to be used as an etching mask during etching.

[0120] The etching stop layer 403, the first insulating layer 404 and the thin film cover layer 405 described above are all transparent material layers.

[0121] In some embodiments, the periphery of the pixel unit 100 is further provided with a partition wall 402, the partition wall 402 is a compound semiconductor, and a ring-shaped partition groove 401 is formed between the pixel unit 100 and the closest partition wall 402 in the periphery, which can be referred to in Figure 1 and Figure 4 .

[0122] The pixel layer 400 comprises a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom.

[0123] The lower end of the ring-shaped partition groove 401 extends between the lower surface of the active layer 102 and the upper surface of the substrate 200, and the upper end of the ring-shaped partition groove 401 extends at least to the upper surface of the first semiconductor layer 101.

[0124] In some embodiments, an ohmic contact layer 500 is further arranged between the pixel layer 400 and the substrate 200, the ohmic contact layer 500 is located between the second semiconductor layer 103 and the bonding layer 300, and according to the etching depth of the ring-shaped partition groove 401, the lower end of the ring-shaped partition groove 401 can extend to or above the lower surface of the ohmic contact layer 500.

[0125] In some embodiments, as Figure 3As shown, the pixel unit 100 is surrounded by at least two annular partition grooves 401. Compound semiconductors are retained between adjacent annular partition grooves 401 on the periphery of each pixel unit 100 to form partition walls 402. Since the partition walls 402 are made of compound semiconductors, the isolation effect is better. Metal atoms on the periphery of the partition walls 402 will be blocked by the partition walls 402 and cannot pass through the partition walls 402 to diffuse to the sidewalls of the pixel unit 100, thereby preventing the pixel unit 100 from short-circuiting.

[0126] In some embodiments, the width of the pixel unit 100 is 0.2 um to 80 um. The width of the pixel unit 100 can be understood as the maximum size of the pixel unit 100 along the width direction (X direction).

[0127] Furthermore, the height of the pixel unit 100 is 0.1 um to 5 um, wherein the height of the pixel unit refers to the distance between the upper surface of the first semiconductor layer 101 and the lower surface of the second semiconductor layer 103 in the pixel unit.

[0128] The shape of the pixel unit 100 includes but is not limited to a circle, an ellipse, a polygon and other shapes, preferably a circle, a quadrilateral and a hexagon.

[0129] In some embodiments, a lens is further disposed on the top of the pixel layer 400 , and the lens covers at least one pixel unit 100 .

[0130] This embodiment also discloses a method for preparing an LED display device, comprising the following steps:

[0131] Step S1: selecting a driving wafer as the substrate 200, on which a first type of electrode contact 201 and a second type of electrode contact 202 with opposite polarities are connected; and selecting a compound semiconductor layer as the pixel layer 400;

[0132] Understandably, Figure 7 As shown, the compound semiconductor layer includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom;

[0133] Step S2: Figure 8 As shown, the pixel layer 400 is connected to the upper portion of the substrate 200;

[0134] Step S3: Figure 9 As shown, the pixel layer 400 is etched to obtain the pixel unit 100 and the core 601 of the interconnected conductive member 600. The core 601 is a compound semiconductor, and the core 601 is located inside the first inner fence 602. The first inner fence 602 is a conductive member.

[0135] The top of the pixel unit 100 is electrically connected to the first inner fence 602 of the interconnection conductive member 600 and the corresponding second type of electrode contact 202, and the bottom of the pixel unit 100 is electrically connected to the corresponding first type of electrode contact 201, so as to realize the electrical connection between the pixel unit 100 and the driving wafer.

[0136] In step S2, when the pixel layer 400 is connected to the upper part of the substrate 200, the pixel layer 400 is connected to the substrate 200 through the bonding layer 300. The bonding layer 300 is a conductive metal layer.

[0137] When the pixel layer 400 and the substrate 200 are connected through the bonding layer 300, a hot-press bonding method can be used.

[0138] In some embodiments, referring to Figure 9 , step S3 can specifically include the following steps:

[0139] Step S31: etching the pixel layer 400 to obtain at least one pixel unit 100;

[0140] Step S32: depositing a first insulating layer 404 on the surface of the pixel layer 400, for example, the first insulating layer 404 can cover the sidewall of the pixel unit 100, so as to better avoid short circuit of the pixel unit 100;

[0141] Step S33: as Figure 9 in stage c, etching the pixel layer 400 above the second type of electrode contact 202 to obtain a ring-shaped first cut groove 407, so that the first cut groove 407 penetrates the bonding layer 300, and then the area surrounded by the inner wall of the first cut groove 407 is reserved to form the interconnection conductive member 600,

[0142] The area surrounded by the inner wall of the above-mentioned first cut groove 407 includes the compound semiconductor and the bonding layer 300 at the bottom thereof, the compound semiconductor in the surrounding area constitutes the core 601 of the interconnection conductive member 600, and the bottom of the bonding layer 300 in the surrounding area is in contact with the second type of electrode contact 202;

[0143] When the above-mentioned first cut groove 407 penetrates the bonding layer 300, the upper part of the bonding layer 300 below the core 601 will be sputtered to form a first inner fence 602-metal fence, so that the core 601 is covered in the inner cavity of the first inner fence 602, and at the same time, the upper part of the bonding layer 300 at the periphery of the interconnection conductive member 600 will also be sputtered to form a first outer fence 301-metal fence, the first outer fence 301 is located on the outer peripheral sidewall of the first cut groove 407, so that the first inner fence 602 surrounds the inside of the first outer fence 301, that is, the interconnection conductive member 600 is located inside the first outer fence 301;

[0144] Step S34: as Figure 9In the middle d stage, the second insulating layer 406 is filled between the first outer fence 301 and the first inner fence 602 inside to realize the insulation isolation of the second electrode contact 202 and the first electrode contact.

[0145] In the specific preparation, the second insulating layer 406 can also be deposited on the upper part of the pixel layer 400.

[0146] Step S35: As Figure 9 In the middle e stage, the top surface of the pixel unit 100 is partially exposed, and then the first conductive layer 700 is deposited on the pixel layer 400 and is in contact with the top surface of the pixel unit 100 to realize the electrical connection.

[0147] And the upper part of the first inner fence 602 of the interconnection conductive member 600 is exposed, and then the metal reinforcing member 800 is plated on the upper part of the interconnection conductive member 600 and is in contact with the first conductive layer 700. At this time, the top of the pixel unit 100 is in electrical connection with the first inner fence 602 of the interconnection conductive member 600 through the conductive structure composed of the first conductive layer 700 and the metal reinforcing member 800, and is in electrical connection with the second electrode contact 202 through the structure composed of the first fence and the bonding layer 300.

[0148] It can be understood that if a part of the second insulating layer 406 covers the top of the interconnection conductive member 600 in step S34, the material of the second insulating layer 406 on the top of the interconnection conductive member 600 needs to be removed first to expose the upper part of the first inner fence 602 and the core 601, and then the metal reinforcing member 800 is arranged.

[0149] When the top surface of the pixel unit 100 is partially exposed or the upper part of the first inner fence 602 is exposed, the upper part material can be removed by etching.

[0150] Before the above step S31, the etching blocking layer 403 can be arranged on the upper surface of the pixel layer 400, and the etching blocking layer 403 is etched to obtain the patterned mask layer, and then the pixel layer 400 is etched by using the mask layer to obtain at least one pixel unit 100.

[0151] After step S35, the following step is further performed: a lens is prepared on the top of the pixel layer 400, and the lens corresponds to one pixel unit 100 or a plurality of pixel units 100 correspond to one lens.

[0152] In the above process, the interconnection conductive member 600 is formed in the periphery of the corresponding pixel unit 100. When the first groove 407 is etched on the pixel layer 400, the compound semiconductor between the pixel unit 100 and the interconnection conductive member 600 in the periphery is also reserved to form the non-light-emitting area 408, which is located between the pixel unit 100 and the first periphery bar 301 in the periphery of the interconnection conductive member 600.

[0153] In some modes, when the pixel layer 400 is etched to obtain at least one pixel unit 100, the periphery of each pixel unit 100 is formed with at least one annular isolation groove 401. For example, the periphery of each pixel unit 100 can be formed with two annular isolation grooves 401, and the compound semiconductor material between the two annular isolation grooves 401 is reserved to form the partition wall 402.

[0154] Further, after the surface of the pixel layer 400 is deposited with the first insulating layer 404 in step S32, the inner wall of the annular isolation groove 401 is also covered with the first insulating layer 404. The annular isolation groove 401 has a filling area 4011, and the periphery of the filling area 4011 is surrounded by the first insulating layer 404 on the inner wall of the annular isolation groove 401. The filling area 4011 can be filled with air to form an air isolation layer, or the filling area 4011 can be filled with a first filler to form a solid structure. A thin film cover layer 405 can also be deposited on the surface of the pixel layer 400 according to needs, and the thin film cover layer 405 can be an insulating material.

[0155] The LED display device obtained by the above preparation method makes full use of the original compound semiconductor material, forms an interconnection conductive member with a core structure of compound semiconductor material, simplifies the preparation process, reduces the production cost, and improves the reliability and stability of the device.

[0156] Embodiment Two

[0157] Referring to Figures 4-5 The main difference between this embodiment and Embodiment One is that the original compound semiconductor material between the pixel unit 100 and the interconnection conductive member 600 in the periphery is not reserved, but is separated by the insulating filling area 410.

[0158] The insulating filling area 410 is located between the pixel unit 100 and the first inner periphery bar 602 of the interconnection conductive member 600. It can be understood that the interconnection conductive member 600 here refers to the conductive member that needs to be electrically connected to the pixel unit 100.

[0159] For example, when the pixel periphery is provided with the annular isolation groove 401, the insulating filling area 410 is located between the annular isolation groove 401 in the outermost periphery of the pixel unit 100 and the first inner periphery bar 602 of the corresponding interconnection conductive member 600.

[0160] In some embodiments, an insulating deposition layer 411 is arranged between the first inner fence 602 and the sidewall of the inner core 601. The insulating deposition layer 411 can be a single layer or a multi-layer structure. For example, the insulating deposition layer 411 can be a composite layer of the first insulating layer 404 and the thin film cover layer 405 reserved at the sidewall of the core 601.

[0161] In other ways, the first inner fence 602 and the sidewall of the inner core 601 can also be directly in contact.

[0162] In some embodiments, the pixel unit 100 is located inside the second outer fence 302, and the second outer fence 302-metal fence is formed on the bonding layer 300 below the pixel unit 100.

[0163] Further, the pixel unit 100 is surrounded by a partition wall 402, and the partition wall 402 is located inside the second outer fence 302.

[0164] When the LED display device of the present embodiment is prepared, the pixel layer 400 is first connected to the substrate 200 through the bonding layer 300, and then the following steps are performed:

[0165] Step S31: as shown in a1 stage in the Figure 10 , the pixel layer 400 is etched to obtain at least one pixel unit 100 and a core 601, wherein the core 601 is located at the periphery of the pixel unit 100. When etching, the first to-be-filled region 409 between the pixel unit 100 and the peripheral core 601 needs to be removed, and the original compound semiconductor material in the first to-be-filled region 409 needs to be removed;

[0166] Step S32: as shown in b1 stage in the Figure 9 , a first insulating layer 404 is deposited on the surface of the pixel layer 400;

[0167] For example, when depositing, at least the top surface and the sidewall of the pixel unit 100, and the top surface and the sidewall of the core 601 need to be covered by the first insulating layer 404;

[0168] Step S33: as shown in c1 stage in the Figure 9 , the bottom surface of the first to-be-filled region 409 is etched to form an insulating filling region 410, which penetrates through the bonding layer 300; that is, the material between the bottom surface of the first to-be-filled region 409 and the bottom surface of the bonding layer 300 needs to be etched;

[0169] When the above-mentioned first area to be filled 409 penetrates the bonding layer 300, the upper part of the bonding layer 300 below the core 601 will be sputtered to form a first inner fence 602-metal fence, so that the core 601 is enclosed inside the first inner fence 602 to form an interconnected conductive member 600; the interconnected conductive member 600 is formed on the periphery of the corresponding pixel unit 100.

[0170] Step S34: Figure 9 In the middle stage d1, the insulating material K is filled in the insulating filling region 410 to achieve insulation isolation between the second type electrode contact 202 and the first electrode contact.

[0171] Step S35: Figure 9 In the middle e1 stage, the top surface of the pixel unit 100 is partially exposed, and then a first conductive layer 700 is deposited on the pixel layer 400 so that the first conductive layer 700 and the top surface of the pixel unit 100 are in contact with each other to achieve electrical connection;

[0172] The upper part of the first inner fence 602 of the interconnected conductive member 600 is exposed, and then a metal reinforcement 800 is plated on the upper part of the interconnected conductive member 600, and the metal reinforcement 800 is brought into contact with the first conductive layer 700. At this point, the top of the pixel unit 100 is electrically connected to the first inner fence 602 of the interconnected conductive member 600 through the conductive structure formed by the first conductive layer 700 and the metal reinforcement 800, and is electrically connected to the second type of electrode contact 202 through the structure formed by the first fence and the bonding layer 300.

[0173] When the top surface of the pixel unit 100 is partially exposed or the upper portion of the first inner fence 602 is exposed, the upper material can be removed by etching.

[0174] Before the above step S31 , an etching stop layer 403 may be provided on the upper surface of the pixel layer 400 , and the etching stop layer 403 may be etched to obtain a patterned mask layer, and then the pixel layer 400 may be etched using the mask layer to obtain the pixel unit 100 and the core 601 .

[0175] In step S33 , when the first area to be filled 409 penetrates the bonding layer 300 , the upper portion of the bonding layer 300 below the pixel unit 100 is also sputtered to form a second outer fence 302 —a metal fence, so that the pixel unit 100 is surrounded by the second outer fence 302 .

[0176] In some ways, when the pixel layer 400 is etched to obtain at least one pixel unit 100, the periphery of each pixel unit 100 is also formed with at least one annular isolation groove 401. For example, the pixel layer 400 can be etched to obtain a ring-shaped isolation wall 402 surrounding the periphery of the pixel unit 100. The isolation wall 402 is composed of the original compound semiconductor material. The part between the pixel unit 100 and the peripheral isolation wall 402 constitutes the above-mentioned annular isolation groove 401. It can be understood that in the structure with the isolation wall 402, the above-mentioned first filling area 409 is formed between the isolation wall 402 surrounding the periphery of the pixel unit 100 and the core 601.

[0177] Embodiment three

[0178] Referring to Figure 6 , the embodiment discloses an LED display device. The main difference between the embodiment and the above-mentioned embodiments is that the periphery of the pixel unit 100 is not provided with the isolation wall 402 structure.

[0179] For example, in the LED display device shown in Embodiment two, the periphery of the pixel unit 100 is not provided with the isolation wall 402 structure. As Figure 6 shown, when the pixel layer 400 is etched, at least one pixel unit 100 and the core 601 are directly etched. The core 601 is located at the periphery of the pixel unit 100. When etching, the compound semiconductor material between the pixel unit 100 and the peripheral core 601 is removed to form the first filling area 409. Then, the first insulating layer 404 is deposited on the surface of the pixel layer 400. Then, the steps S33-S35 in Embodiment two are executed. The preparation process is shown in Figure 11 .

[0180] Similarly, the LED display device shown in Embodiment one can also not be provided with the isolation wall 402 structure. At this time, the sidewalls between the non-light-emitting areas 408 of the periphery of the pixel unit 100 need to be insulated and isolated. For example, the first insulating layer 404 or other insulating structures can be deposited on the sidewalls to achieve insulation and isolation.

[0181] Further, as Figure 6 shown, when the periphery of the pixel unit 100 is not provided with the isolation wall 402, it can also not have the annular isolation groove 401.

[0182] The LED display devices of the above-mentioned embodiments form the interconnection conductive member with the core structure (compound semiconductor material), simplify the preparation process, reduce the production cost, improve the reliability and stability of the device, and also help to ensure the yield of the product.

[0183] All the optional technical solutions above can be combined in any manner to form optional embodiments of the present application, that is, any number of embodiments can be combined to meet the requirements of different application scenarios, which are all within the protection scope of the present application and will not be described one by one here.

[0184] It should be noted that the above embodiments are merely examples for clear illustration, and are not limitations on the embodiments. For ordinary skilled persons in the art, other different forms of changes or variations can be made on the basis of the above description. Here, it is not necessary and also impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An LED display device, characterized by: The application relates to a display device, comprising: a substrate, which is a driving wafer, wherein a first type of electrode contact and a second type of electrode contact are arranged on the driving wafer, and the polarities of the first type of electrode contact and the second type of electrode contact are opposite; a pixel layer, which is arranged on the upper portion of the substrate, wherein a pixel unit and an interconnection conductive member are arranged in the pixel layer, the top portion of the pixel unit is electrically connected to the corresponding second type of electrode contact through the interconnection conductive member, and the bottom portion of the pixel unit is electrically connected to the corresponding first type of electrode contact; wherein the interconnection conductive member comprises a core, the core is a compound semiconductor, the core is arranged in the interior of a first inner fence, the first inner fence is a conductive member, and the top portion of the pixel unit is electrically connected to the corresponding second type of electrode contact through the first inner fence of the interconnection conductive member.

2. The LED display device of claim 1, wherein: The top portion of the pixel unit is connected to a first conductive layer, the upper portion of the first inner fence of the interconnection conductive member is electrically connected to the first conductive layer, and the lower portion is electrically connected to the corresponding second type of electrode contact.

3. The LED display device of claim 3, wherein: The upper portion of the first inner fence of the interconnection conductive member is electrically connected to the first conductive layer through a metal reinforcing member.

4. The LED display device of claim 3, wherein: The upper portion of the first inner fence is covered by the metal reinforcing member.

5. The LED display device of claim 1, wherein: The substrate and the pixel layer are connected through a bonding layer, the bonding layer adopts a metal layer, and the first inner fence is formed on the bonding layer.

6. The LED display device of claim 5, wherein: The interconnection conductive members are all arranged in the periphery of the pixel unit.

7. The LED display device of claim 6, wherein: A first cut groove is arranged on the pixel layer, the first cut groove is annular, the first cut groove penetrates the bonding layer, the periphery of the interconnection conductive member is surrounded by the first cut groove, a first outer fence is further formed on the bonding layer, the inner cavity of the first outer fence penetrates the bonding layer, the first outer fence is arranged in each first cut groove, the first inner fence is arranged in the inner cavity of the first outer fence, the core is arranged in the interior of the first inner fence, and the first outer fence and the first inner fence are isolated through a second insulating layer.

8. The LED display device of claim 7, wherein: The pixel unit and the interconnection conductive member in the periphery are separated through a non-light-emitting area, the non-light-emitting area is a compound semiconductor, and the non-light-emitting area is arranged between the first outer fence in the periphery of the pixel unit and the interconnection conductive member.

9. The LED display device of claim 5, wherein: The pixel unit and the interconnection conductive member in the periphery are separated through an insulating filling area, the insulating filling area is arranged between the first inner fence of the pixel unit and the interconnection conductive member, and the insulating filling area is filled with an insulating material.

10. The LED display device of claim 5, wherein: The sidewall of the first inner fence and the core in the interior directly contact each other, or an insulating deposition layer is arranged between the sidewall of the first inner fence and the core in the interior.

11. The LED display device according to claim 5, characterized in that: The periphery of the pixel unit is surrounded by at least one annular separation groove, and the interconnection conductive members are all arranged in the periphery of the annular separation groove in the outermost periphery of the pixel unit.

12. The LED display device of claim 11, wherein: The inner wall of the annular separation groove is covered with a first insulating layer, the annular separation groove has a filling area in the interior, the periphery of the filling area is surrounded by the first insulating layer on the inner wall of the annular separation groove, the filling area contains an air separation layer formed by air, or the filling area is filled with a first filler to form a solid structure.

13. The LED display device of claim 11, wherein: The pixel unit periphery further has a partition wall, the partition wall is a compound semiconductor, and a ring-shaped partition groove is formed between the pixel unit and the closest partition wall of the periphery.

14. A method of manufacturing an LED display device, characterized by: The method comprises the following steps: selecting a driving wafer as a substrate, the driving wafer being provided with first electrode contacts and second electrode contacts of opposite polarity; and selecting a compound semiconductor layer as a pixel layer; connecting the pixel layer to the upper part of the substrate; performing etching on the pixel layer to obtain a core of the interconnection conductive member, the core being a compound semiconductor, and the core being located inside a first inner fence; the top of the pixel unit being electrically connected to the first inner fence of the interconnection conductive member and the corresponding second electrode contact, and the bottom of the pixel unit being electrically connected to the corresponding first electrode contact.

15. The method of claim 14, wherein: When the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

16. The method of claim 15, wherein: When the core of the interconnection conductive member is obtained by performing etching on the pixel layer, the core being a compound semiconductor and the core being located inside a first inner fence, the method comprises: performing etching on the pixel layer to obtain a first cut groove, the first cut groove being ring-shaped, the first cut groove penetrating through the bonding layer, and a region surrounded by the inner wall of the first cut groove being reserved to form an interconnection conductive member, the interconnection conductive member comprising a core, the core being a compound semiconductor, the bonding layer below the core being connected to the corresponding second electrode contact, and a first inner fence being formed on the bonding layer below the core, so that the core is covered inside the first inner fence, a first outer fence being further formed on the bonding layer of the periphery of the interconnection conductive member, the inner cavity of the first outer fence penetrating through the bonding layer, the first outer fence being located in the first cut groove, and the first inner fence being located in the inner cavity of the first outer fence; a second insulating layer is arranged between the first outer fence and the first inner fence inside to perform insulating isolation.

17. The method of claim 16, wherein: The interconnection conductive member is formed in the periphery of the corresponding pixel unit, and when the first cut groove is obtained by etching on the pixel layer, the compound semiconductor between the pixel unit and the interconnection conductive member of the periphery is reserved to form a non-light-emitting area, the non-light-emitting area being located between the pixel unit and the first outer fence of the periphery of the interconnection conductive member.

18. The method of claim 15, wherein: When the core of the interconnection conductive member is obtained by performing etching on the pixel layer, the core being a compound semiconductor and the core being located inside a first inner fence, the method further comprises: The interconnection conductive member is formed in the periphery of the corresponding pixel unit, and an insulating filling area is constructed between the pixel unit and the first inner fence of the interconnection conductive member of the periphery, and the original material in the insulating filling area is removed and filled with an insulating material.

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