Display device and electronic device including the same

Abstract

The present application relates to a display device and an electronic device including the same, the display device including a display area and a non-display area around the display area, the display device including: a substrate; a passivation layer over the substrate; a light emitting element over the passivation layer; a pixel defining layer over the passivation layer in the display area and the non-display area, and including a first inorganic layer in the display area and the non-display area, a second inorganic layer over the first inorganic layer in the display area and the non-display area, and a third inorganic layer over the second inorganic layer in the display area and the non-display area, a third inorganic layer over the second inorganic layer in the display area; a first bank over the pixel defining layer; and a second bank above the first bank and extending further than a side surface of the first bank.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0050729 filed in the Korean Intellectual Property Office on April 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and an electronic device including the display device. Background Art

[0004] With the development of the information age, the demand for display devices for displaying images has increased in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. Display devices can be flat panel display devices, such as liquid crystal display devices, field emission display devices, and organic light emitting display devices. Among flat panel display devices, light emitting display devices include light emitting elements in which each pixel of a display panel can emit light by itself, thereby displaying an image even without a backlight unit that provides light to the display panel.

[0005] Recently, display devices have been applied to glasses-type devices for providing virtual reality and augmented reality. To be applied to glasses-type devices, the display device is implemented in a very small size of about 2 inches or less, but it should have a high pixel integration so that it can achieve high resolution. For example, the display device can have a high pixel integration of about 400 pixels per inch (PPI) or more. Summary of the Invention

[0006] Aspects of the present disclosure provide a display device in which a light emitting element or a common electrode divided for each light emission region can be formed without a mask process.

[0007] Aspects of the present disclosure provide a display device in which moisture absorption or moisture permeation of a lower organic layer of a light emitting element is reduced to enhance durability.

[0008] Aspects of the present disclosure are not limited to those mentioned above, and additional aspects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0009] According to the display device according to one or more embodiments, the organic layer of the non-display area is covered with the pixel defining layer, and thus may be robust against moisture absorption or moisture penetration.

[0010] According to one or more embodiments of the disclosure, a display device including a display area and a non-display area around the display area includes: a substrate; a passivation layer over the substrate; a light emitting element over the passivation layer; a pixel definition layer over the passivation layer in the display area and the non-display area, and including a first inorganic layer, a second inorganic layer over the first inorganic layer in the display area and the non-display area, and a third inorganic layer over the second inorganic layer in the display area; a first bank over the pixel definition layer; and a second bank over the first bank and extending farther than a side surface of the first bank.

[0011] In at least a portion of the non-display area, the second inorganic layer can not be covered by the third inorganic layer.

[0012] A side surface of the third inorganic layer facing the non-display area can extend farther than a side surface of the second bank facing the non-display area, or be aligned with the side surface of the second bank facing the non-display area.

[0013] The pixel definition layer can be on an upper surface and side surfaces of the passivation layer.

[0014] An angle between a lower surface and a side surface of the passivation layer can be less than about 90°.

[0015] The pixel definition layer can include a first portion at a first height above the substrate, a second portion at a second height above the substrate, and a third portion at a third height above the substrate, wherein the first height is greater than the second height and the third height, wherein the second height is greater than the third height, and wherein the first portion, the second portion, and the third portion of the pixel definition layer are arranged in a longitudinal direction of the substrate in order.

[0016] The passivation layer can extend in the display area and the non-display area.

[0017] A thickness of the first inorganic layer can be less than a thickness of the second inorganic layer.

[0018] A thickness of the first inorganic layer can be less than a thickness of a pixel electrode of the light emitting element.

[0019] The second inorganic layer can include a first side surface facing a side surface of the pixel electrode and a second side surface extending farther than the first side surface.

[0020] The second inorganic layer can include a different material from the first inorganic layer and the third inorganic layer.

[0021] The first inorganic layer and the third inorganic layer can include silicon nitride, and wherein the second inorganic layer includes one or more of silicon oxynitride and silicon oxide.

[0022] The passivation layer can include one or more of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0023] In the display area, the pixel-defining layer can include a side surface extending farther than a side surface of the first bank.

[0024] The display apparatus can further include a residual pattern at an edge of a pixel electrode of the light-emitting element, under the pixel-defining layer.

[0025] The light-emitting element can include a pixel electrode over the passivation layer, a light-emitting layer over the pixel electrode, and a common electrode over the light-emitting layer and contacting the first bank.

[0026] The display apparatus can further include a first inorganic pattern over the light-emitting element in the display area, and a second inorganic pattern over the pixel-defining layer in the non-display area and spaced apart from the first inorganic pattern.

[0027] The first inorganic pattern can be under a lower surface of the second bank.

[0028] According to one or more embodiments of the disclosure, a display apparatus includes a substrate, a light-emitting element over the substrate, a pixel-defining layer over the substrate including a first inorganic layer over the substrate, a second inorganic layer over the first inorganic layer, and a third inorganic layer over the second inorganic layer, a first bank over the pixel-defining layer, and a second bank over the first bank and extending farther than a side surface of the first bank, wherein the third inorganic layer has different corresponding thicknesses in a region overlapping the first bank and in a region not overlapping the first bank.

[0029] The thickness of the third inorganic layer in the region overlapping the first bank can be greater than the thickness of the third inorganic layer in the region not overlapping the first bank.

[0030] According to one or more embodiments of the disclosure, an electronic device including a display apparatus including a display area and a non-display area around the display area, the display apparatus including a substrate, a passivation layer over the substrate, a light-emitting element over the passivation layer, a pixel-defining layer over the passivation layer in the display area and the non-display area and including a first inorganic layer, a second inorganic layer, and a third inorganic layer, the first inorganic layer being in the display area and the non-display area, the second inorganic layer being over the first inorganic layer in the display area and the non-display area, the third inorganic layer being over the second inorganic layer in the display area, a first bank over the pixel-defining layer, and a second bank over the first bank and extending farther than a side surface of the first bank.

[0031] Aspects according to embodiments of the present disclosure are not limited to those mentioned above, and more various aspects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which:

[0033] Figure 1 is a perspective view illustrating a display apparatus according to one or more embodiments;

[0034] Figure 2 is a plan view illustrating the display apparatus of Figure 1 folded and viewed from the front;

[0035] Figure 3 is a sectional view illustrating the display apparatus of Figure 1 folded and viewed from the side;

[0036] Figure 4 is an enlarged plan view illustrating a region A1 of the display apparatus of Figure 2 ;

[0037] Figure 5 is a sectional view illustrating a portion of a display apparatus according to one or more embodiments;

[0038] Figure 6 is an enlarged sectional view illustrating a region A3 of the display apparatus of Figure 5 ;

[0039] Figure 7 is an enlarged sectional view illustrating a region A2 of the display apparatus of Figure 2 ;

[0040] Figure 8 to Figure 11 is a sectional view illustrating a portion of a display apparatus according to one or more embodiments; and

[0041] Figure 12 is an enlarged sectional view illustrating a region A5 of the display apparatus of Figure 11 . DETAILED DESCRIPTION

[0042] Aspects of some embodiments of the present disclosure and methods of implementing them can be more readily understood by reference to the following detailed description and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the scope of the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant, or unnecessary art, elements, and techniques for describing the embodiments can be omitted. Unless otherwise indicated, like reference numerals, characters or combinations thereof in the entire specification and drawings mean the same element or part, and thus, repetitive description thereof can be omitted.

[0043] The described embodiments can have various modifications and can be implemented in different forms and should not be construed as being limited to the embodiments shown herein. The use of "can," "may," or "might" in describing one or more embodiments corresponds to one or more embodiments of the present disclosure.

[0044] In view of the entire disclosure, those of ordinary skill in the art will appreciate that each suitable feature of various embodiments of the present disclosure can be partially or wholly combined or combined with each other, and can be technically interlocked and operated in various suitable ways, and each embodiment can be implemented independently of each other or in combination with each other in any suitable way unless otherwise specified or implied.

[0045] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. In other words, since the sizes and thicknesses of the elements in the drawings are arbitrarily shown for the purpose of facilitating description, the present disclosure is not limited thereto. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries of adjacent elements. Thus, the presence or absence of cross-hatching or shading in no way limits or suggests any preference or requirement for any particular material, material property, size, proportion, commonality of the illustrated elements, and / or any other characteristic, attribute, property, or the like of the elements.

[0046] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic representations of schematics embodiments and / or intermediate structures of embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, the specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative of the embodiments according to the present disclosure. Thus, embodiments disclosed herein are not to be interpreted as being limited to the shapes of the elements as illustrated, but are to include deviations in shapes that result from, for example, manufacturing.

[0047] For example, an implant region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0048] For ease of description, spatially relative terms, such as "below", "beneath", "lower", "bottom", "under", "above", "upper", "top", "higher", "upside", "side" (e.g., as in "sidewall"), and the like, can be used herein for the purpose of describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below", "beneath", or "under" other elements or features would then be oriented "above", "upper", or "top" the other elements or features. Accordingly, the exemplary terms "below" and "under" can encompass both orientations "above" and "below". The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it can mean that the first part is arranged on the upper side or lower side of the second part, without being limited to the upper side thereof based on the direction of gravity.

[0049] Furthermore, the phrase "in plan view" means when viewing a portion of an object from above, and the phrase "in schematic cross-sectional view" means when viewing a schematic cross-section of a portion of an object taken by a vertical cut from the side. The term "overlap" or "overlapped" means that a first object can be above or below a second object, or on a side of the second object, and vice versa. Additionally, the term "overlap" can include stacking, facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by one of ordinary skill in the art. The expression "not overlap" can include the meaning of "spaced apart from" or "separated from" or "offset from" as well as any other suitable equivalent as will be appreciated and understood by one of ordinary skill in the art. The terms "face" and "facing" can mean that a first object can be directly opposite or indirectly opposite a second object. In case a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, but still facing each other.

[0050] It will be understood that when an element, layer, region or component is referred to as being "formed on" another element, layer, region or component, "on" another element, layer, region or component, "connected to" or "(operably or communicatively) coupled to" another element, layer, region or component, it can be directly formed on, directly on, directly connected to or directly coupled to another element, layer, region or component, or indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to another element, layer, region or component, such that one or more intervening elements, layers, regions or components can exist. In addition, this can collectively mean directly coupled or directly connected or indirectly coupled or indirectly connected and integrally coupled or integrally connected or non-integrally coupled or non-integrally connected. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to another layer, region and / or component, or one or more intervening layers, regions or components can exist. The one or more intervening components can include switches, resistors, capacitors, etc. In describing implementations, unless explicitly described as directly connected, expressions of connection indicate electrical connection, and "directly connected / directly coupled" or "directly on" refer to one component directly connected or directly coupled to another component or directly on another component without intervening components.

[0051] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the case where the part is "directly under" another part, but also includes the case where there is another part between the part and another part. At the same time, other expressions describing the relationship between components such as "between", "directly between" or "adjacent to" and "directly adjacent to" can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also exist.

[0052] For the purposes of this disclosure, expressions such as "at least one of" or "any one of" or "one or more of" when preceding a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases, when preceding / following a list of elements, modify the entire list of elements and do not modify the individual elements in the list. When "C to D" is stated, it means C or greater and D or less unless otherwise specified.

[0053] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are used only to distinguish one element, component, component, area, region, layer, section or part from another element, component, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below may be referred to as the second element, second component, second area, second layer or second section. The description of an element as a "first" element may not require or imply the presence of a second element or other element. The terms "first", "second", etc. may also be used herein to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0054] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0055] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "has", "having", "includes" and "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0056] As used herein, the terms "substantially", "about", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% of a recited value. In view of the discussed measurement and the error associated with measuring a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately," as used herein includes the recited value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the recited value. Furthermore, use of "may" when describing embodiments of the present disclosure means "one or more embodiments of the present disclosure."

[0057] Moreover, any numerical range recited herein is intended to include all sub-ranges of the same entire number precision, i.e. one having the same number of decimal places as the numerical precision in the range but a strictly smaller maximum value and smaller minimum value as the maximum and minimum of the numerical range, respectively. For example, a range of "1.0 to 10.0" is intended to include all sub-ranges between (and including) the recited minimum and maximum values and, more generally, to all sub-ranges that would be formed if one removed the end values from the range while maintaining the same number of decimal places throughout the range, e.g. "2.4 to 7.6" or "2.39 to 6.70." Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited in this specification.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0059] Figure 1 is a perspective view illustrating a display device according to one or more embodiments. Figure 2 It shows Figure 1 A plan view of the display device being folded and viewed from the front. Figure 3 It shows Figure 1 A cross-sectional view of the display device being folded and viewed from the side.

[0060] refer to Figure 1 According to one or more embodiments, the display device 10 may be used in electronic devices. Electronic devices including the display device 10 may include portable electronic devices such as mobile phones, smart phones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices. The above-listed ones are merely examples, and the display device 10 may also be used in other electronic devices.

[0061] The display device 10 according to one or more embodiments may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro-light-emitting display device or a nano-light-emitting display device including a micro-light-emitting diode or a nano-light-emitting diode (micro-LED or nano-LED). The following description will be based on the display device 10 being an organic light-emitting display device, but the present disclosure is not limited thereto.

[0062] The display device 10 according to one or more embodiments may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0063] In a plan view, the display panel 100 may be formed into a rectangular plane having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. A corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be formed as a right angle or may be rounded to have a curvature. The planar shape of the display panel 100 is not limited to a rectangular shape and may be formed into another polygonal shape, a circle, or an ellipse.

[0064] The display panel 100 can be substantially flat, but is not limited thereto. For example, the display panel 100 can include curved portions formed at left and right ends, the curved portions having a constant curvature or a variable curvature. Also, the display panel 100 can be flexibly formed to be curved, twisted, bent, folded up, or rolled.

[0065] The display panel 100 can include a main area MA and a sub area SBA.

[0066] The main area MA can include a display area DA for displaying an image and a non-display area NDA not for displaying an image.

[0067] The display area DA can occupy a large portion of an area of the display panel 100. The display area DA can be located at a center of the display panel 100. Pixels each including a plurality of light emission areas can be located in the display area DA to display an image.

[0068] The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can be an outer area of the display area DA and can surround the display area DA (e.g., in a plan view). The non-display area NDA can be an edge area of the display panel 100. Figure 2 The area A2 of FIG. 1A relates to an edge area of the display apparatus 10 and can include a portion of the display area DA and a portion of the non-display area NDA.

[0069] The sub area SBA can be an area extending from one edge of the main area MA. The sub area SBA can include a flexible material capable of withstanding bending, folding, rolling, etc. For example, when the sub area SBA is bent, the sub area SBA can overlap the main area MA in a thickness direction (third direction DR3). The sub area SBA can include the display driver 200 and a pad area connected to the circuit board 300. In one or more other embodiments, the sub area SBA can be omitted, and the display driver 200 and the pad area can be located in the non-display area NDA.

[0070] Referring to FIG. 1A, Figure 1 The sub area SBA can include a display pad, the display driver 200, and the circuit board 300.

[0071] The display pad can be located on one edge of the display panel 100. For example, the display pad can be located on a lower edge of the display panel 100. The display pad can be connected to the display driver 200 and the circuit board 300.

[0072] The display driver 200 can generate and output a signal and a voltage for driving the display panel 100. In detail, the display driver 200 can generate and output a data voltage, a power voltage, a scan timing signal, etc. The display driver 200 can supply the power voltage to a power line, and can supply a gate control signal to a gate driver.

[0073] The display driver 200 can be located between the display pad and the display area DA in the non-display area NDA. The display driver 200 can be attached to the non-display area NDA of the display panel 100 in a chip on glass (COG) method. Alternatively, the display driver 200 can be attached to the circuit board 300 in a chip on plastic (COP) method.

[0074] The circuit board 300 can be located on one edge of the display panel 100, and can be located on the display pad. The circuit board 300 can be attached to the display pad by using a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. Accordingly, the circuit board 300 can be electrically connected to the signal line of the display panel 100. The circuit board 300 can be a flexible printed circuit board or a flexible film such as a chip on film.

[0075] Figure 3 is a cross-sectional view showing Figure 1 the display apparatus of

[0076] Referring to Figure 3 , the display panel 100 can include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0077] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate capable of withstanding bending, folding, curling, etc. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but is not limited thereto. In one or more other embodiments, the substrate SUB can include a glass material or a metal material.

[0078] The thin film transistor layer TFTL can be located on the substrate SUB (as used herein, "on" can mean "over"). The thin film transistor layer TFTL can include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL can further include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 with the data line, and a lead line connecting the display driver 200 with the pad area. Each of the thin film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver can include a thin film transistor.

[0079] The thin film transistor layer TFTL may be located in the display area DA, the non-display area NDA, and the sub-area SBA. Thin film transistors, scan lines, data lines, and power lines of the pixels of the thin film transistor layer TFTL may be located in the display area DA. Scan control lines and fan-out lines of the thin film transistor layer TFTL may be located in the non-display area NDA. Lead lines of the thin film transistor layer TFTL may be located in the sub-area SBA.

[0080] The light emitting element layer EML may be located on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements including a first electrode, a second electrode, and a light emitting layer to emit light, and a pixel defining layer defining pixels. The plurality of light emitting elements of the light emitting element layer EML may be located in the display area DA.

[0081] In one or more embodiments, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may combine with each other in the organic light-emitting layer to emit light.

[0082] In one or more other embodiments, the light emitting element may include a micro light emitting diode, a quantum dot light emitting diode including a quantum dot light emitting layer, or an inorganic light emitting diode including an inorganic semiconductor.

[0083] The thin film encapsulation layer TFEL may cover the upper surface and side surfaces of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer intended to encapsulate the light emitting element layer EML.

[0084] The color filter layer (CFL) may be located on the thin film encapsulation layer (TFEL). The color filter layer (CFL) may include multiple color filters corresponding to the multiple light emission regions. Each color filter can selectively transmit light of a corresponding wavelength (or wavelengths) and can block or absorb light of other wavelengths. The color filter layer (CFL) can absorb a portion of light incident from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer (CFL) can reduce or prevent color distortion caused by external light reflection.

[0085] Since the color filter layer CFL is directly on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the display device 10 may be relatively thin.

[0086] In some embodiments, the display device 10 can further include an optical device. The optical device can emit or receive light in the infrared, ultraviolet, or visible band. For example, the optical device can be an optical sensor for sensing light incident on the display device 10, such as a proximity sensor, an illuminance sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0087] Figure 4 is an enlarged plan view showing a portion of a display device according to one or more embodiments (e.g., a region A1 of Figure 2 ). Figure 4 may be a layout view showing an arrangement of light emission regions EA1, EA2, and EA3 and a pixel definition layer PDL in a display region DA.

[0088] Referring to Figure 4 , the pixel definition layer PDL can cover the display region DA, and can expose the light emission regions EA1, EA2, and EA3. The pixel definition layer PDL can define the light emission regions EA1, EA2, and EA3. In the drawings, the light emission regions EA1, EA2, and EA3 have a circular shape, but can also be polygons such as triangles, squares, or hexagons. The plurality of light emission regions EA1, EA2, and EA3 can be positioned to be spaced apart from each other in a first direction DR1 and a second direction DR2. type, e.g., diamond type is a registered trademark of Samsung Display Co., Ltd., of Korea). For example, the first light emission region EA1 and the third light emission region EA3 can be spaced apart from each other in the first direction DR1, and can be alternately positioned in the first direction DR1 and the second direction DR2. The second light emission region EA2 can be spaced apart from another adjacent second light emission region EA2 in the first direction DR1 and the second direction DR2. The second light emission region EA2 and the first light emission region EA1 or the second light emission region EA2 and the third light emission region EA3 can be alternately positioned in any one direction in a plane defined by the first direction DR1 and the second direction DR2. The shape and arrangement of the plurality of light emission regions are not limited to Figure 4 .

[0089] The first light emission region EA1, the second light emission region EA2, and the third light emission region EA3 can have different sizes. For example, the size of the first light emission region EA1 can be greater than the size of the second light emission region EA2, and the size of the second light emission region EA2 can be less than the size of the third light emission region EA3. The intensity of light emitted from the respective light emission regions EA1, EA2, and EA3 can vary according to the size of the light emission regions EA1, EA2, and EA3, and the color of a picture displayed by the display device 10 can be controlled by adjusting the size of the light emission regions EA1, EA2, and EA3.

[0090] In the display apparatus 10, one first light emission area EA1, one second light emission area EA2, and one third light emission area EA3 adjacent to each other can form one pixel group. One pixel group can include light emission areas EA1, EA2, and EA3 that emit light of different colors to present a white gray scale, but the disclosure is not limited thereto. The combination of light emission areas EA1, EA2, and EA3 constituting one pixel group can be variously modified according to the arrangement of light emission areas EA1, EA2, and EA3, the colors of light emitted from light emission areas EA1, EA2, and EA3, etc.

[0091] Figure 5 is a cross-sectional view illustrating a portion of a display apparatus according to one or more embodiments. In detail, Figure 5 is a cross-sectional view illustrating a portion of a display apparatus according to one or more embodiments. In detail, Figure 4 is a cross-sectional view illustrating a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL taken along line I-I' of

[0092] The thin film transistor layer TFTL can include a first buffer layer BF1, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0093] The first buffer layer BF1 can be located on the substrate SUB. The first buffer layer BF1 can include an inorganic layer capable of reducing or preventing penetration of air or moisture. For example, the first buffer layer BF1 can include a plurality of inorganic layers alternately stacked.

[0094] The lower metal layer BML can be located on the first buffer layer BF1. For example, the lower metal layer BML can be formed of a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0095] The second buffer layer BF2 can cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 can include an inorganic layer capable of reducing or preventing penetration of air or moisture. For example, the second buffer layer BF2 can include a plurality of inorganic layers alternately stacked.

[0096] A thin film transistor TFT can be located on the second buffer layer BF2, and can constitute a pixel circuit of each of a plurality of pixels. For example, the thin film transistor TFT can be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT can include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0097] The semiconductor layer ACT can be located on the second buffer layer BF2. The semiconductor layer ACT can overlap the gate electrode GE in a thickness direction (third direction DR3), and can be insulated from the gate electrode GE by a gate insulating layer GI. A portion of the semiconductor layer ACT can form the source electrode SE and the drain electrode DE by a material of the conductorized semiconductor layer ACT.

[0098] The gate electrode GE can be located on the gate insulating layer GI. The gate electrode GE can overlap the semiconductor layer ACT in a thickness direction (third direction DR3), with the gate insulating layer GI interposed between the gate electrode GE and the semiconductor layer ACT.

[0099] The gate insulating layer GI can be located on the semiconductor layer ACT. For example, the gate insulating layer GI can cover the semiconductor layer ACT and the second buffer layer BF2, and can insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI can include a contact hole through which the first connection electrode CNE1 passes.

[0100] The first interlayer insulating layer ILD1 can cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 can include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 can be connected to the contact hole of the gate insulating layer GI and to a contact hole of a second interlayer insulating layer ILD2.

[0101] The capacitor electrode CPE can be located on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap the gate electrode GE in a thickness direction (third direction DR3). The capacitor electrode CPE and the gate electrode GE can form a capacitor.

[0102] The second interlayer insulating layer ILD2 can cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 can be connected to the contact hole of the first interlayer insulating layer ILD1 and to the contact hole of the gate insulating layer GI.

[0103] The first connection electrode CNE1 can be located on the second interlayer insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the thin film transistor TFT with the pixel electrodes AE1, AE2, and AE3. The first connection electrode CNE1 can be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0104] The first passivation layer PAS1 can cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 can protect the thin film transistor TFT. The first passivation layer PAS1 can include a contact hole through which the second connection electrode CNE2 passes. In one or more embodiments, the first passivation layer PAS1 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin. Alternatively, the first passivation layer PAS1 can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Alternatively, the first passivation layer PAS1 can be formed of a plurality of layers of the above-described organic material or inorganic material.

[0105] The second connection electrode CNE2 can be located on the first passivation layer PAS1. The second connection electrode CNE2 can electrically connect the first connection electrode CNE1 with the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED. The second connection electrode CNE2 can be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0106] The second passivation layer PAS2 can cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 can compensate for a step difference caused by the thin film transistor TFT and the metal wire, and can have a flat top surface. The second passivation layer PAS2 can include a contact hole through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED pass. In one or more embodiments, the second passivation layer PAS2 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin.

[0107] The light emitting element layer EML can be located on the thin film transistor layer TFTL. The light emitting element layer EML can include the light emitting element ED, the pixel definition layer PDL, and the bank structure BNS. The light emitting element ED can include the pixel electrodes AE1, AE2, and AE3, the light emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3.

[0108] Figure 6 is Figure 5An enlarged cross-sectional view of the first light emission area EA1 and its periphery is shown in detail in area A3 of FIG. 8. Hereinafter, the light emitting element layer EML will be described with respect to the first light emission area EA1 by way of example.

[0109] refer to Figure 5 and Figure 6 , the display device 10 may include a plurality of light emission areas EA1, EA2 and EA3 located in the display area DA and a non-light emission area located between the light emission areas EA1, EA2 and EA3. The light emission areas EA1, EA2 and EA3 may be defined as areas where the pixel electrodes AE1, AE2 and AE3, the light emitting layers EL1, EL2 and EL3 and the common electrodes CE1, CE2 and CE3 overlap in the thickness direction (third direction DR3) of the substrate SUB, respectively. The light emission areas EA1, EA2 and EA3 may include a first light emission area EA1, a second light emission area EA2 and a third light emission area EA3 spaced apart from each other, and may emit light of the same color or different colors. In one or more embodiments, the first light emission area EA1 may emit light of a first color, the second light emission area EA2 may emit light of a second color, and the third light emission area EA3 may emit light of a third color.

[0110] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 located in different light emission areas EA1, EA2, and EA3, respectively. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 located in a first light emission area EA1, a second light emitting element ED2 located in a second light emission area EA2, and a third light emitting element ED3 located in a third light emission area EA3.

[0111] The light emitting elements ED1, ED2, and ED3 can each include a pixel electrode AE1, AE2, and AE3, a light emitting layer EL1, EL2, and EL3, and a common electrode CE1, CE2, and CE3, and the light emitting elements ED1, ED2, and ED3 located in different light emission areas EA1, EA2, and EA3, respectively, can emit different corresponding colors of light depending on the materials of the light emitting layers EL1, EL2, and EL3. For example, the first light emitting element ED1 located in the first light emission area EA1 can emit a first light of red color having a peak wavelength in a range of about 610 nm to about 650 nm, the second light emitting element ED2 located in the second light emission area EA2 can emit a second light of green color having a peak wavelength in a range of about 510 nm to about 550 nm, and the third light emitting element ED3 located in the third light emission area EA3 can emit a third light of blue color having a peak wavelength in a range of about 440 nm to about 480 nm. The first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 constituting one pixel can include the light emitting elements ED1, ED2, and ED3 for emitting different colors of light to present a white gray scale. Alternatively, when the light emitting layers EL1, EL2, and EL3 can include two or more materials for emitting different colors of light, one light emitting layer can emit mixed light. For example, the light emitting layers EL1, EL2, and EL3 can collectively include a material for emitting red light and a material for emitting green light to emit yellow light, or can include all of a material for emitting red light, a material for emitting green light, and a material for emitting blue light to emit white light.

[0112] The pixel electrodes AE1, AE2, and AE3 can be located on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 can be located in a plurality of light emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 can include a first pixel electrode AE1 located in the first light emission area EA1, a second pixel electrode AE2 located in the second light emission area EA2, and a third pixel electrode AE3 located in the third light emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be spaced apart from each other on the second passivation layer PAS2.

[0113] The pixel electrodes AE1, AE2, and AE3 can be electrically connected to the respective drain electrodes DE of the thin film transistors TFT through the first connection electrode CNE1. Edges of the spaced apart pixel electrodes AE1, AE2, and AE3 can be covered by the pixel defining layer PDL, such that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be insulated from each other.

[0114] The pixel electrodes AE1, AE2, and AE3 can include a transparent electrode material and / or a conductive metal material, and can have a single layer structure or a multi-layer structure. The metal material can be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material can be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). In one or more embodiments, the pixel electrodes AE1, AE2, and AE3 can have a multi-layer structure including a layer of the metal material and a layer of the transparent electrode material.

[0115] The light emitting layers EL1, EL2, and EL3 can be located on the pixel electrodes AE1, AE2, and AE3. The light emitting layers EL1, EL2, and EL3 can be organic light emitting layers made of an organic material, and can be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. The light emitting layers EL1, EL2, and EL3 can have a multi-layer structure, and each of a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material can constitute a layer. When the thin film transistor TFT applies a voltage (e.g., a predetermined voltage) to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons can be injected and transported, and can combine with each other in the light emitting layers EL1, EL2, and EL3 to emit light.

[0116] The light emitting layers EL1, EL2, and EL3 can include a first light emitting layer EL1, a second light emitting layer EL2, and a third light emitting layer EL3 located in different light emission areas EA1, EA2, and EA3, respectively. The first light emitting layer EL1 can be located on the first pixel electrode AE1 in the first light emission area EA1, the second light emitting layer EL2 can be located on the second pixel electrode AE2 in the second light emission area EA2, and the third light emitting layer EL3 can be located on the third pixel electrode AE3 in the third light emission area EA3. The plurality of light emitting layers EL1, EL2, and EL3 can emit different colors of light, respectively, or one of the light emitting layers EL1, EL2, and EL3 can emit mixed light. In one or more embodiments, the first light emitting layer EL1 can emit red light, the second light emitting layer EL2 can emit green light, and the third light emitting layer EL3 can emit blue light.

[0117] The light emitting layers EL1, EL2, and EL3 can be located on the upper surface of the pixel defining layer PDL. In one or more embodiments, the side surface of the residual pattern RP can be more recessed than the side surface of the pixel defining layer PDL, and a portion of the light emitting layers EL1, EL2, and EL3 can be located in the space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. In one or more embodiments, the light emitting layers EL1, EL2, and EL3 can contact the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0118] The common electrodes CE1, CE2, and CE3 can be located on the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 can include a transparent conductive material so that light generated from the light emitting layers EL1, EL2, and EL3 can be emitted. The common electrodes CE1, CE2, and CE3 can receive a common voltage or a low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to a data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference can be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, whereby the light emitting layers EL1, EL2, and EL3 can emit light.

[0119] The common electrodes CE1, CE2, and CE3 can include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 located in different light emission areas EA1, EA2, and EA3, respectively. The first common electrode CE1 can be located on the first light emitting layer EL1 in the first light emission area EA1, the second common electrode CE2 can be located on the second light emitting layer EL2 in the second light emission area EA2, and the third common electrode CE3 can be located on the third light emitting layer EL3 in the third light emission area EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 can be spaced apart from each other.

[0120] In one or more embodiments, a capping layer can be selectively located on the common electrodes CE1, CE2, and CE3. The capping layer can include an organic material or an inorganic insulating material to cover the pattern located on the light emitting elements ED1, ED2, and ED3. The capping layer can reduce or prevent the light emitting elements ED1, ED2, and ED3 from being damaged due to external air. In one or more embodiments, the capping layer can include an organic material such as a-NPD, NPB, TPD, m-MTDATA, Alq3, and / or CuPc, or an inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0121] The capping layer can include a first capping layer, a second capping layer, and a third capping layer positioned in the different light emission areas EA1, EA2, and EA3, respectively. The first to third capping layers can be spaced apart from each other.

[0122] The pixel definition layer PDL can be positioned on the second passivation layer PAS2 to expose upper surfaces of the pixel electrodes AE1, AE2, and AE3.

[0123] The pixel definition layer PDL can include a first inorganic layer IL1 on the second passivation layer PAS2, a second inorganic layer IL2 on the first inorganic layer IL1, and a third inorganic layer IL3 on the second inorganic layer IL2. The first inorganic layer IL1 can absorb moisture from the second passivation layer PAS2, the second inorganic layer IL2 can protect the first inorganic layer IL1, and the third inorganic layer IL3 can reduce or prevent moisture penetration.

[0124] The first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 of the pixel definition layer PDL can include an inorganic insulating material. The pixel definition layer PDL can include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0125] The first inorganic layer IL1 and the second inorganic layer IL2 adjacent to each other can include different materials and thus can have different etching rates with respect to an etchant. The second inorganic layer IL2 and the third inorganic layer IL3 adjacent to each other can include different materials and thus can have different etching rates with respect to an etchant. In one or more embodiments, the first inorganic layer IL1 and the third inorganic layer IL3 can include the same material or different materials.

[0126] In one or more embodiments, the first inorganic layer IL1 and the third inorganic layer IL3 can include silicon nitride (SiN x ), and the second inorganic layer IL2 can include one or more of silicon oxynitride (SiO x N y ), and silicon oxide (SiO x ).

[0127] A thickness of the first inorganic layer IL1 can be less than a thickness of the second inorganic layer IL2. The thickness T1 of the first inorganic layer IL1 can be less than a thickness of the pixel electrodes AE1, AE2, and AE3. The thickness of the second inorganic layer IL2 can be greater than a thickness of the third inorganic layer IL3. In one or more embodiments, the thickness of the first inorganic layer IL1 can be about to about or about to about In one or more embodiments, the second inorganic layer IL2 can have a thickness of about 100 nm to about 300 nm. or about 200 nm to about 300 nm. or about 200 nm to about 300 nm. or about 200 nm to about 300 nm.

[0128] According to one or more embodiments, the pixel-defining layer PDL is located on edges of the pixel electrodes AE1, AE2, and AE3, and can be spaced apart from upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel-defining layer PDL can not directly contact the upper surfaces of the pixel electrodes AE1, AE2, and AE3, while partially overlapping the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in a thickness direction (third direction DR3) of the substrate SUB, and a residual pattern RP can be located between the pixel-defining layer PDL and the pixel electrodes AE1, AE2, and AE3. However, the pixel-defining layer PDL can directly contact side surfaces of the pixel electrodes AE1, AE2, and AE3.

[0129] The second inorganic layer IL2 can include a first side surface facing side surfaces of the pixel electrodes AE1, AE2, and AE3, a second side surface protruding more toward the light emission areas EA1, EA2, and EA3 than the first side surface, and a first lower surface connecting the first side surface and the second side surface. The first lower surface of the second inorganic layer IL2 can face an upper surface of the residual pattern RP, and the first side surface can face a side surface of the residual pattern RP. The second side surface of the second inorganic layer IL2 can define the light emission areas EA1, EA2, and EA3. The pixel electrodes AE1, AE2, and AE3 can overlap the second inorganic layer IL2 and / or the third inorganic layer IL3 in the thickness direction (third direction DR3), and can not overlap the first inorganic layer IL1.

[0130] The residual pattern RP can be located on an edge of each of the pixel electrodes AE1, AE2, and AE3. The pixel-defining layer PDL can not directly contact the upper surfaces of the pixel electrodes AE1, AE2, and AE3 due to the residual pattern RP. In a manufacturing process of the display device 10, a portion of the sacrificial layer located on the pixel electrodes AE1, AE2, and AE3 can be removed, and thus the residual pattern RP can be formed. The residual pattern RP can include a metal or an oxide semiconductor material. In the drawings, a side surface of the residual pattern RP facing the light emission areas EA1, EA2, and EA3 is only shown as being more recessed than a second side surface of the pixel-defining layer PDL, but the present disclosure is not limited thereto. The side surface of the residual pattern RP can protrude farther toward the light emission areas EA1, EA2, and EA3 than the second side surface of the pixel-defining layer PDL, or can be aligned with the second side surface of the pixel-defining layer PDL.

[0131] The display device 10 can include a bank structure BNS on the pixel definition layer PDL. The bank structure BNS can have a structure in which banks BN1 and BN2 including different corresponding materials are sequentially stacked, and can include / define a plurality of openings overlapping the light emission areas EA1, EA2, and EA3. The bank structure BNS can overlap the non-light emission areas between the light emission areas EA1, EA2, and EA3, and can overlap the light blocking areas of the color filters CF1, CF2, and CF3, which will be described later.

[0132] The first bank BN1 can be located on the pixel definition layer PDL. The side surface of the first bank BN1 can be more recessed than the side surface of the pixel definition layer PDL in the opposite direction of the direction toward the light emission areas EA1, EA2, and EA3. The side surface of the first bank BN1 can be more recessed than the side surface of the second bank BN2, which will be described later, in the opposite direction of the direction toward the light emission areas EA1, EA2, and EA3.

[0133] According to one or more embodiments, the first bank BN1 can include a metallic material. In one or more embodiments, the first bank BN1 can include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al).

[0134] The common electrodes CE1, CE2, and CE3 can directly contact the side surface of the first bank BN1. The end portions of the common electrodes CE1, CE2, and CE3 can contact the side surface(s) of the first bank BN1. The common electrodes CE1, CE2, and CE3 of the spaced apart light emitting elements ED1, ED2, and ED3 can directly contact the first bank BN1, and the first bank BN1 can include a conductive material so that the common electrodes CE1, CE2, and CE3 can be electrically connected to each other through the first bank BN1.

[0135] According to one or more embodiments, the light emitting layers EL1, EL2, and EL3 can directly contact the side surface of the first bank BN1. The area in which the common electrodes CE1, CE2, and CE3 contact the side surface of the first bank BN1 can be greater than the area in which the light emitting layers EL1, EL2, and EL3 contact the side surface of the first bank BN1. The common electrodes CE1, CE2, and CE3 can be positioned to have a greater area on the side surface of the first bank BN1 than the light emitting layers EL1, EL2, and EL3, and / or to have a higher position than the side surface of the first bank BN1. Since the common electrodes CE1, CE2, and CE3 of the different light emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank BN1, it can be appropriate for the common electrodes CE1, CE2, and CE3 to contact the first bank BN1 with a greater area (e.g., the common electrodes CE1, CE2, and CE3 have a greater contact area with the first bank BN1).

[0136] The first bank BN1 can have an upper surface at a higher position than the common electrodes CE1, CE2, and CE3. A height from the substrate SUB to the upper surface of the first bank BN1 can be greater than a height from the substrate SUB to the common electrodes CE1, CE2, and CE3.

[0137] The second bank BN2 can be located on the first bank BN1. The second bank BN2 can include / define openings overlapping the light emission areas EA1, EA2, and EA3, respectively, and each of the openings can include a side surface. The second bank BN2 can include a tip TIP or a eave as a region more protruding than the first bank BN1. The side surface of the second bank BN2 can protrude more toward the light emission areas EA1, EA2, and EA3 than the side surface of the first bank BN1.

[0138] Since the side surface of the second bank BN2 has a shape extending farther toward the light emission areas EA1, EA2, and EA3 than the side surface of the first bank BN1, an undercut structure of the first bank BN1 can be formed under the tip TIP of the second bank BN2.

[0139] In the display apparatus 10 according to one or more embodiments, the bank structure BNS can include the tip TIP protruding toward the light emission areas EA1, EA2, and EA3, so that the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other can be formed by a deposition and etching process, not a mask process. Further, even through the deposition process, different layers can be formed separately in different light emission areas EA1, EA2, and EA3. For example, although the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 are formed by the deposition process without using a mask, the deposited materials can be disconnected by the tip TIP of the second bank BN2 and the bank structure BNS interposed between the deposited materials, rather than connected between the light emission areas EA1, EA2, and EA3. After forming the materials for forming the respective layers on the entire surface of the display apparatus 10, different layers can be formed separately in different light emission areas EA1, EA2, and EA3 by a process of removing the layers formed in undesired areas through etching. In the display apparatus 10, different light emitting elements ED1, ED2, and ED3 can be formed for the light emission areas EA1, EA2, and EA3, respectively, by the deposition and etching process without using a mask process, unnecessary elements in the display apparatus 10 can be omitted, and the size of the non-display area NDA can be reduced or minimized.

[0140] The second bank BN2 can include a metal material different from that of the first bank BN1. The metal material of the second bank BN2 is removed together with the metal material of the first bank BN1 by dry etching, but can be any material having an etching rate significantly slower than that of the first bank BN1 or not etched with respect to wet etching. In one or more embodiments, the first bank BN1 can include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al), and the second bank BN2 can include titanium (Ti), an oxide of titanium (Ti), or an alloy of titanium (Ti).

[0141] The tip TIP of the second bank BN2 can overlap the common electrode CE1, CE2, and CE3, the light emitting layer EL1, EL2, and EL3, and the pixel definition layer PDL in a third direction DR3 orthogonal to the substrate SUB. The common electrode CE1, CE2, and CE3 can be formed under the lower surface of the tip TIP of the second bank BN2. The end portion of each of the common electrode CE1, CE2, and CE3 can overlap the second bank BN2 in the thickness direction (the third direction DR3) of the substrate SUB.

[0142] The thin film encapsulation layer TFEL (e.g., TFE1, TFE2, and TFE3 as shown in FIG. 1B) can be located on and can cover the light emitting elements ED1, ED2, and ED3 and the bank structure BNS. Figure 5 The thin film encapsulation layer TFEL can include at least one inorganic layer to reduce or prevent penetration of oxygen or moisture into the light emitting element layer EML. The thin film encapsulation layer TFEL can include at least one organic layer to protect the light emitting element layer EML from particles such as dust.

[0143] In one or more embodiments, the thin film encapsulation layer TFEL can include a lower inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and an upper inorganic encapsulation layer TFE3 stacked in order.

[0144] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 can include one or more inorganic insulating materials. The inorganic insulating material can be any one of silicon oxide, silicon nitride, and silicon oxynitride, and can be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0145] The organic encapsulation layer TFE2 can include a polymer-based material. The polymer-based material can include an acrylic resin, an epoxy-based resin, a polyimide, and / or a polyethylene. For example, the organic encapsulation layer TFE2 can include an acrylic resin such as polymethyl methacrylate, polyacrylic acid, or the like. The organic encapsulation layer TFE2 can be formed by hardening a monomer or coating a polymer.

[0146] The lower inorganic encapsulation layer TFE1 can be located on the light emitting elements ED1, ED2, and ED3 and the bank structure BNS. The lower inorganic encapsulation layer TFE1 can include a first inorganic pattern IP1, a second inorganic pattern IP2, and a third inorganic pattern IP3 corresponding to different light emission areas EA1, EA2, and EA3, respectively. Each of the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 can include an inorganic insulating material to cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 can reduce or prevent damage to the light emitting elements ED1, ED2, and ED3 due to external air.

[0147] The lower inorganic encapsulation layer TFE1 (IP1, IP2, and IP3) can be formed by a chemical vapor deposition (CVD) method and thus can be formed along the step difference of the deposition layer. For example, the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 can even form a thin film under undercut due to the end of the bank structure BNS. The lower inorganic encapsulation layer IP1, IP2, and IP3 can be positioned along the upper surface, the side surface, and the lower surface of the second bank BN2, the side surface of the first bank BN1, and the upper surface of the common electrodes CE1, CE2, and CE3. For example, the lower inorganic encapsulation layer IP1, IP2, and IP3 can contact the lower surface of the second bank BN2 to reduce or prevent the possibility of moisture penetration from the external air.

[0148] The first inorganic pattern IP1 does not overlap the second light emitting element ED2 and the third light emitting element ED3, and can be located only on the first light emitting element ED1 and the bank structure BNS in the vicinity of the first light emitting element ED1. The second inorganic pattern IP2 does not overlap the first light emitting element ED1 and the third light emitting element ED3, and can be located only on the second light emitting element ED2 and the bank structure BNS in the vicinity of the second light emitting element ED2. The third inorganic pattern IP3 does not overlap the first light emitting element ED1 and the second light emitting element ED2, and can be located only on the third light emitting element ED3 and the bank structure BNS in the vicinity of the third light emitting element ED3.

[0149] The first inorganic pattern IP1 can be formed after the first common electrode CE1 is formed, the second inorganic pattern IP2 can be formed after the second common electrode CE2 is formed, and the third inorganic pattern IP3 can be formed after the third common electrode CE3 is formed. The first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 can be spaced apart from each other on the bank structure BNS.

[0150] The lower inorganic encapsulation layers IP1, IP2, and IP3 are located on upper surfaces of the light emitting elements ED1, ED2, and ED3 and lower surfaces of the second bank BN2 in the vicinity of the light emitting elements ED1, ED2, and ED3, and can be spaced apart from upper surfaces of the second bank BN2. That is, the lower inorganic encapsulation layers IP1, IP2, and IP3 can have an undercut structure on the second bank BN2. Spaces between the lower inorganic encapsulation layers IP1, IP2, and IP3 and the upper surfaces of the second bank BN2 can be spaces from which materials of the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 deposited over the entire surfaces are removed.

[0151] The organic encapsulation layer TFE2 is located on the bank structure BNS and the lower inorganic encapsulation layers IP1, IP2, and IP3. A portion of the organic encapsulation layer TFE2 can be located in the spaces between the lower inorganic encapsulation layers IP1, IP2, and IP3 and the upper surfaces of the second bank BN2. In regions in which the second bank BN2 overlaps the lower inorganic encapsulation layers IP1, IP2, and IP3, the second bank BN2, the organic encapsulation layer TFE2, and the lower inorganic encapsulation layers IP1, IP2, and IP3 can be positioned in order. In regions overlapping the tips TIP, the organic encapsulation layer TFE2 and the lower inorganic encapsulation layers IP1, IP2, and IP3 can be located on the second bank BN2 in order, and the organic encapsulation layer TFE2 can be located again on the lower inorganic encapsulation layers IP1, IP2, and IP3. In other words, a portion of the organic encapsulation layer TFE2 can be located between the upper surfaces of the second bank BN2 and the lower inorganic encapsulation layers IP1, IP2, and IP3 on the tips TIP of the second bank BN2, and another portion thereof can be located on the lower inorganic encapsulation layers IP1, IP2, and IP3.

[0152] In one or more embodiments, the entire upper surface of the second bank BN2 can contact the organic encapsulation layer TFE2. The first lower surfaces of the lower inorganic encapsulation layers IP1, IP2, and IP3 can be surfaces facing the upper surfaces of the second bank BN2, and the first lower surfaces of the lower inorganic encapsulation layers IP1, IP2, and IP3 can contact the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 can contact side surfaces of the second bank BN2.

[0153] The upper inorganic encapsulation layer TFE3 can be located on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 can include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0154] The display apparatus 10 can include a plurality of color filters CF1, CF2, and CF3 located on the light emission areas EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 can include a light filtering pattern area and a light blocking area. The light filtering pattern area can overlap the light emission areas EA1, EA2, and EA3 or the openings of the bank structure BNS and can form an emission area through which light emitted from the light emission areas EA1, EA2, and EA3 is emitted. The light blocking area is an area in which the plurality of color filters CF1, CF2, and CF3 are stacked such that light cannot be transmitted, and can overlap the non-light emission area.

[0155] The color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3 corresponding to the different light emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 can include a colorant such as a dye or a pigment for absorbing light of another wavelength band other than light of a corresponding wavelength band, and can correspond to the color of light emitted from the light emission areas EA1, EA2, and EA3. For example, the first color filter CF1 can be a red color filter overlapping the first light emission area EA1 for transmitting only red first light. The second color filter CF2 can be a green color filter overlapping the second light emission area EA2 for transmitting only green second light. The third color filter CF3 can be a blue color filter overlapping the third light emission area EA3 for transmitting only blue third light.

[0156] Since the color filters CF1, CF2, and CF3 overlap each other, the display apparatus 10 can reduce the intensity of reflected light due to external light. In addition, the display apparatus 10 can control the color sense of reflected light due to external light by adjusting the layout, shape, area, etc. of the color filters CF1, CF2, and CF3 on a plan view.

[0157] An overcoat layer OC can be located on the color filters CF1, CF2, and CF3 to planarize upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC can be a colorless light-transmitting layer having no color of a visible light band. For example, the overcoat layer OC can include a colorless light-transmitting organic material such as an acrylic resin.

[0158] A detailed description of the non-display area NDA will be made with reference to Figure 7 and Figure 8 A detailed description of the non-display area NDA will be made with reference to

[0159] Figure 7 is an enlarged view showing an edge region of the display device 10 as a boundary between the display region DA and the non-display region NDA of the display device 10. Figure 7 is Figure 2 is an enlarged plan view of the region A2 of Figure 8 is a cross-sectional view showing an example of the display device 10 taken along the line II-II' of Figure 7

[0160] Referring to Figure 7 and Figure 8 , the display device 10 includes a display region DA in which the bank structure BNS and the light emitting element ED are positioned and a non-display region NDA located near the display region DA. The bank structure BNS can be a boundary of the display region DA. The pixel definition layer PDL can be positioned not only in the display region DA but also in the non-display region NDA.

[0161] Meanwhile, the light emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the lower inorganic encapsulation layers IP1, IP2, and IP3 of the light emitting elements ED1, ED2, and ED3 can be sequentially formed for each color. After the materials of the first light emitting layer EL1, the first common electrode CE1, and the first inorganic pattern IP1 of the first color are deposited or coated on the entire surface, the first light emitting layer EL1, the first common electrode CE1, and the first inorganic pattern IP1 are retained only in the first light emission region EA1 and in the peripheral region thereof by patterning. Then, the same process can be repeated for the second light emitting layer EL2, the second common electrode CE2, and the second inorganic pattern IP2 of the second color, so that the second light emitting layer EL2, the second common electrode CE2, and the second inorganic pattern IP2 can be formed. The wet etching process or the cleaning process can be performed during the patterning process of the second color. When the second passivation layer PAS2 of the organic layer, on which the organic material is formed on the entire surface, is exposed to a solution of the wet etching process or the cleaning process, the second passivation layer PAS2 of the organic layer can absorb moisture. Since the first light emitting layer EL1 includes an organic material, it can be difficult to dry the moisture of the second passivation layer PAS2 by high-temperature baking during the patterning process of the second color. The remaining moisture can deteriorate the reliability when the display device 10 is driven.

[0162] Referring to Figure 8 , the pixel definition layer PDL can cover the second passivation layer PAS2. The upper surface and the side surface of the second passivation layer PAS2 are covered with the pixel electrodes AE1, AE2, and AE3 and the pixel definition layer PDL, and the lower surface of the second passivation layer PAS2 is covered with the first passivation layer PAS1 thereunder, whereby the penetration of moisture into the second passivation layer PAS2 can be reduced or prevented.

[0163] ​The pixel definition layer PDL can include a first inorganic layer IL1, a second inorganic layer IL2, and a third inorganic layer IL3. Even though the third inorganic layer IL3 at the upper portion is removed by an etchant during patterning for each color, the second inorganic layer IL2 having a different etchant selectivity can be exposed. The second inorganic layer IL2 is not etched by the etchant (etch stopper), and thus can protect the second passivation layer PAS2 from the etchant.

[0164] The third inorganic layer IL3 of the pixel definition layer PDL can be removed from at least a portion of the non-display area NDA. The third inorganic layer IL3 can include a first side IL3_S1 oriented (e.g., facing) toward the non-display area NDA, and the second bank BN2 can include a first side BN2_S1 oriented (e.g., facing) toward the non-display area NDA. The first side IL3_S1 of the third inorganic layer IL3 can be adjacent to the first side BN2_S1 of the second bank BN2. In one or more embodiments, the first side IL3_S1 of the third inorganic layer IL3 can be aligned with the first side BN2_S1 of the second bank BN2, or can protrude farther than the first side BN2_S1 of the second bank BN2.

[0165] The second passivation layer PAS2 can include a side surface inclined from the substrate SUB in the non-display area NDA. An angle θ formed by the lower surface and the side surface of the second passivation layer PAS2 can be less than about 90°.

[0166] The pixel definition layer PDL can include a first portion located at a first height from the substrate SUB, a second portion located at a second height from the substrate SUB, and a third portion located at a third height from the substrate SUB. The first height can be greater than the second height, and the second height can be greater than the third height. The first portion, the second portion, and the third portion of the pixel definition layer PDL can be positioned in sequence in a longitudinal direction of the substrate SUB. In other words, the second portion of the pixel definition layer PDL can be located between the first portion and the third portion in the longitudinal direction of the substrate SUB. The height of the pixel definition layer PDL refers to a vertical distance between the upper surface of the substrate SUB and the lower surface of the corresponding portion of the pixel definition layer PDL.

[0167] A fourth inorganic pattern IP4 can be formed on the second inorganic layer IL2. The fourth inorganic pattern IP4 can be formed concurrently or substantially simultaneously with any of the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 of the lower inorganic encapsulation layer TFE1, and can include the same material as the material of the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3. The fourth inorganic pattern IP4 can be spaced apart from one or more of the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 of the lower inorganic encapsulation layer TFE1. The fourth inorganic pattern IP4 can be located on the second inorganic layer IL2, the first inorganic layer IL1, the first bank BN1, and the second bank BN2.

[0168] Figure 9 is a cross-sectional view illustrating a portion of a display apparatus according to one or more embodiments.

[0169] Figure 9 is different from Figure 8 in that the first passivation layer PAS1' is removed from a portion of the non-display area NDA, and thereby exposes the second interlayer insulating layer ILD2. The first passivation layer PAS1' can be removed in order to enhance a sealing effect in the non-display area NDA. The first inorganic layer IL1' of the pixel definition layer PDL can cover a side surface of the first passivation layer PAS1' and the second interlayer insulating layer ILD2.

[0170] Figure 10 is a cross-sectional view illustrating a portion of a display apparatus according to one or more embodiments.

[0171] Figure 10 is different from Figure 8 in that the second passivation layer PAS2' extends in the non-display area NDA. The second passivation layer PAS2' having a planarization function can extend in the non-display area NDA. The first inorganic layer IL1'' of the pixel definition layer PDL can cover an upper surface of the second passivation layer PAS2'.

[0172] Figure 11 is a cross-sectional view illustrating a portion of a display apparatus according to one or more embodiments, and Figure 12 is an enlarged cross-sectional view illustrating Figure 11 a region A5 of

[0173] Figure 11 and Figure 12 is different from Figure 8 in that a thickness of a portion of the third inorganic layer IL3' of the pixel definition layer PDL is removed from the non-display area NDA. The third inorganic layer IL3' is different from Figure 9The third inorganic layer IL3' is similar in that the third inorganic layer IL3' exposed to the etchant is removed during patterning for each color. However, only a partial thickness, not the total thickness, of the third inorganic layer IL3' is removed in the area exposed to the etchant, and the thickness of the third inorganic layer IL3' can remain thin. Accordingly, the thickness of the third inorganic layer IL3' in a partial area of the non-display area NDA can be different from the thickness of the third inorganic layer IL3' in the display area DA.

[0174] Reference Figure 12 The thickness of the third inorganic layer IL3' can vary based on the boundary of the first side surface IL3'_S1. Based on the first side surface IL3'_S1, the thickness T31 of the portion of the third inorganic layer IL3' adjacent to the bank structure BNS can be greater than the thickness T32 of the portion of the third inorganic layer IL3' away from the bank structure BNS.

[0175] Although the embodiments of the present disclosure have been described with reference to the drawings, it will be apparent to those skilled in the art that the present disclosure can be implemented in other forms without departing from the technical spirit and essential characteristics of the present disclosure. Therefore, the above embodiments should be considered in all aspects as illustrative and not restrictive.

[0176] Embodiments of the present disclosure have been described above with reference to the drawings, but it will be understood by those of ordinary skill in the art to which the present disclosure belongs that various modifications and changes can be made without departing from the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the above-described embodiments are exemplary in all aspects and are not restrictive.

[0177] Features of various embodiments of the present disclosure can be partially or wholly combined. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. Furthermore, the various embodiments can be practiced individually or in combination.

[0178] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the described embodiments without substantially departing from the aspects of the present disclosure. Accordingly, the disclosed embodiments are used in a general and descriptive sense, and are not for limiting purposes.

Claims

1. A display device including a display region and a non-display region around the display region, the display device comprising: a substrate; a passivation layer over the substrate; a light-emitting element over the passivation layer; a pixel-defining layer over the passivation layer in the display region and the non-display region, and including a first inorganic layer, a second inorganic layer, and a third inorganic layer, the first inorganic layer being in the display region and the non-display region, the second inorganic layer being over the first inorganic layer in the display region and the non-display region, the third inorganic layer being over the second inorganic layer in the display region; a first bank over the pixel-defining layer; and a second bank over the first bank, and extending farther than a side surface of the first bank. In at least a portion of the non-display region, the second inorganic layer is not covered with the third inorganic layer.

2. The display device of claim 1, wherein, A side surface of the third inorganic layer facing the non-display region extends farther than a side surface of the second bank facing the non-display region, or is aligned with the side surface of the second bank facing the non-display region.

3. The display device of claim 1, wherein, The pixel-defining layer is on an upper surface and a side surface of the passivation layer.

4. The display device of claim 1, wherein, An angle between a lower surface of the passivation layer and the side surface of the passivation layer is less than 90°.

5. The display device of claim 4, wherein, The pixel-defining layer includes a first portion at a first height over the substrate, a second portion at a second height over the substrate, and a third portion at a third height over the substrate, 6. The display device of claim 5, wherein, wherein the first height is greater than the second height and the third height, wherein the second height is greater than the third height, and wherein the first portion, the second portion, and the third portion of the pixel-defining layer are arranged in a longitudinal direction of the substrate in this order. The passivation layer extends in the display region and the non-display region.

7. The display device of claim 1, wherein, A thickness of the first inorganic layer is less than a thickness of the second inorganic layer.

8. The display device of claim 1, wherein, A thickness of the first inorganic layer is less than a thickness of a pixel electrode of the light-emitting element.

9. The display device of claim 1, wherein, The second inorganic layer includes a first side surface facing a side surface of the pixel electrode, and a second side surface extending farther than the first side surface.

10. The display device of claim 9, wherein, The second inorganic layer includes a material different from the first inorganic layer and the third inorganic layer.

11. The display device of claim 1, wherein, The first inorganic layer and the third inorganic layer include silicon nitride, and 12. The display device of claim 11, wherein, wherein the second inorganic layer includes one or more of silicon oxynitride and silicon oxide. The passivation layer includes one or more of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

13. The display device of claim 1, wherein, In the display region, the pixel-defining layer includes a side surface extending farther than the side surface of the first bank.

14. The display device of claim 1, wherein, 15. The display device according to claim 1, further comprising a residual pattern at an edge of a pixel electrode of the light-emitting element under the pixel-defining layer. The light-emitting element includes a pixel electrode over the passivation layer, a light-emitting layer over the pixel electrode, and a common electrode over the light-emitting layer and in contact with the first bank.

16. The display device of claim 1, wherein, 17. The display device according to claim 1, further comprising: ​ a first inorganic pattern over the light-emitting element in the display region; and a second inorganic pattern over the pixel-defining layer in the non-display region, and spaced apart from the first inorganic pattern.

18. The display device of claim 17, wherein, The first inorganic pattern is below a lower surface of the second bank.

19. A display device, comprising: a substrate; a light-emitting element over the substrate; a pixel-defining layer over the substrate, including a first inorganic layer over the substrate, a second inorganic layer over the first inorganic layer, and a third inorganic layer over the second inorganic layer; a first bank over the pixel-defining layer; and a second bank over the first bank, and extending farther than a side surface of the first bank, wherein the third inorganic layer has a different corresponding thickness in a region overlapping with the first bank and in a region not overlapping with the first bank. The thickness of the third inorganic layer in the region overlapping with the first bank is greater than the thickness of the third inorganic layer in the region not overlapping with the first bank.

20. The display device of claim 19, wherein, 21. An electronic device, comprising: a display device including a display region and a non-display region around the display region, the display device including: a substrate; a passivation layer over the substrate; a light-emitting element over the passivation layer; a pixel-defining layer over the passivation layer in the display region and the non-display region, and including a first inorganic layer, a second inorganic layer, and a third inorganic layer, the first inorganic layer being in the display region and the non-display region, the second inorganic layer being over the first inorganic layer in the display region and the non-display region, the third inorganic layer being over the second inorganic layer in the display region; a first bank over the pixel-defining layer; and a second bank over the first bank, and extending farther than a side surface of the first bank. ​

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