Display device, method for manufacturing display device, and electronic device

Abstract

The invention discloses a display device, a manufacturing method of the display device and an electronic device. The display device includes a substrate including a first surface, a second surface, and a side surface between the first surface and the second surface; a pixel circuit layer disposed on the first surface of the substrate and including a transistor including a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer; and a light emitting element disposed on the pixel circuit layer and electrically connected to the transistor, in which the side surface of the substrate has an inclination, and the insulating layer is disposed on the side surface of the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, a manufacturing method of a display device, and an electronic device. BACKGROUND

[0002] Recently, as the interest in information display has increased, research and development of display devices has been continuously conducted. SUMMARY

[0003] The present application is to solve the technical problem of providing a manufacturing method of a display device capable of improving impact strength of the display device.

[0004] The technical problem of the present application is not limited to the above-mentioned technical problem, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0005] A display device according to an embodiment for solving the above-mentioned technical problem includes a substrate including a first surface, a second surface, and a side surface between the first surface and the second surface; a pixel circuit layer disposed on the first surface of the substrate and including a transistor including a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer; and a light emitting element disposed on the pixel circuit layer to be electrically connected with the transistor, wherein the side surface of the substrate has a slope, and the insulating layer is disposed on the side surface of the substrate.

[0006] The transistor can include a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer, and the insulating layer can be disposed on the side surface of the substrate.

[0007] The insulating layer can have a slope on the side surface of the substrate.

[0008] The display device can further include an encapsulation layer disposed on the light emitting element, and the encapsulation layer can be disposed on the side surface of the substrate.

[0009] The encapsulation layer can have a slope on the side surface of the substrate.

[0010] The display device can further include a bank disposed on the encapsulation layer.

[0011] The display device can further include a light conversion pattern disposed in an opening portion of the bank.

[0012] The light conversion pattern can be directly disposed on the encapsulation layer.

[0013] The display device can further include a color filter disposed on the light conversion pattern.

[0014] The display device can further include a rotating member to wind and unwind the substrate.

[0015] The display device can further include a housing to accommodate the substrate and the rotating member.

[0016] A method of manufacturing a display device according to an embodiment to solve the above technical problems includes the steps of forming a trench on a first surface of a substrate; forming a pixel circuit layer on the trench; forming a light emitting element on the pixel circuit layer; forming a scribe line on a lower surface of the trench; and etching a second surface of the substrate to form a thickness of the substrate to be thinner.

[0017] The pixel circuit layer can have a slope on a side surface of the trench.

[0018] The method of manufacturing the display device can further include the step of forming an encapsulation layer on the light emitting element, the encapsulation layer being formed on the trench.

[0019] The encapsulation layer can have a slope on a side surface of the trench.

[0020] The method of manufacturing the display device can further include the step of forming a light conversion pattern on the encapsulation layer.

[0021] The method of manufacturing the display device can further include the step of forming a color filter on the light conversion pattern.

[0022] The trench can have a depth of 80 μm to 100 μm.

[0023] The scribe line can have a depth of 16 μm to 20 μm.

[0024] In the step of etching the second surface of the substrate, the substrate can be cut along the scribe line.

[0025] To solve the above technical problems, an electronic device according to an embodiment includes a processor; and a display device including a pixel and configured to display an image at the pixel according to a control of the processor, wherein the display device can be the above-described display device.

[0026] Particular matters of other embodiments are contained in the detailed description and the accompanying drawings.

[0027] According to the above-described embodiment, by forming a trench on a substrate, a contact time with an etching solution can be minimized in a process of etching the substrate, thereby improving an impact strength of the substrate.

[0028] The effects according to the embodiments are not limited by the above examples, and more various effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 FIG. 1 is a perspective view schematically illustrating a display device according to an embodiment.

[0030] Figure 2 FIG. 2 is a side perspective view schematically illustrating a display device according to an embodiment.

[0031] Figure 3 FIG. 3 is a perspective view illustrating a display module in an unfolded state in a display device according to an embodiment.

[0032] Figure 4 FIG. 4 is a plan view schematically illustrating a display device according to an embodiment.

[0033] Figure 5 FIG. 5 is a circuit view schematically illustrating an electrical connection relationship of a sub-pixel according to an embodiment.

[0034] Figure 6 FIG. 6 is a plan view schematically illustrating a pixel according to an embodiment.

[0035] Figure 7 FIG. 7 is a cross-sectional view taken along line A-A' of FIG. 6. Figure 6

[0036] Figure 8 FIG. 8 is a cross-sectional view schematically illustrating a non-display area of a display module according to an embodiment.

[0037] Figures 9 to 12 FIG. 9 is a cross-sectional view of a manufacturing method of a display device according to an embodiment, per process step.

[0038] Figure 13 FIG. 10 is a block diagram of an electronic device according to an embodiment.

[0039] Figure 14 FIG. 11 is a schematic view of an electronic device according to various embodiments.

[0040] REFERENCE NUMERALS DETAILED DESCRIPTION

[0041] ​Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present invention will be described, and the description of the parts other than these will be omitted to avoid confusing the gist of the present invention. The present invention is not limited to the embodiments described herein and may also be embodied in other forms. However, the embodiments described herein are provided in order to provide a detailed description to a person having ordinary knowledge in the technical field to which the present invention belongs so as to be able to easily implement the technical concept of the present invention.

[0042] Throughout the specification, when it is mentioned that a part is "connected" to another part, this may include not only the case of "direct connection" but also the case of "indirect connection" with other elements between them. The terms used herein are used to illustrate specific embodiments and are not intended to limit the present invention. Throughout the specification, when it is mentioned that a part may "include" a certain constituent element, unless otherwise stated, it means that other constituent elements may also be included, rather than excluding other constituent elements. "At least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as one X, one Y, one Z or any combination of two or more of X, Y and Z (for example, XYZ, XY, YZ, XZ). Here, "and / or" may include all combinations of one or more of the corresponding constituent elements.

[0043] Herein, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms may be used to distinguish one component from another. Therefore, without departing from the scope of the present disclosure, a first component may refer to a second component.

[0044] Spatially relative terms such as "below" and "above" may be used for illustrative purposes to illustrate the relationship between one element or feature and other element(s) or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacture, in addition to the orientation depicted in the figures. For example, if the device shown in the figures is flipped, an element depicted as being "below" another element or feature may be located "above" the other element or feature. Thus, in embodiments, the term "below" may encompass both above and below. Furthermore, a device may be oriented in other orientations (e.g., rotated 90 degrees or in other orientations), and accordingly, the spatially relative terms used herein may be interpreted accordingly.

[0045] Various embodiments can be described with reference to the accompanying drawings, which illustrate ideal embodiments by which the shapes can vary, for example, depending on tolerances and / or manufacturing techniques. Thus, the embodiments disclosed herein should not be construed as being limited to the particular shapes illustrated, but should be construed as including, for example, variations in shapes that occur due to manufacturing. As described above, the shapes shown in the drawings can not show the actual shapes of the regions of the device, and the present embodiments are not limited thereto.

[0046] Figure 1 FIG. 1 is a perspective view schematically illustrating a display device according to an embodiment. Figure 2 FIG. 2 is a side perspective view schematically illustrating a display device according to an embodiment. Figure 3 FIG. 3 is a perspective view illustrating a display module in an unfolded state in a display device according to an embodiment.

[0047] Referring to Figures 1 to 3 A display device DD according to an embodiment can be a rollable display device RD.

[0048] The display device DD can include a housing HS and a seating portion SDP. The display device DD can further include a display module DM (or, a display panel) equipped inside the housing HS, a rotating member RM, and / or a placing member FM.

[0049] The housing HS can be a structure that accommodates the display module DM rolled with a predetermined curvature. The display module DM can be a rollable display module.

[0050] A slot HSO (or, a housing opening portion) through which the display module DM can pass can be provided at one side of the housing HS. The slot HSO of the housing HS can be a passage for rolling and unrolling (or, unwinding) of the display module DM. As an example, the display module DM can be rolled into the inside of the housing HS or unrolled (or, unwound) to the outside of the housing HS (for example, to the third direction DR3) through the slot HSO of the housing HS. The shape of the slot HSO of the housing HS can correspond to the cross-sectional shape of the display module DM, but is not limited thereto.

[0051] The rotating member RM (or, a roller) can be accommodated in the housing HS to roll and / or unroll the display module DM (or, a display panel). The rotating member RM can be rotatably provided inside the housing HS. The rotating member RM (or, a roller) can be fixed inside the housing HS by the placing member FM. The rotating member RM can have a cylindrical shape extending in the first direction DR1, but is not limited thereto. For example, the rotating member RM can also have a polygonal cross-sectional shape. The display module DM can be rolled at the outer side of the rotating member RM.

[0052] The placement member FM can fix or support the rotation member RM inside the housing HS. For example, the placement member FM is disposed at both side ends of the rotation member RM, and a rotation shaft of the rotation member RM is rotatably coupled to the placement member FM. The placement member FM can rotate the rotation member RM. As an example, the placement member FM includes a motor disposed at at least one side of the rotation member RM, and the rotation shaft can be rotated using the motor. For example, the motor can be implemented as a stepping motor or a thermomotor, etc.

[0053] A side of the housing HS can be equipped with a sticking portion SDP. The sticking portion SDP can include a control portion 30 for outputting an image to the display module DM, a power supply portion 20, a speaker for outputting sound, an input / output terminal capable of inputting or outputting various signals, a wireless transceiver capable of transmitting or receiving signals in a wireless manner. Accordingly, various control printed circuit boards constituting the control portion 30 and power supply printed circuit boards constituting the power supply portion 20 can be provided inside the sticking portion SDP, but are not limited thereto. According to an embodiment, a motor control portion 10 for controlling the motor can be provided in the sticking portion SDP.

[0054] The display module DM can display an image. The display module DM (or a display panel) can also have flexibility. As an example, the display module DM can have a rollable characteristic. Accordingly, in a case where the display device DD is in a closed mode, the display module DM is rolled to be accommodated inside the housing HS, and in a case where the display device DD is in an open mode, the display module DM can be drawn (or unrolled) in a direction opposite to a rolling direction to be unfolded in one direction from the housing HS.

[0055] The display module DM can be converted from a completely rolled state to a completely unfolded state, or from a completely unfolded state to a completely rolled state. The completely rolled state can mean a state in which the display module DM is accommodated inside the housing HS so that the display device DD does not display an image. According to an embodiment, the display module DM can also be converted from the completely rolled state to a state in which only a part is unfolded. The state in which a part of the display module DM is unfolded can mean a state in which a part of the display module DM is disposed outside the housing HS.

[0056] The display module DM can be provided in various shapes, and as an example, can be provided in a rectangular plate shape having two pairs of sides parallel to each other, but is not limited thereto. In a case where the display module DM is provided in a rectangular plate shape, any one of the two pairs of sides can be provided to be longer than the other pair of sides. The case in which the display module DM has a corner portion having an edge formed of a straight line is illustrated in the drawings, but is not limited thereto.

[0057] The display module DM can include a display area DA in which an image is displayed and a non-display area NDA disposed at least one side of the display area DA. The non-display area NDA can be an area in which an image is not displayed.

[0058] According to an embodiment, the display module DM can include a sensing area and a non-sensing area. The display module DM can not only display an image through the sensing area but also sense a touch input made on a display surface (or an input surface) or light incident from the front. The non-sensing area can surround the sensing area, but this is only exemplary and is not limited thereto. According to an embodiment, a part of the display area DA can also correspond to the sensing area.

[0059] Figure 4 FIG. 1 is a plan view schematically illustrating a display device according to an embodiment.

[0060] In Figure 4 , for convenience of explanation, a structure of a display device DD (as an example, a display module DM equipped in the display device DD) is briefly illustrated with the display area DA in which an image is displayed as a center.

[0061] Referring to Figure 4 , the display module DM can include the display area DA and the non-display area NDA. The display module DM can include a substrate SUB, a sub-pixel SP, and a pad PD.

[0062] The substrate SUB can include a transparent insulating substance and can transmit light. The substrate SUB can have flexibility. For example, the substrate SUB can be one of a film substrate including a high molecular organic substance and a plastic substrate. The substrate SUB can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate.

[0063] The sub-pixels SP (or pixels PXL) can be disposed in the display area DA of the substrate SUB. The display area DA can have various shapes. For example, the display area DA can be provided in various shapes including a polygon in a closed form including sides composed of straight lines, a circle including sides composed of curved lines, an ellipse, etc., a semi-circle, a semi-ellipse, etc., including sides composed of straight lines and curved lines.

[0064] The non-display region NDA can be provided at least one side of the display region DA. As an example, the non-display region NDA can surround the edges of the display region DA. The sub-pixels SP can be arranged in a matrix pattern on the substrate SUB along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement pattern of the sub-pixels SP is not limited thereto. As an example, the sub-pixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. As an example, the first direction DR1 can be a row direction, and the second direction DR2 can be a column direction. Two or more of the sub-pixels SP can constitute one pixel PXL, but is not limited thereto.

[0065] A constituent element for controlling the sub-pixel SP can be disposed in the non-display region NDA. For example, a wiring electrically connected to the sub-pixel SP can be disposed in the non-display region NDA. The wiring can include, for example, a gate line, a data line, and the like.

[0066] In order to drive the sub-pixel SP, a driving portion electrically connected to the sub-pixel SP can be disposed (or integrated) in the non-display region NDA of the display module DM. In addition, a pad PD can be disposed in the non-display region NDA. The pad PD can be electrically connected to the sub-pixel SP through a wiring. For example, the pad PD can be electrically connected to the sub-pixel SP through a data line.

[0067] In an embodiment, the circuit board can be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board can be a flexible circuit board or a flexible film having a flexible material. The driving portion can be mounted on the circuit board to be electrically connected to the pad PD.

[0068] Figure 5 FIG. 1 is a circuit diagram schematically showing an electrical connection relationship of a sub-pixel according to an embodiment.

[0069] For convenience of explanation, Figure 5 A sub-pixel SP located at an i-th horizontal line (or i-th pixel row) and connected to a j-th data line Dj is shown.

[0070] The sub-pixel SP can be disposed at the i-th horizontal line (or i-th pixel row). The sub-pixel SP can include a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0071] The first electrode of the light emitting element LD can be electrically connected to the fourth node N4, and the second electrode of the light emitting element LD can be electrically connected to the fourth power supply line PL4. The light emitting element LD can generate light having a predetermined brightness in correspondence with an amount of current (or driving current) supplied from the first transistor T1. In an embodiment, the light emitting element LD can be an organic light emitting diode including an organic light emitting layer.

[0072] The first transistor T1 (or driving transistor) can be electrically connected between the first power supply line PL1 and the first electrode of the light emitting element LD. The first transistor T1 can include a gate electrode electrically connected to the first node N1. The first transistor T1 can control an amount of current (or driving current) flowing from the first power supply line PL1 to the fourth power supply line PL4 via the light emitting element LD based on a voltage of the first node N1. The first power supply line PL1 can be applied with a first power supply voltage VDD, and the fourth power supply line PL4 can be applied with a second power supply voltage VSS, a voltage of the first power supply voltage VDD can be set to be higher than a voltage of the second power supply voltage VSS.

[0073] The second transistor T2 can be electrically connected between the jth data line Dj and the second node N2. A gate electrode of the second transistor T2 can be electrically connected to the 1th scan line S1i (or, first scan line). When a first scan signal GW[i] (e.g., a first scan signal of a low level) is supplied to the 1th scan line S1i, the second transistor T2 can be turned on to electrically connect the jth data line Dj and the second node N2. If the first transistor T1 and the third transistor T3 are turned on, respectively, the second transistor T2 can transmit a data signal of the jth data line Dj to the second node N2 in response to the first scan signal GW[i].

[0074] The third transistor T3 can be electrically connected between the first node N1 and the third node N3. A gate electrode of the third transistor T3 can be electrically connected to the 1th scan line S1i. When a first scan signal GW[i] (e.g., a first scan signal of a high level) is supplied to the 1th scan line S1i, the third transistor T3 can be turned on. If the third transistor T3 is turned on, the first transistor T1 can have a diode-connected form.

[0075] The fourth transistor T4 can be electrically connected between the first node N1 and the second power supply line PL2. A gate electrode of the fourth transistor T4 can be electrically connected to the 2th scan line S2i (or, second scan line). The second power supply line PL2 can be applied with a first initialization power supply voltage Vint1. The fourth transistor T4 can be turned on by a second scan signal GI[i]. If the fourth transistor T4 is turned on, the first initialization power supply voltage Vint1 can be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0076] The fifth transistor T5 can be electrically connected between the first power supply line PL1 and the second node N2. A gate electrode of the fifth transistor T5 can be electrically connected to the i-th light-emitting control line Ei (or the light-emitting control line). The sixth transistor T6 can be electrically connected between the third node N3 and the light-emitting element LD (or the fourth node N4). A gate electrode of the sixth transistor T6 can be electrically connected to the i-th light-emitting control line Ei. When the light-emitting control signal EM[i] (e.g., the light-emitting control signal EM[i] of a high level) is supplied to the i-th light-emitting control line Ei, the fifth transistor T5 and the sixth transistor T6 can be turned off, and in other cases, the fifth transistor T5 and the sixth transistor T6 can be turned on.

[0077] The seventh transistor T7 can be electrically connected between the first electrode of the light-emitting element LD (i.e., the fourth node N4) and the third power supply line PL3. A gate electrode of the seventh transistor T7 can be electrically connected to the 3i-th scan line S3i. The third power supply line PL3 can be applied with the second initialization power supply voltage Vint2. According to an embodiment, the second initialization power supply voltage Vint2 can be the same as or different from the first initialization power supply voltage Vint1. The seventh transistor T7 can be turned on by the third scan signal GB[i] supplied to the 3i-th scan line S3i, so that the second initialization power supply voltage Vint2 is supplied to the first electrode of the light-emitting element LD.

[0078] The storage capacitor Cst can be connected or formed between the first power supply line PL1 and the first node N1.

[0079] In this embodiment, the pixel circuit PXC can include a P-type transistor and an N-type transistor. The third transistor T3 and the fourth transistor T4 can be formed using an oxide transistor including an oxide semiconductor. As an example, the third transistor T3 and the fourth transistor T4 can be N-type oxide semiconductor transistors and can include an oxide semiconductor layer as an active layer, but are not limited thereto. An oxide semiconductor transistor can perform a low-temperature process and can have lower charge mobility than a polysilicon semiconductor transistor. That is, the off-current characteristics of an oxide semiconductor transistor can be excellent, and thus the leakage current in the third transistor T3 and the fourth transistor T4 can be minimized.

[0080] The other transistors (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) other than the third transistor T3 and the fourth transistor T4 can be formed with a polysilicon transistor including a silicon semiconductor, and can include a polysilicon semiconductor layer as an active layer. For example, the active layer can be formed through a low-temperature polysilicon process (e.g., an LTPS (low-temperature poly-silicon) process). For example, the polysilicon transistor can be a P-type polysilicon transistor. The polysilicon semiconductor transistor has an advantage of fast response speed, and thus can be applied to a switching element requiring fast switching.

[0081] Figure 6 is a plan view schematically showing a pixel according to an embodiment.

[0082] Referring to Figure 6 , the pixel PXL can include the first sub-pixel SP1, the second sub-pixel SP2, and / or the third sub-pixel SP3 arranged in a first direction DR1.

[0083] The first sub-pixel SP1 can include a first light emitting area EMA1 and a non-light emitting area NEA around the first light emitting area EMA1. The second sub-pixel SP2 can include a second light emitting area EMA2 and a non-light emitting area NEA around the second light emitting area EMA2. The third sub-pixel SP3 can include a third light emitting area EMA3 and a non-light emitting area NEA around the third light emitting area EMA3.

[0084] The first light emitting area EMA1 can be an area in which light is emitted from a first light emitting element (LD1) disposed in the first sub-pixel SP1. Figure 7 The second light emitting area EMA2 can be an area in which light is emitted from a second light emitting element (LD2) disposed in the second sub-pixel SP2. Figure 7 The third light emitting area EMA3 can be an area in which light is emitted from a third light emitting element (LD3) disposed in the third sub-pixel SP3. Figure 7 The third light emitting area EMA3 can be an area in which light is emitted from a third light emitting element (LD3) disposed in the third sub-pixel SP3.

[0085] The first sub-pixel SP1, the second sub-pixel SP2, and / or the third sub-pixel SP3 can have substantially the same area, but are not limited thereto. According to an embodiment, the second sub-pixel SP2 can have an area greater than that of the first sub-pixel SP1, and the third sub-pixel SP3 can also have an area greater than that of the second sub-pixel SP2.

[0086] The first sub-pixel SP1, the second sub-pixel SP2, and / or the third sub-pixel SP3 can have a polygonal shape. As one example, the first sub-pixel SP1, the second sub-pixel SP2, and / or the third sub-pixel SP3 can have a quadrangular shape or a hexagonal shape, but are not limited thereto. According to an embodiment, the first sub-pixel SP1, the second sub-pixel SP2, and / or the third sub-pixel SP3 can also have a circular shape, a semi-elliptical shape, or the like.

[0087] Figure 6 The arrangement of the sub-pixels SP1, SP2, SP3 shown in FIG. 1 is exemplary and is not necessarily limited thereto. Each pixel PXL can include two or more sub-pixels, the sub-pixels can be arranged in various ways, each of the sub-pixels can have various shapes, and each light emitting region of the sub-pixels can also have various shapes.

[0088] Figure 7 is a cross-sectional view taken along line A-A' of Figure 6 .

[0089] In Figure 7 , for convenience of explanation, a cross-sectional structure (or, a stacked structure) is briefly shown with the sub-pixel SP as the center, and the thickness direction of the substrate SUB is indicated as a third direction DR3.

[0090] Referring to Figure 7 , a pixel circuit layer PCL can be disposed on the substrate SUB. The pixel circuit layer PCL can include a buffer layer BFL, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, a third interlayer insulating layer IL3, a via layer VIA, and / or a transistor T.

[0091] The buffer layer BFL can be disposed on the substrate SUB in its entirety. The buffer layer BFL can prevent impurities from diffusing to the circuit elements (or, driving elements) (as one example, the transistor T) constituting the pixel circuit (PXC) of the pixel PXL. Figure 5 The buffer layer BFL can be an inorganic insulating film including an inorganic substance (or, material).

[0092] The buffer layer BFL can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). The buffer layer BFL can be provided as a single layer film, but can also be provided as a multi-layer film of at least a double layer film or more. In the case where the buffer layer BFL is provided as a multi-layer film, each layer can be formed using the same material as each other, or can be formed using different materials from each other. The buffer layer BFL can also be omitted depending on the material of the substrate SUB, process conditions, and the like.

[0093] The first interlayer insulating layer IL1 can be disposed on the buffer layer BFL in its entirety. The first interlayer insulating layer IL1 can include the same substance as the buffer layer BFL, or can include one or more substances suitable (or selected) for the constituent substance of the buffer layer BFL mentioned (or exemplified).

[0094] The second interlayer insulating layer IL2 can be disposed and / or formed on the first interlayer insulating layer IL1 in its entirety. The second interlayer insulating layer IL2 can include the same substance as the buffer layer BFL, or can include one or more substances suitable (or selected) for the constituent substance of the buffer layer BFL mentioned (or exemplified).

[0095] The third interlayer insulating layer IL3 can be disposed and / or formed on the second interlayer insulating layer IL2 in its entirety. The third interlayer insulating layer IL3 can include the same substance as the buffer layer BFL, or can include one or more substances suitable (or selected) for the constituent substance of the buffer layer BFL mentioned (or exemplified).

[0096] The via layer VIA can be disposed and / or formed on the third interlayer insulating layer IL3 in its entirety. The via layer VIA can be an inorganic insulating film including an inorganic substance or an organic insulating film including an organic substance (or material). The inorganic insulating film can include, for example, at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). The organic insulating film can include, for example, at least one of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In an embodiment, the via layer VIA can be an organic insulating film including an organic substance.

[0097] The via layer VIA can be locally perforated in a manner including a via hole. The via hole can be a connection point for electrically connecting the pixel circuit PXC of each sub-pixel SP to the light emitting element LD.

[0098] A circuit element (or a drive element) of the sub-pixel SP can be disposed in the pixel circuit layer PCL. As an example, a transistor T of the sub-pixel SP can be disposed in the pixel circuit layer PCL. In Figure 7 , one of the transistors T of each sub-pixel SP is shown for convenience of explanation, and the remaining circuit elements are omitted.

[0099] The transistor T of the sub-pixel SP can include a lower metal pattern BML, a semiconductor pattern SCP, a gate electrode GE, a first terminal EL1, and / or a second terminal EL2.

[0100] The lower metal pattern BML can be disposed between the buffer layer BFL and the first interlayer insulating layer IL1. The lower metal pattern BML can be formed using a first conductive layer. The lower metal pattern BML can be electrically connected with the first terminal EL1.

[0101] The semiconductor pattern SCP can be disposed between the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The semiconductor pattern SCP can be a semiconductor layer composed of polysilicon, amorphous silicon, oxide semiconductor, or the like. The semiconductor pattern SCP can include an active pattern, a first contact region, and a second contact region. The active pattern, the first contact region, and the second contact region can be composed of a semiconductor layer which is not doped with impurities or is doped with impurities. As an example, the first contact region and the second contact region can be composed of a semiconductor layer which is doped with impurities, and the active pattern can be composed of a semiconductor layer which is not doped with impurities.

[0102] The active pattern of the semiconductor pattern SCP, as a region overlapping the gate electrode GE, can be a channel region. The first contact region of the semiconductor pattern SCP can be in contact with one end of the active pattern. The first contact region can be electrically connected with the first terminal EL1. The second contact region of the semiconductor pattern SCP can be in contact with the other end of the active pattern. The second contact region can be electrically connected with the second terminal EL2.

[0103] The gate electrode GE can be disposed between the second interlayer insulating layer IL2 and the third interlayer insulating layer IL3. The gate electrode GE can be formed using a second conductive layer. The gate electrode GE can overlap a part of the semiconductor pattern SCP. As an example, the gate electrode GE can overlap the active pattern of the semiconductor pattern SCP.

[0104] The first terminal EL1 can be disposed between the third interlayer insulating layer IL3 and the via layer VIA. The first terminal EL1 can be formed using a third conductive layer. The first terminal EL1 can be in contact with the first contact region of the semiconductor pattern SCP through a contact hole penetrating the third interlayer insulating layer IL3.

[0105] The second terminal EL2 can be disposed between the third interlayer insulating layer IL3 and the via layer VIA. The second terminal EL2 can be formed using a third conductive layer. The second terminal EL2 can be in contact with the second contact region of the semiconductor pattern SCP through a contact hole penetrating the third interlayer insulating layer IL3.

[0106] A light emitting element layer LDL may be disposed on the pixel circuit layer PCL and may include a first lower electrode AE1, a second lower electrode AE2, a third lower electrode AE3, a pixel defining layer PDL, a light emitting layer EML, and / or an upper electrode CE.

[0107] On the pixel circuit layer PCL (or via layer VIA), a first lower electrode AE1, a second lower electrode AE2, and a third lower electrode AE3 may be arranged in the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, respectively. As an example, the first lower electrode AE1 may be arranged on the via layer VIA of the first subpixel SP1, the second lower electrode AE2 may be arranged on the via layer VIA of the second subpixel SP2, and the third lower electrode AE3 may be arranged on the via layer VIA of the third subpixel SP3.

[0108] Each of the first to third lower electrodes AE1 to AE3 may be electrically connected to a circuit element disposed in the pixel circuit layer PCL via a through-hole extending through the via layer VIA. As an example, the first lower electrode AE1 may be electrically connected to the transistor T of the first sub-pixel SP1 via a first through-hole extending through the via layer VIA, the second lower electrode AE2 may be electrically connected to the transistor T of the second sub-pixel SP2 via a second through-hole extending through the via layer VIA, and the third lower electrode AE3 may be electrically connected to the transistor T of the third sub-pixel SP3 via a third through-hole extending through the via layer VIA.

[0109] In an embodiment, the first to third lower electrodes AE1 to AE3 may be anode electrodes. Each of the first to third lower electrodes AE1 to AE3 may have a plane with the same Figure 6 The first lower electrode AE1 may have a shape similar to the first light emitting area EMA1 to the third light emitting area EMA3. As an example, the first lower electrode AE1 may have a shape similar to the first light emitting area EMA1 in a plan view, and the second lower electrode AE2 may have a shape similar to the second light emitting area EMA2 in a plan view. The third lower electrode AE3 may have a shape similar to the third light emitting area EMA3 in a plan view, but is not limited thereto.

[0110] Each of the first to third lower electrodes AE1 to AE3 can be electrically connected to a corresponding pixel circuit to receive a driving current. The first to third lower electrodes AE1 to AE3 can include, but are not limited to, an opaque conductive material capable of reflecting light. Depending on the embodiment, the first to third lower electrodes AE1 to AE3 can also include a transparent conductive material.

[0111] A pixel definition film PDL can be disposed on the first to third lower electrodes AE1 to AE3. The pixel definition film PDL can include an opening portion that at least partially exposes each of the first to third lower electrodes AE1 to AE3. The pixel definition film PDL can be a structure that defines (or, divides) a light emitting area of each of the first to third sub-pixels SP1 to SP3. As an example, the pixel definition film PDL can define a first light emitting area EMA1 of the first sub-pixel SP1, a second light emitting area EMA2 of the second sub-pixel SP2, and a third light emitting area EMA3 of the third sub-pixel SP3.

[0112] The pixel definition film PDL can be configured with an organic insulating film including an organic substance. As the organic material, an acrylate resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like can be included. According to an embodiment, the pixel definition film PDL can include a light absorbing substance or be coated with a light absorbing agent, thereby functioning to absorb light incident from the outside. For example, the pixel definition film PDL can include a carbon-based black pigment, but is not necessarily limited thereto.

[0113] A light emitting layer EML can be disposed on the first to third lower electrodes AE1 to AE3. The light emitting layer EML can be disposed on the first to third lower electrodes AE1 to AE3 exposed through the opening portion of the pixel definition film PDL. The light emitting layer EML can include a light emitting portion configured to generate light, an electron transport portion configured to transport electrons, and a hole transport portion configured to transport holes, but is not limited thereto. The light emitting layer EML can be formed by a process such as vacuum deposition or inkjet printing, but is not necessarily limited thereto.

[0114] An upper electrode CE can be disposed on the light emitting layer EML. In an embodiment, the upper electrode CE can be a cathode electrode. The upper electrode CE can be a common layer commonly provided to the first to third sub-pixels SP1 to SP3. The upper electrode CE can be disposed in a plate form across the entire area of the display area DA. The upper electrode CE can function as a half mirror that partially transmits and partially reflects light emitted from the light emitting layer EML.

[0115] The upper electrode CE can be a thin metal layer having a thickness to a degree that light emitted from the light emitting layer EML is transmitted. The upper electrode CE can be formed to have a relatively thin thickness using a metal material or a transparent conductive material. In an embodiment, the upper electrode CE can include at least one of a plurality of transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In another embodiment, the upper electrode CE can include at least one of magnesium, silver, and a mixture thereof. However, the material forming the upper electrode CE is not limited to the above-described embodiment.

[0116] The first lower electrode AE1, a portion of the light emitting layer EML overlapping the first lower electrode AE1, and a portion of the upper electrode CE overlapping the first lower electrode AE1 can constitute the first light emitting element LD1. The second lower electrode AE2, a portion of the light emitting layer EML overlapping the second lower electrode AE2, and a portion of the upper electrode CE overlapping the second lower electrode AE2 can constitute the second light emitting element LD2. The third lower electrode AE3, a portion of the light emitting layer EML overlapping the third lower electrode AE3, and a portion of the upper electrode CE overlapping the third lower electrode AE3 can constitute the third light emitting element LD3.

[0117] An encapsulation layer TFE can be disposed on the light emitting element layer LDL. The encapsulation layer TFE can cover the light emitting element layer LDL. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture and the like from permeating into the light emitting element layer LDL. The encapsulation layer TFE can include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3.

[0118] The first encapsulation layer TFE1 can be disposed on the upper electrode CE. The second encapsulation layer TFE2 can be disposed on the first encapsulation layer TFE1. The third encapsulation layer TFE3 can be disposed on the second encapsulation layer TFE2. The first encapsulation layer TFE1 can include an inorganic film. For example, the first encapsulation layer TFE1 can include silicon nitride, silicon oxide, or silicon oxynitride, or the like. The second encapsulation layer TFE2 can include an organic film. For example, the second encapsulation layer TFE2 can include an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, or a benzocyclobutene resin, or the like. The third encapsulation layer TFE3 can include silicon nitride, silicon oxide, or silicon oxynitride, or the like. However, the material forming the first encapsulation layer TFE1 to the third encapsulation layer TFE3 is not necessarily limited thereto.

[0119] An optical layer OPL can be disposed on the encapsulation layer TFE. The optical layer OPL can include a bank BNK, a first color conversion pattern CCP1, a second color conversion pattern CCP2, a light scattering pattern LSP, a cover layer CPL, and / or a protective layer PSV.

[0120] The bank BNK can be disposed in the non-emitting area NEA on the encapsulation layer TFE. The bank BNK can be directly disposed on the encapsulation layer TFE. The bank BNK can include at least one light-blocking substance. Accordingly, the bank BNK can prevent light leakage between adjacent sub-pixels SP. According to an embodiment, the bank BNK can include at least one reflective substance. Accordingly, the bank BNK can induce light emitted from each of the first color conversion pattern CCP1, the second color conversion pattern CCP2, and the light scattering pattern LSP to an image display direction of the display device DD, thereby improving light extraction efficiency of the sub-pixel SP. According to an embodiment, in order to further improve the efficiency of light emitted from each sub-pixel SP, a reflective substance layer can be separately provided and / or formed on the bank BNK. According to an embodiment, the bank BNK can include a transparent substance (or material). As an example, the bank BNK can include a polyamide-based resin, a polyimide-based resin, or the like, but is not limited thereto.

[0121] The bank BNK can include an opening portion overlapping the first to third sub-pixels SP1 to SP3. The opening portion of the bank BNK can overlap the first to third emitting areas EMA1 to EMA3, respectively.

[0122] The first color conversion pattern CCP1 can be disposed in the opening portion of the bank BNK of the first sub-pixel SP1. The first color conversion pattern CCP1 can be directly disposed on the encapsulation layer TFE. The first color conversion pattern CCP1 can overlap the first light emitting element LD1 in the third direction DR3. The first color conversion pattern CCP1 can include a plurality of first color conversion particles QD1 dispersed in a predetermined matrix material such as a base resin or the like. For example, the first color conversion particles QD1 can be red quantum dots that absorb incident blue light and emit red light according to energy transfer by wavelength shift. In this case, the first sub-pixel SP1 can be a red sub-pixel. The first color conversion pattern CCP1 can be disposed at least in the first emitting area EMA1.

[0123] The second light conversion pattern CCP2 can be arranged in the opening portion of the bank BNK of the second sub-pixel SP2. The second light conversion pattern CCP2 can be arranged directly on the encapsulation layer TFE. The second light conversion pattern CCP2 can overlap the second light emitting element LD2 in the third direction DR3. The second light conversion pattern CCP2 can include a plurality of second light conversion particles QD2 dispersed in a predetermined matrix material such as a base resin. For example, the second light conversion particles QD2 can be green quantum dots that absorb incident blue light and emit green light by energy transfer. In this case, the second sub-pixel SP2 can be a green sub-pixel. The second light conversion pattern CCP2 can be arranged at least in the second light emitting area EMA2.

[0124] The light scattering pattern LSP can be arranged in the opening portion of the bank BNK of the third sub-pixel SP3. The light scattering pattern LSP can be arranged directly on the encapsulation layer TFE. The light scattering pattern LSP can overlap the third light emitting element LD3 in the third direction DR3. The light scattering pattern LSP can include a plurality of light scattering particles SCT dispersed in a predetermined matrix material such as a base resin. The light scattering pattern LSP can include light scattering particles SCT such as silicon dioxide, but the constituent material of the light scattering particles SCT is not limited thereto. According to an embodiment, a light scattering pattern LSP configured with a transparent polymer can also be provided without the light scattering particles SCT. For example, the light scattering pattern LSP can transmit incident blue light toward the image display direction. In this case, the third sub-pixel SP3 can be a blue sub-pixel. The light scattering pattern LSP can be arranged at least in the third light emitting area EMA3.

[0125] The covering layer CPL can be arranged on the bank BNK, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and / or the light scattering pattern LSP. The covering layer CPL can be configured with an inorganic film (or an inorganic insulating film) including an inorganic substance. For example, the covering layer CPL can include at least one of metal oxides such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ), but is not limited thereto. According to an embodiment, the covering layer CPL can also be configured with an organic insulating film including an organic substance. The covering layer CPL can be positioned on the first light conversion pattern CCP1, the second light conversion pattern CCP2, and / or the light scattering pattern LSP to protect the first light conversion pattern CCP1, the second light conversion pattern CCP2, and / or the light scattering pattern LSP from external moisture, oxygen, and the like, thereby improving reliability.

[0126] A protective layer PSV can be disposed on the cover layer CPL. The protective layer PSV can planarize the step difference of the bank BNK, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and / or the light scattering pattern LSP. According to an embodiment, the protective layer PSV can include a resin and hollow particles dispersed inside the resin. The protective layer PSV can have a refractive index in the range of 1.1 to 1.3, but is not limited thereto. The hollow particles can mean particles in a form in which a hollow space exists on the surface and / or inside of an organic particle or an inorganic particle. The hollow particles can be hollow silica particles. The protective layer PSV can improve the front light emission brightness by changing the path of light among the light emitted from the optical layer OPL to the image display direction by using the refractive index difference. The protective layer PSV can improve the light emission brightness of the sub-pixel SP by repeatedly circulating the light (as an example, blue light) that is not reacted with the first light conversion pattern CCP1 and / or the second light conversion pattern CCP2 to be converted by being reacted with the first light conversion pattern CCP1 and / or the second light conversion pattern CCP2.

[0127] A color filter layer CFL can be disposed on the optical layer OPL. The color filter layer CFL can include a first color filter CF1, a second color filter CF2, a third color filter CF3, and / or a light blocking pattern LBP. As an example, the first color filter CF1 can be a red color filter, the second color filter CF2 can be a green color filter, and the third color filter CF3 can be a blue color filter, but is not limited thereto.

[0128] The first color filter CF1 can overlap the first light emission area EMA1 of the first sub-pixel SP1 in the third direction DR3. The second color filter CF2 can overlap the second light emission area EMA2 of the second sub-pixel SP2 in the third direction DR3. The third color filter CF3 can overlap the third light emission area EMA3 of the third sub-pixel SP3 in the third direction DR3.

[0129] The first color filter CF1 to the third color filter CF3 can be disposed to overlap each other in the non-emission area NEA, and thus can be used as the light blocking pattern LBP that blocks the light interference between the adjacent sub-pixels SP.

[0130] An overcoat layer OC can be disposed on the color filter layer CFL. The overcoat layer OC can cover the color filter layer CFL, the optical layer OPL, the encapsulation layer TFE, the light emitting element layer LDL, and / or the pixel circuit layer PCL. The overcoat layer OC can include various substances suitable for protecting the lower layers thereunder from foreign substances such as dust, moisture, etc. For example, the overcoat layer OC can include at least one of an inorganic insulating film and an organic insulating film. For example, the overcoat layer OC can include an epoxy resin, but is not necessarily limited thereto.

[0131] Figure 8is a cross-sectional view schematically showing a non-display area of a display module according to an embodiment.

[0132] In Figure 8 , for convenience of explanation, a cross-sectional structure (or, a stack structure) is briefly shown with the non-display area NDA as a center, and a thickness direction of the substrate SUB is indicated as a third direction DR3.

[0133] The substrate SUB can include a first surface S1, a second surface S2, and a side surface S3. The pixel circuit layer PCL, the light emitting element layer LDL, the encapsulation layer TFE, the optical layer OPL, and / or the color filter layer CFL, and the like described above can be formed on the first surface S1 of the substrate SUB. The second surface S2 of the substrate SUB can face the first surface S1. The side surface S3 of the substrate SUB can be disposed between the first surface S1 and the second surface S2. The side surface S3 of the substrate SUB can correspond to an outer side edge of the substrate SUB. The side surface S3 of the substrate SUB can have a slope. In an embodiment, an inclination angle formed by the side surface S3 of the substrate SUB and the second surface S2 can be 70° to 80°, but is not necessarily limited thereto. The side surface S3 of the substrate SUB can correspond to a side surface of the trench TR formed in the substrate SUB. Figure 9 As described above, in a case where the trench TR is formed in the substrate SUB, the impact strength of the substrate SUB can be improved by minimizing the contact time with the etching solution in the process of etching the substrate SUB. Detailed descriptions thereof will be described later with reference to Figure 9 , and the like.

[0134] The pixel circuit layer PCL can be disposed on the first surface S1 and the side surface S3 of the substrate SUB. For example, the insulating layer of the pixel circuit layer PCL can be disposed on the first surface S1 of the substrate SUB in its entirety and cover the side surface S3 of the substrate SUB. As an example, the buffer layer BFL, the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and / or the third interlayer insulating layer IL3 can be disposed on the side surface S3 of the substrate SUB. The buffer layer BFL, the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and / or the third interlayer insulating layer IL3 can have a slope on the side surface S3 of the substrate SUB.

[0135] The encapsulation layer TFE can be disposed on the first surface S1 and the side surface S3 of the substrate SUB. For example, the third encapsulation layer TFE3 can be disposed on the first surface S1 of the substrate SUB entirely and cover the side surface S3 of the substrate SUB. As an example, the third encapsulation layer TFE3 can be disposed on the side surface S3 of the substrate SUB. The third encapsulation layer TFE3 can have a slope on the side surface S3 of the substrate SUB. According to an embodiment, the first encapsulation layer TFE1 and / or the cover layer CPL can also be disposed on the side surface S3 of the substrate SUB, in which case the first encapsulation layer TFE1 and / or the cover layer CPL can have a slope on the side surface S3 of the substrate SUB.

[0136] A power wiring PL can be disposed in the non-display area NDA. The power wiring PL can be electrically connected with the upper electrode CE. The power wiring PL can be disposed on the third interlayer insulation layer IL3. The power wiring PL can be formed using the third conductive layer. The power wiring PL can be disposed on the same layer as the first terminal EL1 and / or the second terminal EL2. The power wiring PL can include the same substance as the first terminal EL1 and / or the second terminal EL2. The power wiring PL can be formed simultaneously with the first terminal EL1 and / or the second terminal EL2 in the same process, but is not necessarily limited thereto. The power wiring PL can correspond to the fourth power wiring PL4 described with reference to FIG. 1. Figure 5

[0137] The first dam member DM1, the second dam member DM2, the third dam member DM3, and the fourth dam member DM4 can also be disposed in the non-display area NDA. The first dam member DM1 to the fourth dam member DM4 can be disposed outside with respect to the power wiring PL. As an example, the power wiring PL can be disposed between the first dam member DM1 to the fourth dam member DM4 and the display area DA.

[0138] The first dam member DM1 can at least partially overlap the power wiring PL in the third direction DR3. The first dam member DM1 can include a lower dam pattern disposed on the third interlayer insulation layer IL3 and an upper dam pattern disposed on the lower dam pattern.

[0139] The second dam member DM2 can be disposed outside of the first dam member DM1. The second dam member DM2 can be spaced apart from the first dam member DM1. The second dam member DM2 can include a lower dam pattern disposed on the third interlayer insulation layer IL3 and an upper dam pattern disposed on the lower dam pattern.

[0140] The third dam member DM3 can be disposed outside of the second dam member DM2. The third dam member DM3 can be spaced apart from the second dam member DM2. The third dam member DM3 can include a lower dam pattern disposed on the third interlayer insulation layer IL3 and an upper dam pattern disposed on the lower dam pattern.​

[0141] The fourth dam part DM4 can be disposed outside the third dam part DM3. The fourth dam part DM4 can be spaced apart from the third dam part DM3. The fourth dam part DM4 can be disposed on the third interlayer insulation layer IL3.

[0142] The lower dam patterns of the first to third dam parts DM1, DM2, DM3 and the fourth dam part DM4 can be disposed on the same layer as the via layer VIA. The lower dam patterns of the first to third dam parts DM1, DM2, DM3 and the fourth dam part DM4 can include the same material as the via layer VIA. The lower dam patterns of the first to third dam parts DM1, DM2, DM3 and the fourth dam part DM4 can be formed simultaneously in the same process as the via layer VIA, but are not necessarily limited thereto.

[0143] In an embodiment, the heights of the first to fourth dam parts DM1, DM2, DM3, DM4 can be different from each other. For example, the height of the second dam part DM2 in the third direction DR3 can be higher than the height of the first dam part DM1 in the third direction DR3. The height of the third dam part DM3 in the third direction DR3 can be higher than the height of the second dam part DM2 in the third direction DR3. Accordingly, overflow of organic material can be effectively prevented in forming the encapsulation layer TFE, particularly the second encapsulation layer TFE2. The height of the fourth dam part DM4 in the third direction DR3 can be lower than the height of the first dam part DM1 in the third direction DR3.

[0144] The first and second pad electrodes PD1, PD2 can also be disposed in the non-display area NDA. Figure 4 The first and second pad electrodes PD1, PD2 can be disposed outside the dam parts DM1, DM2, DM3, DM4. The first pad electrode PD1 can be disposed on the third interlayer insulation layer IL3. The first pad electrode PD1 can be formed using the third conductive layer. The first pad electrode PD1 can be disposed on the same layer as the first terminal EL1 and / or the second terminal EL2. The first pad electrode PD1 can include the same material as the first terminal EL1 and / or the second terminal EL2. The first pad electrode PD1 can be formed simultaneously in the same process as the first terminal EL1 and / or the second terminal EL2, but is not necessarily limited thereto. The first pad electrode PD1 can be electrically connected to the wiring layer WL through a contact hole penetrating the third interlayer insulation layer IL3.

[0145] The wiring layer WL can be disposed between the second interlayer insulating layer IL2 and the third interlayer insulating layer IL3. The wiring layer WL can be formed using a second conductive layer. The wiring layer WL can be disposed in the same layer as the gate electrode GE. The wiring layer WL can include the same substance as the gate electrode GE. The wiring layer WL can be formed simultaneously with the gate electrode GE in the same process, but is not necessarily limited thereto.

[0146] The second pad electrode PD2 can be disposed on the first pad electrode PD1. The second pad electrode PD2 can overlap the first pad electrode PD1 in the third direction DR3. The second pad electrode PD2 can be electrically connected to the first pad electrode PD1. The second pad electrode PD2 can be disposed directly on the first pad electrode PD1 to contact the first pad electrode PD1.

[0147] The bank BNK and / or the color filter layer CFL can also be disposed in the non-display area NDA. For example, the bank BNK can at least partially overlap the first dam member DM1 and / or the second dam member DM2 in the third direction DR3. The color filter layer CFL, as an example, the third color filter CF3 can at least partially overlap the bank BNK in the non-display area NDA in the third direction DR3.

[0148] Next, a manufacturing method of a display device according to the above-described embodiment is described.

[0149] Figures 9 to 12 is a cross-sectional view of a manufacturing method of a display device according to the embodiment, per process step. Figures 9 to 12 As a cross-sectional view for explaining Figures 1 to 8 a manufacturing method of a display device, for ease of explanation, detailed reference numerals are briefly shown and omitted.

[0150] Referring to Figure 9 , first, a trench TR is formed on the first surface S1 of the substrate SUB. The trench TR can have a shape recessed from the first surface S1 of the substrate SUB. The trench TR can function to form a pre-segmentation to minimize the contact time with an etching solution in the process of etching the substrate SUB. Thereby, the substrate SUB can be easily cut off while minimizing the reduction in impact strength of the substrate SUB.

[0151] The side surface S3 of the trench TR can have a slope. The slope angle formed by the side surface S3 of the trench TR and the second surface S2 can be 70° to 80°, but is not necessarily limited thereto. The width WT of the trench TR in the first direction DR1 can be 8 μm to 12 μm, but is not necessarily limited thereto. The depth DT of the trench TR in the third direction DR3 can be 80 μm to 100 μm, but is not necessarily limited thereto.

[0152] Referring to Figure 10Next, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical layer OPL, a color filter layer CFL, and / or an overcoat layer OC are formed on the first surface S1 of the substrate SUB.

[0153] The pixel circuit layer PCL can be formed on the trench TR. As an example, the buffer layer BFL, the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and / or the third interlayer insulating layer IL3 can be formed on the trench TR. The buffer layer BFL, the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and / or the third interlayer insulating layer IL3 can have a slope on the side surface S3 of the trench TR.

[0154] The encapsulation layer TFE can be formed on the trench TR. As an example, the third encapsulation layer TFE3 can be formed on the trench TR. The third encapsulation layer TFE3 can have a slope on the side surface S3 of the trench TR. According to an embodiment, the first encapsulation layer TFE1 and / or the cover layer CPL can also be formed on the trench TR, in which case the first encapsulation layer TFE1 and / or the cover layer CPL can have a slope on the side surface S3 of the trench TR.

[0155] Referring to Figure 11 Next, a scribe line CL is formed on the lower surface of the trench TR. The scribe line CL can be formed locally in the substrate SUB, but is not necessarily limited thereto. The depth DC in the third direction DR3 of the scribe line CL can be 16 to 20 μm, but is not necessarily limited thereto.

[0156] Referring to Figure 12 Next, the second surface S2 of the substrate SUB is etched. The thickness of the substrate SUB in the third direction DR3 can be formed to be thin by etching the second surface S2 of the substrate SUB. The thickness of the substrate SUB in the third direction DR3 can be formed to be 80 to 100 μm, but is not necessarily limited thereto.

[0157] In the step of etching the second surface S2 of the substrate SUB, the substrate SUB can be cut while being etched along the scribe line CL. Thereby, as shown in Figure 8 the side surface S3 of the trench TR can be formed as a side surface of the substrate SUB.

[0158] According to the above-described method, when the trench TR is formed in the substrate SUB and the scribe line CL is formed, and then the substrate SUB is etched to be cut, since the contact time with the etching solution can be minimized during the etching of the substrate SUB, the impact strength of the substrate SUB can be improved.

[0159] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to an embodiment includes the display device described above, and can further include a module or a device having other additional functions besides the display device.

[0160] Figure 13 is a block diagram of an electronic device according to an embodiment. Referring to Figure 13 The electronic device 10 according to an embodiment can include a display module 11, a processor 12, a memory 13, and a power module 14.

[0161] The processor 12 can include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), or a controller.

[0162] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. If the processor 12 executes an application stored in the memory 13, an image data signal and / or an input control signal are delivered to the display module 11, and the display module 11 can process the received signal and output image information through a display screen.

[0163] The power module 14 can include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device 10.

[0164] At least one of the respective components of the electronic device 10 described above can be included in the display device according to the above-described embodiments. Also, a part of the individual modules functionally included in one module can be included in the display device, and the other part can be provided independently of the display device. For example, the display device includes the display module 11, and the processor 12, the memory 13, and the power module 14 can be provided in the form of other devices within the electronic device 10 other than the display device.

[0165] Figure 14 is a schematic view showing an electronic device according to various embodiments.

[0166] Referring to Figure 14Various electronic devices to which the display device according to the embodiment is applied can not only include electronic devices for displaying images of a smart phone 10_1a, a tablet personal computer (PC) 10_1b, a notebook computer 10_1c, a television (TV) 10_1d, a desktop computer 10_1e, and the like, but also include wearable electronic devices including display modules such as smart glasses 10_2a, a head-mounted display 10_2b, a smart watch 10_2c, and the like, vehicle electronic devices including display modules such as an instrument panel of a car, a center instrument panel, a center information display (CID) disposed on the instrument panel, and a car-mounted room mirror display, and the like.

[0167] Although specific embodiments have been described herein, other embodiments and variations can be derived from the above description without departing from the scope of the invention. Therefore, the concept of the present invention is not limited to these embodiments, but relates to the scope recited in the claims, various obvious modifications, and equivalents.

Claims

1. A display device comprising: a substrate including a first surface, a second surface, and a side surface between the first surface and the second surface; a pixel circuit layer disposed on the first surface of the substrate and including a transistor including a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer; and a light emitting element disposed on the pixel circuit layer and electrically connected to the transistor, wherein the side surface of the substrate has a slope, the insulating layer is disposed on the side surface of the substrate.

2. The display device according to claim 1, wherein the insulating layer has a slope on the side surface of the substrate.

3. The display device according to claim 1, further comprising: an encapsulation layer disposed on the light emitting element, the encapsulation layer is disposed on the side surface of the substrate.

4. The display device according to claim 3, wherein the encapsulation layer has a slope on the side surface of the substrate.

5. The display device according to claim 3, further comprising: a bank disposed on the encapsulation layer.

6. The display device according to claim 5, further comprising: a light conversion pattern disposed in an opening portion of the bank.

7. The display device according to claim 6, wherein the light conversion pattern is directly disposed on the encapsulation layer.

8. The display device according to claim 6, further comprising: a color filter disposed on the light conversion pattern.

9. The display device according to claim 1, further comprising: a rotating member that winds and unwinds the substrate.

10. The display device according to claim 9, further comprising: a housing that accommodates the substrate and the rotating member.

11. A manufacturing method of a display device, comprising the steps of: forming a trench on a first surface of a substrate; forming a pixel circuit layer on the trench; forming a light emitting element on the pixel circuit layer; forming a scribe line on a lower surface of the trench; and etching a second surface of the substrate to form a thickness of the substrate to be thinner.

12. The manufacturing method of a display device according to claim 11, wherein the pixel circuit layer has a slope on a side surface of the trench.

13. The manufacturing method of a display device according to claim 11, further comprising the step of: forming an encapsulation layer on the light emitting element, the encapsulation layer is formed on the trench.

14. The manufacturing method of a display device according to claim 13, wherein the encapsulation layer has a slope on a side surface of the trench.

15. The manufacturing method of a display device according to claim 13, further comprising the step of: forming a light conversion pattern on the encapsulation layer.

16. The manufacturing method of a display device according to claim 15, further comprising the step of: forming a color filter on the light conversion pattern.

17. The manufacturing method of a display device according to claim 11, wherein a depth of the trench is 80 μm to 100 μm.

18. The manufacturing method of a display device according to claim 11, wherein a depth of the scribe line is 16 μm to 20 μm. ​ ​ 19. The method for manufacturing a display device according to claim 11, wherein In the step of etching the second surface of the substrate, the substrate is cut along the cutting line.

20. An electronic device comprising: a processor; and a display device including a pixel and configured to display an image at the pixel in accordance with control by the processor, wherein the display device is the display device according to any one of claims 1 to 10. ​

Images