Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes: a substrate including a display area and a peripheral area surrounding a part of the display area; a gate driver disposed in the display area on the substrate, including a driver transistor, and generating a first gate signal; first pixel members disposed on the gate driver, each including a first pixel transistor, and overlapping the gate driver in a plan view; a connection portion disposed on the substrate in a peripheral region adjacent to the gate driver and including a first conductive pattern and a second conductive pattern disposed on the first conductive pattern and connected to the first conductive pattern through the contact hole; a connection line extending from the first conductive pattern and connected to the gate driver; and a gate signal line disposed on the connection line, extending from the second conductive pattern, and connected to each of the first pixel members.

Description

TECHNICAL FIELD

[0001] Embodiments generally provide a display device. Embodiments relate to a display device that provides visual information. BACKGROUND

[0002] With the development of information technology, the importance of a display device as a communication medium between a user and information is being highlighted. Accordingly, the use of display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, etc. is increasing.

[0003] Generally, a display device can include a display area that displays an image, and a peripheral area that sets a gate driver, a data driver, etc. and surrounds the display area. The larger the area occupied by the gate driver in the peripheral area, the larger the dead space of the display device can be.

[0004] It will be appreciated that this Background section is intended to provide a useful background for understanding the technology. However, this Background section can also include ideas, concepts or recognitions not yet known or appreciated by persons of ordinary skill in the pertinent art as of the corresponding effective filing date of the subject matter disclosed herein. SUMMARY

[0005] Embodiments provide a display device having a reduced dead space.

[0006] A display device according to an embodiment can include a substrate including a display area and a peripheral area surrounding at least a portion of the display area; a gate driver disposed in the display area on the substrate, the gate driver including a driver transistor and generating a first gate signal; a plurality of first pixel components disposed on the gate driver, each of the plurality of first pixel components including a first pixel transistor and at least partially overlapping the gate driver in a plan view; a connection portion disposed in the peripheral area adjacent to the gate driver on the substrate, the connection portion including a first conductive pattern and a second conductive pattern disposed on the first conductive pattern and electrically connected to the first conductive pattern through a contact hole; a connection line extending from the first conductive pattern and electrically connected to the gate driver; and a gate signal line disposed on the connection line, extending from the second conductive pattern, and electrically connected to each of the plurality of first pixel components.

[0007] In an embodiment, the gate driver can overlap at least one of a left edge of the display area and a right edge of the display area.

[0008] In an embodiment, the display device can further include a shielding pattern disposed between the gate driver and the plurality of first pixel components and at least partially overlapping the driver transistor in a plan view.

[0009] In an embodiment, the display device can further include a plurality of second pixel components disposed in the display area on the gate driver, each of the plurality of second pixel components including a second pixel transistor, and not overlapping the gate driver in a plan view.

[0010] In an embodiment, the first pixel transistor can include a first pixel active layer disposed on the gate driver, and a pixel gate electrode disposed on the first pixel active layer and partially overlapping a channel region of the first pixel active layer in a plan view. Each of the plurality of first pixel components can further include a first electrode disposed on the first pixel active layer and electrically connected to a first doped region of the first pixel active layer through a first contact hole, and a second electrode disposed on the first pixel active layer and electrically connected to a second doped region of the first pixel active layer through a second contact hole.

[0011] In an embodiment, a size of the contact hole can be different from a size of each of the first contact hole and the second contact hole.

[0012] In an embodiment, a size of the contact hole can be greater than a size of each of the first contact hole and the second contact hole.

[0013] In an embodiment, the first pixel active layer can include a metal oxide semiconductor.

[0014] In an embodiment, the driver transistor can include a driver active layer disposed on the substrate, and a driver gate electrode disposed on the driver active layer and overlapping a channel region of the driver active layer.

[0015] In an embodiment, the driver active layer can include a silicon semiconductor.

[0016] In an embodiment, the gate driver can further include a lower metal layer disposed between the substrate and the driver active layer and electrically connected to the driver active layer, and a connection pattern disposed in the same layer as the driver gate electrode and electrically connected to the lower metal layer.

[0017] In an embodiment, the first conductive pattern and the driver gate electrode can be disposed in the same layer, and the second conductive pattern and the first electrode and the second electrode can be disposed in the same layer.

[0018] In an embodiment, the first conductive pattern and the lower metal layer can be disposed in the same layer, and the second conductive pattern and the first electrode and the second electrode can be disposed in the same layer.

[0019] In an embodiment, the first conductive pattern and the driver gate electrode can be disposed in the same layer, and the second conductive pattern and the pixel gate electrode can be disposed in the same layer.

[0020] In an embodiment, the first conductive pattern and the lower metal layer can be disposed in the same layer, and the second conductive pattern and the pixel gate electrode can be disposed in the same layer.

[0021] In an embodiment, the first conductive pattern can include a first-first conductive pattern disposed in the same layer as the lower metal layer, and a first-second conductive pattern disposed in the same layer as the driver gate electrode. The connection line can include a first-first connection line extending from the first-first conductive pattern and a first-second connection line extending from the first-second conductive pattern. The second conductive pattern and the first and second electrodes can be disposed in the same layer.

[0022] In an embodiment, the display device can further include at least one dummy gate driver disposed in the display area on the substrate, including a dummy transistor, and spaced apart from the gate driver, and a plurality of second pixel components disposed in the display area on the dummy gate driver, each of the plurality of second pixel components including a second pixel transistor.

[0023] In an embodiment, the display device can further include at least one additional gate driver disposed in the display area on the substrate and generating a second gate signal, and a plurality of second pixel components disposed in the display area on the additional gate driver, each of the plurality of second pixel components including a second pixel transistor. The additional gate driver can be electrically connected to at least one of the plurality of first pixel components and the plurality of second pixel components.

[0024] A display device according to an embodiment can include a substrate including a display area and a peripheral area surrounding at least a portion of the display area, a gate driver disposed in the display area on the substrate, generating a first gate signal, the gate driver including a plurality of gate stages, each of the plurality of gate stages including a driver transistor, a plurality of first pixel components disposed on the gate driver, each of the plurality of first pixel components including a first pixel transistor, and at least partially overlapping the plurality of gate stages in a plan view, a connection portion disposed in the peripheral area adjacent to the gate driver on the substrate, the connection portion including a plurality of sub-connection portions each including a first conductive pattern and a second conductive pattern disposed on the first conductive pattern and electrically connected to the first conductive pattern through a contact hole, a connection line each extending from the first conductive pattern of a corresponding one of the plurality of sub-connection portions, and each electrically connected to a corresponding one of the gate stages, and a gate signal line disposed on the connection line, each extending from the second conductive pattern of a corresponding one of the plurality of sub-connection portions, and each electrically connected to a corresponding one of the first pixel components.

[0025] In an embodiment, the display device can further include a shielding pattern disposed between the gate driver and the plurality of first pixel components, and at least partially overlapping the driver transistor in a plan view.

[0026] In an embodiment, the display device can further include a plurality of second pixel components disposed in the display area on the gate driver, each of the plurality of second pixel components including a second pixel transistor, and not overlapping the gate driver in a plan view.

[0027] In an embodiment, the first pixel transistor can include a first pixel active layer disposed on the gate driver, and a pixel gate electrode disposed on the first pixel active layer and partially overlapping a channel region of the first pixel active layer in a plan view. Each of the plurality of first pixel components can further include a first electrode disposed on the first pixel active layer and electrically connected to a first doped region of the first pixel active layer through a first contact hole, and a second electrode disposed on the first pixel active layer and electrically connected to a second doped region of the first pixel active layer through a second contact hole.

[0028] In an embodiment, a size of the contact hole can be greater than a size of each of the first and second contact holes.

[0029] In an embodiment, the driver transistor can include a driver active layer disposed on the substrate, and a driver gate electrode disposed on the driver active layer and overlapping a channel region of the driver active layer.

[0030] In an embodiment, the gate driver can further include a lower metal layer disposed between the substrate and the driver active layer and electrically connected to the driver active layer, and a connection pattern disposed in the same layer as the driver gate electrode and electrically connected to the lower metal layer.

[0031] In an embodiment, one of the first conductive pattern and the lower metal layer and the driver gate electrode can be disposed in the same layer, and one of the first electrode and the pixel gate electrode can be disposed in the same layer as the second conductive pattern.

[0032] In an embodiment, the display device can further include at least one dummy gate driver disposed in the display area on the substrate, including a dummy transistor, and spaced apart from the gate driver, and a plurality of second pixel components disposed in the display area on the dummy gate driver, each of the plurality of second pixel components including a second pixel transistor.

[0033] In an embodiment, the display device can further include at least one additional gate driver disposed in the display area on the substrate and generating a second gate signal, and a plurality of second pixel components disposed in the display area on the additional gate driver, and each of the plurality of second pixel components including a second pixel transistor. The additional gate driver can be electrically connected to at least one of the plurality of first pixel components and the plurality of second pixel components.

[0034] An electronic device according to an embodiment can include a display device, and a processor controlling the display device. The display device includes a substrate including a display area and a peripheral area surrounding at least a portion of the display area, a gate driver disposed in the display area on the substrate, the gate driver including a driver transistor and generating a first gate signal, a plurality of first pixel components disposed on the gate driver, each of the plurality of first pixel components including a first pixel transistor and at least partially overlapping the gate driver in a plan view, a connection portion disposed in the peripheral area adjacent to the gate driver on the substrate, the connection portion including a first conductive pattern and a second conductive pattern disposed on the first conductive pattern and electrically connected to the first conductive pattern through a contact hole, a connection line extending from the first conductive pattern and electrically connected to the gate driver, and a gate signal line disposed on the connection line, extending from the second conductive pattern, and electrically connected to each of the plurality of first pixel components.

[0035] In the display device according to an embodiment, a gate driver generating a gate signal can be disposed in a display area, and a pixel structure at least partially overlapping the gate driver in a plan view can be disposed in the display area on the gate driver. The gate driver can be connected to the pixel structure through a connection portion disposed in a peripheral area. Accordingly, a dead zone of the display device can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0036] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1 FIG. 1 is a schematic plan view illustrating a display device according to an embodiment.

[0038] Figure 2 is a schematic plan view illustrating a display device according to an embodiment. Figure 1

[0039] Figure 3 is a schematic cross-sectional view taken along line I-I' of Figure 1

[0040] Figure 4 is a schematic plan view illustrating a display device according to an embodiment. Figure 2 ​​Schematic cross-sectional views of an embodiment of the cross-section taken along lines II-II' and III-III'.

[0041] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 and Figure 11 It is used to illustrate the use of Figure 4 A schematic cross-sectional view of a method of displaying a device.

[0042] Figure 12 It is shown along Figure 2 Schematic cross-sectional views of an embodiment of the cross-section taken along lines II-II' and III-III'.

[0043] Figure 13 It is shown along Figure 2 Schematic cross-sectional views of an embodiment of the cross-section taken along lines II-II' and III-III'.

[0044] Figure 14 It is shown along Figure 2 Schematic cross-sectional views of an embodiment of the cross-section taken along lines II-II' and III-III'.

[0045] Figure 15 It is shown along Figure 2 Schematic cross-sectional views of an embodiment of the cross-section taken along lines II-II' and III-III'.

[0046] Figure 16 is a schematic plan view showing a display device according to an embodiment.

[0047] Figure 17 is a schematic plan view showing a portion of a display device according to an embodiment.

[0048] Figure 18 It is along Figure 17 Schematic cross-sectional view taken along line IV-IV'.

[0049] Figure 19 is a schematic plan view showing a portion of a display device according to an embodiment.

[0050] Figure 20 is a schematic block diagram illustrating an electronic device according to an embodiment. DETAILED DESCRIPTION

[0051] Hereinafter, a display device according to an embodiment will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components may be omitted.

[0052] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the disclosure are shown. The present disclosure may, however, be implemented in many different forms and should not be construed as limited to the embodiments set forth in this document. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0053] In the drawings, the size, thickness, proportion, and dimension of each element can be exaggerated for the sake of description and clarity and thus, is for illustrative purposes only. Identical reference numerals denote identical elements throughout the specification.

[0054] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0055] In the specification and claims, the term “and / or” is intended to include any combination of the terms “and” and “or,” unless the context clearly indicates otherwise. For example, “A and / or B” can be understood to mean “A, B, or A and B.” The terms “and” and “or” can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to “and / or.”

[0056] In the specification and claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group consisting of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” can be understood to mean “A, B, or A and B.”

[0057] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[0058] The term “overlapping” or “overlap” means that a first object can be above or below a second object, or on a side of the second object, and means that the second object can be above or below the first object, or on a side of the first object. Additionally, the term “overlapping” can include layering, stacking, facing or facing towards, extending over, covering or partially covering, or can be any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0059] The terms “facing” and “facing towards” mean that a first element can be directly or indirectly opposite to a second element. In the case where a third element is interposed between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, but still facing each other.

[0060] When an element is described as "not overlapping" or "not in overlapping with" another element, it can include that the elements are spaced apart from each other, are offset from each other, or are disposed beside each other, or can include any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0061] The terms "comprise", "comprising", "include", and / or "including", "has", "have", and / or "having", and variations thereof, when used in this description, mean that the stated feature, integer, step, operation, element, component, and / or group is present, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] In view of the measurements at issue and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately", as used in this document, includes the recited value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the recited value.

[0063] Unless otherwise defined or implied in this document, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0064] It will be understood that when an element (or components, regions, layers, parts, etc.) is referred to as being "on" another element, "connected to" another element or "coupled to" another element, it can be directly on, directly connected to or directly coupled to the above-mentioned other element or intervening elements can be present therebetween.

[0065] It will be understood that the terms "connected" or "coupled" can include physical or electrical connections or couplings.

[0066] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0067] In the present specification, a plane can be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 can be perpendicular to the second direction DR2. A third direction DR3 can be perpendicular to the plane.

[0068] Referring to Figure 1 The display device DD according to the embodiment can include pixel structures (or pixel members) PX1 and PX2, a display panel driver DPD, a circuit board CB, a first gate driver GDV1, a second gate driver GDV2, a first connection part CP1, and a second connection part CP2.

[0069] The display device DD can be divided into a display area DA and a peripheral area PA. The display area DA can be an area in which an image can be displayed by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area PA can be an area in which an image is not displayed. The peripheral area PA can surround at least a portion of the display area DA. For example, the peripheral area PA can completely surround the display area DA.

[0070] The peripheral area PA can include a bending area BA and a pad area PDA. The bending area BA can be located (or disposed) between the display area DA and the pad area PDA in a plan view. The bending area BA can be bent based on a bending axis extending in the first direction DR1. The pad area PDA can have a shape extending along a side of the display device DD. For example, the pad area PDA can have a shape extending along the first direction DR1.

[0071] The pixel structures PX1 and PX2 can be arranged (or disposed) in the display area DA. Each of the pixel structures PX1 and PX2 can include a driving element (e.g., a thin film transistor) generating a driving current, and a light emitting element electrically connected to the driving element and generating light based on the driving current. Accordingly, each of the pixel structures PX1 and PX2 can generate light according to the driving current. The pixel structures PX1 and PX2 can be integrally arranged in the display area DA in a matrix form along the first direction DR1 and the second direction DR2.

[0072] The pixel structures PX1 and PX2 can include first pixel structures PX1 and second pixel structures PX2. The second pixel structures PX2 can be arranged at left and right edges of the display area DA. The first pixel structures PX1 can be arranged in the remaining area of the display area DA except for the area in which the second pixel structures PX2 are arranged.

[0073] Drivers for driving the pixel structures PX1 and PX2 can be disposed in the peripheral area PA. For example, the display panel driver DPD can be disposed in the peripheral area PA.

[0074] The data line DL, the first gate signal line GL1, the second gate signal line GL2, and the driving voltage line PL connected to the pixel structures PX1 and PX2 can be provided in the display area DA. Although not shown in detail in Figure 1 the data line DL and the driving voltage line PL can also be connected to the second pixel structure PX2. The first control signal line CSL1 connected to the first gate driver GDV1 and the second control signal line CSL2 connected to the second gate driver GDV2 can be provided in the peripheral area PA.

[0075] The first gate signal line GL1 can be electrically connected to the first gate driver GDV1 and extend in the first direction DR1. The first gate signal line GL1 can receive the first gate signal from the first gate driver GDV1 and provide the first gate signal to the pixel structures PX1 and PX2.

[0076] The second gate signal line GL2 can be electrically connected to the second gate driver GDV2 and can extend in the first direction DR1. The second gate signal line GL2 can receive the second gate signal from the second gate driver GDV2 and provide the second gate signal to the pixel structures PX1 and PX2.

[0077] For example, the first gate signal can be an electrical signal of a different type than the second gate signal. However, embodiments are not limited thereto. By way of example, the first gate signal can be an electrical signal of the same type as the second gate signal.

[0078] The data line DL can be electrically connected to the display panel driver DPD and can extend along the second direction DR2. The data line DL can receive the data voltage from the display panel driver DPD and provide the data voltage to the data line DL. The data line DL can provide the data voltage to the pixel structures PX1 and PX2.

[0079] The driving voltage line PL can be electrically connected to the display panel driver DPD and extend along the second direction DR2. The driving voltage line PL can receive the driving voltage from the display panel driver DPD and provide the driving voltage to the pixel structures PX1 and PX2. For example, the driving voltage can be a high power voltage for driving the pixel structures PX1 and PX2.

[0080] The first control signal line CSL1 can be electrically connected to the display panel driver DPD. The first control signal line CSL1 can receive the first control signal from the display panel driver DPD and provide the first control signal to the first gate driver GDV1.

[0081] The second control signal line CSL2 can be electrically connected to the display panel driver DPD. The second control signal line CSL2 can receive the second control signal from the display panel driver DPD and provide the second control signal to the second gate driver GDV2.

[0082] The display panel driver DPD can be disposed in the pad area PDA. The display panel driver DPD can be formed as an integrated circuit (IC). For example, in a case where the substrate of the display device DD can include glass, the display panel driver DPD can have a chip on glass (COG) structure disposed directly on the substrate. By way of example, in a case where the substrate can include plastic, the display panel driver DPD can be a chip on plastic (COP) structure disposed directly on the substrate. However, embodiments are not limited thereto.

[0083] The display panel driver DPD can generate various signals and / or voltages. For example, within the spirit and scope of the present disclosure, the display panel driver DPD can generate a first control signal, a second control signal, a driving voltage, a data voltage, etc.

[0084] The first gate driver GDV1 can include at least one driver transistor. In an embodiment, the first gate driver GDV1 can be disposed in the display area DA. For example, the first gate driver GDV1 can completely overlap the display area DA and can not overlap the peripheral area PA. In this case, the first gate driver GDV1 can at least partially overlap the second pixel structure PX2 in a plan view. For example, the first gate driver GDV1 can overlap a left edge of the display area DA.

[0085] The first gate driver GDV1 can receive the first control signal from the display panel driver DPD and generate a first gate signal based on the first control signal.

[0086] The second gate driver GDV2 can include at least one driver transistor. In an embodiment, the second gate driver GDV2 can be disposed in the display area DA. For example, the second gate driver GDV2 can completely overlap the display area DA and can not overlap the peripheral area PA. In this case, the second gate driver GDV2 can at least partially overlap the second pixel structure PX2 in a plan view. For example, the second gate driver GDV2 can overlap a right edge of the display area DA.

[0087] The second gate driver GDV2 can receive the second control signal from the display panel driver DPD and generate a second gate signal based on the second control signal.

[0088] The first gate driver GDV1 and the second gate driver GDV2 can not overlap the first pixel structure PX1 in a plan view.

[0089] The first connection portion CP1 and the second connection portion CP2 can be disposed in the peripheral area PA. For example, the first connection portion CP1 can be disposed in the peripheral area PA adjacent to the first gate driver GDV1, and the second connection portion CP2 can be disposed in the peripheral area PA adjacent to the second gate driver GDV2.

[0090] In an embodiment, the first gate driver GDV1 and the first connection portion CP1 can be connected by a connection line, and the first connection portion CP1 and the pixel structures PX1 and PX2 can be connected by the first gate signal line GL1. Likewise, the second gate driver GDV2 and the second connection portion CP2 can be connected by a connection line, and the second connection portion CP2 and the pixel structures PX1 and PX2 can be connected by the second gate signal line GL2. Accordingly, the first gate driver GDV1 can be electrically connected to the pixel structures PX1 and PX2 through the first connection portion CP1, and provide the first gate signal to the pixel structures PX1 and PX2 through the first connection portion CP1. The second gate driver GDV2 can be electrically connected to the pixel structures PX1 and PX2 through the second connection portion CP2, and provide the second gate signal to the pixel structures PX1 and PX2 through the second connection portion CP2.

[0091] The circuit board CB can be disposed in the pad area PDA. For example, the circuit board CB can partially overlap the pad area PDA. For example, a first portion of the circuit board CB can overlap the pad area PDA, and a second portion of the circuit board CB other than the first portion can not overlap the pad area PDA. The circuit board CB can be bonded to the substrate by an adhesive layer (e.g., anisotropic conductive film). The circuit board CB can provide a voltage, a control signal, etc. to the display panel driver DPD.

[0092] For example, the circuit board CB can include a rigid printed circuit board (PCB), a flexible printed circuit board (FPCB), or a flexible flat cable (FFC). However, embodiments are not limited thereto.

[0093] Figure 2 is an enlarged schematic plan view of the area A of Figure 1 For example, Figure 2 is a schematic plan view showing respective components of the first gate driver GDV1 and the first connection portion CP1 of Figure 1

[0094] Referring to Figure 2 ​The first gate driver GDV1 can include gate stages. For example, the gate stages can include a first gate stage GST1, a second gate stage GST2, a third gate stage GST3, a fourth gate stage GST4, a fifth gate stage GST5, a sixth gate stage GST6, a seventh gate stage GST7, and an eighth gate stage GST8. The first gate stage GST1, the second gate stage GST2, the third gate stage GST3, the fourth gate stage GST4, the fifth gate stage GST5, the sixth gate stage GST6, the seventh gate stage GST7, and the eighth gate stage GST8 can be disposed to be spaced apart from each other in the second direction DR2. However, Figure 2 The number of gate stages shown is for ease of explanation, and the number of gate stages is not limited thereto.

[0095] The first gate stage GST1, the second gate stage GST2, the third gate stage GST3, the fourth gate stage GST4, the fifth gate stage GST5, the sixth gate stage GST6, the seventh gate stage GST7, and the eighth gate stage GST8 can receive various control signals and voltages. The first gate stage GST1, the second gate stage GST2, the third gate stage GST3, the fourth gate stage GST4, the fifth gate stage GST5, the sixth gate stage GST6, the seventh gate stage GST7, and the eighth gate stage GST8 can generate first gate signals in response to the various control signals and voltages. The first gate signals can be applied to connection lines (for example, a first connection line CL1, a second connection line CL2, a third connection line CL3, a fourth connection line CL4, a fifth connection line CL5, a sixth connection line CL6, a seventh connection line CL7, and an eighth connection line CL8).

[0096] The first connection part CP1 can include sub-connection parts. For example, the sub-connection parts can include a first sub-connection part SCP1, a second sub-connection part SCP2, a third sub-connection part SCP3, a fourth sub-connection part SCP4, a fifth sub-connection part SCP5, a sixth sub-connection part SCP6, a seventh sub-connection part SCP7, and an eighth sub-connection part SCP8. The first sub-connection part SCP1, the second sub-connection part SCP2, the third sub-connection part SCP3, the fourth sub-connection part SCP4, the fifth sub-connection part SCP5, the sixth sub-connection part SCP6, the seventh sub-connection part SCP7, and the eighth sub-connection part SCP8 can be disposed to be spaced apart from each other in the second direction DR2. However, Figure 2 The number of sub-connection parts shown is for ease of explanation, and the number of sub-connection parts is not limited thereto.

[0097] The first sub connection part SCP1 and the first gate stage GST1 can be connected through a first connection line CL1, and the first sub connection part SCP1 and the second pixel structure PX2 located in the first row can be connected through a first-first gate signal line GL11. The first-first gate signal line GL11 can also be connected to the first pixel structure PX1 located in the first row. Figure 1 The first sub connection part SCP1 and the first gate stage GST1 can be connected through a first connection line CL1, and the first sub connection part SCP1 and the second pixel structure PX2 located in the first row can be connected through a first-first gate signal line GL11. The first-first gate signal line GL11 can also be connected to the first pixel structure PX1 located in the first row.

[0098] The second sub connection part SCP2 and the second gate stage GST2 can be connected through a second connection line CL2, and the second sub connection part SCP2 and the second pixel structure PX2 located in the second row can be connected through a first-second gate signal line GL12. The first-second gate signal line GL12 can also be connected to the first pixel structure PX1 located in the second row. Figure 1 The second sub connection part SCP2 and the second gate stage GST2 can be connected through a second connection line CL2, and the second sub connection part SCP2 and the second pixel structure PX2 located in the second row can be connected through a first-second gate signal line GL12. The first-second gate signal line GL12 can also be connected to the first pixel structure PX1 located in the second row.

[0099] The third sub connection part SCP3 and the third gate stage GST3 can be connected through a third connection line CL3, and the third sub connection part SCP3 and the second pixel structure PX2 located in the third row can be connected through a first-third gate signal line GL13. The first-third gate signal line GL13 can also be connected to the first pixel structure PX1 located in the third row. Figure 1 The third sub connection part SCP3 and the third gate stage GST3 can be connected through a third connection line CL3, and the third sub connection part SCP3 and the second pixel structure PX2 located in the third row can be connected through a first-third gate signal line GL13. The first-third gate signal line GL13 can also be connected to the first pixel structure PX1 located in the third row.

[0100] The fourth sub connection part SCP4 and the fourth gate stage GST4 can be connected through a fourth connection line CL4, and the fourth sub connection part SCP4 and the second pixel structure PX2 located in the fourth row can be connected through a first-fourth gate signal line GL14. The first-fourth gate signal line GL14 can also be connected to the first pixel structure PX1 located in the fourth row. Figure 1 The fourth gate stage GST4 can be electrically connected to the first pixel structure PX1 and the second pixel structure PX2 located in the fourth row through the fourth sub connection part SCP4. In this case, the first gate signal can be provided to the first pixel structure PX1 and the second pixel structure PX2 located in the fourth row through the fourth connection line CL4, the fourth sub connection part SCP4, and the first-fourth gate signal line GL14.

[0101] The fifth sub connection part SCP5 and the fifth gate stage GST5 can be connected through a fifth connection line CL5, and the fifth sub connection part SCP5 and the second pixel structure PX2 located in the fifth row can be connected through a first-fifth gate signal line GL15. The first-fifth gate signal line GL15 can also be connected to the first pixel structure PX1 located in the fifth row. Figure 1 The fifth gate stage GST5 can be electrically connected to the first pixel structure PX1 and the second pixel structure PX2 located in the fifth row through the fifth sub connection part SCP5. In this case, the first gate signal can be provided to the first pixel structure PX1 and the second pixel structure PX2 located in the fifth row through the fifth connection line CL5, the fifth sub connection part SCP5, and the first-fifth gate signal line GL15.

[0102] The sixth sub connection part SCP6 and the sixth gate stage GST6 can be connected through a sixth connection line CL6, and the sixth sub connection part SCP6 and the second pixel structure PX2 located in the sixth row can be connected through a first-sixth gate signal line GL16. The first-sixth gate signal line GL16 can also be connected to the first pixel structure PX1 located in the sixth row. Figure 1 The sixth gate stage GST6 can be electrically connected to the first pixel structure PX1 and the second pixel structure PX2 located in the sixth row through the sixth sub connection part SCP6. In this case, the first gate signal can be provided to the first pixel structure PX1 and the second pixel structure PX2 located in the sixth row through the sixth connection line CL6, the sixth sub connection part SCP6, and the first-sixth gate signal line GL16.

[0103] The seventh sub-connection portion SCP7 and the seventh gate stage GST7 may be connected via a seventh connection line CL7, and the seventh sub-connection portion SCP7 and the second pixel structure PX2 located in the seventh row may be connected via a first-seventh gate signal line GL17. The first-seventh gate signal line GL17 may also be connected to the second pixel structure PX2 located in the seventh row. Figure 1 The first pixel structure PX1 of the seventh row is provided in the seventh gate stage GST7. Therefore, the seventh gate stage GST7 can be electrically connected to the first pixel structure PX1 and the second pixel structure PX2 located in the seventh row through the seventh sub-connection portion SCP7. In this case, the first gate signal can be provided to the first pixel structure PX1 and the second pixel structure PX2 located in the seventh row through the seventh connection line CL7, the seventh sub-connection portion SCP7 and the first-seventh gate signal line GL17.

[0104] The eighth sub-connection portion SCP8 and the eighth gate stage GST8 may be connected via an eighth connection line CL8, and the eighth sub-connection portion SCP8 and the second pixel structure PX2 located in the eighth row may be connected via the first to eighth gate signal lines GL18. The first to eighth gate signal lines GL18 may also be connected to the second pixel structure PX2 located in the eighth row. Figure 1 The eighth gate stage GST8 may be electrically connected to the first pixel structure PX1 and the second pixel structure PX2 located in the eighth row through the eighth sub-connection portion SCP8. In this case, the first gate signal may be provided to the first pixel structure PX1 and the second pixel structure PX2 located in the eighth row through the eighth connection line CL8, the eighth sub-connection portion SCP8, and the first to eighth gate signal lines GL18.

[0105] Figure 2 Each of the first-first gate signal line GL11, the first-second gate signal line GL12, the first-third gate signal line GL13, the first-fourth gate signal line GL14, the first-fifth gate signal line GL15, the first-sixth gate signal line GL16, the first-seventh gate signal line GL17, and the first-eighth gate signal line GL18 may correspond to Figure 1 The first gate signal line GL1.

[0106] Figure 2 The components of the first gate driver GDV1 can be connected with Figure 1 The components of the second gate driver GDV2 are substantially the same or similar. For example, Figure 1 The second gate driver GDV2 may also include a gate stage. Figure 2 The components of the first connection part CP1 can be connected with Figure 1 The components of the second connecting portion CP2 are substantially the same or similar. For example, Figure 1The second connection portion CP2 can also comprise sub-connection portions. Figure 1 The gate stages of the second gate driver GDV2 can be electrically connected to the first and second pixel structures PX1 and PX2, respectively, by connection lines, sub-connection portions of the second connection portion CP2, and gate signal lines.

[0107] Figure 3 is a schematic cross-sectional view taken along the line I-I’ of Figure 1 Figure 4 is a schematic cross-sectional view taken along the line II-II’ and III-III’ of Figure 2

[0108] For example, Figure 3 shows the first pixel structure PX1 of Figure 1 and the first gate driver GDV1 of Figure 4 shows the second pixel structure PX2 of Figure 2 , the first gate driver GDV1 (e.g., the first gate stage GST1 of Figure 2 ), and the first connection portion CP1 (e.g., the first sub-connection portion SCP1 of Figure 2 ). Figure 2 The cross-sectional structures of the first, second, third, fourth, fifth, sixth, seventh, and eighth gate stages GST1, GST2, GST3, GST4, GST5, GST6, GST7, and GST8 of Figure 2 The first, second, third, fourth, fifth, sixth, seventh, and eighth sub-connection portions SCP1, SCP2, SCP3, SCP4, SCP5, SCP6, SCP7, and SCP8 of

[0109] Reference is made to Figure 3 and Figure 4 ​​According to an embodiment, the display device DD can include a substrate SUB, a barrier layer BAR, a buffer layer BUR, a first lower metal layer BML1, a second lower metal layer BML2, a driver transistor TR_G, a connection pattern BCNE, a first sub-connection part SCP1, a first connection line CL1, a first-first gate signal line GL11, a shielding pattern SP, a first pixel gate electrode GE1_P, a first pixel transistor TR1_P and a second pixel transistor TR2_P, a first electrode E1, a second electrode E2, a third electrode E3, and a fourth electrode E4, a first connection electrode CNE1 and a second connection electrode CNE2, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, a fifth insulating layer IL5, a sixth insulating layer IL6, and a seventh insulating layer IL7, a pixel definition layer PDL, a first light emitting element LED1 and a second light emitting element LED2, and a sealing layer TFE.

[0110] Here, the driver transistor TR_G can include a driver active layer ACT_G and a driver gate electrode GE_G, the first pixel transistor TR1_P can include a first pixel active layer ACT1 and a second-first pixel gate electrode GE21_P, and the second pixel transistor TR2_P can include a second pixel active layer ACT2 and a second-second pixel gate electrode GE22_P. The first light emitting element LED1 can include a first pixel electrode PE1, a first light emitting layer EML1, and a first common electrode CE1, and the second light emitting element LED2 can include a second pixel electrode PE2, a second light emitting layer EML2, and a second common electrode CE2.

[0111] As described above, the display device DD can be divided into the display area DA and the peripheral area PA. When the display device DD is divided into the display area DA and the peripheral area PA, components (e.g., the substrate SUB, etc.) of the display device DD can include the display area DA and the peripheral area PA.

[0112] The substrate SUB can include a transparent material or an opaque material. The substrate SUB can be made of a transparent resin substrate. Examples of the transparent resin substrate include a polyimide substrate. In this case, within the spirit and scope of the present disclosure, the polyimide substrate can include a first organic layer, a first barrier layer, a second organic layer, etc. By way of example, within the spirit and scope of the present disclosure, the substrate SUB can include a quartz substrate (such as a synthetic quartz substrate or a fluorine (F) doped quartz substrate), a calcium fluoride substrate, a soda lime glass substrate, a non-alkali glass substrate, etc. These can be used alone or in combination with each other.

[0113] A barrier layer BAR can be disposed on the substrate SUB. The barrier layer BAR can prevent permeation of unnecessary components such as impurities or moisture. In the spirit and scope of the present disclosure, the barrier layer BAR can include inorganic materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc. These can be used alone or in combination with each other.

[0114] The first lower metal layer BML1 can be disposed in the display area DA on the barrier layer BAR. Various electrical signals and / or voltages can be applied to the first lower metal layer BML1. For example, in the spirit and scope of the present disclosure, the first lower metal layer BML1 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. In the spirit and scope of the present disclosure, examples of the metal can include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), etc. In the spirit and scope of the present disclosure, examples of the conductive metal oxide can include indium tin oxide, indium zinc oxide, etc. In the spirit and scope of the present disclosure, examples of the metal nitride can include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN x ), etc. Each of these can be used alone or in combination with each other.

[0115] The second lower metal layer BML2 can be disposed in the display area DA on the barrier layer BAR. The second lower metal layer BML2 can be disposed in the same layer as the first lower metal layer BML1. For example, the second lower metal layer BML2 can include the same material as the first lower metal layer BML1 and can be formed by the same process as the first lower metal layer BML1.

[0116] The buffer layer BUR can be disposed on the barrier layer BAR. The buffer layer BUR can cover the first lower metal layer BML1 and the second lower metal layer BML2. The buffer layer BUR can prevent diffusion of metal atoms or impurities from the substrate SUB to the transistor. In the case where the surface of the substrate SUB is not uniform, the buffer layer BUR can improve the flatness of the surface of the substrate SUB. For example, in the spirit and scope of the present disclosure, the buffer layer BUR can include inorganic materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc. These can be used alone or in combination with each other.

[0117] The driver active layer ACT_G can be disposed in the display area DA on the buffer layer BUR. In an embodiment, the driver active layer ACT_G can include a silicon semiconductor (e.g., amorphous silicon, polysilicon, etc., within the spirit and scope of the present disclosure). However, embodiments are not limited thereto, and the driver active layer ACT_G can include a metal oxide semiconductor or an organic semiconductor.

[0118] The driver active layer ACT_G can include a first doped region DR1_G, a channel region CH_G, and a second doped region DR2_G. The channel region CH_G can be located between the first doped region DR1_G and the second doped region DR2_G. For example, each of the first doped region DR1_G and the second doped region DR2_G can be doped with a P-type impurity. By way of example, each of the first doped region DR1_G and the second doped region DR2_G can be doped with an N-type impurity. The channel region CH_G can not be doped with an impurity.

[0119] The first doped region DR1_G of the driver active layer ACT_G can be connected to the first lower metal layer BML1 through a contact hole that penetrates the buffer layer BUR. The second doped region DR2_G of the driver active layer ACT_G can be connected to the second lower metal layer BML2 through a contact hole that penetrates the buffer layer BUR.

[0120] The first insulating layer IL1 can be disposed on the buffer layer BUR. The first insulating layer IL1 can cover the driver active layer ACT_G. For example, the first insulating layer IL1 can cover the driver active layer ACT_G and can be disposed with a uniform thickness along the profile of the driver active layer ACT_G. By way of example, the first insulating layer IL1 can sufficiently cover the driver active layer ACT_G and can have a substantially flat upper surface without creating a step around the driver active layer ACT_G. For example, the first insulating layer IL1 can include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc., within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0121] The driver gate electrode GE_G can be disposed in the display area DA on the first insulating layer IL1. In a plan view, the driver gate electrode GE_G can overlap the channel region CH_G of the driver active layer ACT_G. For example, the driver gate electrode GE_G can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc., within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0122] Accordingly, the driver transistor TR G including the driver active layer ACT G and the driver gate electrode GE G can be disposed in the display area DA on the substrate SUB.

[0123] The connection pattern BCNE can be disposed in the display area DA on the first insulating layer IL1. The connection pattern BCNE can be connected to the second lower metal layer BML2 through a contact hole that penetrates the buffer layer BUR and the first insulating layer IL1. The connection pattern BCNE can be disposed in the same layer as the driver gate electrode GE G. For example, the connection pattern BCNE can include the same material as the driver gate electrode GE G and can be formed through the same process as the driver gate electrode GE G.

[0124] The first lower metal layer BML1, the second lower metal layer BML2, the driver transistor TR G, and the connection pattern BCNE can constitute a part of the first gate driver GDV1. For example, the first lower metal layer BML1, the second lower metal layer BML2, the driver transistor TR G, and the connection pattern BCNE can be included to the first gate driver GDV1 (e.g., Figure 2 the first gate stage GST1 of the first gate driver GDV1 of FIG. 1).

[0125] The second insulating layer IL2 can be disposed on the first insulating layer IL1. The second insulating layer IL2 can cover the driver gate electrode GE G and the connection pattern BCNE. For example, the second insulating layer IL2 can sufficiently cover the driver gate electrode GE G and the connection pattern BCNE and have an essentially flat upper surface without creating a step around the driver gate electrode GE G and the connection pattern BCNE. By way of example, the second insulating layer IL2 can cover the driver gate electrode GE G and the connection pattern BCNE and be disposed with a uniform thickness along each of the contours of the driver gate electrode GE G and the connection pattern BCNE. For example, the second insulating layer IL2 can include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. within the spirit and scope of the present disclosure. These can be used individually or in combination with each other.

[0126] The first pixel gate electrode GE1 P can be disposed in the display area DA on the second insulating layer IL2. The first pixel gate electrode GE1 P can be disposed to at least partially overlap the first pixel transistor TR1 P in a plan view. For example, the first pixel gate electrode GE1 P can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. within the spirit and scope of the present disclosure. These can be used individually or in combination with each other.

[0127] The shield pattern SP can be disposed in the display area DA on the second insulating layer IL2. The shield pattern SP can be disposed in the same layer as the first pixel gate electrode GE1_P. For example, the shield pattern SP can include the same material as the first pixel gate electrode GE1_P and can be formed by the same process as the first pixel gate electrode GE1_P. In an embodiment, the shield pattern SP can be disposed between the first gate driver GDV1 and the second pixel structure PX2. The shield pattern SP can at least partially overlap the driver transistor TR_G in a plan view. The shield pattern SP can shield the effect of an electrical signal applied to the first gate driver GDV1 on the second pixel structure PX2 and the effect of an electrical signal applied to the second pixel structure PX2 on the first gate driver GDV1.

[0128] The third insulating layer IL3 can be disposed on the second insulating layer IL2. The third insulating layer IL3 can cover the first pixel gate electrode GE1_P and the shield pattern SP. For example, the third insulating layer IL3 can sufficiently cover the first pixel gate electrode GE1_P and the shield pattern SP and have a substantially flat upper surface without creating a step around the first pixel gate electrode GE1_P and the shield pattern SP. By way of example, the third insulating layer IL3 can cover the first pixel gate electrode GE1_P and the shield pattern SP and be disposed with a uniform thickness along the contour of each of the first pixel gate electrode GE1_P and the shield pattern SP. For example, the third insulating layer IL3 can include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0129] The first pixel active layer ACT1 can be disposed in the display area DA on the third insulating layer IL3. In an embodiment, the first pixel active layer ACT1 can include a metal oxide semiconductor. Within the spirit and scope of the present disclosure, the metal oxide semiconductor can include a binary compound (AB x ), a ternary compound (AB x C y ), a quaternary compound (AB x C y D z , etc. For example, within the spirit and scope of the present disclosure, the metal oxide semiconductor can include zinc oxide (e.g., ZnO or ZnO2), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These can be used alone or in combination with each other. However, embodiments are not limited thereto, and the first pixel active layer ACT1 can include a silicon semiconductor or an organic semiconductor.

[0130] The first pixel active layer ACT1 can include a first doped region DR1_P, a first channel region CH1, and a second doped region DR2_P. The first channel region CH1 can be located between the first doped region DR1_P and the second doped region DR2_P. For example, each of the first doped region DR1_P and the second doped region DR2_P can be doped with an N-type impurity. By way of example, each of the first doped region DR1_P and the second doped region DR2_P can be doped with a P-type impurity. The first channel region CH1 can not be doped with an impurity.

[0131] The second pixel active layer ACT2 can be disposed in the display area DA on the third insulating layer IL3. The second pixel active layer ACT2 can be disposed in the same layer as the first pixel active layer ACT1. For example, the second pixel active layer ACT2 can include the same material as the first pixel active layer ACT1, and can be formed by the same process as the first pixel active layer ACT1.

[0132] The second pixel active layer ACT2 can include a third doped region DR3_P, a second channel region CH2, and a fourth doped region DR4_P. The second channel region CH2 can be located between the third doped region DR3_P and the fourth doped region DR4_P. For example, each of the third doped region DR3_P and the fourth doped region DR4_P can be doped with an N-type impurity. By way of example, each of the third doped region DR3_P and the fourth doped region DR4_P can be doped with a P-type impurity. The second channel region CH2 can not be doped with an impurity.

[0133] The fourth insulating layer IL4 can be disposed on the first pixel active layer ACT1 and the second pixel active layer ACT2, respectively. The fourth insulating layer IL4 can not overlap the first doped region DR1_P, the second doped region DR2_P, the third doped region DR3_P, and the fourth doped region DR4_P in a plan view, and can overlap the first channel region CH1 and the second channel region CH2 in a plan view. For example, the fourth insulating layer IL4 can include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0134] The second-first pixel gate electrode GE21_P can be disposed on the fourth insulating layer IL4. In a plan view, the second-first pixel gate electrode GE21_P can overlap the fourth insulating layer IL4 and the first channel region CH1. For example, the second-first pixel gate electrode GE21_P can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like, within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0135] Accordingly, the first pixel transistor TR1_P including the first pixel active layer ACT1 and the second-first pixel gate electrode GE21_P can be disposed in the display area DA on the substrate SUB.

[0136] The second-second pixel gate electrode GE22_P can be disposed on the fourth insulating layer IL4. The second-second pixel gate electrode GE22_P can overlap the fourth insulating layer IL4 and the second channel region CH2 in a plan view. The second-second pixel gate electrode GE22_P can be disposed in the same layer as the second-first pixel gate electrode GE21_P. For example, the second-second pixel gate electrode GE22_P can include the same material as the second-first pixel gate electrode GE21_P and can be formed by the same process as the second-first pixel gate electrode GE21_P.

[0137] Accordingly, the second pixel transistor TR2_P including the second pixel active layer ACT2 and the second-second pixel gate electrode GE22_P can be disposed in the display area DA on the substrate SUB. The second pixel transistor TR2_P can at least partially overlap the driver transistor TR_G in a plan view.

[0138] The fifth insulating layer IL5 can be disposed on the third insulating layer IL3, the first pixel active layer ACT1, the second pixel active layer ACT2, and the fourth insulating layer IL4. The fifth insulating layer IL5 can cover the first pixel active layer ACT1, the second pixel active layer ACT2, and the fourth insulating layer IL4. For example, the fifth insulating layer IL5 can cover the first pixel active layer ACT1, the second pixel active layer ACT2, and the fourth insulating layer IL4, and be disposed with a uniform thickness along each of the outlines of the first pixel active layer ACT1, the second pixel active layer ACT2, and the fourth insulating layer IL4. By way of example, the fifth insulating layer IL5 can sufficiently cover the first pixel active layer ACT1, the second pixel active layer ACT2, and the fourth insulating layer IL4, and have a substantially flat upper surface, without creating a step around the first pixel active layer ACT1, the second pixel active layer ACT2, and the fourth insulating layer IL4. For example, the fifth insulating layer IL5 can include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0139] The first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4 can be disposed in the display area DA on the fifth insulating layer IL5. The first electrode E1 can be connected to the first doped region DR1_P of the first pixel active layer ACT1 through a first contact hole CNT1 that penetrates the fifth insulating layer IL5, and the second electrode E2 can be connected to the second doped region DR2_P of the first pixel active layer ACT1 through a second contact hole CNT2 that penetrates the fifth insulating layer IL5. The third electrode E3 can be connected to the third doped region DR3_P of the second pixel active layer ACT2 through a third contact hole CNT3 that penetrates the fifth insulating layer IL5, and the fourth electrode E4 can be connected to the fourth doped region DR4_P of the second pixel active layer ACT2 through a fourth contact hole CNT4 that penetrates the fifth insulating layer IL5. For example, the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0140] The first sub-connection portion SCP1 of the first connection portion CP1 can include at least one conductive pattern. For example, the first sub-connection portion SCP1 of the first connection portion CP1 can include a first conductive pattern CMP1 and a second conductive pattern CMP2 disposed on the first conductive pattern CMP1. In an embodiment, the first conductive pattern CMP1 can be disposed in the same layer as the driver gate electrode GE_G, and the second conductive pattern CMP2 can be disposed in the same layer as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4. For example, the first conductive pattern CMP1 can include the same material as the driver gate electrode GE_G, and can be formed by the same process as the driver gate electrode GE_G. The second conductive pattern CMP2 can include the same material as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4, and can be formed by the same process as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4. However, embodiments are not limited thereto.

[0141] In an embodiment, the second conductive pattern CMP2 can be connected to the first conductive pattern CMP1 through a contact hole CNT_C that penetrates the second insulating layer IL2, the third insulating layer IL3, and the fifth insulating layer IL5. The first connection line CL1 can extend from the first conductive pattern CMP1, and the first-first gate signal line GL11 can extend from the second conductive pattern CMP2. For example, the first connection line CL1 can be integral with the first conductive pattern CMP1, and the first-first gate signal line GL11 can be integral with the second conductive pattern CMP2. In other words, the first connection line CL1 can be disposed in the same layer as the first conductive pattern CMP1, and the first-first gate signal line GL11 can be disposed in the same layer as the second conductive pattern CMP2.

[0142] The area or size or diameter of each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 can be different from the area of the contact hole CNT_C. In an embodiment, the area of the contact hole CNT_C can be greater than the area of each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4. Accordingly, electrical connection between the first gate driver GDV1 and the pixel structures PX1 and PX2 can be facilitated.

[0143] A sixth insulating layer IL6 can be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 can sufficiently cover the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4, the second conductive pattern CMP2, and the first-first gate signal line GL11. The sixth insulating layer IL6 can have a substantially flat upper surface. For example, the sixth insulating layer IL6 can include an organic material such as a phenol resin, a polyacrylate resin, a polyimide resin, a polyamide resin, a siloxane resin, an epoxy resin, or the like, within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0144] The first connection electrode CNE1 and the second connection electrode CNE2 can be disposed in the display area DA on the sixth insulating layer IL6. The first connection electrode CNE1 can be connected to the second electrode E2 (or the first electrode E1) through a contact hole that penetrates the sixth insulating layer IL6. The second connection electrode CNE2 can be connected to the fourth electrode E4 (or the third electrode E3) through a contact hole that penetrates the sixth insulating layer IL6. For example, the first connection electrode CNE1 and the second connection electrode CNE2 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like, within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0145] A seventh insulating layer IL7 can be disposed on the sixth insulating layer IL6. The seventh insulating layer IL7 can sufficiently cover the first connection electrode CNE1 and the second connection electrode CNE2. The seventh insulating layer IL7 can have a substantially flat upper surface. For example, the seventh insulating layer IL7 can include an organic material such as a phenol resin, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an epoxy resin, or the like, within the spirit and scope of the present disclosure. These can be used alone or in combination with each other.

[0146] The first pixel electrode PE1 and the second pixel electrode PE2 can be disposed in the display area DA on the seventh insulating layer IL7. The first pixel electrode PE1 can be connected to the first connection electrode CNE1 through a contact hole that penetrates the seventh insulating layer IL7. The second pixel electrode PE2 can be connected to the second connection electrode CNE2 through a contact hole that penetrates the seventh insulating layer IL7. For example, the first pixel electrode PE1 and the second pixel electrode PE2 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like, within the spirit and scope of the present disclosure. These can be used alone or in combination with each other. The first pixel electrode PE1 and the second pixel electrode PE2 can each be an anode electrode.

[0147] A pixel definition layer PDL can be disposed in the display area DA on the seventh insulating layer IL7. The pixel definition layer PDL can cover edges of each of the first and second pixel electrodes PE1 and PE2. A pixel opening can be defined in the pixel definition layer PDL, which exposes at least a portion of each of the first and second pixel electrodes PE1 and PE2. For example, the pixel definition layer PDL can include an organic material such as an epoxy resin, a siloxane resin, or the like, within the spirit and scope of the present disclosure. These can be used alone or in combination with each other. By way of example, the pixel definition layer PDL can include an inorganic material.

[0148] A first light emitting layer EML1 can be disposed on the first pixel electrode PE1, and a second light emitting layer EML2 can be disposed on the second pixel electrode PE2. Each of the first and second light emitting layers EML1 and EML2 can include a light emitting material that generates light of a preset color (e.g., red, green, or blue).

[0149] A first common electrode CE1 can be disposed on the pixel definition layer PDL and the first light emitting layer EML1, and a second common electrode CE2 can be disposed on the pixel definition layer PDL and the second light emitting layer EML2. The first common electrode CE1 can be integral with the second common electrode CE2. For example, the first and second common electrodes CE1 and CE2 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like, within the spirit and scope of the present disclosure. These can be used alone or in combination with each other. Each of the first and second common electrodes CE1 and CE2 can be a cathode electrode.

[0150] Accordingly, a first light emitting element LED1 including the first pixel electrode PE1, the first light emitting layer EML1, and the first common electrode CE1 can be disposed in the display area DA on the substrate SUB, and a second light emitting element LED2 including the second pixel electrode PE2, the second light emitting layer EML2, and the second common electrode CE2 can be disposed in the display area DA on the substrate SUB.

[0151] The first pixel transistor TR1_P and the first light emitting element LED1 can constitute a part of a first pixel structure PX1, and the second pixel transistor TR2_P and the second light emitting element LED2 can constitute a part of a second pixel structure PX2. For example, the first pixel transistor TR1_P and the first light emitting element LED1 can be included in the first pixel structure PX1, and the second pixel transistor TR2_P and the second light emitting element LED2 can be included in the second pixel structure PX2.

[0152] A sealing layer TFE can be disposed in the display area DA on the first and second common electrodes CE1 and CE2. Although not shown in the drawings, a sealing layer TFE can be disposed on the first and second common electrodes CE1 and CE2 in the display area DA.Figure 4 The encapsulation layer TFE is not illustrated in detail, but can also be provided in a portion of the peripheral area PA. The encapsulation layer TFE can prevent impurities, moisture, external air, etc. from penetrating from the outside into the first light emitting element LED1 and the second light emitting element LED2. The encapsulation layer TFE can include at least one inorganic layer and at least one organic layer. For example, the inorganic layer can include silicon oxide, silicon nitride, silicon oxynitride, etc. within the spirit and scope of the present disclosure. These can be used alone or in combination with each other. The organic layer can include a cured polymer such as polyacrylate, etc. within the spirit and scope of the present disclosure.

[0153] Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 are schematic cross-sectional views for explaining a method for manufacturing a display device of Figure 4 In the following, contents overlapping with those described with reference to Figure 4 may be omitted or simplified.

[0154] With reference to Figure 5 , a barrier layer BAR can be formed on the substrate SUB. The barrier layer BAR can be formed in the display area DA and the peripheral area PA.

[0155] A first lower metal layer BML1 and a second lower metal layer BML2 can be formed on the barrier layer BAR in the display area DA. A buffer layer BUR covering the first lower metal layer BML1 and the second lower metal layer BML2 can be formed on the barrier layer BAR. The buffer layer BUR can be formed in the display area DA and the peripheral area PA.

[0156] A preliminary driver active layer ACT_G' can be formed on the buffer layer BUR. The preliminary driver active layer ACT_G' can be connected to the first lower metal layer BML1 and the second lower metal layer BML2 via contact holes formed by removing a portion of the buffer layer BUR. In an embodiment, the preliminary driver active layer ACT_G' can be formed using polysilicon. A first insulating layer IL1 can be formed on the buffer layer BUR. The first insulating layer IL1 can be formed in the display area DA and the peripheral area PA.

[0157] Further with reference to Figure 6 , a driver gate electrode GE_G and a connection pattern BCNE can be formed on the first insulating layer IL1 in the display area DA by the same process. The connection pattern BCNE can be connected to the second lower metal layer BML2 via a contact hole formed by removing a portion of the buffer layer BUR and the first insulating layer IL1. ​​​​​​

[0158] The first conductive pattern CMP1 and the first connection line CL1 can be formed in the peripheral area PA on the first insulating layer IL1. The first conductive pattern CMP1 and the first connection line CL1 can be formed by the same process as the driver gate electrode GE_G and the connection pattern BCNE.

[0159] The preliminary driver active layer ACT_G' can be doped using the driver gate electrode GE_G as a mask. Accordingly, the driver active layer ACT_G including the first doped region DR1_G and the second doped region DR2_G doped with impurities (e.g., P-type impurities) and the channel region CH_G not doped with impurities can be formed.

[0160] Further referring to Figure 7 A second insulating layer IL2 can be formed on the first insulating layer IL1. The second insulating layer IL2 can be formed in the display area DA and the peripheral area PA. The second insulating layer IL2 can cover the driver gate electrode GE_G, the connection pattern BCNE, the first conductive pattern CMP1, and the first connection line CL1.

[0161] A shield pattern SP can be formed on the second insulating layer IL2 in the display area DA. The shield pattern SP can be formed to cover at least a portion of the driver transistor TR_G. A third insulating layer IL3 can be formed on the second insulating layer IL2. The third insulating layer IL3 can be formed in the display area DA and the peripheral area PA. The third insulating layer IL3 can cover the shield pattern SP.

[0162] Further referring to Figure 8 A second pixel active layer ACT2 can be formed on the third insulating layer IL3 in the display area DA. In an embodiment, the second pixel active layer ACT2 can be formed using a metal oxide semiconductor.

[0163] A fourth insulating layer IL4 can be formed on the second pixel active layer ACT2. The fourth insulating layer IL4 can be patterned to overlap a portion of the second pixel active layer ACT2. During a process of patterning the fourth insulating layer IL4, hydrogen can flow into the second pixel active layer ACT2. In this case, the portion of the second pixel active layer ACT2 into which hydrogen flows has an increased carrier concentration due to the introduced hydrogen and becomes conductive, so that the second pixel active layer ACT2 can include a third doped region DR3_P and a fourth doped region DR4_P doped with impurities (e.g., N-type impurities) and a second channel region CH2 not doped with impurities.

[0164] A second-second pixel gate electrode GE22_P can be formed in the display region DA on the fourth insulating layer IL4. The second-second pixel gate electrode GE22_P can be patterned to overlap with a second channel region CH2 of the second pixel active layer ACT2. A fifth insulating layer IL5 can be formed on the second pixel active layer ACT2, the fourth insulating layer IL4, and the second-second pixel gate electrode GE22_P. The fifth insulating layer IL5 can be formed in the display region DA and the peripheral region PA.

[0165] Further referring to Figure 9 In the display region DA, a third contact hole CNT3 exposing the third doped region DR3_P and a fourth contact hole CNT4 exposing the fourth doped region DR4_P can be formed by removing a portion of the fifth insulating layer IL5. Meanwhile, in the peripheral region PA, a contact hole CNT_C exposing the first conductive pattern CMP1 can be formed by removing portions of the second insulating layer IL2, the third insulating layer IL3, and the fifth insulating layer IL5.

[0166] Further referring to Figure 10 A third electrode E3 can be formed to fill the third contact hole CNT3, a fourth electrode E4 can be formed to fill the fourth contact hole CNT4, and a second conductive pattern CMP2 can be formed to fill the contact hole CNT_C. Meanwhile, a first-first gate signal line GL11 can be formed in the peripheral region PA on the fifth insulating layer IL5.

[0167] Further referring to Figure 11 A sixth insulating layer IL6 covering the third electrode E3, the fourth electrode E4, the second conductive pattern CMP2, and the first-first gate signal line GL11 can be formed on the fifth insulating layer IL5. The sixth insulating layer IL6 can be formed in the display region DA and the peripheral region PA.

[0168] A second connection electrode CNE2 can be formed in the display region DA on the sixth insulating layer IL6. The second connection electrode CNE2 can be connected to the fourth electrode E4 via a contact hole formed by removing a portion of the sixth insulating layer IL6. A seventh insulating layer IL7 covering the second connection electrode CNE2 can be formed on the sixth insulating layer IL6. The seventh insulating layer IL7 can be formed in the display region DA and the peripheral region PA.

[0169] A second pixel electrode PE2 can be formed over the seventh insulating layer IL7 in the display area DA. The second pixel electrode PE2 can be connected to the second connection electrode CNE2 via a contact hole formed by removing a portion of the seventh insulating layer IL7. A pixel definition layer PDL exposing at least a portion of the second pixel electrode PE2 can be formed over the seventh insulating layer IL7 in the display area DA. A second light-emitting layer EML2 can be formed in a pixel opening of the pixel definition layer PDL. A second common electrode CE2 can be formed over the second light-emitting layer EML2 and the pixel definition layer PDL.

[0170] Referring again to Figure 4 , a sealing layer TFE can be formed over the second common electrode CE2.

[0171] Thus, a display device DD as illustrated in Figure 4 may be manufactured.

[0172] Figure 12 is a schematic cross-sectional view of an embodiment illustrating a cross-section taken along lines II-II' and III-III' of Figure 2 . Figure 13 is a schematic cross-sectional view of an embodiment illustrating a cross-section taken along lines II-II' and III-III' of Figure 2 . Figure 14 is a schematic cross-sectional view of an embodiment illustrating a cross-section taken along lines II-II' and III-III' of Figure 2 . Figure 15 is a schematic cross-sectional view of an embodiment illustrating a cross-section taken along lines II-II' and III-III' of Figure 2 .

[0173] The display devices described with reference to Figure 12 , Figure 13 , Figure 14 and Figure 15 may be substantially the same as or similar to the display device DD described with reference to Figure 3 and Figure 4 . Hereinafter, overlapping descriptions can be omitted or simplified.

[0174] With reference to Figure 12 , the first sub-connection portion SCP1 of the first connection portion CP1 can include at least one conductive pattern. For example, the first sub-connection portion SCP1 of the first connection portion CP1 can include a first conductive pattern CMP1 and a second conductive pattern CMP2 disposed on the first conductive pattern CMP1.

[0175] In an embodiment, the first conductive pattern CMP1 can be disposed in the same layer as the first lower metal layer BML1 and the second lower metal layer BML2, and the second conductive pattern CMP2 can be disposed in the same layer as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4. For example, the first conductive pattern CMP1 can include the same material as the first lower metal layer BML1 and the second lower metal layer BML2, and can be formed by the same process as the first lower metal layer BML1 and the second lower metal layer BML2. The second conductive pattern CMP2 can include the same material as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4, and can be formed by the same process as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4.

[0176] In an embodiment, the second conductive pattern CMP2 can be connected to the first conductive pattern CMP1 through a contact hole CNT_C that penetrates the buffer layer BUR, the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fifth insulating layer IL5. The first connection line CL1 can extend from the first conductive pattern CMP1, and the first-first gate signal line GL11 can extend from the second conductive pattern CMP2.

[0177] Reference Figure 13 The first sub-connection part SCP1 of the first connection part CP1 can include at least one conductive pattern. For example, the first sub-connection part SCP1 of the first connection part CP1 can include a first-first conductive pattern CMP11, a first-second conductive pattern CMP12 disposed on the first-first conductive pattern CMP11, and a second conductive pattern CMP2 disposed on the first-second conductive pattern CMP12.

[0178] In an embodiment, the first-first conductive pattern CMP11 can be disposed in the same layer as the first lower metal layer BML1 and the second lower metal layer BML2, the first-second conductive pattern CMP12 can be disposed in the same layer as the driver gate electrode GE_G, and the second conductive pattern CMP2 can be disposed in the same layer as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4. For example, the first-first conductive pattern CMP11 can include the same material as the first lower metal layer BML1 and the second lower metal layer BML2, and can be formed by the same process as the first lower metal layer BML1 and the second lower metal layer BML2. The first-second conductive pattern CMP12 can include the same material as the driver gate electrode GE_G, and can be formed by the same process as the driver gate electrode GE_G. The second conductive pattern CMP2 can include the same material as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4, and can be formed by the same process as the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4.

[0179] In an embodiment, the second conductive pattern CMP2 can be connected to the first-first conductive pattern CMP11 through a first contact hole CNT_C1 that penetrates the buffer layer BUR, the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fifth insulating layer IL5. The second conductive pattern CMP2 can be connected to the first-second conductive pattern CMP12 through a second contact hole CNT_C2 that penetrates the second insulating layer IL2, the third insulating layer IL3, and the fifth insulating layer IL5.

[0180] The first-first connection line CL11 can extend from the first-first conductive pattern CMP11, the first-second connection line CL12 can extend from the first-second conductive pattern CMP12, and the first-first gate signal line GL11 can extend from the second conductive pattern CMP2. For example, one gate stage and one first sub-connection portion SCP1 of the first gate driver GDV1 can be connected by two connection lines.

[0181] Reference Figure 14 The first sub-connection portion SCP1 of the first connection portion CP1 can include at least one conductive pattern. For example, the first sub-connection portion SCP1 of the first connection portion CP1 can include the first conductive pattern CMP1 and the second conductive pattern CMP2 disposed on the first conductive pattern CMP1.

[0182] In an embodiment, the first conductive pattern CMP1 can be disposed in the same layer as the driver gate electrode GE_G, and the second conductive pattern CMP2 can be disposed in the same layer as the second-second pixel gate electrode GE22_P. For example, the first conductive pattern CMP1 can include the same material as the driver gate electrode GE_G, and can be formed by the same process as the driver gate electrode GE_G. The second conductive pattern CMP2 can include the same material as the second-second pixel gate electrode GE22_P, and can be formed by the same process as the second-second pixel gate electrode GE22_P.

[0183] In an embodiment, the second conductive pattern CMP2 can be connected to the first conductive pattern CMP1 through a contact hole CNT_C that penetrates the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. The first connection line CL1 can extend from the first conductive pattern CMP1, and the first-first gate signal line GL11 can extend from the second conductive pattern CMP2.

[0184] Reference Figure 15 The first sub-connection portion SCP1 of the first connection portion CP1 can include at least one conductive pattern. For example, the first sub-connection portion SCP1 of the first connection portion CP1 can include the first conductive pattern CMP1 and the second conductive pattern CMP2 disposed on the first conductive pattern CMP1.

[0185] In an embodiment, the first conductive pattern CMP1 can be disposed in the same layer as the first lower metal layer BML1 and the second lower metal layer BML2, and the second conductive pattern CMP2 can be disposed in the same layer as the second-second pixel gate electrode GE22_P. For example, the first conductive pattern CMP1 can include the same material as the first lower metal layer BML1 and the second lower metal layer BML2, and can be formed by the same process as the first lower metal layer BML1 and the second lower metal layer BML2. The second conductive pattern CMP2 can include the same material as the second-second pixel gate electrode GE22_P, and can be formed by the same process as the second-second pixel gate electrode GE22_P.

[0186] In an embodiment, the second conductive pattern CMP2 can be connected to the first conductive pattern CMP1 through a contact hole CNT_C that penetrates the buffer layer BUR, the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. The first connection line CL1 can extend from the first conductive pattern CMP1, and the first-first gate signal line GL11 can extend from the second conductive pattern CMP2.

[0187] As a result, the first conductive pattern CMP1 can be disposed in the same layer as any one of the first lower metal layer BML1 and the second lower metal layer BML2 and the driver gate electrode GE_G, and the second conductive pattern CMP2 can be disposed in the same layer as any one of the third electrode E3, the fourth electrode E4, and the second-second pixel gate electrode GE22_P.

[0188] Referring again to Figure 12 , Figure 13 , Figure 14 and Figure 15 , in an embodiment, an area of the contact hole CNT_C, CNT_C1, and CNT_C2 can be greater than an area of each of the third contact hole CNT3 and the fourth contact hole CNT4.

[0189] Figure 16 is a schematic plan view illustrating a display device according to an embodiment. Except for positions of the first gate driver GDV1 and the second gate driver GDV2, Figure 16 , the display device DD' can be substantially the same as or similar to the display device DD described with reference to Figure 1 . Hereinafter, overlapping descriptions can be omitted.

[0190] In an embodiment, the first gate driver GDV1 and the second gate driver GDV2 can be partially disposed in the display area DA. For example, each of the first gate driver GDV1 and the second gate driver GDV2 can partially overlap with the display area DA. For example, each of the first gate driver GDV1 and the second gate driver GDV2 can partially overlap with the display area DA and partially overlap with the peripheral area PA. In this case, each of the first gate driver GDV1 and the second gate driver GDV2 can at least partially overlap with a pixel structure (e.g., the second pixel structure PX2) in a plan view.

[0191] Figure 17 is a schematic plan view illustrating a portion of a display device according to an embodiment. Figure 18 is a schematic cross-sectional view taken along the line IV-IV' of Figure 17 .

[0192] Except that the display device DD" can further include a dummy gate driver DGDV, the display device DD" described with reference to Figure 17 and Figure 18 may be substantially the same as or similar to the display device DD described with reference to Figure 1 , Figure 2 , Figure 3 and Figure 4 . Hereinafter, overlapping descriptions can be omitted.

[0193] Reference is made to Figure 17 and Figure 18 In an embodiment, the display device DD” can further include at least one dummy gate driver DGDV which is disposed in the display area DA and spaced apart from the first gate driver GDV1 and the second gate driver GDV2. The dummy gate driver DGDV can not be electrically connected to the first pixel structure PX1 and the second pixel structure PX2.

[0194] The dummy gate driver DGDV can be disposed below or under the first pixel structure PX1. For example, the first pixel structure PX1 can at least partially overlap the dummy gate driver DGDV in a plan view.

[0195] The dummy gate driver DGDV can include a dummy transistor TR_D, a first dummy lower metal layer BML1_D, a second dummy lower metal layer BML2_D, and a dummy connection pattern BCNE_D. The dummy transistor TR_D can include a dummy active layer ACT_D and a dummy gate electrode GE_D. The dummy active layer ACT_D can include a doped region DR1_D and a doped region DR2_D connected to the first dummy lower metal layer BML1_D and the second dummy lower metal layer BML2_D, respectively, and a channel region CH_D disposed between the doped regions DR1_D and DR2_D.

[0196] The dummy active layer ACT_D and the dummy gate electrode GE_D can include the same materials as the driver active layer ACT_G and the driver gate electrode GE_G of Figure 4 , respectively, and can be disposed in the same layers as the driver active layer ACT_G and the driver gate electrode GE_G of Figure 4 The first dummy lower metal layer BML1_D, the second dummy lower metal layer BML2_D, and the dummy connection pattern BCNE_D can include the same materials as the first lower metal layer BML1, the second lower metal layer BML2, and the connection pattern BCNE of Figure 4 , respectively, and can be disposed in the same layers as the first lower metal layer BML1, the second lower metal layer BML2, and the connection pattern BCNE of Figure 4 .

[0197] Figure 19 is a schematic plan view illustrating a portion of a display device according to an embodiment.

[0198] The display device DD”’ described with reference to Figure 19 may be the same as the display device DD” described with reference to Figure 1 , Figure 2 , Figure 3 and Figure 4The described display device DD is substantially the same or similar. Hereinafter, overlapping descriptions can be omitted.

[0199] Referring to Figure 19 In an embodiment, the display device DD”’ can further include at least one additional gate driver GDV3 disposed in the display area DA and spaced apart from the first gate driver GDV1 and the second gate driver GDV2. The additional gate driver GDV3 can generate a gate signal and be electrically connected to at least one of the first pixel structure PX1 and the second pixel structure PX2. For example, like the first gate driver GDV1 and the second gate driver GDV2, the additional gate driver GDV3 can be connected to at least one of the first pixel structure PX1 and the second pixel structure PX2 through a connection portion disposed in the peripheral area PA.

[0200] The additional gate driver GDV3 can be disposed under or below the first pixel structure PX1. For example, the first pixel structure PX1 can at least partially overlap the additional gate driver GDV3 in a plan view.

[0201] A cross-sectional structure of the additional gate driver GDV3 can be substantially the same or similar to that of the dummy gate driver DGDV of Figure 18

[0202] Referring again to Figures 1 to 9 In the display device according to an embodiment, a gate driver (for example, Figure 1 the first gate driver GDV1 or the second gate driver GDV2 of Figure 1 and Figure 2 the second pixel structure PX2 of) generating a gate signal can be disposed in the display area DA and at least partially overlap the gate driver in a plan view. The pixel structure (for example,) can be disposed in the display area DA on the gate driver. The gate driver can be connected to the pixel structure through a connection portion (for example, ) the first connection portion CP1 or the second connection portion CP2 of disposed in the peripheral area PA. Accordingly, a dead zone of the display device can be reduced. Figure 1

[0203] Figure 20 is a schematic block diagram illustrating an electronic device according to an embodiment.

[0204] Referring to Figure 20 In an embodiment, the electronic device 900 can include a processor 910, a memory device 920, a storage device 930, an input / output device (I / O device) 940, a power supply 950, and a display device 960. In this case, the display device 960 can correspond to the display device DD of Figures 1 to 19The described display apparatus DD, DD', DD", or DD"' is described. The electronic apparatus 900 can further include a number of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc.

[0205] In an embodiment, the electronic apparatus 900 can be implemented as a television. In another embodiment, the electronic apparatus 900 can be implemented as a smart phone. However, the electronic apparatus 900 is not limited thereto, and for example, the electronic apparatus 900 can be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a tablet personal computer (PC), a vehicle navigation apparatus, a computer display screen, a laptop computer, a head-mounted display (HMD), etc.

[0206] The processor 910 can perform a specific computation or task. The processor 910 can control the display apparatus 960. In an embodiment, the processor 910 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 910 can be connected to other components through an address bus, a control bus, a data bus, etc. The processor 910 can also be connected to an extension bus, such as a peripheral component interconnect (PCI) bus.

[0207] The memory apparatus 920 can store data required for the operation of the electronic apparatus 900. For example, the memory apparatus 920 can include an erasable programmable read-only memory (EPROM) apparatus, an electrically erasable programmable read-only memory (EEPROM) apparatus, a flash memory apparatus, a phase change random access memory (PRAM) apparatus, a resistive random access memory (RRAM) apparatus, a nano floating GEe memory (NFGM) apparatus, a polymer random access memory (PoRAM) apparatus, a magnetic random access memory (MRAM) apparatus, a non-volatile memory apparatus such as a ferroelectric random access memory (FRAM) apparatus, and / or a volatile memory apparatus such as a dynamic random access memory (DRAM) apparatus, a static random access memory (SRAM) apparatus, and a mobile DRAM apparatus, etc.

[0208] The storage apparatus 930 can include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0209] The input / output apparatus 940 can include an input apparatus such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc., and an output apparatus such as a speaker, a printer, etc.

[0210] The power supply 950 can supply power required for the operation of the electronic apparatus 900. The display apparatus 960 can be connected to other components through a bus or other communication link. In an embodiment, the display apparatus 960 can be included in the input / output apparatus 940.

[0211] The present disclosure can be applied to various display apparatuses. For example, the present disclosure can be applied to various display apparatuses such as display apparatuses for vehicles, ships, and airplanes, portable communication apparatuses, display apparatuses for exhibition or information transmission, medical display apparatuses, etc., within the spirit and scope of the present disclosure.

[0212] The above are examples of embodiments and should not be construed as limiting thereto. Although embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure and the scope of the claims as defined below. It is therefore to be understood that the foregoing is an example of various embodiments and is intended to be illustrative only and is not to be limiting as to the scope of the disclosed embodiments and modifications are intended to be included within the scope of the appended claims.

Claims

1. A display device comprising: a substrate including a display region and a peripheral region surrounding at least a portion of the display region; a gate driver provided on the substrate in the display region, the gate driver including a driver transistor and generating a first gate signal; a plurality of first pixel constituents provided on the gate driver, each of the plurality of first pixel constituents including a first pixel transistor and at least partially overlapping the gate driver in a plan view; a connection portion provided on the substrate in the peripheral region adjacent to the gate driver, the connection portion including a first conductive pattern and a second conductive pattern provided on the first conductive pattern and electrically connected to the first conductive pattern through a contact hole; a connection line extending from the first conductive pattern and electrically connected to the gate driver; and a gate signal line provided on the connection line, extending from the second conductive pattern, the gate signal line electrically connected to each of the plurality of first pixel constituents. The gate driver overlaps at least one of a left edge of the display region and a right edge of the display region.

2. The display device according to claim 1, wherein 3. The display device according to claim 1, further comprising: a shielding pattern provided between the gate driver and the plurality of first pixel constituents and at least partially overlapping the driver transistor in the plan view.

4. The display device according to claim 1, further comprising: a plurality of second pixel constituents provided on the gate driver in the display region, each of the plurality of second pixel constituents including a second pixel transistor and not overlapping the gate driver in the plan view. The first pixel transistor includes:

5. The display device according to claim 1, wherein a first pixel active layer provided on the gate driver; and a pixel gate electrode provided on the first pixel active layer and partially overlapping a channel region of the first pixel active layer in the plan view, each of the plurality of first pixel constituents further includes: a first electrode provided on the first pixel active layer and electrically connected to a first doped region of the first pixel active layer through a first contact hole; and a second electrode provided on the first pixel active layer and electrically connected to a second doped region of the first pixel active layer through a second contact hole. A size of the contact hole is different from a size of each of the first contact hole and the second contact hole.

6. The display device of claim 5, wherein, The size of the contact hole is greater than the size of each of the first contact hole and the second contact hole.

7. The display device according to claim 5, wherein The first pixel active layer includes a metal oxide semiconductor.

8. The display device according to claim 5, wherein The driver transistor includes:

9. The display device according to claim 5, wherein a driver active layer provided on the substrate; and a driver gate electrode provided on the driver active layer and overlapping a channel region of the driver active layer. The driver active layer includes a silicon semiconductor.

10. The display device of claim 9, wherein, The gate driver further includes:

11. The display device of claim 9, wherein, a lower metal layer provided between the substrate and the driver active layer and electrically connected to the driver active layer; and a connection pattern provided in a same layer as the driver gate electrode and electrically connected to the lower metal layer. ​ 12. The display device according to claim 11, wherein the first conductive pattern is provided in the same layer as the driver gate electrode, and the second conductive pattern is provided in the same layer as the first electrode and the second electrode.

13. The display device according to claim 11, wherein the first conductive pattern is provided in the same layer as the lower metal layer, and the second conductive pattern is provided in the same layer as the first electrode and the second electrode.

14. The display device according to claim 11, wherein the first conductive pattern is provided in the same layer as the driver gate electrode, and the second conductive pattern is provided in the same layer as the pixel gate electrode.

15. The display device according to claim 11, wherein the first conductive pattern is provided in the same layer as the lower metal layer, and the second conductive pattern is provided in the same layer as the pixel gate electrode.

16. The display device according to claim 11, wherein the first conductive pattern includes: a first-first conductive pattern provided in the same layer as the lower metal layer, and a first-second conductive pattern provided in the same layer as the driver gate electrode, the connection line includes a first-first connection line extending from the first-first conductive pattern and a first-second connection line extending from the first-second conductive pattern, and the second conductive pattern is provided in the same layer as the first electrode and the second electrode.

17. The display device according to claim 1, further comprising: at least one dummy gate driver provided on the substrate in the display region, including a dummy transistor, and spaced apart from the gate driver; and a plurality of second pixel members provided on the dummy gate driver in the display region, each of the plurality of second pixel members including a second pixel transistor.

18. The display device according to claim 1, further comprising: at least one additional gate driver provided on the substrate in the display region and generating a second gate signal; and a plurality of second pixel members provided on the additional gate driver in the display region, each of the plurality of second pixel members including a second pixel transistor, wherein the additional gate driver is electrically connected to at least one of the plurality of first pixel members and the plurality of second pixel members.

19. A display device comprising: a substrate including a display region and a peripheral region surrounding at least a portion of the display region; a gate driver provided on the substrate in the display region, generating a first gate signal, and including a plurality of gate stages each including a driver transistor; a plurality of first pixel members provided on the gate driver, each of the plurality of first pixel members including a first pixel transistor, and at least partially overlapping the plurality of gate stages in a plan view; a connection portion provided in the peripheral region adjacent to the gate driver on the substrate and including a plurality of sub-connection portions each including a first conductive pattern and a second conductive pattern provided on the first conductive pattern and electrically connected to the first conductive pattern through a contact hole; connection lines each extending from the first conductive pattern of a corresponding one of the sub-connection portions and each electrically connected to a corresponding one of the plurality of gate stages; and gate signal lines provided on the connection lines, each extending from the second conductive pattern of a corresponding one of the sub-connection portions and each electrically connected to a corresponding one of the plurality of first pixel components.

20. The display device according to claim 19, further comprising: a shield pattern provided between the gate driver and the plurality of first pixel components and at least partially overlapping the driver transistor in the plan view.

21. The display device according to claim 19, further comprising: a plurality of second pixel components provided in the display region on the gate driver, each of the plurality of second pixel components including a second pixel transistor and not overlapping the gate driver in the plan view.

22. The display device of claim 19, wherein, the first pixel transistor including: a first pixel active layer provided on the gate driver; and a pixel gate electrode provided on the first pixel active layer and partially overlapping a channel region of the first pixel active layer in the plan view, each of the plurality of first pixel components further including: a first electrode provided on the first pixel active layer and electrically connected to a first doped region of the first pixel active layer through a first contact hole; and a second electrode provided on the first pixel active layer and electrically connected to a second doped region of the first pixel active layer through a second contact hole.

23. The display device of claim 22, wherein, a size of the contact hole is larger than a size of each of the first contact hole and the second contact hole.

24. The display device of claim 22, wherein, the driver transistor including: a driver active layer provided on the substrate; and a driver gate electrode provided on the driver active layer and overlapping a channel region of the driver active layer.

25. The display device of claim 24, wherein, the gate driver further including: a lower metal layer provided between the substrate and the driver active layer and electrically connected to the driver active layer; and a connection pattern provided in the same layer as the driver gate electrode and electrically connected to the lower metal layer.

26. The display device of claim 25, wherein, the first conductive pattern is provided in the same layer as one of the lower metal layer and the driver gate electrode, and the second conductive pattern is provided in the same layer as one of the first electrode and the pixel gate electrode.

27. The display device according to claim 19, further comprising: at least one dummy gate driver provided in the display region on the substrate, including a dummy transistor, and spaced apart from the gate driver; and A plurality of second pixel units is provided in the display region over the dummy gate driver, and each of the plurality of second pixel units includes a second pixel transistor.

28. The display device according to claim 19, further comprising: at least one additional gate driver provided in the display region over the substrate and generating a second gate signal; and a plurality of second pixel units provided in the display region over the additional gate driver, each of the plurality of second pixel units including a second pixel transistor, wherein the additional gate driver is electrically connected to at least one of the plurality of first pixel units and the plurality of second pixel units.

29. An electronic device comprising: a display device; and a processor controlling the display device, wherein the display device includes: a substrate including a display region and a peripheral region surrounding at least a portion of the display region; a gate driver provided in the display region over the substrate, the gate driver including a driver transistor and generating a first gate signal; a plurality of first pixel units provided over the gate driver, each of the plurality of first pixel units including a first pixel transistor and at least partially overlapping the gate driver in a plan view; a connection portion provided in the peripheral region adjacent to the gate driver over the substrate, the connection portion including a first conductive pattern and a second conductive pattern provided over the first conductive pattern and electrically connected to the first conductive pattern through a contact hole; a connection line extending from the first conductive pattern and electrically connected to the gate driver; and a gate signal line provided over the connection line, extending from the second conductive pattern, the gate signal line being electrically connected to each of the plurality of first pixel units. ​ ​

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