Display device

Abstract

The invention discloses a display device and an electronic device including the same. The display device includes: a substrate including a display area and a peripheral area; a light emitting element disposed in the display area and including an anode electrode, a light emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light emitting layer and extending from the display area to the peripheral area; a common voltage supply line disposed in the peripheral region, electrically connected to the cathode electrode, and including: a first metal line; a second metal line disposed on the first metal line; a third metal line disposed on the second metal line; and a connection pattern including the same material as that of the anode electrode and contacting the third metal line and the cathode electrode; and a transmission line disposed in the peripheral region, including the same material as that of the third metal line, and connected to the common voltage supply line.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device. More particularly, the present application relates to a display device providing visual information. BACKGROUND

[0002] As information technology continues to develop, the importance of display devices is increasing. The display device can be a device for communicating information to a user. Accordingly, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing. SUMMARY

[0003] Embodiments provide a display device having reduced power consumption and improved mura phenomenon.

[0004] A display device according to an embodiment of the present application includes a substrate including a display area and a peripheral area disposed at a side of the display area; a light emitting element disposed in the display area and including an anode electrode, a light emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light emitting layer and extending from the display area to the peripheral area; a common voltage supply line disposed in the peripheral area, electrically connected to the cathode electrode, and including a first metal line, a second metal line disposed on the first metal line and contacting the first metal line, a third metal line disposed on the second metal line and contacting the second metal line, and a connection pattern including a same material as a material of the anode electrode and contacting the third metal line and the cathode electrode; and a transfer line disposed in the peripheral area, including a same material as a material of the third metal line, and connected to the common voltage supply line through the connection pattern.

[0005] In an embodiment, the display device can further include a gate driver disposed in the peripheral area and including at least one driver transistor, and a control signal line disposed in the peripheral area and electrically connected to the gate driver. The connection pattern can overlap the control signal line in a plan view and can be spaced apart from the control signal line.

[0006] In an embodiment, the display device can further include a first organic insulating layer disposed on the substrate and extending from the display area to the peripheral area to cover an end portion of the first metal line, a second organic insulating layer disposed on the first organic insulating layer and extending from the display area to the peripheral area to cover an end portion of the second metal line, and a third organic insulating layer disposed on the second organic insulating layer and extending from the display area to the peripheral area to cover an end portion of the third metal line.

[0007] In an embodiment, an opening can be defined in the third organic insulating layer to expose at least a portion of the transfer line, and the connection pattern can contact the transfer line through the opening.

[0008] In an embodiment, the transmission line can be directly connected to an end of the common voltage supply line adjacent to the pad area of the peripheral area.

[0009] In an embodiment, a plurality of vias exposing at least a portion of the third organic insulating layer can be defined in the connection pattern.

[0010] In an embodiment, the cathode electrode can extend from the display area to a position overlapping an end of the third metal line in contact with the third organic insulating layer.

[0011] In an embodiment, the display device can further include: a first voltage line disposed in the display area and extending in a first direction; and a second voltage line disposed in the display area, disposed in a different layer from the first voltage line, and extending in a second direction crossing the first direction.

[0012] In an embodiment, the transmission line can be connected to the first voltage line through a first contact hole penetrating the first organic insulating layer and the second organic insulating layer, and the transmission line can be connected to the second voltage line through a second contact hole penetrating the second organic insulating layer.

[0013] In an embodiment, in a region adjacent to an edge portion of the display area adjacent to the pad area of the peripheral area, the first voltage line can be divided into a first portion connected to the second voltage line, a second portion spaced apart from the first portion in a direction opposite to the first direction and connected to a first transmission line portion of the transmission line, and a third portion spaced apart from the first portion in the first direction and connected to a second transmission line portion of the transmission line.

[0014] In an embodiment, the display device can further include: a common voltage line disposed in the display area, electrically connected to the common voltage supply line, and having a mesh structure.

[0015] In an embodiment, the common voltage line can be directly connected to an end of the common voltage supply line adjacent to the pad area of the peripheral area.

[0016] In an embodiment, the display device can further include: a data line extending in the second direction. In a plan view, the anode electrode can at least partially overlap the data line. The common voltage line can include: a first common voltage line overlapping the first voltage line in a plan view and extending in the first direction; and a second common voltage line covering a portion of the data line overlapping the anode electrode and extending in the second direction.

[0017] In an embodiment, the common voltage line can cover at least one disconnected portion of at least one of the first voltage line and the second voltage line.

[0018] A display device according to an embodiment of the present application includes a substrate including a display area and a peripheral area surrounding at least a portion of the display area; a light emitting element disposed in the display area and including an anode electrode, a light emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light emitting layer and extending from the display area to the peripheral area; a common voltage supply line including a plurality of metal layers sequentially stacked and disposed in the peripheral area and contacting the cathode electrode; a first voltage line disposed in the display area and extending in a first direction; a second voltage line disposed in the display area, disposed in a different layer from the first voltage line, and extending in a second direction crossing the first direction; and a common voltage line disposed in the display area, electrically connected to the common voltage supply line, and having a mesh structure.

[0019] In an embodiment, the display device can further include a first organic insulating layer disposed on the substrate and extending from the display area to the peripheral area; a second organic insulating layer disposed on the first organic insulating layer and extending from the display area to the peripheral area; and a third organic insulating layer disposed on the second organic insulating layer and extending from the display area to the peripheral area. The common voltage line can be disposed between the second organic insulating layer and the third organic insulating layer.

[0020] In an embodiment, the common voltage line can be directly connected to an end portion of the common voltage supply line adjacent to a pad area of the peripheral area.

[0021] In an embodiment, the display device can further include a data line extending in the second direction. In a plan view, the anode electrode can at least partially overlap the data line, and the common voltage line can include a first common voltage line covering a disconnected portion of the first voltage line in the plan view and extending in the first direction, and a second common voltage line covering a portion of the data line overlapping the anode electrode and extending in the second direction.

[0022] In an embodiment, the mesh structure can be formed in a portion of the display area including the first voltage line and the second voltage line.

[0023] In an embodiment, at least a portion of the common voltage line covers a portion of the first voltage line, and at least a portion of the anode electrode covers a portion of the second voltage line.

[0024] An electronic device according to an embodiment of the disclosure includes a display device and a processor that controls the display device. The display device includes a substrate including a display area and a peripheral area disposed at a side of the display area; a light emitting element disposed in the display area and including an anode electrode, a light emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light emitting layer and extending from the display area to the peripheral area; a common voltage supply line disposed in the peripheral area, electrically connected to the cathode electrode, and including a first metal line, a second metal line disposed on the first metal line and contacting the first metal line, a third metal line disposed on the second metal line and contacting the second metal line, and a connection pattern including a same material as a material of the anode electrode and contacting the third metal line and the cathode electrode; and a transmission line disposed in the peripheral area, including a same material as a material of the third metal line, and connected to the common voltage supply line through the connection pattern.

[0025] A display device according to an embodiment of the disclosure can include a common voltage supply line disposed in a peripheral area, can provide a common voltage, and include a first metal line, a second metal line, a third metal line, and a connection pattern sequentially stacked, a transmission line disposed in the peripheral area, including a same material as a material of the third metal line, and connected to the common voltage supply line through the connection pattern, and a common voltage line disposed in the display area, integrally formed with the transmission line, and having a mesh structure in the entire display area. Accordingly, a voltage drop (IR drop) of the common voltage can be minimized or reduced. In this case, power consumption of the display device can be improved.

[0026] In addition, the common voltage line can include a first common voltage line extending in a first direction and a second common voltage line extending in a second direction, and the second common voltage line can cover (or shield) a portion of the data line overlapping the anode electrode. In addition, the first common voltage line can cover (or shield) a first disconnected portion of the first voltage line, and the second common voltage line can cover (or shield) a second disconnected portion of the second voltage line. Accordingly, coupling between the data line and the anode electrode can be suppressed or prevented, and the first disconnected portion and the second disconnected portion can be invisible. BRIEF DESCRIPTION OF DRAWINGS

[0027] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a plan view illustrating a display device according to an embodiment of the disclosure.

[0029] Figure 2 is a circuit diagram illustrating a circuit structure of a pixel of Figure 1 .

[0030] Figure 3is a cross-sectional view showing a portion of the display area of Figure 1

[0031] Figure 4 is an enlarged plan view of area A of Figure 1

[0032] Figure 5 is a cross-sectional view taken along line I-I' of Figure 4

[0033] Figure 6 is an enlarged plan view of area B of Figure 1

[0034] Figure 7 is a cross-sectional view taken along line II-II' of Figure 6

[0035] Figure 8 is a plan view showing an embodiment of the first voltage line and the second voltage line of Figure 1

[0036] Figure 9 is a plan view showing an embodiment of the common voltage line of Figure 1

[0037] Figure 10 is a plan view showing an embodiment of the first voltage line and the second voltage line of Figure 1

[0038] Figure 11 is a plan view showing an embodiment of area C of Figure 1

[0039] Figure 12 , Figure 13 , Figure 14 and Figure 15 is a cross-sectional view showing an embodiment of a cross-section taken along line III-III' of Figure 11

[0040] Figure 16 is a plan view showing an embodiment of area C of Figure 1

[0041] Figure 17 is a plan view showing an embodiment of area C of Figure 1

[0042] Figure 18 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] ​​​​​​​​​​​​Hereinafter, a display device according to an embodiment of the disclosure will be described in detail with reference to the accompanying drawings. The inventive concept can be embodied in various modifications and can have various forms. However, it will be understood that the inventive concept is not intended to be limited to the particular forms disclosed and is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the inventive concept. The same reference numbers are used throughout the drawings to refer to the same components and redundant descriptions of the same components will be omitted or simplified. In the drawings, the thickness, proportions, and sizes of elements can be exaggerated for the sake of efficiency in explaining the technical content.

[0044] In this specification, a plane can be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 can be perpendicular to the second direction DR2. In addition, a third direction DR3 can be perpendicular to the plane.

[0045] Figure 1 is a plan view showing a display device according to an embodiment of the disclosure.

[0046] Referring to Figure 1 The display device DD according to an embodiment of the disclosure can include a plurality of pixels PX disposed on a substrate SUB, a display panel driver DPD, a circuit board CB, a first gate driver GDV1 and a second gate driver GDV2, a first gate signal line GL1 and a second gate signal line GL2, a common voltage supply line CVSL, a driving voltage supply line DVSL, a data line DL, a driving voltage line ELVDL, a common voltage line ELVSL, a transmission line SL, a first voltage line VL1 and a second voltage line VL2, and a first control signal line CSL1 and a second control signal line CSL2.

[0047] The display device DD can include a display area DA and a non-display area NDA. The display area DA can be an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area NDA can be an area in which an image is not displayed. The non-display area NDA can be disposed at a side of the display area DA. The non-display area NDA can surround at least a portion of the display area DA. For example, the non-display area NDA can completely surround the display area DA.

[0048] Since the display device DD includes the display area DA and the non-display area NDA, components included in the display device DD (e.g., the substrate SUB, etc.) can be disposed in the display area DA and / or the non-display area NDA and can correspondingly include the display area DA and / or the non-display area NDA.

[0049] The peripheral area NDA may include a bending area BA and a pad area PDA. In a plan view, the bending area BA may be located between the display area DA and the pad area PDA. The bending area BA may be bent along a bending axis extending in a first direction DR1. Furthermore, the pad area PDA may have a shape extending along a side of the display device DD. For example, the pad area PDA may have a shape extending along the first direction DR1.

[0050] A plurality of pixels PX may be arranged in the display area DA. Each pixel PX may include a drive transistor that may generate a drive current and a light-emitting element that may be electrically connected to the drive transistor and may generate light based on the drive current. Accordingly, the pixel PX may generate light based on the drive current. The pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 throughout the display area DA.

[0051] Drivers for driving the pixels PX may be provided in the peripheral area NDA. For example, a first gate driver GDV1, a second gate driver GDV2, and a display panel driver DPD may be provided in the peripheral area NDA.

[0052] In an embodiment, the light emitting element may also be provided in a portion of the peripheral area NDA adjacent to the edge portion of the display area DA. In this case, the driving transistor generating the driving current may not be provided in the peripheral area NDA.

[0053] For example, the first gate driver GDV1 may be disposed in the peripheral area NDA adjacent to the left edge portion of the display area DA. The first gate driver GDV1 may include at least one driver transistor. The first gate driver GDV1 may receive a first control signal from the display panel driver DPD and generate a first gate signal based on the first control signal. For example, the first gate signal may be Figure 2 For example, the first gate signal may be at least one of the gate signal GW, the gate signal GI, the gate signal GB, and the light emitting control signal EM.

[0054] For example, the second gate driver GDV2 may be provided in the peripheral area NDA adjacent to the right edge portion of the display area DA. The second gate driver GDV2 may include at least one driver transistor. The second gate driver GDV2 may receive a second control signal from the display panel driver DPD and generate a second gate signal based on the second control signal. For example, the second gate signal may be Figure 2 For example, the second gate signal may be at least one of the gate signal GW, the gate signal GI, the gate signal GB, and the light emitting control signal EM.

[0055] At least a portion of the data line DL, the first gate signal line GL1, the second gate signal line GL2, and the drive voltage line ELVDL connected to the pixel PX can be disposed in the display area DA. In an embodiment, a portion of the common voltage line ELVSL, a portion of the first voltage line VL1, and a portion of the second voltage line VL2 can be further disposed in the display area DA.

[0056] In addition, at least a portion of the first control signal line CSL1 connected to the first gate driver GDV1, the second control signal line CSL2 connected to the second gate driver GDV2, the drive voltage supply line DVSL connected to the display panel driver DPD, the common voltage supply line CVSL connected to the display panel driver DPD, and the transmission line SL connected to the common voltage supply line CVSL can be disposed in the non-display area NDA.

[0057] The first gate signal line GL1 can be electrically connected to the first gate driver GDV1 and can extend in the first direction DR1. The first gate signal line GL1 can receive the first gate signal from the first gate driver GDV1 and can provide the first gate signal to the pixel PX.

[0058] The second gate signal line GL2 can be electrically connected to the second gate driver GDV2 and can extend in the first direction DR1. The second gate signal line GL2 can receive the second gate signal from the second gate driver GDV2 and can provide the second gate signal to the pixel PX.

[0059] The data line DL can be electrically connected to the display panel driver DPD and can extend in the second direction DR2. The data line DL can receive the data voltage from the display panel driver DPD. The data voltage can be Figure 2 a data voltage DATA. The data line DL can provide the data voltage to the pixel PX.

[0060] In a plan view, the drive voltage supply line DVSL can be disposed between the display panel driver DPD and the display area DA. The drive voltage supply line DVSL can be electrically connected to the drive voltage line ELVDL. The drive voltage supply line DVSL can receive the drive voltage from the display panel driver DPD and can provide the drive voltage to the drive voltage line ELVDL. The drive voltage can be Figure 2 a drive voltage ELVDD.

[0061] The drive voltage line ELVDL can extend along the second direction DR2. The drive voltage line ELVDL can provide the drive voltage to the pixel PX.

[0062] The common voltage supply line CVSL can extend along the edge portion of the peripheral area NDA. That is, the common voltage supply line CVSL can be disposed to surround at least a portion of the display area DA. Specifically, the common voltage supply line CVSL can include a first portion extending in the second direction DR2 and disposed at a left edge portion of the peripheral area NDA, a second portion extending in the first direction DR1 from the first portion and disposed at an upper edge portion of the peripheral area NDA, and a third portion extending in the second direction DR2 from the second portion and disposed at a right edge portion of the peripheral area NDA. The common voltage supply line CVSL can receive a common voltage from the display panel driver DPD and can supply the common voltage to the cathode electrode. The common voltage can be Figure 2 a common voltage ELVSS. The cathode electrode can be Figure 3 a cathode electrode CME.

[0063] The transmission line SL can be connected to an end portion of the common voltage supply line CVSL adjacent to the pad area PDA. For example, the transmission line SL can be directly connected to the end portion of the common voltage supply line CVSL adjacent to the pad area PDA. The transmission line SL can extend along the edge portion of the peripheral area NDA between the display area DA and the common voltage supply line CVSL. The common voltage supply line CVSL can supply the common voltage to the cathode electrode through the transmission line SL.

[0064] The first voltage line VL1 can extend in the first direction DR1, and the second voltage line VL2 can extend in the second direction DR2. The first voltage line VL1 can be connected to the second voltage line VL2 through the contact hole.

[0065] In an embodiment, the first voltage line VL1 and the second voltage line VL2 can be connected to the transmission line SL. In this case, the common voltage can be applied to the first voltage line VL1 and the second voltage line VL2. Accordingly, the first voltage line VL1 and the second voltage line VL2 can supply the common voltage to the cathode electrode. However, embodiments of the disclosure are not necessarily limited thereto, and the first voltage line VL1 and the second voltage line VL2 can not be connected to the transmission line SL and the common voltage supply line CVSL. In this case, a voltage other than the common voltage can be applied to the first voltage line VL1 and the second voltage line VL2. The voltage other than the common voltage can be Figure 2 an initialization voltage VINT.

[0066] The common voltage line ELVSL can include a first common voltage line ELVSL1 and a second common voltage line ELVSL2. The first common voltage line ELVSL1 can extend in a first direction DR1, and the second common voltage line ELVSL2 can extend in a second direction DR2. In an embodiment, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be integrally formed. For example, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be formed by the same material in the same process.

[0067] In an embodiment, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be connected to the transmission line SL. Accordingly, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be electrically connected to the common voltage supply line CVSL. In this case, the common voltage can be applied to the first common voltage line ELVSL1 and the second common voltage line ELVSL2. Accordingly, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can provide the common voltage to the cathode electrode.

[0068] The first control signal line CSL1 can be electrically connected to the display panel driver DPD. The first control signal line CSL1 can receive the first control signal from the display panel driver DPD, and can provide the first control signal to the first gate driver GDV1.

[0069] The second control signal line CSL2 can be electrically connected to the display panel driver DPD. The second control signal line CSL2 can receive the second control signal from the display panel driver DPD, and can provide the second control signal to the second gate driver GDV2.

[0070] The display panel driver DPD can be disposed in the pad area PDA. The display panel driver DPD can be formed as an integrated circuit (IC). For example, when the substrate SUB of the display device DD includes glass, the display panel driver DPD can have a chip on glass (COG) structure disposed directly on the substrate SUB. In an example in which the substrate SUB includes plastic, the display panel driver DPD can have a chip on plastic (COP) structure disposed directly on the substrate SUB. However, embodiments of the present disclosure are not necessarily limited thereto.

[0071] The display panel driver DPD can generate various signals and / or voltages. For example, the display panel driver DPD can generate the first control signal, the second control signal, a driving voltage, a common voltage, and / or a data voltage.

[0072] The circuit board CB can be disposed in the pad area PDA. Specifically, the circuit board CB can partially overlap the pad area PDA. That is, a first portion of the circuit board CB can overlap the pad area PDA, and a second portion of the circuit board CB other than the first portion can not overlap the pad area PDA. The circuit board CB can be bonded to the substrate SUB through an adhesive layer. For example, the adhesive layer can be anisotropic conductive film. The circuit board CB can provide various signals and / or voltages to the display panel driver DPD.

[0073] For example, the circuit board CB can include a rigid printed circuit board (PCB), a flexible printed circuit board (FPCB), or a flexible flat cable (FFC). However, embodiments of the present disclosure are not necessarily limited thereto.

[0074] Figure 2 is a circuit diagram illustrating a circuit structure of a pixel of Figure 1 .

[0075] Referring to Figure 2 , each pixel PX can include a pixel driving circuit portion PC and a light emitting element LED electrically connected to the pixel driving circuit portion PC. The pixel driving circuit portion PC can generate a driving current Ioled, and the light emitting element LED can generate light based on the driving current Ioled.

[0076] The pixel driving circuit portion PC can include a storage capacitor Cst and a plurality of transistors. For example, the pixel driving circuit portion PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and the storage capacitor Cst.

[0077] In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a PMOS transistor, and each of the third transistor T3 and the fourth transistor T4 can be an NMOS transistor. However, embodiments of the present disclosure are not necessarily limited thereto.

[0078] When the pixel driving circuit portion PC includes an NMOS transistor and a PMOS transistor, an active pattern of the NMOS transistor can include an oxide semiconductor and an active pattern of the PMOS transistor can include a silicon semiconductor. However, embodiments of the present disclosure are not necessarily limited thereto. For example, the active pattern of the NMOS transistor can include a silicon semiconductor, and the active pattern of the PMOS transistor can include an oxide semiconductor.

[0079] The first transistor T1 can include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 can be connected to the first node N1. The first electrode of the first transistor T1 can be connected to the second node N2. The second electrode of the first transistor T1 can be connected to the third node N3. The first transistor T1 can provide a driving current Ioled to the light emitting element LED.

[0080] The second transistor T2 can include a gate electrode, a first electrode, and a second electrode. A first gate signal GW can be applied to the gate electrode of the second transistor T2. A data voltage DATA can be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 can be connected to the second node N2.

[0081] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the first gate signal GW has an activation level, the second transistor T2 can be turned on. In this case, the second transistor T2 can provide the data voltage DATA to the second node N2. When the first gate signal GW has a deactivation level, the second transistor T2 can be turned off. In this case, the second transistor T2 can block the supply of the data voltage DATA.

[0082] The third transistor T3 can include a gate electrode, a first electrode, and a second electrode. The first gate signal GW can be applied to the gate electrode of the third transistor T3. The first electrode of the third transistor T3 can be connected to the third node N3. The second electrode of the third transistor T3 can be connected between the first node N1 and the first electrode of the fourth transistor T4.

[0083] The fourth transistor T4 can include a gate electrode, a first electrode, and a second electrode. A second gate signal GI can be applied to the gate electrode of the fourth transistor T4. The first electrode of the fourth transistor T4 can be connected to the second electrode of the third transistor T3. An initialization voltage VINT can be applied to the second electrode of the fourth transistor T4.

[0084] The fourth transistor T4 can be turned on or off in response to the second gate signal GI. For example, when the second gate signal GI has an activation level, the fourth transistor T4 can be turned on. In this case, the fourth transistor T4 can provide the initialization voltage VINT to the second electrode of the third transistor T3. When the second gate signal GI has a deactivation level, the fourth transistor T4 can block the supply of the initialization voltage VINT.

[0085] The fifth transistor T5 can include a gate electrode, a first electrode, and a second electrode. The emission control signal EM can be applied to the gate electrode of the fifth transistor T5. The driving voltage ELVDD can be applied to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 can be connected to the second node N2.

[0086] The sixth transistor T6 can include a gate electrode, a first electrode, and a second electrode. The emission control signal EM can be applied to the gate electrode of the sixth transistor T6. The first electrode of the sixth transistor T6 can be connected to the third node N3. The second electrode of the sixth transistor T6 can be connected to the second electrode of the seventh transistor T7.

[0087] The fifth transistor T5 and the sixth transistor T6 can be turned on or off in response to the emission control signal EM. For example, when the emission control signal EM has an activation level, the fifth transistor T5 and the sixth transistor T6 can be turned on. In this case, the fifth transistor T5 and the sixth transistor T6 can supply the driving current Ioled generated by the first transistor T1 to the anode electrode of the light emitting element LED. When the emission control signal EM has a deactivation level, the fifth transistor T5 and the sixth transistor T6 can block the supply of the driving current Ioled generated by the first transistor T1.

[0088] The seventh transistor T7 can include a gate electrode, a first electrode, and a second electrode. The third gate signal GB can be applied to the gate electrode of the seventh transistor T7. The initialization voltage VINT can be applied to the first electrode of the seventh transistor T7. The second electrode of the seventh transistor T7 can be connected to the second electrode of the sixth transistor T6.

[0089] The seventh transistor T7 can be turned on or off in response to the third gate signal GB. For example, when the third gate signal GB has an activation level, the seventh transistor T7 can be turned on. In this case, the seventh transistor T7 can supply the initialization voltage VINT to the anode electrode of the light emitting element LED. When the third gate signal GB has a deactivation level, the seventh transistor T7 can block the supply of the initialization voltage VINT.

[0090] In an embodiment, the first electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a source electrode, and the second electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a drain electrode. However, embodiments of the present disclosure are not necessarily limited thereto, and the first electrode of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a drain electrode, and the second electrode of the remaining transistors of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a source electrode.

[0091] The storage capacitor Cst can include a first electrode and a second electrode. The drive voltage ELVDD can be applied to the first electrode of the storage capacitor Cst. The second electrode of the storage capacitor Cst can be connected to the first node N1.

[0092] The light emitting element LED can include an anode electrode and a cathode electrode. The anode electrode of the light emitting element LED can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The common voltage ELVSS can be applied to the cathode electrode of the light emitting element LED. The common voltage ELVSS can have a voltage level lower than that of the drive voltage ELVDD.

[0093] In Figure 2 , the pixel driving circuit portion PC is shown to include seven transistors and one capacitor. Embodiments of the present disclosure are not necessarily limited thereto.

[0094] Figure 3 is a cross-sectional view showing a portion of the display area of Figure 1 . For example, Figure 3 is a cross-sectional view showing the pixel PX, the data line DL, the first voltage line VL1, and the second voltage line VL2 of Figure 1 .

[0095] Referring to Figure 3 , the display device DD can include the substrate SUB, the inorganic insulating layer IOL, the first transistor TR1 and the second transistor TR2, the first organic insulating layer OL1, the second organic insulating layer OL2, and the third organic insulating layer OL3, the first voltage line VL1, the second voltage line VL2, the data line DL, the first connection electrode CE1 and the second connection electrode CE2, the pixel definition layer PDL, the light emitting element LED, the spacer SPC, and the encapsulation layer ENC.

[0096] Here, the inorganic insulating layer IOL can include a buffer layer BUF, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, and a fifth insulating layer IL5. The first transistor TR1 can include a first active pattern ACT1, a first gate electrode GE1, a second gate electrode GE2, a first source electrode SE1, and a first drain electrode DE1. The second transistor TR2 can include a second active pattern ACT2, a third gate electrode GE3, a second source electrode SE2, and a second drain electrode DE2. In addition, the light emitting element LED can include an anode electrode AE, a light emitting layer EML, and a cathode electrode CME. The encapsulating layer ENC can include a first inorganic encapsulating layer ENCl, an organic encapsulating layer ENC2, and a second inorganic encapsulating layer ENC3.

[0097] The substrate SUB can form a base of the display device DD. For example, the substrate SUB can include glass, quartz, silicon, or a polymer. In addition, the substrate SUB can have a single layer structure or a multi layer structure in which a plurality of layers including different materials can be stacked.

[0098] The buffer layer BUF can be disposed on the substrate SUB. The buffer layer BUF can inhibit or prevent diffusion of metal atoms or impurities from the substrate SUB. For example, the buffer layer BUF can inhibit or prevent diffusion of metal atoms or impurities from the substrate SUB to the first transistor TR1 and the second transistor TR2. For example, the buffer layer BUF can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. These can be used alone or in combination with each other.

[0099] The first active pattern ACT1 can be disposed on the buffer layer BUF. For example, the first active pattern ACT1 can include a metal oxide semiconductor, a silicon semiconductor, or an organic semiconductor. In an embodiment, the first active pattern ACT1 can include a silicon semiconductor such as polysilicon. The first active pattern ACT1 can include a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region. The first source region and the first drain region can have a higher conductivity than that of the first channel region.

[0100] The first insulating layer IL1 can be disposed on the buffer layer BUF. The first insulating layer IL1 can be disposed on the first active pattern ACT1. For example, the first insulating layer IL1 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. These can be used alone or in combination with each other.

[0101] A first gate electrode GE1 can be disposed on the first insulating layer IL1. In a plan view, the first gate electrode GE1 can overlap the first channel region of the first active pattern ACT1. For example, the first gate electrode GE1 can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used alone or in combination with each other.

[0102] A second insulating layer IL2 can be disposed on the first insulating layer IL1. The second insulating layer IL2 can be disposed on the first gate electrode GE1. For example, the second insulating layer IL2 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. These example materials can be used alone or in combination with each other.

[0103] A second gate electrode GE2 can be disposed on the second insulating layer IL2. In a plan view, the second gate electrode GE2 can overlap the first gate electrode GE1. For example, the second gate electrode GE2 can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used alone or in combination with each other.

[0104] A third insulating layer IL3 can be disposed on the second insulating layer IL2. The third insulating layer IL3 can be disposed on the second gate electrode GE2. For example, the third insulating layer IL3 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. These example materials can be used alone or in combination with each other.

[0105] A second active pattern ACT2 can be disposed on the third insulating layer IL3. For example, the second active pattern ACT2 can include a metal oxide semiconductor, a silicon semiconductor, or an organic semiconductor. In an embodiment, the second active pattern ACT2 can include a metal oxide semiconductor. The second active pattern ACT2 can include a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region. The second source region and the second drain region can have a higher electrical conductivity than that of the second channel region.

[0106] A fourth insulating layer IL4 can be disposed on the third insulating layer IL3. The fourth insulating layer IL4 can be disposed on the second active pattern ACT2. For example, the fourth insulating layer IL4 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. These example materials can be used alone or in combination with each other.

[0107] A third gate electrode GE3 can be disposed on the fourth insulating layer IL4. In a plan view, the third gate electrode GE3 can overlap the second channel region of the second active pattern ACT2. For example, the third gate electrode GE3 can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used alone or in combination with each other.

[0108] A fifth insulating layer IL5 can be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 can be disposed on the third gate electrode GE3. For example, the fifth insulating layer IL5 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. These example materials can be used alone or in combination with each other.

[0109] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can be disposed on the fifth insulating layer IL5. The first source electrode SE1 can be connected to a first source region of the first active pattern ACT1 through a contact hole that penetrates the inorganic insulating layer IOL except for the buffer layer BUF, and the first drain electrode DE1 can be connected to a first drain region of the first active pattern ACT1 through a contact hole that penetrates the inorganic insulating layer IOL except for the buffer layer BUF. For example, one or more first contact holes can be defined in the first to fifth insulating layers IL1, IL2, IL3, IL4, and IL5 to expose a portion of the first active pattern ACT1 disposed on the buffer layer BUF. Also, the second source electrode SE2 can be connected to a second source region of the second active pattern ACT2 through a contact hole that penetrates the fourth insulating layer IL4 and the fifth insulating layer IL5, and the second drain electrode DE2 can be connected to a second drain region of the second active pattern ACT2 through a contact hole that penetrates the fourth insulating layer IL4 and the fifth insulating layer IL5. For example, one or more second contact holes can be defined in the fourth insulating layer IL4 and the fifth insulating layer IL5 to expose a portion of the second active pattern ACT2 disposed on the third insulating layer IL3.

[0110] For example, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used alone or in combination with each other.

[0111] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can include the same material and can be formed through the same process.

[0112] Accordingly, the first transistor TR1 and the second transistor TR2 can be formed in the display area DA. For example, the first transistor TR1 can correspond to a sixth transistor T6 or a seventh transistor T7 of Figure 2 , and the second transistor TR2 can correspond to a third transistor T3 or a fourth transistor T4 of Figure 2 .

[0113] The first voltage line VL1 can be disposed on the fifth insulating layer IL5. In an embodiment, the first voltage line VL1 can be disposed in the same layer as the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. That is, the first voltage line VL1 can include the same material as the material of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2, and can be formed with the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 by the same process.

[0114] As described herein, the first voltage line VL1 can be applied with a common voltage or a voltage other than the common voltage. The common voltage can be a common voltage ELVSS of Figure 2 the common voltage ELVSS. The voltage other than the common voltage can be an initialization voltage VINT of Figure 2 the common voltage ELVSS.

[0115] The first organic insulating layer OL1 can be disposed on the fifth insulating layer IL5. The first organic insulating layer OL1 can sufficiently cover the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, and the first voltage line VL1. For example, the first organic insulating layer OL1 can include an organic material such as a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, or an epoxy resin. These example materials can be used alone or in combination with each other.

[0116] The first connection electrode CE1, the data line DL, and the second voltage line VL2 can be disposed on the first organic insulating layer OL1. The first connection electrode CE1 can be connected to the first drain electrode DE1 (or the first source electrode SE1) through a contact hole that penetrates the first organic insulating layer OL1. The second voltage line VL2 can be connected to the first voltage line VL1 through a contact hole that penetrates the first organic insulating layer OL1. For example, one or more fourth contact holes can be defined in the first organic insulating layer OL1.

[0117] For example, the first connection electrode CE1 can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used alone or in combination with each other. In addition, the first connection electrode CE1, the data line DL, and the second voltage line VL2 can include the same material, and can be formed by the same process.

[0118] However, embodiments of the present disclosure are not necessarily limited thereto. For example, the first voltage line VL1 can be disposed on the first organic insulating layer OL1, and the second voltage line VL2 can be disposed on the fifth insulating layer IL5.

[0119] A second organic insulating layer OL2 can be disposed on the first organic insulating layer OL1. The second organic insulating layer OL2 can sufficiently cover the first connection electrode CE1, the data line DL, and the second voltage line VL2. For example, the second organic insulating layer OL2 can include an organic material such as a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, or an epoxy resin. These example materials can be used alone or in combination with each other.

[0120] A second connection electrode CE2 can be disposed on the second organic insulating layer OL2. The second connection electrode CE2 can be connected to the first connection electrode CE1 through a contact hole that penetrates the second organic insulating layer OL2. For example, one or more fifth contact holes can be defined in the second organic insulating layer OL2. For example, the second connection electrode CE2 can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used alone or in combination with each other.

[0121] A third organic insulating layer OL3 can be disposed on the second organic insulating layer OL2. The third organic insulating layer OL3 can sufficiently cover the second connection electrode CE2. For example, the third organic insulating layer OL3 can include an organic material such as a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, or an epoxy resin. These example materials can be used alone or in combination with each other.

[0122] An anode electrode AE can be disposed on the third organic insulating layer OL3. The anode electrode AE can be connected to the second connection electrode CE2 through a contact hole that penetrates the third organic insulating layer OL3. For example, one or more sixth contact holes can be defined in the third organic insulating layer OL3. The anode electrode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. For example, the anode electrode AE can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used alone or in combination with each other.

[0123] A pixel definition layer PDL can be disposed on the third organic insulating layer OL3. The pixel definition layer PDL can define a pixel opening that exposes at least a portion of the anode electrode AE. The pixel definition layer PDL can include an inorganic material and / or an organic material. For example, the pixel definition layer PDL can include an organic material such as an epoxy resin or a siloxane resin. These example materials can be used alone or in combination with each other. In another example, the pixel definition layer PDL can include an inorganic material and / or an organic material including a light-shielding material such as a black pigment or a black dye.

[0124] A spacer SPC can be disposed on the pixel defining layer PDL. The spacer SPC can be used to support a mask used in a process of forming an emission layer EML. The spacer SPC can be formed with the pixel defining layer PDL through separate processes. In another example, the spacer SPC can be formed simultaneously with the pixel defining layer PDL through the same process. For example, the spacer SPC can include an organic material such as polyimide.

[0125] The emission layer EML can be disposed on the anode electrode AE. In particular, the emission layer EML can be disposed in the pixel opening of the pixel defining layer PDL. For example, the emission layer EML can include a light emitting material that can generate light of a specific color. For example, the emission layer EML can generate red light, green light, or blue light. Embodiments are not limited thereto. For example, the emission layer EML can generate white light.

[0126] The cathode electrode CME can be disposed on at least a portion of each of the pixel defining layer PDL, the spacer SPC, and the emission layer EML. The cathode electrode CME can be disposed throughout the entire display area DA. The cathode electrode CME can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. For example, the cathode electrode CME can include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. These example materials can be used individually or in combination with each other.

[0127] Accordingly, a light emitting element LED can be formed in the display area DA. The light emitting element LED can be electrically connected to the first transistor TR1.

[0128] An encapsulation layer ENC can be disposed on the cathode electrode CME. The encapsulation layer ENC can cover at least a portion of the light emitting element LED. The encapsulation layer ENC can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, as described herein, the encapsulation layer ENC can include a first inorganic encapsulation layer ENCl, a second inorganic encapsulation layer ENC3, and an organic encapsulation layer ENC2 disposed between the first inorganic encapsulation layer ENCl and the second inorganic encapsulation layer ENC3.

[0129] For example, the first inorganic encapsulation layer ENCl and the second inorganic encapsulation layer ENC3 can include a silicon compound or a metal oxide. The organic encapsulation layer ENC2 can include a polymer-based material. Examples of the polymer-based material can include an acrylic resin, an epoxy resin, or a polyimide resin. These example materials can be used individually or in combination with each other.

[0130] Figure 4 is an enlarged plan view of the area A of Figure 1 is a cross-sectional view taken along line I-I’ of Figure 5 is a cross-sectional view taken along line I-I’ of Figure 4 is a cross-sectional view taken along line I-I’ of Figure 6 isFigure 1 is an enlarged plan view of the region B. Figure 7 is a cross-sectional view taken along Figure 6 line II-II’.

[0131] For example, Figure 4 is an enlarged plan view of a portion of the display region DA from a common voltage supply line CVSL provided at a left edge portion of the peripheral region NDA. Figure 6 is an enlarged plan view of a portion of the display region DA from a common voltage supply line CVSL provided at an upper edge portion of the peripheral region NDA. For ease of illustration, in Figure 4 and Figure 6 only some of the metal layers constituting the common voltage supply line CVSL are shown.

[0132] Hereinafter, content that is repetitive of that described with respect to the display device DD of Reference Figure 3 may be omitted or simplified.

[0133] With reference to Figure 4 , Figure 5 , Figure 6 and Figure 7 , the first gate driver GDV1 can include a first driver transistor TR1_G and a second driver transistor TR2_G. The first control signal line CSL1 connected to the first gate driver GDV1 can include a first connection line CL1 and a second connection line CL2 provided on the first connection line CL1. For example, the first connection line CL1 can be provided in the same layer as the first source electrode SE1 and the first drain electrode DE1 of Figure 3 and can include the same material as that of the first source electrode SE1 and the first drain electrode DE1 of Figure 3 , and the second connection line CL2 can be provided in the same layer as the first connection electrode CE1 of Figure 3 and can include the same material as that of the first connection electrode CE1 of Figure 3 . However, embodiments of the present disclosure are not necessarily limited thereto. Figure 1 The second control signal line CSL2 of

[0134] The buffer layer BUF and the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 can extend from the display region DA to the peripheral region NDA. In addition, the first organic insulating layer OL1, the second organic insulating layer OL2, and the third organic insulating layer OL3 and the pixel definition layer PDL can extend from the display region DA to the peripheral region NDA.

[0135] In an embodiment, in the peripheral area NDA, a first opening OP1 exposing a portion of the fifth insulating layer IL5 can be defined in the first organic insulating layer OL1, and a second opening OP2 exposing the first opening OP1 can be defined in the second organic insulating layer OL2, and a third-first opening OP31 exposing the second opening OP2 can be defined in the third organic insulating layer OL3. In addition, a third-second opening OP32 spaced apart from the third-first opening OP31 can be further defined in the third organic insulating layer OL3.

[0136] The second opening OP2 can be spatially connected to the first opening OP1, and the third-first opening OP31 can be spatially connected to the second opening OP2. Accordingly, the first opening OP1, the second opening OP2, and the third-first opening OP31 can form a valley portion VH.

[0137] The valley portion VH can be disposed to surround at least a portion of the display area DA. In a plan view, the valley portion VH can be disposed between the common voltage supply line CVSL and the transmission line SL. In addition, in the plan view, the valley portion VH can overlap the first gate driver GDV1. The valley portion VH can separate each of the first organic insulating layer OL1, the second organic insulating layer OL2, the third organic insulating layer OL3, and the pixel definition layer PDL, thereby blocking or reducing a path through which moisture can penetrate into the display area DA from the outside of the substrate SUB through the organic layer.

[0138] The display device DD can further include a first dam DAM1 and a second dam DAM2 disposed in the peripheral area NDA. The first dam DAM1 can be closer to an edge portion of the peripheral area NDA than the second dam DAM2. In addition, the first dam DAM1 can be disposed to be spaced apart from the second dam DAM2.

[0139] The first dam DAM1 can be disposed to overlap an outer edge portion of the common voltage supply line CVSL. The first dam DAM1 can include a plurality of insulating layers. In an embodiment, the first dam DAM1 can include a first-first sub-layer SL11, a first-second sub-layer SL12, a first-third sub-layer SL13, and a first-fourth sub-layer SL14 sequentially stacked on an inorganic insulating layer IOL in the third direction DR3. However, embodiments of the disclosure are not necessarily limited thereto. For example, some of the first-first sub-layer SL11, the first-second sub-layer SL12, the first-third sub-layer SL13, and the first-fourth sub-layer SL14 can be omitted.

[0140] In an embodiment, the first-first sub-layer SL11 may include the same material as the first organic insulating layer OL1 and may be formed by the same process as the first organic insulating layer OL1. The first-second sub-layer SL12 may include the same material as the second organic insulating layer OL2 and may be formed by the same process as the second organic insulating layer OL2. The first-third sub-layer SL13 may include the same material as the pixel defining layer PDL and may be formed by the same process as the pixel defining layer PDL. The first-fourth sub-layer SL14 may include the same material as the first organic insulating layer OL1 and may be formed by the same process as the first organic insulating layer OL2. Figure 3 The material of the spacer SPC is the same material and can be used with Figure 3 The spacer SPC is formed by the same process.

[0141] The second dam DAM2 may be disposed on the common voltage supply line CVSL. The second dam DAM2 may include a plurality of insulating layers. In an embodiment, the second dam DAM2 may include a second-first sub-layer SL21, a second-second sub-layer SL22, and a second-third sub-layer SL23 sequentially stacked on the inorganic insulating layer IOL. However, embodiments of the present disclosure are not necessarily limited thereto. For example, some of the second-first sub-layer SL21, the second-second sub-layer SL22, and the second-third sub-layer SL23 may be omitted.

[0142] In an embodiment, the second-first sub-layer SL21 may include the same material as the second organic insulating layer OL2 and may be formed by the same process as the second organic insulating layer OL2. The second-second sub-layer SL22 may include the same material as the pixel defining layer PDL and may be formed by the same process as the pixel defining layer PDL. The second-third sub-layer SL13 may include the same material as the second organic insulating layer OL2 and may be formed by the same process as the second organic insulating layer OL2. Figure 3 The material of the spacer SPC is the same material and can be used with Figure 3 The spacer SPC is formed by the same process.

[0143] The common voltage supply line CVSL may include a plurality of metal layers sequentially stacked in the third direction DR3. In an embodiment, the common voltage supply line CVSL may include a first metal line ML1, a second metal line ML2, a third metal line ML3 and a connection pattern CNP sequentially stacked on the inorganic insulating layer IOL in the third direction DR3.

[0144] The end of the first metal line ML1 may be covered by the first-first sub-layer SL11 and the first organic insulating layer OL1. In an embodiment, the first metal line ML1 may include Figure 3 The material of the first source electrode SE1 and the first drain electrode DE1 is the same material and can be Figure 3 The first source electrode SE1 and the first drain electrode DE1 are formed by the same process.

[0145] The second metal line ML2 may contact the first metal line ML1. The end of the second metal line ML2 may contact the upper surface of the first-first sub-layer SL11 and the upper surface of the first organic insulating layer OL1. In addition, the end of the second metal line ML2 may be covered by the first-second sub-layer SL12 and the second organic insulating layer OL2. In an embodiment, the second metal line ML2 may include Figure 3 The material of the first connection electrode CE1 is the same as that of Figure 3 The first connection electrode CE1 is formed by the same process.

[0146] The third metal line ML3 may contact the second metal line ML2. The third metal line ML3 may be disposed on the second-first sub-layer SL21, and an end portion of the third metal line ML3 may contact an upper surface of the first-second sub-layer SL12 and an upper surface of the second organic insulating layer OL2. In addition, an end portion of the third metal line ML3 may be covered by the first-third sub-layer SL13 and the third organic insulating layer OL3. In an embodiment, the third metal line ML3 may include Figure 3 The second connection electrode CE2 is made of the same material and can be Figure 3 The second connection electrode CE2 is formed by the same process.

[0147] The connection pattern CNP may contact the third metal line ML3. Furthermore, the connection pattern CNP may be arranged to cover the first, second, and third metal lines ML1, ML2, and ML3, the valley VH, and the transmission line SL. That is, the connection pattern CNP may extend from the first, second, and third metal lines ML1, ML2, and ML3 through the upper surface of the third organic insulating layer OL3 and the valley VH to the transmission line SL. Furthermore, the connection pattern CNP may contact the transmission line SL through the third-second opening OP32. Accordingly, the common voltage supply line CVSL and the transmission line SL may be electrically connected via the connection pattern CNP.

[0148] In an embodiment, the connection pattern CNP may include Figure 3 The material of the anode electrode AE ​​is the same material and can be Figure 3 The anode electrode AE ​​is formed by the same process.

[0149] A plurality of through holes HL may be defined in the connection pattern CNP, except for the region where the valley VH is provided. Some of the through holes HL may expose at least a portion of the third metal line ML3, and other portions may expose at least a portion of the third organic insulating layer OL3. The through holes HL may serve as a path for exhausting gas generated from the organic layer provided below the connection pattern CNP.

[0150] In an embodiment, the transmission line SL can be disposed on the second organic insulating layer OL2. That is, the transmission line SL can be disposed in the same layer as the second connection electrode CE2 of the second thin film transistor T2. Figure 3 The transmission line SL can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2. Figure 3 The transmission line SL can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2. Figure 3 The transmission line SL can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2.

[0151] In an embodiment, the connection pattern CNP can overlap the control signal lines (e.g., the first control signal line CSL1 and the second control signal line CSL2 of the second thin film transistor T2) in a plan view, and can be spaced apart from the control signal lines in the third direction DR3. For example, the connection pattern CNP disposed on the third metal line ML3 and the transmission line SL can be spaced apart from the control signal lines. Accordingly, coupling between the control signal lines and the third metal line ML3 and the transmission line SL can be suppressed or prevented. Figure 1 A portion of the first voltage line VL1 can extend to the peripheral area NDA. In addition, a portion of the second voltage line VL2 can extend to the peripheral area NDA.

[0152] The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be disposed on the first voltage line VL1 and the second voltage line VL2. In an embodiment, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be disposed in the same layer as the second connection electrode CE2 of the second thin film transistor T2. That is, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2.

[0153] The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2. Figure 3 The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2. Figure 3 The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2. Figure 3 The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can include the same material as the material of the second connection electrode CE2 of the second thin film transistor T2, and can be formed through the same process as the second connection electrode CE2 of the second thin film transistor T2.

[0154] The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be integrally formed with the transmission line SL. Accordingly, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be electrically connected to the common voltage supply line CVSL through the transmission line SL to receive a common voltage (e.g., the common voltage ELVSS of the second thin film transistor T2). Figure 2 The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be integrally formed with the transmission line SL. Accordingly, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be electrically connected to the common voltage supply line CVSL through the transmission line SL to receive a common voltage (e.g., the common voltage ELVSS of the second thin film transistor T2).

[0155] In an embodiment, the transmission line SL can be connected to the first voltage line VL1 through a first contact hole CNT1 that penetrates the first organic insulating layer OL1 and the second organic insulating layer OL2, and can be connected to the second voltage line VL2 through a second contact hole CNT2 that penetrates the second organic insulating layer OL2. Accordingly, the first voltage line VL1 and the second voltage line VL2 can be electrically connected to the common voltage supply line CVSL through the transmission line SL to receive the common voltage. In another example, the first voltage line VL1 and the second voltage line VL2 can not be connected to the transmission line SL.

[0156] The cathode electrode CME can extend from the display area DA to the peripheral area NDA. Specifically, the cathode electrode CME can extend from the display area DA to a position overlapping with an end portion of the third metal line ML3 contacting the third organic insulating layer OL3.

[0157] The cathode electrode CME can contact the connection pattern CNP of the common voltage supply line CVSL in the peripheral area NDA. Specifically, the cathode electrode CME can contact the connection pattern CNP at a portion of the pixel definition layer PDL located between the through holes HL and at the valley portion VH. Accordingly, the common voltage supply line CVSL can be electrically connected to the cathode electrode CME and can supply the common voltage to the cathode electrode CME.

[0158] The encapsulation layer ENC can extend from the display area DA to the peripheral area NDA. The first inorganic encapsulation layer ENCl and the second inorganic encapsulation layer ENC3 of the encapsulation layer ENC can be disposed on the entire surface of the substrate SUB. The organic encapsulation layer ENC2 can extend from the display area DA to the second dam DAM2. In another example, the organic encapsulation layer ENC2 can extend from the display area DA to the first dam DAM1.

[0159] Figure 8 is a plan view illustrating an embodiment of the first voltage line and the second voltage line of Figure 1 .

[0160] Referring to Figure 8 , the transmission line SL can include a first transmission line portion SLP11, a second transmission line portion SLP12, and a third transmission line portion SLP13.

[0161] The first transmission line portion SLP11 can be disposed at a left edge portion of the peripheral area NDA and can extend in the second direction DR2. The third transmission line portion SLP13 can be disposed at a right edge portion of the peripheral area NDA and can extend in the second direction DR2. The second transmission line portion SLP12 can connect the first transmission line portion SLP11 and the third transmission line portion SLP13, can be disposed at an upper edge portion of the peripheral area NDA, and extend in the first direction DR1.

[0162] In the display area DA, a plurality of first voltage lines VL1 and a plurality of second voltage lines VL2 can be provided. The plurality of first voltage lines VL1 can be disposed along the second direction DR2, and the plurality of second voltage lines VL2 can be disposed along the first direction DR1.

[0163] As described herein, in an embodiment, the first voltage lines VL1 and the second voltage lines VL2 can be connected to the transmission lines SL. Specifically, the first voltage lines VL1 can be directly connected to the first transmission line portions SLP11 and the third transmission line portions SLP13, and the second voltage lines VL2 can be directly connected to the second transmission line portions SLP12. In addition, the second voltage lines VL2 can be directly connected to an end portion of the common voltage supply line CVSL adjacent to a pad area (e.g., a pad area PDA) of the display area DA. Accordingly, a common voltage can be applied to the first voltage lines VL1 and the second voltage lines VL2. Figure 1

[0164] In an embodiment, the first voltage lines VL1 and the second voltage lines VL2 can have a grid structure in some regions of the display area DA, and can not have a grid structure in remaining regions of the display area DA (i.e., regions adjacent to the pad area). For example, the first voltage lines VL1 and the second voltage lines VL2 can form a grid structure together in some regions of the display area DA.

[0165] In an embodiment, in a region adjacent to an edge portion of the display area DA adjacent to the pad area, the first voltage lines VL1 can be divided into a second portion VL12 connected to the second voltage lines VL2, a first portion VL11 spaced apart from the second portion VL12 in a direction opposite to the first direction DR1 and connected to the first transmission line portions SLP11 and the second voltage lines VL2, and a third portion VL13 spaced apart from the second portion VL12 in the first direction DR1 and connected to the third transmission line portions SLP13 and the second voltage lines VL2.

[0166] The second voltage lines VL2 can include a first portion VL21, a second portion VL22, and a third portion VL23. The first portion VL21 of the second voltage lines VL2 can be disposed at a left edge portion of the display area DA, and can be directly connected to a lower portion of the common voltage supply line CVSL. The third portion VL23 of the second voltage lines VL2 can be disposed at a right edge portion of the display area DA, and can be directly connected to a lower portion of the common voltage supply line CVSL. In addition, the second portion VL22 of the second voltage lines VL2 can be disposed at a center of the display area DA, and connected to the second portion VL12 of the first voltage lines VL1.

[0167] ​For example, a length of the second portion VL22 of the second voltage line VL2 in the second direction DR2 can be shorter than a length of each of the first portion VL21 and the third portion VL23 of the second voltage line VL2 in the second direction DR2.

[0168] Figure 9 is a plan view showing an embodiment of the common voltage line. Figure 1

[0169] Hereinafter, a description overlapping with the contents described with reference to FIGS. 1A to 1C can be omitted or simplified. Figure 8

[0170] With reference to Figure 9 As described herein, the common voltage line ELVSL can include a first common voltage line ELVSL1 and a second common voltage line ELVSL2. The first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be integrally formed.

[0171] A plurality of first common voltage lines ELVSL1 can be provided, and a plurality of second common voltage lines ELVSL2 can be provided. The plurality of first common voltage lines ELVSL1 can be arranged along the second direction DR2, and the plurality of second common voltage lines ELVSL2 can be arranged along the first direction DR1.

[0172] As described herein, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can be integrally formed with the transmission line SL. Specifically, the first common voltage line ELVSL1 can be directly connected to the first transmission line portion SLP11 and the third transmission line portion SLP13, and the second common voltage line ELVSL2 can be directly connected to the second transmission line portion SLP12. In addition, the second common voltage line ELVSL2 can be directly connected to a lower portion of the common voltage supply line CVSL adjacent to the pad area. Accordingly, a common voltage can be applied to the first common voltage line ELVSL1 and the second common voltage line ELVSL2.

[0173] In an embodiment, the first common voltage line ELVSL1 and the second common voltage line ELVSL2 can have a grid structure throughout the display area DA.

[0174] ​​The second common voltage line ELVSL2 can include a first portion ELVSL21, a second portion ELVSL22, and a third portion ELVSL23. The first portion ELVSL21 of the second common voltage line ELVSL2 can be disposed at a left edge portion of the display area DA and can be directly connected to a lower portion of the common voltage supply line CVSL. The third portion ELVSL23 of the second common voltage line ELVSL2 can be disposed at a right edge portion of the display area DA and can be directly connected to a lower portion of the common voltage supply line CVSL. In addition, the second portion ELVSL22 of the second common voltage line ELVSL2 can be disposed at a center of the display area DA.

[0175] For example, a length of the second portion ELVSL22 of the second common voltage line ELVSL2 in the second direction DR2 can be shorter than a length of each of the first portion ELVSL21 and the third portion ELVSL23 of the second common voltage line ELVSL2 in the second direction DR2.

[0176] Figure 10 is a plan view illustrating an embodiment of the first and second voltage lines of Figure 1 .

[0177] Hereinafter, a content which is repeated with the content described with reference to Figure 8 may be omitted or simplified.

[0178] With reference to Figure 10 , in an embodiment, the first and second voltage lines VL1 and VL2 can not be connected to the transmission line SL and the common voltage supply line CVSL. In this case, a voltage other than the common voltage can be applied to the first and second voltage lines VL1 and VL2.

[0179] Figure 10 The arrangement of the first and second voltage lines VL1 and VL2 in the display area DA of Figure 8 may be substantially the same as the arrangement of the first and second voltage lines VL1 and VL2 in the display area DA of

[0180] Figure 11 is a plan view illustrating an embodiment of the area C of Figure 1 .

[0181] With reference to Figure 11 , as described herein, the display area DA can include a driving voltage line ELVDL, a data line DL, a first voltage line VL1, a second voltage line VL2, and a common voltage line ELVSL. The common voltage line ELVSL can include a first common voltage line ELVSL1 and a second common voltage line ELVSL2.

[0182] The driving voltage lines ELVDL, the data lines DL, and the second voltage lines VL2 can be disposed in the same layer and can include the same material.

[0183] In an embodiment, in a plan view, the second voltage lines VL2 can be disposed between adjacent data lines DL. For example, in a plan view, two second voltage lines VL2 can be disposed between two data lines DL.

[0184] The anode electrodes AE can be disposed on the driving voltage lines ELVDL, the data lines DL, the first voltage lines VL1, the second voltage lines VL2, and the common voltage lines ELVSL. In a plan view, the anode electrodes AE can at least partially overlap the driving voltage lines ELVDL, the data lines DL, the first voltage lines VL1, the second voltage lines VL2, and the common voltage lines ELVSL. In this case, the light emitting layer disposed on the anode electrodes AE can include a light emitting material that can generate red light or blue light. Accordingly, a mura phenomenon that can be caused by coupling between the data lines DL and the anode electrodes AE can be improved. The mura phenomenon refers to uniformity or consistency (or non-uniformity or inconsistency) in, for example, brightness, color, or texture across a display panel.

[0185] At least one of the first voltage lines VL1 can include a first disconnected portion DCP1, and at least one of the second voltage lines VL2 can include a second disconnected portion DCP2.

[0186] At least some of the driving voltage lines ELVDL can extend in the second direction DR2 to cover (or shield) the first disconnected portions DCP1 of the first voltage lines VL1. Also, in an embodiment, some of the first common voltage lines ELVSL1 can overlap the first voltage lines VL1 in a plan view and can extend in the first direction DR1 to cover (or shield) the first disconnected portions DCP1 of the first voltage lines VL1. Accordingly, the first disconnected portions DCP1 can be invisible.

[0187] At least some of the anode electrodes AE can cover (or shield) the second disconnected portions DCP2 of the second voltage lines VL2. Accordingly, the second disconnected portions DCP2 can be invisible.

[0188] In an embodiment, at least some of the second common voltage lines ELVSL2 can extend in the second direction DR2 to cover (or shield) portions of the data lines DL that overlap the anode electrodes AE. Accordingly, a mura phenomenon that can be caused by coupling between the data lines DL and the anode electrodes AE can be further improved.

[0189] Figure 12 、 Figure 13 、 Figure 14 and Figure 15is a cross-sectional view of an embodiment showing a cross-section taken along line III-III' of Figure 11 In Figure 12 to Figure 15 , the components can be illustrated as having different cross-hatching according to different layers of material as illustrated in Figure 3 and as will be described below.

[0190] Referring to Figure 11 and Figure 12 , in an embodiment, the first voltage line VL1 can be disposed in the same layer as the first source electrode SE1 and the first drain electrode DE1 of Figure 3 . The first voltage line VL1, the first source electrode SE1, and the first drain electrode DE1 can include the same material. The first voltage line VL1, the first source electrode SE1, and the first drain electrode DE1 can be formed by the same process. The data line DL and the second voltage line VL2 can be disposed in the same layer as the first connection electrode CE1 of Figure 3 . The data line DL and the second voltage line VL2 can include the same material as the material of the first connection electrode CE1 of Figure 3 , and can be formed by the same process as the first connection electrode CE1 of Figure 3 . Further, the common voltage line ELVSL can be disposed in the same layer as the second connection electrode CE2 of Figure 3 , can include the same material as the material of the second connection electrode CE2 of Figure 3 , and can be formed by the same process as the second connection electrode CE2 of Figure 3 .

[0191] Referring to Figure 11 and Figure 13 , in another embodiment, the first voltage line VL1 can be disposed in the same layer as the first source electrode SE1 and the first drain electrode DE1 of Figure 3 , can include the same material as the material of the first source electrode SE1 and the first drain electrode DE1 of Figure 3 , and can be formed by the same process as the first source electrode SE1 and the first drain electrode DE1 of Figure 3 . The common voltage line ELVSL can be disposed in the same layer as the first connection electrode CE1 of Figure 3 , can include the same material as the material of the first connection electrode CE1 of Figure 3 , and can be formed by the same process as the first connection electrode CE1 of Figure 3 . Further, the data line DL and the second voltage line VL2 can be disposed in the same layer as the second connection electrode CE2 of Figure 3 , can include the same material as the material of the second connection electrode CE2 of Figure 3 , and can be formed by the same process as the second connection electrode CE2 of Figure 3 .

[0192] refer to Figure 11 and Figure 14 In another embodiment, the data line DL and the second voltage line VL2 can be connected to Figure 3 The first source electrode SE1 and the first drain electrode DE1 are provided in the same layer and may include Figure 3 The material of the first source electrode SE1 and the first drain electrode DE1 is the same material and can be Figure 3 The first source electrode SE1 and the first drain electrode DE1 are formed by the same process. The common voltage line ELVSL can be connected to Figure 3 The first connection electrode CE1 is provided in the same layer and may include Figure 3 The material of the first connection electrode CE1 is the same as that of Figure 3 The first connection electrode CE1 is formed by the same process. In addition, the first voltage line VL1 can be connected to the Figure 3 The second connection electrode CE2 is provided in the same layer and may include Figure 3 The second connection electrode CE2 is made of the same material and can be Figure 3 The second connection electrode CE2 is formed by the same process.

[0193] refer to Figure 11 and Figure 15 In another embodiment, the data line DL and the second voltage line VL2 can be connected to Figure 3 The first source electrode SE1 and the first drain electrode DE1 are provided in the same layer and may include Figure 3 The material of the first source electrode SE1 and the first drain electrode DE1 is the same material and can be Figure 3 The first source electrode SE1 and the first drain electrode DE1 are formed by the same process. The first voltage line VL1 can be connected to Figure 3 The first connection electrode CE1 is provided in the same layer and may include Figure 3 The material of the first connection electrode CE1 is the same as that of Figure 3 The first connection electrode CE1 is formed by the same process. In addition, the common voltage line ELVSL can be connected to the common voltage line ELVSL. Figure 3 The second connection electrode CE2 is provided in the same layer and may include Figure 3 The second connection electrode CE2 is made of the same material and can be Figure 3 The second connection electrode CE2 is formed by the same process.

[0194] Figure 16 It shows Figure 1 A plan view of an embodiment of area C. Figure 17 It shows Figure 1a plan view of an embodiment of region C.

[0195] In the following, it can be omitted or simplified to refer to Figure 11 repetitive content of the description.

[0196] Reference is made to Figure 16 and Figure 17 As described herein, some of the anode electrodes AE can cover (or shield) the second disconnected portion DCP2 of the second voltage line VL2. In addition, in embodiments, the common voltage lines ELVSL’ and ELVSL” can cover (or shield) the second disconnected portion DCP2 of the second voltage line VL2. In particular, the second common voltage line ELVSL2 of the common voltage lines ELVSL’ and ELVSL” can cover (or shield) the second disconnected portion DCP2. Accordingly, the second disconnected portion DCP2 can be invisible.

[0197] For example, as shown in Figure 16 the second common voltage line ELVSL2 of the common voltage line ELVSL’ can include a protrusion PP that protrudes in the first direction DR1 and covers (or shields) the second disconnected portion DCP2.

[0198] In another example, as shown in Figure 17 the second common voltage line ELVSL2 of the common voltage line ELVSL” can be divided into a first pattern that covers portions of the data lines DL overlapping with the anode electrodes AE, a second pattern overlapping with the second voltage line VL2 and covering (or shielding) the second disconnected portion DCP2, and a third pattern covering portions of the data lines DL overlapping with the anode electrodes AE and spaced apart from the first pattern, the second pattern being between the first pattern and the third pattern. Each of the first pattern, the second pattern, and the third pattern can extend in the second direction DR2.

[0199] Reference is again made to Figure 1 to Figure 17According to embodiments of the disclosure, the display device DD can include a common voltage supply line CVSL disposed in the peripheral area NDA, a transmission line SL disposed in the peripheral area NDA, and a common voltage line ELVSL, ELVSL', or ELVSL'' disposed in the display area DA. The common voltage supply line CVSL can provide a common voltage ELVSS and include a first metal line ML1, a second metal line ML2, a third metal line ML3, and a connection pattern CNP sequentially stacked. The transmission line SL can include the same material as that of the third metal line ML3 and be connected to the common voltage supply line CVSL through the connection pattern CNP. The common voltage line ELVSL, ELVSL', or ELVSL'' can be integrally formed with the transmission line SL and have a mesh structure throughout the display area DA. Accordingly, a voltage drop (IR drop) of the common voltage ELVSS can be minimized or reduced. In this case, power consumption of the display device DD can be improved.

[0200] In addition, the common voltage line ELVSL, ELVSL', or ELVSL'' includes a first common voltage line ELVSL1 extending in the first direction DR1 and a second common voltage line ELVSL2 extending in the second direction DR2, and the second common voltage line ELVSL2 can cover (or shield) at least a portion of the data line DL overlapping the anode electrode AE. In addition, the first common voltage line ELVSL1 can cover (or shield) the first disconnected portion DCP1 of the first voltage line VL1, and the second common voltage line ELVSL2 can cover (or shield) the second disconnected portion DCP2 of the second voltage line VL2. Accordingly, coupling between the data line DL and the anode electrode AE can be suppressed or prevented, and the first disconnected portion DCP1 and the second disconnected portion DCP2 can be invisible.

[0201] Figure 18 FIG. 1 is a block diagram illustrating an electronic device according to an embodiment of the disclosure.

[0202] Referring to FIG. 1, Figure 18 In an embodiment, the electronic device 900 can include a processor 910, a memory device 920, a storage device 930, an input / output (I / O) device 940, a power supply 950, and a display device 960. In this case, the display device 960 can correspond to the display device DD described with reference to FIGS. 1 to 8. The electronic device 900 can further include several ports capable of communicating with a video card, a sound card, a memory card, and a USB device, etc. Figure 1 to Figure 17

[0203] ​In an embodiment, the electronic device 900 can be implemented as a television. In another embodiment, the electronic device 900 can be implemented as a smart phone. However, the electronic device 900 is not limited thereto, and for example, the electronic device 900 can be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation device, a computer monitor, a laptop computer, a head-mounted display (HMD), or the like.

[0204] The processor 910 can perform a specific computation or task. The processor 910 can control the display device 960. In an embodiment, the processor 910 can be a microprocessor, a central processing unit (CPU), and / or an application processor (AP), or the like. The processor 910 can be connected to other components through an address bus, a control bus, and a data bus, or the like. The processor 910 can also be connected to an extension bus such as a peripheral component interconnect (PCI) bus.

[0205] The memory device 920 can store data required for the operation of the electronic device 900. For example, the memory device 920 can include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, or the like.

[0206] The storage device 930 can include a solid state drive (SSD), a hard disk drive (HDD), and a CD-ROM, or the like.

[0207] The input / output device 940 can include an input device such as a keyboard, a keypad, a touchpad, a touch screen, and a mouse, and an output device such as a speaker and a printer.

[0208] The power supply 950 can supply power required for the operation of the electronic device 900. The display device 960 can be connected to other components via a bus or other communication link. In an embodiment, the display device 960 can be included in the input / output device 940.

[0209] The present disclosure can be applied to various display devices. For example, the present disclosure can be applied to various display devices such as a display device for a vehicle, a ship, and an airplane, a portable communication device, a display device for exhibition or information transmission, or a medical display device, or the like.

[0210] The foregoing is a summary of an embodiment and is not to be construed as a limitation. Although an embodiment has been described, it will be readily apparent to those skilled in the art that many modifications are possible in the embodiment without materially departing from the novel teachings and advantages of the application concept. Accordingly, all such variations are intended to be included within the scope of the present application concept as defined in the claims. Thus, it is understood that the foregoing is a description of various embodiments and is not intended to be limiting. Modifications to the disclosed embodiments, as well as other embodiments, are intended to be within the scope of the application concept.

Claims

1. A display device comprising: a substrate including a display region and a peripheral region provided at a side of the display region; a light-emitting element provided in the display region and including an anode electrode, a light-emitting layer provided over the anode electrode, and a cathode electrode provided over the light-emitting layer and extending from the display region to the peripheral region; a common voltage supply line provided in the peripheral region, electrically connected to the cathode electrode, and including a first metal line, a second metal line provided over and in contact with the first metal line, a third metal line provided over and in contact with the second metal line, and a connection pattern including a material same as that of the anode electrode and in contact with the third metal line and the cathode electrode; and a transfer line provided in the peripheral region, including a material same as that of the third metal line, and connected to the common voltage supply line through the connection pattern.

2. The display device according to claim 1, further comprising: a gate driver provided in the peripheral region and including at least one driver transistor; and a control signal line provided in the peripheral region and electrically connected to the gate driver, wherein the connection pattern overlaps and is spaced apart from the control signal line in a plan view.

3. The display device according to claim 1, further comprising: a first organic insulating layer provided over the substrate and extending from the display region to the peripheral region to cover end portions of the first metal line; a second organic insulating layer provided over the first organic insulating layer and extending from the display region to the peripheral region to cover end portions of the second metal line; and a third organic insulating layer provided over the second organic insulating layer and extending from the display region to the peripheral region to cover end portions of the third metal line. an opening is defined in the third organic insulating layer to expose at least a portion of the transfer line, and 4. The display device according to claim 3, wherein the connection pattern contacts the transfer line through the opening. the transfer line is directly connected to an end portion of the common voltage supply line adjacent to a pad region of the peripheral region.

5. The display device of claim 4, wherein, a plurality of through-holes exposing at least a portion of the third organic insulating layer are defined in the connection pattern.

6. The display device according to claim 3, wherein the cathode electrode extends from the display region to a position overlapping with an end portion of the third organic insulating layer in contact with the third metal line.

7. The display device according to claim 3, wherein 8. The display device according to claim 3, further comprising: a first voltage line provided in the display region and extending in a first direction; and a second voltage line provided in the display region, provided in a different layer from the first voltage line, and extending in a second direction intersecting the first direction. the transfer line is connected to the first voltage line through a first contact hole penetrating the first organic insulating layer and the second organic insulating layer, and the transfer line is connected to the second voltage line through a second contact hole penetrating the second organic insulating layer.

9. The display device of claim 8, wherein, ​ ​ 10. The display device of claim 8, wherein, in a region adjacent to an edge portion of the display region adjacent to a pad region of the peripheral region, the first voltage line is divided into a first portion connected to the second voltage line, a second portion spaced apart from the first portion in a direction opposite to the first direction and connected to a first transmission line portion of the transmission line, and a third portion spaced apart from the first portion in the first direction and connected to a second transmission line portion of the transmission line.

11. The display device according to claim 8, further comprising: a common voltage line provided in the display region, electrically connected to the common voltage supply line, and having a mesh structure.

12. The display device of claim 11, wherein, the common voltage line is directly connected to an end portion of the common voltage supply line adjacent to a pad region of the peripheral region.

13. The display device according to claim 11, further comprising: a data line extending in the second direction, wherein the anode electrode at least partially overlaps the data line in a plan view, and the common voltage line includes: a first common voltage line overlapping the first voltage line in the plan view and extending in the first direction; and a second common voltage line covering a portion of the data line overlapping the anode electrode and extending in the second direction.

14. The display device of claim 13, wherein, the common voltage line covers at least one disconnected portion of at least one of the first voltage line and the second voltage line.

15. A display device comprising: a substrate including a display region and a peripheral region surrounding at least a portion of the display region; a light-emitting element provided in the display region and including an anode electrode, a light-emitting layer provided over the anode electrode, and a cathode electrode provided over the light-emitting layer and extending from the display region to the peripheral region; a common voltage supply line including a plurality of metal layers sequentially stacked and provided in the peripheral region and contacting the cathode electrode; a first voltage line provided in the display region and extending in a first direction; a second voltage line provided in the display region, provided in a different layer from the first voltage line, and extending in a second direction intersecting the first direction; and a common voltage line provided in the display region, electrically connected to the common voltage supply line, and having a mesh structure.

16. The display device according to claim 15, further comprising: a first organic insulating layer provided over the substrate and extending from the display region to the peripheral region; a second organic insulating layer provided over the first organic insulating layer and extending from the display region to the peripheral region; and a third organic insulating layer provided over the second organic insulating layer and extending from the display region to the peripheral region, wherein the common voltage line is provided between the second organic insulating layer and the third organic insulating layer.

17. The display device of claim 15, wherein, the common voltage line is directly connected to an end portion of the common voltage supply line adjacent to a pad region of the peripheral region.

18. The display device according to claim 15, further comprising: a data line extending in the second direction, wherein, in a plan view, the anode electrode at least partially overlaps the data line, and the common voltage line includes: a first common voltage line covering a disconnected portion of the first voltage line in the plan view and extending in the first direction; and a second common voltage line covering a portion of the data line overlapping the anode electrode and extending in the second direction.

19. The display device of claim 15, wherein, a grid structure is formed in a portion of the display region including the first voltage line and the second voltage line.

20. The display device of claim 15, wherein, at least a portion of the common voltage line covers a portion of the first voltage line, and at least a portion of the anode electrode covers a portion of the second voltage line.

Images