Display device and method for manufacturing display device

Abstract

The present disclosure relates to a display device capable of providing high-brightness light and a method of manufacturing the same. According to one or more embodiments, a display device includes: a substrate; an anode electrode over the substrate and including a first layer, a second layer on the first layer, a third layer on an upper surface and a side surface of the second layer, and a fourth layer connected to the first layer and on the upper surface of the first layer, the upper surface of the third layer, and the side surface of the third layer; a light emitting stack over the anode electrode; and a cathode electrode over the light emitting stack.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0050560, filed on April 16, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a display device capable of providing light of relatively high luminance and a method of manufacturing the same. BACKGROUND

[0003] A head-mounted display (HMD) is an image display device worn in the form of glasses or a helmet on a user's head and forms a focal point of an image in front of the user's eyes at a distance close to the user's eyes. The head-mounted display can implement virtual reality (VR) or augmented reality (AR).

[0004] The head-mounted display uses a plurality of lenses to magnify and display an image displayed by a small display device. Accordingly, a display device applied to the head-mounted display needs to provide a high-resolution image, for example, an image having a resolution of about 3000 pixels per inch (PPI) or more. To this end, an organic light emitting diode on silicon (OLEDoS), which is a small organic light emitting display device having a high resolution, has been used as a display device applied to the head-mounted display. The OLEDoS is a device that displays an image by placing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is positioned. SUMMARY

[0005] Aspects of the present disclosure provide a display device capable of providing light of high luminance and a method of manufacturing the same.

[0006] According to one or more embodiments, a display device includes a substrate; an anode electrode over the substrate and including a first layer, a second layer on the first layer, a third layer on an upper surface and a side surface of the second layer, and a fourth layer connected to the first layer and on an upper surface of the first layer, an upper surface of the third layer, and a side surface of the third layer; a light emitting stack over the anode electrode; and a cathode electrode over the light emitting stack.

[0007] The second layer and the third layer can be surrounded by the first layer and the fourth layer.

[0008] The first layer can be connected to a transistor through a via hole.

[0009] The fourth layer can be connected to the light emitting stack.

[0010] The fourth layer can be directly connected to the first layer.

[0011] The fourth layer can be directly connected to the upper surface of the first layer.

[0012] The second layer can be at a central portion of the upper surface of the first layer.

[0013] The first layer can include titanium, wherein the second layer includes aluminum, wherein the third layer includes aluminum oxide, and wherein the fourth layer includes a transparent conductive material.

[0014] The transparent conductive material can include indium tin oxide.

[0015] The anode electrode can further include a fifth layer between the third layer and the fourth layer.

[0016] The fifth layer can include an inorganic layer.

[0017] The anode electrode can be provided as a plurality, and can include a first anode electrode of a first pixel, a second anode electrode of a second pixel, and a third anode electrode of a third pixel.

[0018] The fifth layer of the first anode electrode, the fifth layer of the second anode electrode, and the fifth layer of the third anode electrode have different respective thicknesses.

[0019] The display apparatus can further include a first color filter above the first anode electrode, a second color filter above the second anode electrode, and a third color filter above the third anode electrode.

[0020] The first color filter can be configured to transmit red light, wherein the second color filter is configured to transmit green light, and wherein the third color filter is configured to transmit blue light.

[0021] The thickness of the fifth layer of the second anode electrode can be less than the thickness of the fifth layer of the first anode electrode, and can be greater than the thickness of the fifth layer of the third anode electrode.

[0022] According to one or more embodiments disclosed, a method of manufacturing a display device includes the steps of: forming an insulating layer over a substrate; forming a first material layer over the insulating layer; forming a first photoresist pattern having an inverse trapezoidal shape of a side surface over the first material layer; forming a second material layer including a first sub-material layer over the first material layer and a second sub-material layer over the first photoresist pattern; forming a third layer separated by the first photoresist pattern over the first sub-material layer and over the second sub-material layer; removing the first photoresist pattern such that a second layer is retained over the first material layer; forming a fourth material layer over the third layer; forming a second photoresist pattern over the fourth material layer; selectively removing the fourth material layer and the first material layer using the second photoresist pattern as a mask such that a fourth layer and a first layer are retained; removing the second photoresist pattern such that an anode electrode including the first layer, the second layer, the third layer, and the fourth layer is retained; forming a pixel defining film over the anode electrode; forming a light emitting stack over the pixel defining film and the anode electrode; and forming a cathode electrode over the light emitting stack.

[0023] The second layer can be on the first layer, wherein the third layer is on an upper surface and a side surface of the second layer, and wherein the fourth layer is on an upper surface of the first layer, an upper surface of the third layer, and a side surface of the third layer.

[0024] The second layer and the third layer can be surrounded by the first layer and the fourth layer.

[0025] The fourth layer can be directly connected to the first layer.

[0026] The fourth layer can be directly connected to an edge of the first layer.

[0027] The second layer can be at a center portion of an upper surface of the first layer.

[0028] The first layer can include titanium, wherein the second layer includes aluminum, wherein the third layer includes aluminum oxide, and wherein the fourth layer includes a transparent conductive material.

[0029] The method can further include forming a fifth layer between the third layer and the fourth layer.

[0030] The fifth layer can include an inorganic layer.

[0031] A display device according to one or more embodiments can have a relatively excellent reflectance (e.g., excellent reflectance caused by an aluminum layer), in addition, can have a high transmittance (e.g., high transmittance caused on the basis of omission of a TiN layer). Accordingly, the display device according to one or more embodiments can provide light of high brightness even in a low power case.

[0032] The effects of the present disclosure are not limited to the above-mentioned aspects, and other aspects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which: Figure 1 is an exploded perspective view showing a display device according to one or more embodiments; Figure 2 is a layout view showing an example of a display panel shown in Figure 1 ; Figure 3 is an equivalent circuit diagram of a first pixel according to one or more embodiments; Figure 4 is a layout view showing an example of a display panel according to one or more embodiments; Figure 5 is a layout view showing an example of a display region of Figure 4 ; Figure 6 is a cross-sectional view showing an example of a display panel taken along a line X-X' of Figure 5 ; Figure 7 is a cross-sectional view of a display device according to one or more embodiments; Figures 8 to 17 is a cross-sectional view of a process for describing a method for manufacturing a display device according to one or more embodiments; Figure 18 is a cross-sectional view of a display device according to one or more other embodiments; Figure 19 is a graph for describing a resonance distance for each pixel in a display device according to one or more embodiments; Figure 20 is a perspective view showing a head-mounted display according to one or more embodiments; Figure 21 is an exploded perspective view showing an example of a head-mounted display of Figure 20 ; and Figure 22 is a perspective view showing a head-mounted display according to one or more other embodiments. DETAILED DESCRIPTION

[0034] Aspects of some embodiments of the present disclosure and methods of implementing them can be more readily understood by reference to the following detailed description, taken with the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the scope of the aspects of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are redundant, or that are not directly related to the description of the embodiments, or that are well known in the art can be omitted for the sake of conciseness and clarity. Identical reference numerals, symbols or their combinations, throughout the drawings and written description, indicate same elements, and thus, repeated description of them can be omitted.

[0035] The described embodiments can have various modifications and can be implemented in different forms and should not be construed as being limited to the embodiments shown in the drawings. The use of "can", "may" or "might" in describing the embodiments corresponds to one or more embodiments of the present disclosure.

[0036] In view of the entire disclosure, those of ordinary skill in the art will understand that each suitable feature of various embodiments of the present disclosure can be combined or combined with each other, in part or in whole, unless otherwise stated or implied, and can be technically interlocked and operated in various suitable ways, and each embodiment can be implemented independently of each other or in any suitable way.

[0037] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. In other words, since the sizes and thicknesses of the elements in the drawings are arbitrarily shown for the purpose of facilitating description, the disclosure is not limited thereto. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to illustrate boundaries of adjacent elements. As such, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for specific material, material properties, dimensions, proportions, commonality of the illustrated elements between the elements, and / or any other characteristic, attribute, property, etc. unless recited.

[0038] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic representations of schematics embodiments and / or intermediate structures of embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. In addition, the specific structural or functional descriptions disclosed herein are not to be interpreted as being limiting but are merely exemplary for purposes of describing the embodiments according to the present disclosure. Thus, embodiments disclosed herein are not to be interpreted as being limited to the shapes of the elements as illustrated but are to include deviations in shapes that result, for example, from manufacturing.

[0039] For example, an implant region shown as rectangular will typically have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation occurs.

[0040] For purposes of explanation, spatially relative terms such as "beneath", "below", "lower", "bottom", "under", "above", "upper", "on", "over", "higher", "top", "side" (as in "sidewall") and the like can be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it can be either be directly on the second part or otherwise be on the second part with one or more intervening parts. The spatially relative terms used herein are in reference to the device as shown in the figures and are intended to encompass different positions of the device in use or in operation in addition to the positions depicted in the figures. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. The terminology used herein should not be interpreted as implying any particular ordering of steps or sequence of things described unless required by the context of the particular claim.

[0041] Furthermore, the phrase "in plan view" means when viewing a portion of an object from above, and the phrase "in schematic cross-sectional view" means when viewing a schematic cross-section of a portion of an object taken by a vertical cut from the side. The term "overlying" or its variants, means that a first object can be above or below a second object or on a side of the second object, and vice versa. Furthermore, the term "overlying" can include stacked, facing or facing away, extending over (extending over), covering or partially covering, or any other suitable term that will be appreciated and understood by one of ordinary skill in the art. The expression "not overlying" can include the meaning of "away from", or "leaving space from", or "offset from", as well as any other suitable equivalent that will be appreciated and understood by one of ordinary skill in the art. The terms "facing" and "facing away" can mean that a first object can be directly or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, although they are still facing each other.

[0042] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that one or more intervening elements, layers, regions, or components may be present. Additionally, this may be collectively referred to as being directly or indirectly coupled or connected, and integrally or non-integrally coupled or connected. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected to or electrically coupled to the other layer, region, and / or component, or one or more intervening layers, regions, or components may be present. The one or more intervening components may include switches, resistors, and / or capacitors, etc. In describing embodiments, unless explicitly described as being directly connected, the statement of connection indicates an electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected to or directly coupled to another component, or is directly on another component, without intervening components.

[0043] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the case where the part is "directly under" the other part, but also includes the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between...", "immediately between...", "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0044] For purposes of this disclosure, the expression "at least one of (a / n) or (an) (X, Y, and Z)" or "at least one of (a / n) or (an) selected from the group consisting of X, Y, and Z" should be considered synonymous with "X, Y, and Z viewed individually" or "X, Y, and Z viewed collectively." For example, "at least one of X, Y, and Z" and "at least one of selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, two (a / n) or more of X, Y, and Z in any combination (such as XYZ, XY, YZ, and XZ), or any variant of the above. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" is generally employed in its sense including "and / or" and the term "and / or" includes any combination or all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when the expression such as "at least one of (a / n) or (an) (X, Y, and Z)" or "a plurality of (a / n) or (an) (X, Y, and Z)" or other prepositional phrases is used before / after a list of elements, it modifies the list of elements as a whole and not the individual elements in the list. When the statement "C to D" is made, "C to D" means C or greater and D or less, unless otherwise stated.

[0045] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure. An element described as "first" need not necessarily be "second" or "third." The terms "first," "second," "third," etc. can be used herein to distinguish different categories or groups of elements. For the sake of clarity, the terms "first," "second," etc. can be used herein to simply denote "a first category (or first group)," "a second category (or second group)," etc.

[0046] In examples, the x-axis, the y-axis, and / or the z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0047] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," "includes" and / or "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] When one or more embodiments can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the described order.

[0049] As used herein, the terms "substantially," "approximately," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% from a corresponding value. As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art to which the discussed measurement pertains and the error in measurement associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the stated value. Furthermore, the use of "may" indicates "one or more embodiments of the disclosure" when describing embodiments of the disclosure.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0051] Figure 1 FIG. 1 is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 FIG. 2 is a layout view showing an example of a display panel shown in FIG. 1. Figure 1 FIG. 3 is a layout view showing an example of a display panel shown in FIG. 1. Figure 3 FIG. 4 is an equivalent circuit diagram of a first pixel according to one or more embodiments. FIG. 5 is an equivalent circuit diagram of a second pixel according to one or more embodiments.

[0052] Referring to Figure 1 and Figure 2 The display device 10 according to one or more embodiments is a device that displays a moving image or a still image. The display device 10 according to one or more embodiments can be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC). For example, the display device 10 according to one or more embodiments can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IOT) device. Alternatively, the display device 10 according to one or more embodiments can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for implementing virtual reality and augmented reality.

[0053] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply unit 500.

[0054] The display panel 100 can have a shape similar to a rectangular shape in a plan view. For example, the display panel 100 can have a shape similar to a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 crossing the first direction DR1 in a plan view. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be rounded with a curvature (e.g., a predetermined curvature) or be a right angle. The shape of the display panel 100 in a plan view is not limited to a rectangular shape, and can be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The shape of the display device 10 in a plan view can follow the shape of the display panel 100 in a plan view, but the present disclosure is not limited thereto.

[0055] As shown in Figure 2 , the display panel 100 can include a display area DAA that displays an image and a non-display area NDA that does not display an image.

[0056] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0057] The plurality of pixels PX can be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can extend in the first direction DR1 and can be positioned in the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 and can be positioned in the first direction DR1.

[0058] The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL includes a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0059] The plurality of unit pixels UPX includes a plurality of pixels PX1, PX2, and PX3. The plurality of pixels PX1, PX2, and PX3 can include a plurality of pixel transistors as shown in Figure 3 FIG. 1, and the plurality of pixel transistors can be formed by a semiconductor process and positioned on a semiconductor substrate S SUB (see FIG. 1). For example, the plurality of pixel transistors of the data driver 700 can be formed as complementary metal-oxide-semiconductor (CMOS). Figure 6

[0060] Each of the plurality of pixels PX1, PX2, and PX3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and can allow the light emitting element to emit light according to the data voltage.

[0061] The non-display area NDA includes the scan driver 610, the emission driver 620, and the data driver 700.

[0062] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors can be formed by a semiconductor process, and can be formed on a semiconductor substrate S SUB (see FIG. 1). For example, the plurality of scan transistors and the plurality of light emitting transistors can be formed as CMOS. Figure 6 Figure 2 The scan driver 610 has been shown to be positioned at the left side of the display area DAA, and the emission driver 620 is positioned at the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 can be positioned at both the left and right sides of the display area DAA.

[0063] ​​The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing controller 400 and may sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal based on the scan timing control signal SCS and may sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS and may sequentially output the bias scan signal to the bias scan line EBL.

[0064] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing controller 400. The first emission control driver 621 can generate a first emission control signal based on the emission timing control signal ECS and can sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 622 can generate a second emission control signal based on the emission timing control signal ECS and can sequentially output the second emission control signal to the second emission control line EL2.

[0065] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see FIG. Figure 6 For example, the plurality of data transistors may be formed as CMOS.

[0066] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing controller 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0067] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be positioned on one surface (e.g., the rear surface) of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer made of graphite or a metal (such as silver (Ag), copper (Cu), or aluminum (Al) with high thermal conductivity).

[0068] The circuit board 300 may be electrically connected to the first pad unit PDA1 (see FIG. 1 ) of the display panel 100 using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of the multiple first pad PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 1 The circuit board 300 is shown as being unbent, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be positioned on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be connected to the first pad unit PDA1 (see FIG. 1 ) of the display panel 100 using a conductive adhesive member. Figure 4 ) of the multiple first pad PD1 (see Figure 4 ) at the other end opposite to the end.

[0069] The timing controller 400 can receive digital video data DATA and timing signals from the outside. The timing controller 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 based on the timing signals. The timing controller 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing controller 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0070] The power supply unit 500 may generate a plurality of panel driving voltages according to an external source voltage. For example, the power supply unit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and may supply the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT to the display panel 100. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0071] Each of the timing controller 400 and the power supply unit 500 can be formed as an integrated circuit (IC), and can be attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing controller 400 can be supplied to the display panel 100 through the circuit board 300. Also, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply unit 500 can be supplied to the display panel 100 through the circuit board 300.

[0072] Alternatively, each of the timing controller 400 and the power supply unit 500 can be positioned in the non-display area NDA of the display panel 100, similar to the scan driver 610, the emission driver 620, and the data driver 700. In this case, the timing controller 400 can include a plurality of timing transistors, and the power supply unit 500 can include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed through a semiconductor process, and can be formed on a semiconductor substrate SSUB (see Figure 6 ). For example, the plurality of timing transistors and the plurality of power transistors can be formed as CMOS. Each of the timing controller 400 and the power supply unit 500 can be positioned between the data driver 700 and the first pad unit PDA1 (see Figure 4 ).

[0073] Figure 3 is an equivalent circuit diagram of a first pixel according to one or more embodiments.

[0074] Referring to Figure 3 , the first pixel PX1 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line EBL, a first emission control line EL1, a second emission control line EL2, and a data line DL. Also, the first pixel PX1 can be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In this case, the first driving voltage VSS can be a voltage lower than the third driving voltage VINT. The second driving voltage VDD can be a voltage higher than the third driving voltage VINT.

[0075] The first pixel PX1 includes a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0076] The light emitting element LE emits light according to a driving current flowing through a channel of the first transistor T1. The amount of light emitted from the light emitting element LE can be proportional to the driving current. The light emitting element LE can be positioned between the fourth transistor T4 and the first driving voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE can be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer positioned between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0077] The first transistor T1 can be a driving transistor that controls a source-drain current (hereinafter, referred to as a "driving current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode thereof. The first transistor T1 includes the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0078] The second transistor T2 can be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. For this reason, a data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes the gate electrode connected to the write scan line GWL, the source electrode connected to the data line DL, and the drain electrode connected to one electrode of the first capacitor CP1.

[0079] The third transistor T3 can be positioned between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. For this reason, the gate electrode and the drain electrode of the first transistor T1 are connected to each other, and thus, the first transistor T1 can operate like a diode. The third transistor T3 includes the gate electrode connected to the control scan line GCL, the source electrode connected to the second node N2, and the drain electrode connected to the first node N1.

[0080] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. For this reason, the driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0081] The fifth transistor T5 can be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. For this reason, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0082] The sixth transistor T6 can be positioned between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. For this reason, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0083] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0084] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0085] The first node N1 is a contact point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a contact point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0086] Each of the first transistor T1 to the sixth transistor T6 can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 can be an N-type MOSFET. Alternatively, one or more transistors of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, and one or more other transistors of the first transistor T1 to the sixth transistor T6 can be an N-type MOSFET.

[0087] In Figure 3 , it has been shown that the first pixel PX1 includes six transistors T1 to T6 and two capacitors CP1 and CP2, but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 3 the equivalent circuit diagram shown in Figure 3 . For example, the number of transistors and capacitors of the first pixel PX1 is not limited to the number shown in

[0088] . In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be substantially the same as the equivalent circuit diagram of the first pixel PX1 described with reference to Figure 3 . Therefore, the description of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 is omitted in the present disclosure.

[0089] Figure 4 is a layout diagram showing an example of a display panel according to one or more embodiments.

[0090] With reference to Figure 4 , the display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad unit PDA1, and a second pad unit PDA2.

[0091] The scan driver 610 can be positioned at a first side of the display area DAA, and the emission driver 620 can be positioned at a second side of the display area DAA. For example, the scan driver 610 can be positioned at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be positioned at the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be positioned at a left side of the display area DAA, and the emission driver 620 can be positioned at a right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 can be positioned at both the first side and the second side of the display area DAA.

[0092] The first pad unit PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through conductive adhesive members. The first pad unit PDA1 can be positioned at a third side of the display area DAA. For example, the first pad unit PDA1 can be positioned at one side of the display area DAA in the second direction DR2.

[0093] The first pad unit PDA1 can be positioned outside the data driver 700 in the second direction DR2. That is, the first pad unit PDA1 can be closer to an edge of the display panel 100 than the data driver 700.

[0094] The second pad unit PDA2 can include a plurality of second pads PD2 corresponding to inspection pads for inspecting whether the display panel 100 operates normally. The plurality of second pads PD2 can be connected to a jig or a probe pin or to a circuit board to perform inspection in an inspection process. The circuit board for inspection can be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0095] The first distribution circuit 710 distributes a data voltage applied through the first pad unit PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute a data voltage applied through one first pad PD1 of the first pad unit PDA1 to P data lines DL (P is a positive integer of 2 or more), for which reason the number of first pads PD1 can be reduced. The first distribution circuit 710 can be positioned at a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be positioned at one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be positioned at a lower side of the display area DAA.

[0096] The second distribution circuit 720 distributes a signal applied through the second pad unit PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad unit PDA2 and the second distribution circuit 720 can be components for checking an operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be positioned at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be positioned at another side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be positioned at an upper side of the display area DAA.

[0097] Figure 5 is a layout diagram illustrating an example of a display area of Figure 4 .

[0098] Referring to Figure 5 , each of the plurality of unit pixels UPX includes a first emission area EA1 that is an emission area of a first pixel PX1, a second emission area EA2 that is an emission area of a second pixel PX2, and a third emission area EA3 that is an emission area of a third pixel PX3. In other words, the unit pixel UPX can include a unit emission area UEA, and the unit emission area UEA includes the first emission area EA1, the second emission area EA2, and the third emission area EA3 described above.

[0099] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in a plan view, but the shape of each of the emission areas EA1 to EA3 is not limited thereto.

[0100] A maximum length of the third emission area EA3 in the first direction DR1 can be less than a maximum length of the first emission area EA1 in the first direction DR1 and a maximum length of the second emission area EA2 in the first direction DR1. The maximum length of the first emission area EA1 in the first direction DR1 and the maximum length of the second emission area EA2 in the first direction DR1 can be substantially the same as each other.

[0101] A maximum length of the third emission area EA3 in the second direction DR2 can be greater than a maximum length of the first emission area EA1 in the second direction DR2 and a maximum length of the second emission area EA2 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 can be greater than the maximum length of the second emission area EA2 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 can be less than the maximum length of the third emission area EA3 in the second direction DR2.

[0102] As Figure 5As shown in the figure, in a plan view, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape including six straight lines, but the present disclosure is not limited thereto. Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a hexagonal shape, a circular shape, an elliptical shape, or an irregular shape in a plan view.

[0103] like Figure 5 As shown in , in each of the plurality of pixels PX, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. In addition, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different from each other.

[0104] The first emission area EA1 can emit light of a first color, the second emission area EA2 can emit light of a second color, and the third emission area EA3 can emit light of a third color. Here, the first color of light can be light in a red wavelength band, the second color of light can be light in a green wavelength band, and the third color of light can be light in a blue wavelength band. For example, the blue wavelength band can indicate that the main peak wavelength of light is included in a wavelength band of approximately 380nm to approximately 480nm, the green wavelength band can indicate that the main peak wavelength of light is included in a wavelength band of approximately 480nm to approximately 560nm, and the red wavelength band can indicate that the main peak wavelength of light is included in a wavelength band of approximately 600nm to approximately 750nm.

[0105] exist Figure 5 and Figure 6 , each of the plurality of unit pixels UPX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of unit pixels UPX may also include four emission areas.

[0106] In addition, the arrangement of the emission regions of the plurality of unit pixels UPX is not limited to Figure 5 For example, the emission regions of the plurality of unit pixels UPX may be positioned as a stripe structure in which the emission regions are arranged in the first direction DR1, a PenTile structure in which the emission regions have a diamond arrangement, or a PenTile structure in which the emission regions have a diamond arrangement. ® Structure (PenTile ® is a registered trademark of Samsung Display Co., Ltd. of South Korea) or a hexagonal structure in which an emission area having a hexagonal shape in a plan view is arranged.

[0107] Figure 6is a cross-sectional view showing an example of a display panel taken along a line X-X' of Figure 5

[0108] Referring to Figure 6 , the display panel 100 includes a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EML, a sealing layer TFE, and an optical layer OPL.

[0109] The semiconductor backplane SBP can include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be the first transistor T1 to the sixth transistor T6 described with reference to Figure 3

[0110] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. A plurality of well regions WA can be positioned in an upper surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0111] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH positioned between the source region SA and the drain region DA.

[0112] A bottom insulating film BINS can be positioned between the gate electrode GE and the well region WA. A side surface insulating film SINS can be positioned on a side surface of the gate electrode GE. The side surface insulating film SINS can be positioned on the bottom insulating film BINS.

[0113] Each of the source region SA and the drain region DA can be a region doped with the first type of impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be positioned on one side of the gate electrode GE, and the drain region DA can be positioned on the other side of the gate electrode GE (e.g., in a plan view).

[0114] ​​Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 positioned between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 positioned between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA due to the bottom insulating film BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA due to the bottom insulating film BINS. The distance between the source region SA and the drain region DA can be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Accordingly, the length of the channel region CH of each of the pixel transistors PTR can be increased, and thus, the possibility of punch-through and hot carrier phenomena caused by a short channel can be reduced or prevented.

[0115] The first semiconductor insulating film SINS1 can be positioned on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed as a silicon carbon nitride (SiCN) or silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0116] The second semiconductor insulating film SINS2 can be positioned on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed as a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0117] The plurality of contact terminals CTE can be positioned on the second semiconductor insulating film SINS2. The plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of the pixel transistor PTR, respectively, through holes that penetrate the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0118] The third semiconductor insulating film SINS3 can be positioned on a side surface of each of the plurality of contact terminals CTE. An upper surface of each of the plurality of contact terminals CTE can be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 can be formed as a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0119] The semiconductor substrate S SUB can be replaced with a glass substrate or a polymer resin substrate such as a polyimide substrate. In this case, the thin-film transistor can be positioned on the glass substrate or the polymer resin substrate. The glass substrate can be a non-flexible rigid substrate, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0120] The light-emitting element backplane EBP includes a plurality of conductive layers MTL1 to MTL8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9. Specifically, the light-emitting element backplane EBP includes the plurality of insulating films INS1 to INS9 positioned between, on, or under respective ones of the first conductive layer MTL1 to the eighth conductive layer MTL8.

[0121] The first conductive layer MTL1 to the eighth conductive layer MTL8 are used to implement the circuit of the first pixel PX1 shown in FIG. 1 by connecting the plurality of contact terminals CTE exposed from the semiconductor backplane SBP to each other. Figure 3 For example, only the first transistor T1 to the sixth transistor T6 are formed in the semiconductor backplane SBP, and the connections between the first transistor T1 to the sixth transistor T6 and the formation of the first capacitor CP1 and the second capacitor CP2 are performed by the first conductive layer MTL1 to the eighth conductive layer MTL8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE is also performed by the first conductive layer MTL1 to the eighth conductive layer MTL8.

[0122] The first insulating film INS1 can be positioned on the semiconductor backplane SBP. Each of the first vias VA1 can penetrate the first insulating film INS1 to connect to the contact terminals CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers MTL1 can be positioned on the first insulating film INS1 and can connect to the first vias VA1.

[0123] The second insulating film INS2 can be positioned on the first insulating film INS1 and the first conductive layers MTL1. Each of the second vias VA2 can penetrate the second insulating film INS2 to connect to the exposed first conductive layers MTL1. Each of the second conductive layers MTL2 can be positioned on the second insulating film INS2 and can connect to the second vias VA2.

[0124] The third insulating film INS3 can be positioned on the second insulating film INS2 and the second conductive layers MTL2. Each of the third vias VA3 can penetrate the third insulating film INS3 to connect to the exposed second conductive layers MTL2. Each of the third conductive layers MTL3 can be positioned on the third insulating film INS3 and can connect to the third vias VA3.

[0125] The fourth insulating film INS4 can be positioned on the third insulating film INS3 and the third conductive layer MTL3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 to connect to the exposed third conductive layer MTL3. Each of the fourth conductive layers MTL4 can be positioned on the fourth insulating film INS4 and can connect to the fourth vias VA4.

[0126] The fifth insulating film INS5 can be positioned on the fourth insulating film INS4 and the fourth conductive layer MTL4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 to connect to the exposed fourth conductive layer MTL4. Each of the fifth conductive layers MTL5 can be positioned on the fifth insulating film INS5 and can connect to the fifth vias VA5.

[0127] The sixth insulating film INS6 can be positioned on the fifth insulating film INS5 and the fifth conductive layer MTL5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 to connect to the exposed fifth conductive layer MTL5. Each of the sixth conductive layers MTL6 can be positioned on the sixth insulating film INS6 and can connect to the sixth vias VA6.

[0128] The seventh insulating film INS7 can be positioned on the sixth insulating film INS6 and the sixth conductive layer MTL6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 to connect to the exposed sixth conductive layer MTL6. Each of the seventh conductive layers MTL7 can be positioned on the seventh insulating film INS7 and can connect to the seventh vias VA7.

[0129] The eighth insulating film INS8 can be positioned on the seventh insulating film INS7 and the seventh conductive layer MTL7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 to connect to the exposed seventh conductive layer MTL7. Each of the eighth conductive layers MTL8 can be positioned on the eighth insulating film INS8 and can connect to the eighth vias VA8.

[0130] The first conductive layers MTL1 to the eighth conductive layers MTL8 and the first vias VA1 to the eighth vias VA8 can be made of substantially the same material. Each of the first conductive layers MTL1 to the eighth conductive layers MTL8 and the first vias VA1 to the eighth vias VA8 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first insulating film INS1 to the eighth insulating film INS8 can be made of substantially the same material. The first insulating film INS1 to the eighth insulating film INS8 can be formed as a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0131] Each of the thickness of the first conductive layer MTL1, the thickness of the second conductive layer MTL2, the thickness of the third conductive layer MTL3, the thickness of the fourth conductive layer MTL4, the thickness of the fifth conductive layer MTL5, and the thickness of the sixth conductive layer MTL6 can be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. Each of the thickness of the second conductive layer MTL2, the thickness of the third conductive layer MTL3, the thickness of the fourth conductive layer MTL4, the thickness of the fifth conductive layer MTL5, and the thickness of the sixth conductive layer MTL6 can be greater than the thickness of the first conductive layer MTL1. The thickness of the second conductive layer MTL2, the thickness of the third conductive layer MTL3, the thickness of the fourth conductive layer MTL4, the thickness of the fifth conductive layer MTL5, and the thickness of the sixth conductive layer MTL6 can be substantially the same as one another. For example, the thickness of the first conductive layer MTL1 can be approximately 1360 A, each of the thickness of the second conductive layer MTL2, the thickness of the third conductive layer MTL3, the thickness of the fourth conductive layer MTL4, the thickness of the fifth conductive layer MTL5, and the thickness of the sixth conductive layer MTL6 can be approximately 1440 A, and each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 can be approximately 1150 A.

[0132] Each of the thickness of the seventh conductive layer MTL7 and the thickness of the eighth conductive layer MTL8 can be greater than each of the thickness of the first conductive layer MTL1, the thickness of the second conductive layer MTL2, the thickness of the third conductive layer MTL3, the thickness of the fourth conductive layer MTL4, the thickness of the fifth conductive layer MTL5, and the thickness of the sixth conductive layer MTL6. Each of the thickness of the seventh conductive layer MTL7 and the thickness of the eighth conductive layer MTL8 can be greater than each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 can be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer MTL7 and the thickness of the eighth conductive layer MTL8 can be substantially the same as one another. For example, each of the thickness of the seventh conductive layer MTL7 and the thickness of the eighth conductive layer MTL8 can be approximately 9000 A. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 can be approximately 6000 A.

[0133] The ninth insulating film INS9 can be positioned on the eighth insulating film INS8 and the eighth conductive layer MTL8. The ninth insulating film INS9 can be formed as a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0134] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 to connect to the exposed eighth conductive layer MTL8. Each of the ninth vias VA9 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the ninth via VA9 can be approximately 16500 Å.

[0135] The display element layer EML can be positioned on the light emitting element back plate EBP. The display element layer EML can include a reflective electrode layer RL, a tenth insulating film INS10 and an eleventh insulating film INS11, a tenth via VA10, a light emitting element LE including a first electrode AND, a light emitting stack ES, and a second electrode CAT, a pixel definition film PDL, and a plurality of trenches TRC.

[0136] The reflective electrode layer RL can be positioned on the ninth insulating film INS9. The reflective electrode layer RL can include one or more reflective electrodes RL1, RL2, RL3, and RL4. For example, as shown in FIG. 1A, the reflective electrode layer RL can include first to fourth reflective electrodes RL1, RL2, RL3, and RL4. Figure 6

[0137] Each of the first reflective electrodes RL1 can be positioned on the ninth insulating film INS9 and can be connected to the ninth via VA9. Each of the first reflective electrodes RL1 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, each of the first reflective electrodes RL1 can include titanium nitride (TiN).

[0138] The second reflective electrode RL2 can be positioned on the corresponding first reflective electrode RL1. Each of the second reflective electrodes RL2 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, each of the second reflective electrodes RL2 can include aluminum (Al).

[0139] ​The third reflective electrode RL3 can be positioned on the corresponding second reflective electrode RL2. Each of the third reflective electrodes RL3 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, each of the third reflective electrodes RL3 can include titanium nitride (TiN).

[0140] The fourth reflective electrode RL4 can be positioned on the corresponding third reflective electrode RL3. Each of the fourth reflective electrodes RL4 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, each of the fourth reflective electrodes RL4 can include titanium (Ti).

[0141] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4. For example, each of the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately 100 Å, and the thickness of the second reflective electrode RL2 can be approximately 850 Å.

[0142] The tenth insulating film INS10 can be positioned on the ninth insulating film INS9. The tenth insulating film INS10 can be positioned between the reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating film INS10 can be positioned on the reflective electrode layers RL in the third pixel PX3. The tenth insulating film INS10 can be formed as a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0143] The eleventh insulating film INS11 can be positioned on the tenth insulating film INS10 and the reflective electrode layers RL. The eleventh insulating film INS11 can be formed as a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 can be an optical auxiliary layer through which light reflected by the reflective electrode layers RL among light emitted from the light emitting element LE passes.

[0144] In one or more embodiments, in order to adjust the resonance distance of light emitted from the light emitting element LE in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating film INS10 and the eleventh insulating film INS11 can not be positioned under the first electrode AND of the first pixel PX1. The first electrode AND of the first pixel PX1 can be positioned directly on the reflective electrode layer RL. The eleventh insulating film INS11 can be positioned under the first electrode AND of the second pixel PX2. In one or more embodiments, the tenth insulating film INS10 and the eleventh insulating film INS11 can be positioned under the first electrode AND of the third pixel PX3.

[0145] In summary, in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the distance between the first electrode AND and the reflective electrode layer RL can be different. That is, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating film INS10 and / or the eleventh insulating film INS11 can be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, in the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating film INS10 and the eleventh insulating film INS11 can be positioned under the first electrode AND. Figure 6 It has been shown in the third pixel PX3 that the distance between the first electrode AND and the reflective electrode layer RL is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 and the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1. In addition, the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, but the present disclosure is not limited thereto.

[0146] In addition, the tenth insulating film INS10 and the eleventh insulating film INS11 have been shown in one or more embodiments of the present disclosure, but a twelfth insulating film positioned under the first electrode AND of the first pixel PX1 can be added. In this case, in one or more embodiments, the eleventh insulating film INS11 and the twelfth insulating film can be positioned under the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film can be positioned under the first electrode AND of the third pixel PX3.

[0147] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second pixel PX2 and the third pixel PX3 to be connected to the exposed fourth reflective electrode RL4. Each of the tenth vias VA10 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the tenth via VA10 in the second pixel PX2 can be smaller than the thickness of the tenth via VA10 in the third pixel PX3.

[0148] The first electrode AND of each of the light emitting elements LE can be positioned on the tenth insulating film INS10 and can be connected to the tenth via VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers MTL1 to MTL8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the first electrode AND of each of the light emitting elements LE can be made of titanium nitride (TiN).

[0149] The pixel definition film PDL can be positioned on a partial region of the first electrode AND of each of the light emitting elements LE. The pixel definition film PDL can cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel definition film PDL serves to divide the first to third emission areas EA1 to EA3.

[0150] The first emission area EA1 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emission area EA2 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emission area EA3 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0151] The pixel definition films PDLs can include a first pixel definition film to a third pixel definition film PDL1, PDL2, and PDL3. The first pixel definition film PDL1 can be positioned on an edge of the first electrode AND of each of the light emitting elements LE, the second pixel definition film PDL2 can be positioned on the first pixel definition film PDL1, and the third pixel definition film PDL3 can be positioned on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can be formed as a silicon oxide (SiO x )-type inorganic film, but the disclosure is not limited thereto. Each of a thickness of the first pixel definition film PDL1, a thickness of the second pixel definition film PDL2, and a thickness of the third pixel definition film PDL3 can be approximately 500 Å.

[0152] When the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 are formed as one pixel definition film, a height of the one pixel definition film increases, so that the first encapsulation inorganic film TFE1 can be disconnected due to step coverage. The step coverage refers to a ratio of a degree to which a thin film is coated on an inclined portion to a degree to which the thin film is coated on a flat portion. The lower the step coverage, the more likely the thin film will be disconnected at the inclined portion.

[0153] Therefore, in order to reduce or prevent the possibility that the first encapsulation inorganic film TFE1 is disconnected due to the step coverage, the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a cross-sectional structure having a step having a stepped shape. For example, a width of the first pixel definition film PDL1 can be greater than a width of the second pixel definition film PDL2 and a width of the third pixel definition film PDL3. In addition, the width of the second pixel definition film PDL2 can be greater than the width of the third pixel definition film PDL3. The width of the first pixel definition film PDL1 refers to a length of the first pixel definition film PDL1 in a horizontal direction defined by the first direction DR1 and / or the second direction DR2.

[0154] Each of the plurality of trenches TRC can penetrate the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3. In addition, each of the plurality of trenches TRC can penetrate the eleventh insulating film INS11. In each of the plurality of trenches TRC, the tenth insulating film INS10 can have a shape in which a portion thereof is trenchified.

[0155] At least one trench TRC can be positioned between the pixels PX1, PX2, and PX3 adjacent to each other. Figure 6 Two trenches TRC have been shown to be positioned between the pixels PX1, PX2, and PX3 adjacent to each other in the above, but the disclosure is not limited thereto.

[0156] The light emitting stack ES can include a plurality of intermediate layers. In Figure 6 The light emitting stack ES has been shown to have a triple series structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, but the disclosure is not limited thereto. For example, the light emitting stack ES can have a double series structure including two intermediate layers.

[0157] In the triple series structure, the light emitting stack ES can have a series structure including a plurality of stack layers IL1, IL2, and IL3 for emitting different light. For example, the light emitting stack ES can include a first stack layer IL1 emitting a first color of light, a second stack layer IL2 emitting a second color of light, and a third stack layer IL3 emitting a third color of light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be sequentially stacked.

[0158] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer for emitting a first color of light, and a first electron transport layer are sequentially stacked. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer for emitting a second color of light, and a second electron transport layer are sequentially stacked. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer for emitting a third color of light, and a third electron transport layer are sequentially stacked. In this case, the light emitting stack ES can emit white light in which a first color of light (e.g., red light) from the first organic light emitting layer, a second color of light (e.g., green light) from the second organic light emitting layer, and a third color of light (e.g., blue light) from the third organic light emitting layer are mixed. Accordingly, white light can be provided from the first emission area EA1, the second emission area EA2, and the third emission area EA3. Here, the white light passing through the first emission area EA1 can be incident on the first color filter CF1, the white light passing through the second emission area EA2 can be incident on the second color filter CF2, and the white light passing through the third emission area EA3 can be incident on the third color filter CF3.

[0159] A first charge generation layer for supplying holes to the second stack layer IL2 and for supplying electrons to the first stack layer IL1 can be positioned between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type charge generation layer supplying electrons to the first stack layer IL1 and a P-type charge generation layer supplying holes to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metal material.

[0160] A second charge generation layer for supplying holes to the third stack layer IL3 and for supplying electrons to the second stack layer IL2 can be positioned between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type charge generation layer for supplying electrons to the second stack layer IL2 and a P-type charge generation layer for supplying holes to the third stack layer IL3.

[0161] The first stack layer IL1 can be positioned on the first electrode AND and the pixel definition film PDL, and can be positioned on a bottom surface of each of the trenches TRC. The first stack layer IL1 can be broken between the pixels PX1, PX2, and PX3 adjacent to each other due to the trenches TRC. The second stack layer IL2 can be positioned on the first stack layer IL1. The second stack layer IL2 can be broken between the pixels PX1, PX2, and PX3 adjacent to each other due to the trenches TRC. The cavities ESS or empty spaces can be positioned between the adjacent first stack layers IL1 and between the adjacent second stack layers IL2. The third stack layer IL3 can be positioned on the second stack layer IL2. The third stack layer IL3 can not be broken by the trenches TRC, and can be positioned to cover the second stack layer IL2 in each of the trenches TRC. For example, in a triple series structure, each of the plurality of trenches TRC can be a structure of the first stack layer IL1 and the second stack layer IL2, the first charge generation layer, and the second charge generation layer for breaking the display element layer EML between the pixels PX1, PX2, and PX3 adjacent to each other. Also, in a double series structure, each of the plurality of trenches TRC can be a structure for breaking the charge generation layer positioned between the lower intermediate layer and the upper intermediate layer.

[0162] In order to stably break the first stack layer IL1 and the second stack layer IL2 of the display element layer EML between the pixels PX1, PX2, and PX3 adjacent to each other, a height of each of the plurality of trenches TRC can be greater than a height of the pixel definition film PDL. The height of each of the plurality of trenches TRC refers to a length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel definition film PDL refers to a length of the pixel definition film PDL in the third direction DR3. In order to break the first stack layer IL1 and the second stack layer IL2 of the display element layer EML between the pixels PX1, PX2, and PX3 adjacent to each other, there can be other structures instead of the trenches TRC. For example, instead of the trenches TRC, a partition wall having an inverted trapezoidal shape can be positioned on the pixel definition film PDL.

[0163] The number of the stack layers IL1, IL2, and IL3 emitting different light is not limited to Figure 6The light-emitting stack ES can include one or more intermediate layers in addition to the first stack layer IL1. For example, the light-emitting stack ES can include two intermediate layers. In this case, any one of the two intermediate layers can be substantially the same as the first stack layer IL1, and the other one of the two intermediate layers can include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and / or a second electron transport layer. In this case, a charge generation layer for supplying electrons to any one of the intermediate layers and for supplying holes to the other intermediate layer can be positioned between the two intermediate layers.

[0164] In Figure 6 The first to third stack layers IL1, IL2, and IL3 have been shown to be positioned in the first, second, and third emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. For example, the first stack layer IL1 can be positioned in the first emission area EA1 and can not be positioned in the second and third emission areas EA2 and EA3. Also, the second stack layer IL2 can be positioned in the second emission area EA2 and can be omitted from the first and third emission areas EA1 and EA3. Also, the third stack layer IL3 can be positioned in the third emission area EA3 and can be omitted from the first and second emission areas EA1 and EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0165] The second electrode CAT can be positioned on the third stack layer IL3. The second electrode CAT can be positioned on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag) capable of transmitting light therethrough. When the second electrode CAT is made of a semi-transmissive conductive material, light emission efficiency of each of the first to third pixels PX1, PX2, and PX3 can be increased by the microcavity.

[0166] The encapsulation layer TFE can be positioned on the display element layer EML. The encapsulation layer TFE can include at least one inorganic film TFE1 or TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE can include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0167] The first encapsulation inorganic film TFE1 can be positioned on the second electrode CAT. The first encapsulation inorganic film TFE1 can be formed to include a silicon nitride (SiN x ) layer, a silicon oxynitride (SiON) layer, and a silicon oxide (SiO xa plurality of films alternately stacked with one or more inorganic films in the layer. The first encapsulation inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0168] The second encapsulation inorganic film TFE2 can be positioned on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can be formed as a titanium oxide (TiO x ) layer or an aluminum oxide (AlO x ) layer, but the present disclosure is not limited thereto. The second encapsulation inorganic film TFE2 can be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0169] The organic film APL can be a layer for increasing the interfacial adhesion strength between the encapsulation layer TFE and the optical layer OPL. The organic film APL can be an organic film made of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

[0170] The optical layer OPL includes a color filter layer CFL, a lens layer LSL, a fill layer FIL, a cover layer CVL, and a polarizing layer POL.

[0171] The color filter layer CFL can include a plurality of color filters CF1, CF2, and CF3. The plurality of color filters CF1, CF2, and CF3 can include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 can be positioned on the organic film APL.

[0172] The first color filter CF1 can overlap the first emission area EA1 of the first pixel PX1. The first color filter CF1 can transmit light of a first color, for example, light of a red wavelength band therethrough. The red wavelength band can be approximately 600 nm to approximately 750 nm. Accordingly, the first color filter CF1 can transmit light of the first color among light emitted from the first emission area EA1 therethrough.

[0173] The second color filter CF2 can overlap the second emission area EA2 of the second pixel PX2. The second color filter CF2 can transmit light of a second color, for example, light of a green wavelength band therethrough. The green wavelength band can be approximately 480 nm to approximately 560 nm. Accordingly, the second color filter CF2 can transmit light of the second color among light emitted from the second emission area EA2 therethrough.

[0174] The third color filter CF3 can overlap the third emission area EA3 of the third pixel PX3. The third color filter CF3 can transmit a third color of light, for example, light of a blue wavelength band therethrough. The blue wavelength band can be approximately 380 nm to approximately 480 nm. Accordingly, the third color filter CF3 can transmit the third color of light among the light emitted from the third emission area EA3 therethrough.

[0175] The lens layer LSL can be positioned on the color filter layer CFL. The lens layer LSL can include a plurality of lenses LNS. Each of the plurality of lenses LNS can be positioned on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS can be a structure for increasing a ratio of light directed to a front surface of the display apparatus 10. Each of the plurality of lenses LNS can have a cross-sectional shape convex in an upward direction.

[0176] The filling layer FIL can be positioned on the lens layer LSL. For example, the filling layer FIL can be positioned on the plurality of lenses LNS. The filling layer FIL can have a refractive index (for example, a predetermined refractive index) such that light travels in the third direction DR3 at an interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL can be a planarization layer. The filling layer FIL can be an organic film made of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

[0177] The cover layer CVL can be positioned on the filling layer FIL. The cover layer CVL can be a glass substrate or a resin such as a polymer resin. When the cover layer CVL is a glass substrate, the cover layer CVL can be attached to the filling layer FIL. In this case, the filling layer FIL can be used to adhere the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL can function as an encapsulation substrate. When the cover layer CVL is a resin such as a polymer resin, the cover layer CVL can be directly applied to the filling layer FIL.

[0178] The polarization layer POL can be positioned on the cover layer CVL. The polarization layer POL can be a structure for reducing or preventing visibility degradation due to external light reflection. The polarization layer POL can include a linear polarization plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (a quarter wave plate), but the present disclosure is not limited thereto. However, when visibility degradation due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarization layer POL can be omitted.

[0179] Figure 7 is a cross-sectional view of a display apparatus according to one or more embodiments.

[0180] The display device 10 according to one or more embodiments can include an anode electrode AND (i.e., a first electrode AND), a pixel definition film PDL, an emission stack ES, and a cathode electrode CAT (i.e., a second electrode CAT).

[0181] The anode electrode AND can include a first layer LL1, a second layer LL2, a third layer LL3, and a fourth layer LL4.

[0182] The first layer LL1 can be positioned on the eleventh insulating film INS11. The first layer LL1 can be connected to the tenth via hole VA10 on the eleventh insulating film INS11. For example, the first layer LL1 can be connected to the tenth via hole VA10 inside a through hole that penetrates the eleventh insulating film INS11. The first layer LL1 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the first layer LL1 can be made of titanium (Ti). The thickness of the first layer LL1 can be about 200 or less. Meanwhile, in a plan view, the first layer LL1 can have a larger area than the second layer LL2. Here, the thickness can mean a dimension in the third direction DR3, and the area can mean a dimension in the first direction DR1 and the second direction DR2.

[0183] The second layer LL2 can be positioned on the first layer LL1. For example, the second layer LL2 can be positioned at a central portion of an upper surface of the first layer LL1. The second layer LL2 can be positioned between the first layer LL1 and the third layer LL3, which will be described later. For example, the second layer LL2 can be surrounded by the first layer LL1 and the third layer LL3. The second layer LL2 can be in contact with the first layer LL1 on the first layer LL1. The second layer LL2 can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the second layer LL2 can include aluminum (Al). The thickness of the second layer LL2 can be about 200 or more, and the width of the second layer LL2 can be about 3 µm or less. Here, the thickness can mean a dimension in the third direction DR3, and the width can mean a dimension in the first direction DR1 or the second direction DR2.

[0184] The third layer LL3 can be positioned on an upper surface and a side surface of the second layer LL2. The third layer LL3 can be positioned between the second layer LL2 and the fourth layer LL4, which will be described later. The third layer LL3 can include an oxide (e.g., aluminum oxide). For example, the third layer LL3 can be an oxide layer formed on a surface of the second layer LL2, and can include aluminum oxide (AlOx ). The third layer LL3 may have a thickness of about 30 Here, the thickness may refer to a dimension in the third direction DR3.

[0185] The fourth layer LL4 can be positioned on the upper surface and side surface of the third layer LL3. One end of the fourth layer LL4 can be positioned to correspond to one end of the first layer LL1, and the other end of the fourth layer LL4 can be positioned to correspond to the other end of the first layer LL1. Therefore, in a plan view, the edge of the fourth layer LL4 can overlap the edge of the first layer LL1. The fourth layer LL4 can be connected to the first layer LL1. For example, the fourth layer LL4 can be directly connected to the first layer LL1. In other words, the fourth layer LL4 can be directly connected (or coated) to the edge of the upper surface of the first layer LL1. The fourth layer LL4 can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO) or a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). For example, the fourth layer LL4 can include ITO. The thickness of the fourth layer LL4 can be about 300 or less. Meanwhile, in a plan view, the fourth layer LL4 may have a larger area than the second layer LL2. Here, thickness may refer to a size in the third direction DR3, and area may refer to a size in the first direction DR1 and the second direction DR2. Meanwhile, the length of the interface between the fourth layer LL4 and the first layer LL1 may be about 38 nm or more. For example, in Figure 7 , a length of an interface between a left side of the fourth layer LL4 and a left side of the first layer LL1 may be about 38 nm or more, and a length of an interface between a right side of the fourth layer LL4 and a right side of the first layer LL1 may be about 38 nm.

[0186] The pixel defining film PDL may define the emission area EA of the pixel. The pixel defining film PDL may be positioned on the edge and side surface of the upper surface of the fourth layer LL4. In addition, the pixel defining film PDL may also be positioned on the side surface of the first layer LL1. The emission area EA may overlap with the second layer LL2 of the anode electrode AND. For example, in a plan view, the emission area EA may be surrounded by the edge of the second layer LL2. At the same time, as described above Figure 6 Like the pixel defining film PDL, the pixel defining film PDL may include a first pixel defining film PDL1, a second pixel defining film PDL2, and a third pixel defining film PDL3.

[0187] The light emitting stack ES may be positioned on the anode electrode AND and the pixel definition film PDL. Figure 6The light emitting stack ES can have a three-series structure including the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3, as in the light emitting stack ES.

[0188] The cathode electrode CAT can be positioned on the light emitting stack ES. The cathode electrode CAT can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) or a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag) that is capable of transmitting light.

[0189] Meanwhile, Figure 6 The semiconductor back plate SBP, the light emitting element back plate EBP, the reflective electrode layer RL, and the tenth insulating film INS10 can be positioned under the eleventh insulating film INS11. In addition, the encapsulation layer TFE, the organic film APL, and the optical layer OPL can be positioned on Figure 7 the cathode electrode CAT.

[0190] According to one or more embodiments, the first layer LL1 (e.g., a titanium layer) and the fourth layer LL4 (e.g., an ITO layer) of the anode electrode can be in direct contact with each other. Thus, the anode electrode AND according to one or more embodiments can include aluminum, but can not require a TiN layer to reduce or prevent oxidation of the aluminum. An oxide layer of a surface of the aluminum layer shields the electrical connection of the aluminum layer and the titanium layer, and to address such a problem, an additional metal layer (e.g., a TiN layer) can be required between the aluminum layer and the titanium layer. However, the display device 10 according to one or more embodiments does not require such an additional metal layer. Thus, the display device 10 according to one or more embodiments can have high transmittance (e.g., high transmittance due to the omission of the TiN layer) as well as excellent reflectance (e.g., excellent reflectance due to the aluminum layer). Thus, the display device 10 according to one or more embodiments can provide light of high brightness even in a low power case.

[0191] Figures 8 to 17 is a cross-sectional view illustrating a process of a method of manufacturing a display device according to one or more embodiments.

[0192] As Figure 8 As shown in FIG. 1A, after the tenth via hole VA10 and the eleventh insulating film INS11 are formed on the semiconductor substrate SSUB, a first material layer ML1 can be positioned on the eleventh insulating film INS11. For example, the first material layer ML1 can be deposited on the entire surface of the eleventh insulating film INS11 on the semiconductor substrate SSUB. The first material layer ML1 can include titanium.

[0193] Subsequently, as Figure 9As shown in FIG. 1A, a first material layer ML1 can be positioned on the semiconductor substrate S SUB. The first material layer ML1 can include a first sub-material layer SML1 and a second sub-material layer SML2. The first sub-material layer SML1 can be positioned on the semiconductor substrate S SUB. The second sub-material layer SML2 can be positioned on the first sub-material layer SML1. The first sub-material layer SML1 can include a first material. The second sub-material layer SML2 can include a second material. The first material can be different from the second material. For example, the first material can include aluminum (Al). The second material can include titanium (Ti). The first sub-material layer SML1 can be positioned on the semiconductor substrate S SUB. The second sub-material layer SML2 can be positioned on the first sub-material layer SML1.

[0194] Next, as shown in FIG. 1B, a first photoresist pattern PR1 can be positioned on the first material layer ML1. The first photoresist pattern PR1 can have an inverted trapezoidal shape. For example, the first photoresist pattern PR1 can have a width gradually increasing along a third direction DR3. The first photoresist pattern PR1 can be formed as a negative photoresist. For example, the first photoresist pattern PR1 can be formed as a lift-off type photoresist. Figure 10 Next, as shown in FIG. 1C, a second material layer ML2 can be positioned on the first material layer ML1 and the first photoresist pattern PR1. For example, the second material layer ML2 can be deposited on an entire surface of the first material layer ML1 and the first photoresist pattern PR1 on the semiconductor substrate S SUB. The second material layer ML2 can include aluminum (Al). At this time, the second material layer ML2 can be separated into a plurality of portions by the first photoresist pattern PR1 having an inverted trapezoidal shape. For example, the second material layer ML2 can include a first sub-material layer SML1 and a second sub-material layer SML2 separated from each other by the first photoresist pattern PR1. The first sub-material layer SML1 can be positioned on the first material layer ML1. The second sub-material layer SML2 can be positioned on the first photoresist pattern PR1.

[0195] Figure 11 Thereafter, as shown in FIG. 1D, when the second material layer ML2 is maintained for a period of time (e.g., a predetermined time), a third layer LL3 (e.g., an oxide layer) can be formed on a surface of the second material layer ML2. For example, the third layer LL3 (e.g., an oxide layer) can be formed on each of a surface of the first sub-material layer SML1 and a surface of the second sub-material layer SML2. The third layer LL3 can include aluminum oxide.

[0196] Next, as shown in FIG. 1E, the first photoresist pattern PR1 can be removed. At this time, since the first photoresist pattern PR1 is removed, the second sub-material layer SML2 and the third layer LL3 on the first photoresist pattern PR1 can be removed together with the first photoresist pattern PR1. Since the second sub-material layer SML2 of the second material layer ML2 is removed, a second layer LL2 can be formed on the first material layer ML1. In other words, after the first photoresist pattern PR1 and the second sub-material layer SML2 are removed, the first sub-material layer SML1 remaining on the first material layer ML1 can be used as the second layer LL2. The first photoresist pattern PR1 can be removed by a lift-off agent. Figure 12 Subsequently, as shown in FIG. 1F, a third material layer ML3 can be positioned on the second layer LL2. The third material layer ML3 can include a third material. The third material can be different from the first material and the second material. For example, the third material can include titanium (Ti). The third material layer ML3 can be deposited on the second layer LL2. The third material layer ML3 can be deposited on the second layer LL2 by a physical vapor deposition (PVD) method. The third material layer ML3 can be deposited on the second layer LL2 by a chemical vapor deposition (CVD) method.

[0197] Figure 13 ​​As shown in FIG. 1A, a fourth material layer ML4 can be positioned on the third layer LL3. The fourth material layer ML4 can be deposited on the entire surface of the third layer LL3 on the semiconductor substrate SSUB. The fourth material layer ML4 can include ITO.

[0198] Thereafter, as shown in FIG. 1C, a second photoresist pattern PR2 can be positioned on the fourth material layer ML4. The second photoresist pattern PR2 can have a positive taper shape. For example, the second photoresist pattern PR2 can have a width that gradually decreases along the third direction DR3. The second photoresist pattern PR2 can be formed as a positive photoresist. Figure 14

[0199] Next, as shown in FIG. 1D, the fourth material layer ML4 and the first material layer ML1 can be removed using the second photoresist pattern PR2 as a mask. For example, portions of the fourth material layer ML4 and the first material layer ML1 that are not covered by and exposed by the second photoresist pattern PR2 can be removed by an etchant. As each of the portions of the fourth material layer ML4 and the first material layer ML1 is removed by an etching process in which the second photoresist pattern PR2 is used as a mask, a fourth layer LL4 and a first layer LL1 can be formed. Accordingly, an anode electrode AND including the first layer LL1, the second layer LL2, the third layer LL3, and the fourth layer LL4 can be formed. Figure 15 Thereafter, as shown in FIG. 1E, the second photoresist pattern PR2 can be removed. The second photoresist pattern PR2 can be removed by a stripper.

[0200] Figure 16 Subsequently, as shown in FIG. 1F, a pixel definition layer PDL can be positioned on the anode electrode AND. For example, the pixel definition layer PDL can be positioned on the fourth layer LL4 of the anode electrode AND.

[0201] Next, a light emitting stack ES can be positioned on the anode electrode AND and the pixel definition layer PDL, and a cathode electrode CAT can be positioned on the light emitting stack ES. Figure 17

[0202] FIG. 1G is a cross-sectional view of a display apparatus according to one or more other embodiments.

[0203] Figure 18 FIG. 1G is a cross-sectional view of a display apparatus according to one or more other embodiments.

[0204] Figure 18 The display apparatus 10 of FIG. 1G is different from the display apparatus 10 of FIG. 1A in that the anode electrode AND further includes a fifth layer LL5, and the following will mainly describe this difference. Figure 7 As shown in FIG. 1G, a fifth material layer ML5 can be positioned on the fourth layer LL4. The fifth material layer ML5 can be deposited on the entire surface of the fourth layer LL4 on the semiconductor substrate SSUB. The fifth material layer ML5 can include ITO.

[0205] Figure 18 ​​​​As shown in FIG. 1, the anode electrode AND can include a first layer LL1, a second layer LL2, a third layer LL3, a fourth layer LL4, and a fifth layer LL5. Here, the fifth layer LL5 can be positioned between the third layer LL3 and the fourth layer LL4. The fifth layer LL5 can include an inorganic layer.

[0206] The fifth layer LL5 of the anode electrode AND can be surrounded by the third layer LL3 and the fourth layer LL4. The third layer LL3 can be positioned on a lower surface of the fifth layer LL5, and the fourth layer LL4 can be positioned on an upper surface and side surfaces of the fifth layer LL5.

[0207] One end of the fifth layer LL5 and one end of the second layer LL2 can be positioned to correspond to each other, and the other end of the fifth layer and the other end of the second layer LL2 can be positioned to correspond to each other. Thus, in a plan view, edges of the fifth layer LL5 and edges of the second layer LL2 can be overlapped with each other.

[0208] Due to the fifth layer LL5, the resonance distance for each pixel can become different, and as described below with reference to Figure 19 Detailed Description.

[0209] Figure 19 is a diagram for describing a resonance distance for each pixel in a display device according to one or more embodiments.

[0210] As Figure 19 As shown in FIG. 1, the first pixel PX1 can include a first anode electrode AND1 and a first color filter CF1, the second pixel PX2 can include a second anode electrode AND2 and a second color filter CF2, and the third pixel PX3 can include a third anode electrode AND3 and a third color filter CF3.

[0211] The first anode electrode AND1 can be positioned to correspond to the first color filter CF1. The first anode electrode AND1 can include a first layer LL1, a second layer LL2, a third layer LL3, a fourth layer LL4, and a fifth layer LL5.

[0212] The second anode electrode AND2 can be positioned to correspond to the second color filter CF2. The second anode electrode AND2 can include a first layer LL1', a second layer LL2', a third layer LL3', a fourth layer LL4', and a fifth layer LL5'. A thickness tk2 of the fifth layer LL5' of the second anode electrode AND2 can be different from a thickness tk1 of the fifth layer LL5 of the first anode electrode AND1. For example, when the thickness tk1 of the fifth layer LL5 of the first anode electrode AND1 is defined as a first thickness tk1 and the thickness tk2 of the fifth layer LL5' of the second anode electrode AND2 is defined as a second thickness tk2, the second thickness tk2 can be smaller than the first thickness tk1. According to one or more embodiments, the first thickness tk1 can be twice the second thickness tk2. Here, the thickness can mean a size in the third direction DR3.

[0213] The third anode electrode AND3 can be positioned to correspond to the third color filter CF3. The third anode electrode AND3 can include a first layer LL1'', a second layer LL2'', a third layer LL3'', and a fourth layer LL4''. For example, the third anode electrode AND3 can not include a fifth layer. In other words, a thickness of the fifth layer of the third anode electrode AND3 can be zero.

[0214] As described above, because the first pixel PX1, the second pixel PX2, and the third pixel PX3 include the fifth layers LL5 / LL5' of different thicknesses, a resonance distance in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can become different. For example, a resonance distance rd1 (hereinafter, a first resonance distance) of the first pixel PX1 can be the largest, a resonance distance rd3 (hereinafter, a third resonance distance) of the third pixel PX3 can be the smallest, and a resonance distance rd2 (hereinafter, a second resonance distance) of the second pixel PX2 can be greater than the third resonance distance rd3 and smaller than the first resonance distance rd1. Here, the resonance distance can mean a distance in the third direction DR3.

[0215] Each of the resonance distances rd1, rd2, and rd3 can be defined as a distance between the anode electrodes AND1, AND2, and AND3 and the cathode electrode CAT of the respective pixels PX1, PX2, and PX3. For example, the first resonance distance rd1 can be defined as a distance between the second layer LL2 of the first anode electrode AND1 and the cathode electrode CAT, the second resonance distance rd2 can be defined as a distance between the second layer LL2' of the second anode electrode AND2 and the cathode electrode CAT, and the third resonance distance rd3 can be defined as a distance between the second layer LL2'' of the third anode electrode AND3 and the cathode electrode CAT.

[0216] Accordingly, the microcavity (or thin film resonance) effect on light can be increased and / or can be optimized according to the wavelength of light to be emitted from each of the pixels PX1, PX2, and PX3 and the corresponding resonance distance and / or resonance order. For example, the first color light, the second color light, and the third color light can be appropriately amplified in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. As one or more embodiments, the first color light emitted through the first emission area EA1 can be red light corresponding to the first color filter CF1, the second color light emitted through the second emission area EA2 can be green light corresponding to the second color filter CF2, and the third color light emitted through the third emission area EA3 can be blue light corresponding to the third color filter CF3. In other words, the second resonance distance rd2 of the second emission area EA2 emitting green light can be smaller than the first resonance distance rd1 of the first emission area EA1 emitting red light, and can be greater than the third resonance distance rd3 of the third emission area EA3 emitting blue light.

[0217] According to one or more embodiments, after the third layer LL3 is formed, the fifth layer LL5 of the above-described Figure 18 is formed through a photolithography process and an etching process of an inorganic layer (e.g., a material layer of the fifth layer LL5). For example, the fifth layer LL5 can be formed by patterning an inorganic layer positioned on the third layer LL3 after the process of the above-described Figure 12 . For example, the forming process of the fifth layer LL5 can be performed between the process of the above-described Figure 12 and the process of the above-described Figure 13 . Meanwhile, as shown in the above-described Figure 19 , in the case where the thickness of the fifth layer is different from each other for each pixel, a half-tone mask can be used to form the fifth layer of different thicknesses. Alternatively, since a separate photolithography process and an etching process are separately performed after the inorganic layer of different heights is formed for each pixel, the fifth layer having different thicknesses for each pixel can be sequentially formed.

[0218] Meanwhile, Figure 19 the encapsulation layer TFE of the above-described Figure 6 may include the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE2 of the above-described

[0219] Figure 20 is a perspective view illustrating a head-mounted display according to one or more embodiments. Figure 21 is an exploded perspective view illustrating an example of the head-mounted display of the above-described Figure 20 .

[0220] Referring to Figure 20 and Figure 21, the head-mounted display device 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing part 1100, a housing part cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0221] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described with reference to Figures 1 to 19 The display device 10 described is substantially the same as the first display device 10_1 and the second display device 10_2, and thus a repeated description of the first display device 10_1 and the second display device 10_2 is omitted.

[0222] The first optical member 1510 can be positioned between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 can be positioned between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0223] The intermediate frame 1400 can be positioned between the first display device 10_1 and the control circuit board 1600, and can be positioned between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 serves to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0224] The control circuit board 1600 can be positioned between the intermediate frame 1400 and the display device housing part 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA, and can transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0225] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0226] The display device housing part 1100 serves to accommodate the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing part cover 1200 is positioned to cover one surface of the display device housing part 1100 which is open. The housing part cover 1200 can include a first ocular lens 1210 on which a left eye of a user is positioned and a second ocular lens 1220 on which a right eye of the user is positioned. In Figure 20 and Figure 21 The first ocular lens 1210 and the second ocular lens 1220 have been shown to be positioned individually, but the present disclosure is not limited thereto. The first ocular lens 1210 and the second ocular lens 1220 can be merged into one ocular lens.

[0227] The first ocular lens 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second ocular lens 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first ocular lens 1210, and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second ocular lens 1220.

[0228] The head-mounted band 1300 serves to fix the display device housing part 1100 to the head of the user so that the first ocular lens 1210 and the second ocular lens 1220 of the housing part cover 1200 can be maintained in a state in which they are positioned on the left eye and the right eye of the user, respectively. When the display device housing part 1100 is implemented to have a light weight and a small size, the head-mounted display device 1000 can include a spectacle frame as shown in Figure 22 instead of the head-mounted band 1300.

[0229] In addition, the head-mounted display device 1000 can further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a wireless fidelity (WiFi ® ) module, or a Bluetooth ® module (Bluetooth ® is a registered trademark of Bluetooth Sig, Inc. of Kirkland, Washington, and Wi Fi ® is a registered trademark of the non-profit Wireless Fidelity Alliance).

[0230] Figure 22is a perspective view showing a head-mounted display according to one or more other embodiments.

[0231] Referring to Figure 22 , the head-mounted display device 1000_1 according to one or more other embodiments can be a glasses-type display device in which the display device housing part 1200_1 is implemented to have a light mass and a small size. The head-mounted display device 1000_1 according to one or more other embodiments can include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, glasses frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing part 1200_1.

[0232] The display device housing part 1200_1 can accommodate the display device 10_3, the optical member 1060, and the optical path conversion member 1070. An image displayed on the display device 10_3 can be enlarged by the optical member 1060, converted in an optical path by the optical path conversion member 1070, and provided to the user's right eye through the right eye lens 1020. For this reason, the user can watch an augmented reality image in which a real image displayed on the display device 10_3 and a virtual image seen through the right eye lens 1020 are combined with each other through his / her right eye.

[0233] In Figure 22 , it has been shown that the display device housing part 1200_1 is positioned at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing part 1200_1 can be positioned at the left end of the support frame 1030, in which case an image of the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing part 1200_1 can be positioned at both the left end and the right end of the support frame 1030, in which case the user can watch an image displayed on the display device 10_3 through both his / her left eye and right eye.

[0234] It will be understood by those of ordinary skill in the art to which the present disclosure pertains that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it will be understood that the above-described embodiments are illustrative, not limiting. It will be understood that the scope of the present disclosure is defined by the claims, not the above detailed description, and all modifications and alterations derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device comprising: a substrate; an anode electrode over the substrate and comprising: a first layer; a second layer over the first layer; a third layer over an upper surface and a side surface of the second layer; and a fourth layer connected to the first layer and over an upper surface of the first layer, an upper surface of the third layer, and a side surface of the third layer; a light emitting stack over the anode electrode; and a cathode electrode over the light emitting stack.

2. The display device according to claim 1, wherein The second layer and the third layer are surrounded by the first layer and the fourth layer.

3. The display device according to claim 1, wherein The first layer is connected to a transistor by a via.

4. The display device according to claim 1, wherein The fourth layer is connected to the light emitting stack.

5. The display device according to claim 1, wherein The fourth layer is directly connected to the first layer.

6. The display device of claim 5, wherein, The fourth layer is directly connected to the upper surface of the first layer.

7. The display device according to claim 1, wherein The second layer is at a central portion of the upper surface of the first layer.

8. The display device according to claim 1, wherein The first layer comprises titanium, wherein the second layer comprises aluminum, wherein the third layer comprises aluminum oxide, and wherein the fourth layer comprises a transparent conductive material.

9. The display device of claim 8, wherein, The transparent conductive material comprises indium tin oxide.

10. The display device according to claim 1, wherein The anode electrode further comprises a fifth layer between the third layer and the fourth layer.

11. The display device of claim 10, wherein, The fifth layer comprises an inorganic layer.

12. The display device of claim 11, wherein, The anode electrode is provided as a plurality and comprises a first anode electrode of a first pixel, a second anode electrode of a second pixel, and a third anode electrode of a third pixel.

13. The display device of claim 12, wherein, The fifth layer of the first anode electrode, the fifth layer of the second anode electrode, and the fifth layer of the third anode electrode have different respective thicknesses.

14. The display device of claim 13, further comprising: a first color filter over the first anode electrode; a second color filter over the second anode electrode; and a third color filter over the third anode electrode. The first color filter is configured to transmit red light, 15. The display device of claim 14, wherein, wherein the second color filter is configured to transmit green light, and wherein the third color filter is configured to transmit blue light. A thickness of the fifth layer of the second anode electrode is less than a thickness of the fifth layer of the first anode electrode and greater than a thickness of the fifth layer of the third anode electrode.

16. The display device of claim 15, wherein, 17. A method of manufacturing a display device, the method comprising the steps of: forming an insulating layer over a substrate; forming a first material layer over the insulating layer; forming a first photoresist pattern having an inverse-trapezoidal shape of a side surface over the first material layer; forming a second material layer comprising a first sub-material layer over the first material layer and a second sub-material layer over the first photoresist pattern; forming a third layer separated by the first photoresist pattern over the first sub-material layer and over the second sub-material layer; removing the first photoresist pattern such that a second layer is left over the first material layer; forming a fourth material layer over the third layer; forming a second photoresist pattern over the fourth material layer; ​ selectively removing the fourth layer of material and the first layer of material using the second photoresist pattern as a mask such that a fourth layer and a first layer are retained; removing the second photoresist pattern such that an anode electrode comprising the first layer, the second layer, the third layer, and the fourth layer is retained; forming a pixel defining film over the anode electrode; forming a light emitting stack over the pixel defining film and the anode electrode; and forming a cathode electrode over the light emitting stack.

18. The method of claim 17, wherein, the second layer is on the first layer, wherein the third layer is on an upper surface and side surfaces of the second layer, and wherein the fourth layer is on an upper surface of the first layer, an upper surface of the third layer, and side surfaces of the third layer.

19. The method of claim 17, wherein, the second layer and the third layer are surrounded by the first layer and the fourth layer.

20. The method of claim 17, wherein, the fourth layer is directly connected to the first layer.

21. The method of claim 20, wherein, the fourth layer is directly connected to an edge of the first layer.

22. The method of claim 17, wherein, the second layer is at a central portion of an upper surface of the first layer.

23. The method of claim 17, wherein, the first layer comprises titanium, wherein the second layer comprises aluminum, wherein the third layer comprises aluminum oxide, and wherein the fourth layer comprises a transparent conductive material.

24. The method of claim 17, further comprising forming a fifth layer between the third layer and the fourth layer.

25. The method of claim 24, wherein, the fifth layer comprises an inorganic layer.

Images