Display device, method of manufacturing same, and electronic device

Abstract

A display device, a method of manufacturing the same, and an electronic device are provided. The display device includes: a semiconductor backplane including a pixel transistor; a light emitting element backplane over the semiconductor backplane and including a conductive layer, a via hole, and an insulating film; and a display element layer over the light emitting element backplane, in which a light emitting element for emitting light is disposed, and including: a reflective electrode layer; a first electrode over the reflective electrode layer and in direct contact with the reflective electrode layer; and a stacked layer and a second electrode sequentially stacked over the first electrode.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0050738, filed on April 16, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates to a display device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] A wearable device that forms a focal point at a distance close to a user's eyes has been developed in the form of glasses or a helmet. For example, the wearable device can be a head-mounted display (HMD) device or AR glasses. The wearable device provides a user with an augmented reality (referred to as "AR") screen or a virtual reality (hereinafter, referred to as "VR") screen.

[0004] The wearable device such as the HMD device or the AR glasses can appropriately use a display specification of at least about 2000 PPI (pixels per inch), so that the user can use it for a long time without dizziness. For this, silicon-based organic light emitting diode (OLED) technology, which is a high-resolution small organic light emitting display device, is on the rise. Silicon-based organic light emitting diode (OLEDoS) is a technology for disposing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is positioned. SUMMARY

[0005] Aspects of the disclosure provide a display device that provides an ultra-high resolution display panel and is capable of improving light efficiency of a light emitting element, and also provide a manufacturing method thereof and an electronic device.

[0006] According to one or more embodiments of the disclosure, a display device includes a semiconductor backplane including a pixel transistor, a light emitting element backplane above the semiconductor backplane and including a conductive layer, a via, and an insulating film, and a display element layer above the light emitting element backplane, in which a light emitting element for emitting light is disposed, and includes a reflective electrode layer, a first electrode above the reflective electrode layer and directly contacting the reflective electrode layer, and a stack layer and a second electrode sequentially stacked above the first electrode.

[0007] The reflective electrode layer can include a first reflective electrode, a second reflective electrode above the first reflective electrode, a third reflective electrode above the second reflective electrode, and a fourth reflective electrode above the third reflective electrode.

[0008] The first electrode can be above the fourth reflective electrode and can directly contact the fourth reflective electrode.

[0009] The display element layer can include a pixel defining film that covers edges of the first electrode and defines a first light emitting area of the first sub-pixel, a second light emitting area of the second sub-pixel, and a third light emitting area of the third sub-pixel.

[0010] The pixel defining film can include a first pixel defining film, a second pixel defining film above the first pixel defining film, and a third pixel defining film above the second pixel defining film, wherein the pixel defining film has a cross-sectional structure having a stepped portion.

[0011] The display element layer can define at least one trench that penetrates the first pixel defining film to the third pixel defining film.

[0012] The at least one trench can penetrate some of the insulating films of the light emitting element backplane between the reflective electrode layer and the adjacent reflective electrode layer.

[0013] The at least one trench can include a pair of trenches between adjacent sub-pixels among the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0014] According to one or more embodiments disclosed, a method of manufacturing a display device includes forming a semiconductor backplane including a pixel transistor above a semiconductor substrate, forming a light emitting element backplane including a conductive layer, a via, and an insulating film above the semiconductor backplane, and forming a display element layer including a light emitting element that emits light above the light emitting element backplane, the display element layer being formed by sequentially stacking a first metal layer for a reflective electrode layer and a second metal layer for a first electrode, forming the reflective electrode layer and the first electrode corresponding to each of the sub-pixels by patterning the second metal layer and the first metal layer, depositing an additional insulating film for a pixel defining film above the reflective electrode layer and the first electrode, and patterning the additional insulating film to form the pixel defining film that covers edges of the first electrode and defines a first light emitting area of the first sub-pixel, a second light emitting area of the second sub-pixel, and a third light emitting area of the third sub-pixel.

[0015] The first electrode can directly contact the reflective electrode layer.

[0016] The reflective electrode layer can include a first reflective electrode, a second reflective electrode above the first reflective electrode, a third reflective electrode above the second reflective electrode, and a fourth reflective electrode above the third reflective electrode.

[0017] The first electrode can be above the fourth reflective electrode and can directly contact the fourth reflective electrode.

[0018] The pixel definition film can include a first pixel definition film, a second pixel definition film above the first pixel definition film, and a third pixel definition film above the second pixel definition film, wherein the forming of the pixel definition film includes selectively patterning the other insulating film such that the pixel definition film has a cross-sectional structure having a stepped portion.

[0019] The forming of the display element layer can further include forming at least one trench penetrating the first pixel definition film, the second pixel definition film, and the third pixel definition film.

[0020] The at least one trench can penetrate some of the insulating films of the light emitting element backplane between the reflective electrode layer and an adjacent reflective electrode layer.

[0021] According to one or more embodiments disclosed, an electronic device includes a display panel over a semiconductor base, the display panel including: a semiconductor backplane including a pixel transistor; a light emitting element backplane over the semiconductor backplane and including a conductive layer, a via, and an insulating film; and a display element layer over the light emitting element backplane, in which a light emitting element for emitting light is disposed, and including: a reflective electrode layer; a first electrode over the reflective electrode layer and directly contacting the reflective electrode layer; and a stack layer and a second electrode sequentially stacked over the first electrode.

[0022] The reflective electrode layer can include a first reflective electrode, a second reflective electrode over the first reflective electrode, a third reflective electrode over the second reflective electrode, and a fourth reflective electrode over the third reflective electrode.

[0023] The first electrode can be over the fourth reflective electrode and can directly contact the fourth reflective electrode.

[0024] The display element layer can include a pixel definition film covering edges of the first electrode and defining a first light emitting area of a first sub-pixel, a second light emitting area of a second sub-pixel, and a third light emitting area of a third sub-pixel.

[0025] The pixel definition film can include a first pixel definition film, a second pixel definition film over the first pixel definition film, and a third pixel definition film over the second pixel definition film, wherein the pixel definition film has a cross-sectional structure having a stepped portion.

[0026] In the display device according to the embodiments, the electronic device including the same, and the manufacturing method thereof, an ultra-high resolution display panel can be provided, and light efficiency of a light emitting element can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which: Figure 1 is an exploded perspective view illustrating a display apparatus according to one or more embodiments; Figure 2 is a block diagram illustrating a display apparatus according to one or more embodiments; Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments; Figure 4 is a layout diagram illustrating an example of a display panel according to one or more embodiments; Figure 5 and Figure 6 is a layout diagram illustrating an example of a display panel according to one or more embodiments; Figure 4 Figure 7 is a cross-sectional view illustrating an example of a display panel taken along a line I1-I1' of Figure 5 Figure 8 is a perspective view illustrating a head-mounted display according to one or more embodiments; Figure 9 is an exploded perspective view illustrating an example of a head-mounted display of Figure 8 Figure 10 is a perspective view illustrating a head-mounted display according to one or more embodiments; Figure 11 is a cross-sectional view illustrating a display element layer of a display panel according to one or more embodiments; Figures 12 to 17 is a cross-sectional view illustrating a process step of a method of manufacturing a display element layer of a display panel according to one or more embodiments; Figure 18 is a layout diagram illustrating a display area according to a comparative example; and Figure 19 is a layout diagram illustrating a display area according to one or more embodiments. DETAILED DESCRIPTION

[0028] Aspects of some embodiments of the present disclosure and methods implementing the same can be more readily understood by reference to the following detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are redundant, that are unrelated to the embodiments, or that are otherwise not necessary to understanding the aspects of the present disclosure can be omitted from the description. Identical reference numerals, characters or combinations thereof throughout the accompanying drawings and written description indicate the same elements, and thus, repetitive descriptions can be omitted.

[0029] ​​​The described embodiments can have various modifications and can be implemented in different forms and should not be construed as being limited to the embodiments shown in the drawings. The use of "can," "could," or "might" corresponds to one or more embodiments of the present disclosure.

[0030] Those of ordinary skill in the art will appreciate that, in light of the overall disclosure, the present disclosure encompasses all modifications and alternatives in the scope of the ideas and techniques of the present disclosure, each of the features of the embodiments of the present disclosure can be partially or wholly combined with each other, and technically various interlocks and operations are possible, and each embodiment can be implemented independently of each other or can be implemented together in association unless otherwise stated or implied, or each embodiment can be implemented independently of each other or can be implemented together in association unless otherwise stated or implied.

[0031] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. In other words, since the sizes and thicknesses of the elements in the drawings are arbitrarily shown for the purpose of facilitating description, the disclosure is not limited thereto. In addition, the use of cross-hatching and / or shading in the drawings is for clarity and is not intended to convey or imply any preference or requirement regarding particular materials, material properties, dimensions, proportions, commonality of elements between illustrations, and / or any other characteristic, attribute, property, or the like of the elements shown.

[0032] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures being described and / or illustrated. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, the specific structural and functional details disclosed herein are merely representative for purposes of describing and illustrating the embodiments in accordance with the present disclosure. Thus, the embodiments disclosed herein are not to be interpreted as being limited to the particular combinations or sequences of elements as set forth herein.

[0033] For example, an implant region shown as rectangular will typically have rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation was performed.

[0034] For ease of explanation, spatially relative terms, such as "beneath", "below", "lower", "underside", "under", "above", "upper", "over", "higher", "top", "side" (as in "sidewall") and the like, can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "beneath" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it can mean that the first part is arranged on the upper side or lower side of the second part, without being limited to a direction based on a gravitational direction.

[0035] Further, the phrase "in plan view" means when viewing the object portion from above, and the phrase "in schematic cross-sectional view" means when viewing a schematic cross-section taken through a vertical cut of the object portion from the side. The term "overlie" or "overlap" means that a first object can be above or below or to the side of a second object, or vice versa. Additionally, the term "overlie" can include stack, face or confront, extend above, cover or partially cover, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The expression "not overlie" can include the meaning of "away from" or "offset from" or "offset from", as well as any other suitable equivalent as would be appreciated and understood by one of ordinary skill in the art. The terms "confront" and "face" can mean that a first object can be directly or indirectly opposite a second object. In case a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, although still confronting each other.

[0036] It will be understood that when an element, layer, region or component is referred to as being "formed on" another element, layer, region or component, "on" another element, layer, region or component, "connected to" or "coupled to" another element, layer, region or component, it can be directly formed on, on, directly connected to, or coupled to, the other element, layer, region or component, or indirectly formed on, on, indirectly connected to, or coupled to, the other element, layer, region or component, such that one or more intervening elements, layers, regions or components can exist. In addition, this can be collectively referred to as direct or indirect coupling or connection and unitary or non-unitary coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or coupled to the other layer, region and / or component, or one or more intervening layers, regions or components can exist. The one or more intervening components can include switches, resistors, capacitors, etc. In describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected or coupled to another component, or directly on another component, without an intermediate component.

[0037] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the case where the part is "directly under" the other part, but also includes the case where there is still another part between the part and the other part. Meanwhile, other expressions describing the relationship between components, such as "between", "immediately between", or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also exist.

[0038] For purposes of this disclosure, expressions such as “at least one of,” or “one or more of,” when preceding a list of two or more items, modify the entire list of items and do not modify the individual items of the list. For example, “at least one of X, Y, and Z” and “at least one of, from, or selected from the group consisting of X, Y, and Z” can be interpreted to mean X alone, Y alone, Z alone, or any combination or subset of X, Y, and Z such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any combination or all combinations of one or more of the associated list items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of,” “one or more of,” “one of,” and other similar phrases preceding a list of two or more items are intended to mean one or more of the individual items in the list and not a combination of the items in the list. When the phrase “from C to D” is used, it means C or greater and D or less, unless otherwise stated.

[0039] It will be understood that, although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, section or part from another element, component, region, layer, section or part. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure. An element described as “first” need not necessarily be present before an element described as “second.” The terms “first,” “second,” etc. can also be used herein for the sake of clarity to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc. can be used herein to designate the “first category (or first group)” and the “second category (or second group),” respectively.

[0040] In examples, the x-axis, the y-axis, and / or the z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0041] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] As used herein, the terms "substantially," "approximately," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% of a value. As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value of measurement, as determined by one of ordinary skill in the art, taking into account measurement error associated with the particular quantity measured. For example, "about" can mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of a stated value. Furthermore, the use of "may" in describing embodiments of the disclosure is intended to mean that one or more embodiments of the disclosure.

[0043] In some embodiments, well-known structures and devices are described in the figures according to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring various embodiments. Those skilled in the art will appreciate that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, lines of code, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software, optionally driven by firmware and / or software. Also, each block, unit, and / or module can be implemented by dedicated hardware, or a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform functions different from that of the dedicated hardware. Further, in some embodiments, blocks, units, and / or modules can be physically separated without departing from the scope of the disclosure, and can be physically combined in a single block, unit, and / or module without departing from the scope of the disclosure.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0045] Figure 1 is an exploded perspective view illustrating a display apparatus according to one or more embodiments. Figure 2 is a block diagram illustrating a display apparatus according to one or more embodiments.

[0046] Referring to Figure 1 and Figure 2 The display apparatus 10 according to one or more embodiments is an apparatus that displays a moving image or a still image. The display apparatus 10 according to one or more embodiments can be applied to a portable electronic apparatus such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), etc. For example, the display apparatus 10 according to one or more embodiments can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. Alternatively, the display apparatus 10 according to one or more embodiments can be applied to a smart watch, a watch phone, a head-mounted display (HMD) for implementing virtual reality and augmented reality, etc.

[0047] The display apparatus 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply circuit 500.

[0048] The display panel 100 can have a planar shape similar to a quadrilateral shape. For example, the display panel 100 can have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 crossing the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be a right angle or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to the quadrilateral shape, and can be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display apparatus 10 can conform to the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0049] As Figure 2As shown in FIG. 1, the display panel 100 includes a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0050] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0051] The plurality of pixels PX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can extend in the first direction DR1 while being arranged in the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 while being arranged in the first direction DR1.

[0052] The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL includes a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0053] The plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 can include a plurality of pixel transistors as shown in FIG. 2, and the plurality of pixel transistors can be formed by a semiconductor process and can be located on a semiconductor substrate SSUB (see FIG. 3) (as used herein, "on" or "formed on" can mean "over"). For example, the plurality of pixel transistors of the plurality of sub-pixels SP1, SP2, and SP3 can be formed of a complementary metal-oxide semiconductor (CMOS). Figure 3 Figure 7 The plurality of sub-pixels SP1, SP2, and SP3 can each be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines GBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and can emit light from a light emitting element according to the data voltage.

[0054] The plurality of sub-pixels SP1, SP2, and SP3 can each be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines GBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and can emit light from a light emitting element according to the data voltage.

[0055] The non-display area NDA includes a scan driver 610, an emission driver 620, and a data driver 700.

[0056] ​The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emission transistors. The plurality of scan transistors and the plurality of light emission transistors can be formed on a semiconductor substrate S SUB (see Figure 7 ) by a semiconductor process. For example, the plurality of scan transistors and the plurality of light emission transistors can be formed by CMOS. Although the scan driver 610 is shown to be located at the left side of the display area DAA and the emission driver 620 is shown to be located at the right side of the display area DAA in Figure 2 , the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 can be located at both the left side and / or the right side of the display area DAA.

[0057] The scan driver 610 can include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 can receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 can generate write scan signals in accordance with the scan timing control signal SCS from the timing controller 400, and can sequentially output them to the write scan lines GWL. The control scan signal output unit 612 can generate control scan signals in response to the scan timing control signal SCS, and can sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 can generate bias scan signals in accordance with the scan timing control signal SCS, and can sequentially output them to the bias scan lines GBL.

[0058] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing controller 400. The first emission control driver 621 can generate first emission control signals in accordance with the emission timing control signal ECS, and can sequentially output them to the first emission control lines EL1. The second emission control driver 622 can generate second emission control signals in accordance with the emission timing control signal ECS, and can sequentially output them to the second emission control lines EL2.

[0059] The data driver 700 can include a plurality of data transistors, and the plurality of data transistors can be formed on a semiconductor substrate S SUB (see Figure 7 ) by a semiconductor process. For example, the plurality of data transistors can be formed by CMOS.

[0060] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing controller 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0061] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be located on one surface of the display panel 100, for example, on the rear surface thereof. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer containing a high thermal conductivity material such as silver (Ag), copper (Cu), or aluminum (Al), or graphite.

[0062] The circuit board 300 may be electrically connected to the first pad portion PDA1 (see FIG. 1 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of the multiple first pad PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Although the circuit board 300 is Figure 1 100, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be located on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be the first pad portion PDA1 of the circuit board 300 connected to the display panel 100 by using a conductive adhesive member (see FIG. Figure 4 ) of the multiple first pad PD1 (see Figure 4 ) at the opposite end of the other end.

[0063] The timing controller 400 may receive digital video data DATA and timing signals input from the outside. The timing controller 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing controller 400 may output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing controller 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0064] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and can supply them to the display panel 100. Details thereof will be described later in connection with Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0065] Each of the timing controller 400 and the power supply circuit 500 can be formed as an integrated circuit (IC), and can be attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing controller 400 can be supplied to the display panel 100 through the circuit board 300. Further, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0066] Alternatively, each of the timing controller 400 and the power supply circuit 500 can be located in the non-display area NDA of the display panel 100, similar to the scan driver 610, the emission driver 620, and the data driver 700. In this case, the timing controller 400 can include a plurality of timing transistors, and each of the power supply circuits 500 can include a plurality of power supply transistors. The plurality of timing transistors and the plurality of power supply transistors can be formed on a semiconductor substrate SSUB (see Figure 7 ) by a semiconductor process. For example, the plurality of timing transistors and the plurality of power supply transistors can be formed by CMOS. Each of the timing controller 400 and the power supply circuit 500 can be located between the data driver 700 and the first pad portion PDA1 (see Figure 4 ).

[0067] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments.

[0068] Referring to Figure 3The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Further, the first sub-pixel SP1 can be connected to the first drive voltage line VSL to which the first drive voltage VSS corresponding to a low potential voltage is applied, the second drive voltage line VDL to which the second drive voltage VDD corresponding to a high potential voltage is applied, and the third drive voltage line VIL to which the third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0069] The first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0070] The light emitting element LE emits light in response to a drive current flowing through a channel of the first transistor T1. An emission amount of the light emitting element LE can be proportional to the drive current. The light emitting element LE can be located between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode thereof can be connected to the first drive voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer located between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0071] The first transistor T1 can be a drive transistor that controls a source-drain current (e.g., a drive current) flowing between a source electrode and a drain electrode thereof according to a voltage applied to a gate electrode thereof. The first transistor T1 includes the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0072] The second transistor T2 can be located between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Accordingly, a data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0073] The third transistor T3 can be located between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, since the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0074] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, a driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0075] The fifth transistor T5 can be located between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, a third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0076] The sixth transistor T6 can be located between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, a second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0077] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0078] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second drive voltage line VDL.

[0079] The first node N1 is a junction point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0080] Each of the first transistor T1 to the sixth transistor T6 can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 can be an N-type MOSFET. Alternatively, one or more of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, and one or more of the remaining transistors can be an N-type MOSFET.

[0081] Although the first sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors CP1 and CP2 in Figure 3 , it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to the equivalent circuit diagram shown in Figure 3 . For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to the numbers shown in Figure 3 .

[0082] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in connection with Figure 3 . Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 is not repeated in the present disclosure.

[0083] Figure 4 is a layout diagram showing an example of a display panel according to one or more embodiments.

[0084] Referring to Figure 4 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0085] The scan driver 610 can be located at a first side of the display area DAA, and the emission driver 620 can be located at a second side of the display area DAA. For example, the scan driver 610 can be located at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be located at the other side of the display area DAA in the first direction DR1 (e.g., the scan driver 610 can be located at the left side of the display area DAA, and the emission driver 620 can be located at the right side of the display area DAA). However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 can be located at both the first side and the second side of the display area DAA.

[0086] The first pad portion PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through conductive adhesive members. The first pad portion PDA1 can be located at a third side of the display area DAA. For example, the first pad portion PDA1 can be located at one side of the display area DAA in the second direction DR2.

[0087] The first pad portion PDA1 can be located outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 can be positioned closer to the edge of the display panel 100 than the data driver 700.

[0088] The second pad portion PDA2 can include a plurality of second pads PD2 corresponding to check pads for checking whether the test display panel 100 operates normally. The plurality of second pads PD2 can be connected to a jig or a probe pin during a checking process, or can be connected to a circuit board for checking. The circuit board for checking can be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0089] The first distribution circuit 710 distributes data voltages applied through the first pad portions PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute data voltages applied through one first pad PD1 of the first pad portions PDA1 to P (P is a positive integer of 2 or more) data lines DL, as a result, the number of the plurality of first pads PD1 can be reduced. The first distribution circuit 710 can be located at a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be located at one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be located at a lower side of the display area DAA.

[0090] The second distribution circuit 720 distributes signals applied through the second pad portions PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portions PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be located at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located at the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be located at an upper side of the display area DAA.

[0091] Figure 5 and Figure 6 is a layout diagram illustrating an embodiment of a display area of Figure 4 .

[0092] Referring to Figure 5 and Figure 6 , each of the pixels PX includes a first emission area EA1 that is an emission area of a first sub-pixel SP1, a second emission area EA2 that is an emission area of a second sub-pixel SP2, and a third emission area EA3 that is an emission area of a third sub-pixel SP3.

[0093] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or a non-typical shape in a plan view.

[0094] A maximum length of the third emission area EA3 in the first direction DR1 can be less than a maximum length of the first emission area EA1 in the first direction DR1 and a maximum length of the second emission area EA2 in the first direction DR1. The maximum length of the first emission area EA1 in the first direction DR1 and the maximum length of the second emission area EA2 in the first direction DR1 can be substantially the same.

[0095] The maximum length of the third light emitting area EA3 in the second direction DR2 may be greater than the maximum length of the first light emitting area EA1 and the second light emitting area EA2 in the second direction DR2.

[0096] The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a shape as shown in a plan view. Figure 6 The first, second, and third emission areas EA1, EA2, and EA3 may have polygonal shapes other than hexagonal shapes, circular shapes, elliptical shapes, or atypical shapes in a plan view.

[0097] like Figure 5 As shown in FIG, in each of the plurality of pixels PX, the first light emitting area EA1 and the second light emitting area EA2 may be adjacent to each other in the second direction DR2. In addition, the first light emitting area EA1 and the third light emitting area EA3 may be adjacent to each other in the first direction DR1. In addition, the second light emitting area EA2 and the third light emitting area EA3 may be adjacent to each other in the first direction DR1. The area of ​​the first light emitting area EA1, the area of ​​the second light emitting area EA2, and the area of ​​the third light emitting area EA3 may be different.

[0098] Alternatively, as Figure 6 As shown in , the first light-emitting area EA1 and the second light-emitting area EA2 may be adjacent to each other in the first direction DR1, but the second light-emitting area EA2 and the third light-emitting area EA3 may be adjacent to each other in the first oblique direction DD1, and the first light-emitting area EA1 and the third light-emitting area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0099] The first light emitting area EA1 may emit a first light, the second light emitting area EA2 may emit a second light, and the third light emitting area EA3 may emit a third light. Here, the first light may be light in a blue wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a red wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 600 nm to about 750 nm.

[0100] In Figure 5 and Figure 6 , each of the plurality of pixels PX is illustrated as including three light emitting regions EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX can include four light emitting regions.

[0101] In addition, the layout of the light emitting regions of the plurality of pixels PX is not limited to the layout illustrated in Figure 5 and Figure 6 . For example, the light emitting regions of the plurality of pixels PX can be positioned in a stripe structure in which the light emitting regions are arranged in the first direction DR1, a PenTile ® structure (PenTile ® ) in which the light emitting regions are arranged in a diamond shape, or a hexagonal structure in which the light emitting regions having a hexagonal shape in a plan view are arranged as illustrated in Figure 6 .

[0102] Figure 7 is a cross-sectional view illustrating an example of the display panel taken along a line I1-I1' of Figure 5 .

[0103] Referring to Figure 7 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, a encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0104] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be the first to sixth transistors T1 to T6 described with reference to Figure 4 .

[0105] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type impurity. A plurality of well regions WA can be located on a top surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type impurity. The second type impurity can be different from the aforementioned first type impurity. For example, when the first type impurity is a p-type impurity, the second type impurity can be an n-type impurity. Alternatively, when the first type impurity is an n-type impurity, the second type impurity can be a p-type impurity.

[0106] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DA.

[0107] A lower insulating film BINS can be located between the gate electrode GE and the well region WA. A side insulating film SINS can be located on a side surface of the gate electrode GE. The side insulating film SINS can be located on the lower insulating film BINS.

[0108] Each of the source region SA and the drain region DA can be a region doped with a first type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0109] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. A distance between the source region SA and the drain region DA can be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Accordingly, a length of the channel region CH of each of the pixel transistors PTR can be increased, so that punch-through phenomenon and hot carrier phenomenon that can be caused by a short channel can be reduced or prevented.

[0110] A first semiconductor insulating film SINS1 can be located on (e.g., above) the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto.

[0111] A second semiconductor insulating film SINS2 can be located on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed of silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto.

[0112] The plurality of contact terminals CTE can be located on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole that penetrates the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them.

[0113] The third semiconductor insulating film SINS3 can be located on a side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE can be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 can be formed of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto.

[0114] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin (such as polyimide) substrate. In this case, the thin film transistor can be located on the glass substrate or the polymer resin substrate. The glass substrate can be a non-flexible rigid substrate, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0115] The light emitting element backplane EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9.

[0116] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect the plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing the circuit of the first sub-pixel SP1 shown in FIG. 1B. For example, the first transistor T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection of the first transistor T1 to the sixth transistor T6 and the first capacitor CP1 and the second capacitor CP2 is completed through the first conductive layer ML1 to the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE is also completed through the first conductive layer ML1 to the eighth conductive layer ML8. Figure 3

[0117] The first insulating film INS1 can be located on the semiconductor backplane SBP. Each of the first vias VA1 can penetrate the first insulating film INS1 and can be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 can be located on the first insulating film INS1 and can be connected to the first via VA1. ​

[0118] The second insulating film INS2 can be located on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and can be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be located on the second insulating film INS2 and can be connected to the second via VA2.

[0119] The third insulating film INS3 can be located on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate the third insulating film INS3 and can be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be located on the third insulating film INS3 and can be connected to the third via VA3.

[0120] The fourth insulating film INS4 can be located on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and can be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be located on the fourth insulating film INS4 and can be connected to the fourth via VA4.

[0121] The fifth insulating film INS5 can be located on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and can be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be located on the fifth insulating film INS5 and can be connected to the fifth via VA5.

[0122] The sixth insulating film INS6 can be located on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and can be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be located on the sixth insulating film INS6 and can be connected to the sixth via VA6.

[0123] The seventh insulating film INS7 can be located on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and can be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be located on the seventh insulating film INS7 and can be connected to the seventh via VA7.

[0124] The eighth insulating film INS8 can be located on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 and can be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 can be located on the eighth insulating film INS8 and can be connected to the eighth via VA8.

[0125] The first to eighth conductive layers ML1 to ML8 and the first to eighth via holes VA1 to VA8 can be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth via holes VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any of them. The first to eighth insulating films INS1 to INS8 can be made of substantially the same material. The first to eighth insulating films INS1 to INS8 can be formed of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited to this.

[0126] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be about 1360 A. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be about 1440 A. The thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6 can be about 1150 A.

[0127] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be about 9000 A. The thickness of each of the seventh via VA7 and the eighth via VA8 can be about 6000 A.

[0128] The ninth insulating film INS9 can be located on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be formed of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto.

[0129] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and can be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them. The thickness of the ninth via VA9 can be about 16500 A.

[0130] The display element layer EML can be located on the light emitting element back plate EBP. The display element layer EML can include the light emitting elements LE each including the first electrode AND, the light emitting stack IL, and the second electrode CAT, the reflective electrode layer RL, the tenth insulating film INS10 and the eleventh insulating film INS11, and the tenth via VA10. The display element layer EML can further include the pixel definition film PDL and the plurality of trenches TRC.

[0131] The reflective electrode layer RL can be located on the ninth insulating film INS9. The reflective electrode layer RL can include at least one of the first to fourth reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL can include the first to fourth reflective electrodes RL1, RL2, RL3, and RL4 as shown in Figure 7

[0132] ​Each of the first reflective electrodes RL1 can be located on the ninth insulating film INS9 and can be connected to the ninth via VA9. The first reflective electrodes RL1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them. For example, the first reflective electrodes RL1 can include titanium nitride (TiN).

[0133] Each of the second reflective electrodes RL2 can be located on the corresponding first reflective electrode RL1. The second reflective electrodes RL2 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them. For example, the second reflective electrodes RL2 can include aluminum (Al).

[0134] Each of the third reflective electrodes RL3 can be located on the corresponding second reflective electrode RL2. The third reflective electrodes RL3 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them. For example, the third reflective electrodes RL3 can include titanium nitride (TiN).

[0135] Each of the fourth reflective electrodes RL4 can be located on the corresponding third reflective electrode RL3. The fourth reflective electrodes RL4 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them. For example, the fourth reflective electrodes RL4 can include titanium (Ti).

[0136] Since the second reflective electrodes RL2 are electrodes that substantially reflect light from the light emitting elements LE, the thickness of the second reflective electrodes RL2 can be greater than the thickness of each of the first reflective electrodes RL1, the third reflective electrodes RL3, and the fourth reflective electrodes RL4. For example, the thickness of each of the first reflective electrodes RL1, the third reflective electrodes RL3, and the fourth reflective electrodes RL4 can be about 100 Å, and the thickness of the second reflective electrodes RL2 can be about 850 Å.

[0137] The tenth insulating film INS10 can be located on the ninth insulating film INS9. The tenth insulating film INS10 can be located between the reflective electrode layers RL adjacent to each other in a horizontal direction. The tenth insulating film INS10 can be formed of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto.

[0138] The eleventh insulating film INS11 can be located on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be formed of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited to this. The tenth insulating film INS10 and the eleventh insulating film INS11 can be optical auxiliary layers through which light reflected by the reflective electrode layer RL among light emitted from the light emitting element LE passes.

[0139] To match the resonance distance of light emitted from the light emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating film INS10 and / or the eleventh insulating film INS11 can be omitted below the first electrode AND. For example, the first electrode AND of the first sub-pixel SP1 can be directly located on the reflective electrode layer RL. The eleventh insulating film INS11 can be located below the first electrode AND of the second sub-pixel SP2. The tenth insulating film INS10 and the eleventh insulating film INS11 can be located below the first electrode AND of the third sub-pixel SP3.

[0140] In summary, in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the distance between the first electrode AND and the reflective electrode layer RL can be different. That is, to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main peak wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. The distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. The present disclosure is not limited to the above-described example.

[0141] In addition, although the tenth insulating film INS10 and the eleventh insulating film INS11 are shown in the present disclosure, in one or more embodiments, a twelfth insulating film that is positioned below the first electrode AND of the first sub-pixel SP1 can be added. In this case, the eleventh insulating film INS11 and the twelfth insulating film can be positioned below the first electrode AND of the second sub-pixel SP2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film can be positioned below the first electrode AND of the third sub-pixel SP3.

[0142] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and can be connected to the exposed reflective electrode layer RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0143] The first electrode AND of each of the light emitting elements LE can be positioned on the eleventh insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or a compound including any one of them. For example, the first electrode AND of each of the light emitting elements LE can be titanium nitride (TiN).

[0144] The pixel definition film PDL can be positioned on a portion of the first electrode AND of each of the light emitting elements LE. The pixel definition film PDL can cover the edge of the first electrode AND of each of the light emitting elements LE. The pixel definition film PDL can be used to divide the first, second, and third light emitting areas EA1, EA2, and EA3.

[0145] The first light emitting area EA1 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light emitting area EA2 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light emitting area EA3 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0146] The pixel definition film PDL can include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 can be located on an edge of the first electrode AND of each of the light emitting elements LE, the second pixel definition film PDL2 can be located on the first pixel definition film PDL1, and the third pixel definition film PDL3 can be located on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can be formed of a silicon oxide (SiO x ) based inorganic film, but the disclosure is not limited thereto. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can each have a thickness of about 500 Å.

[0147] When the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 are formed as one pixel definition film, the height of one pixel definition film increases, so that the first encapsulation inorganic film TFE1 can be cut off due to step coverage. The step coverage refers to a ratio of a degree to which a thin film is coated on an inclined portion to a degree to which the thin film is coated on a flat portion. The lower the step coverage, the more likely the thin film will be cut off at the inclined portion.

[0148] Therefore, in order to reduce or prevent the possibility that the first encapsulation inorganic film TFE1 is cut off due to step coverage, the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a cross-sectional structure having a step portion. For example, the width of the first pixel definition film PDL1 can be greater than the width of the second pixel definition film PDL2 and the width of the third pixel definition film PDL3. The width of the second pixel definition film PDL2 can be greater than the width of the third pixel definition film PDL3. The width of the first pixel definition film PDL1 refers to a horizontal length of the first pixel definition film PDL1 defined in the first direction DR1 and / or the second direction DR2.

[0149] Each of the plurality of trenches TRC can penetrate the first, second, and third pixel definition films PDL1, PDL2, and PDL3. Also, each of the plurality of trenches TRC can penetrate the eleventh insulating film INS11. The tenth insulating film INS10 can be partially recessed at each of the plurality of trenches TRC.

[0150] The at least one trench TRC can be located between the adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Although two trenches TRC are shown to be located between the adjacent sub-pixels SP1, SP2, and SP3, the disclosure is not limited thereto.

[0151] The light emitting stack IL can include a plurality of intermediate layers. Figure 7 Although the light emitting stack IL is shown to have a triple series structure including the first, second, and third stack layers IL1, IL2, and IL3, the disclosure is not limited thereto. For example, the light emitting stack IL can have a double series structure including two intermediate layers.

[0152] In the triple series structure, the light emitting stack IL can have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different light. For example, the light emitting stack IL can include a first stack layer IL1 that emits first light, a second stack layer IL2 that emits second light, and a third stack layer IL3 that emits third light. The first, second, and third stack layers IL1, IL2, and IL3 can be sequentially stacked.

[0153] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer that emits first light, and a first electron transport layer are sequentially stacked. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer that emits second light, and a second electron transport layer are sequentially stacked. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer that emits third light, and a third electron transport layer are sequentially stacked.

[0154] A first charge generation layer for supplying holes to the second stack layer IL2 and for supplying electrons to the first stack layer IL1 can be located between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type charge generation layer that supplies electrons to the first stack layer IL1 and a P-type charge generation layer that supplies holes to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metal material.

[0155] A second charge generation layer for supplying holes to the third stack layer IL3 and for supplying electrons to the second stack layer IL2 can be located between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type charge generation layer for supplying electrons to the second stack layer IL2 and a P-type charge generation layer for supplying holes to the third stack layer IL3.

[0156] The first stack layer IL1 can be located on the first electrode AND and the pixel definition film PDL, and can be located on a bottom surface of each of the trenches TRC. The first stack layer IL1 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. The second stack layer IL2 can be located on the first stack layer IL1. The second stack layer IL2 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. The cavity ESS or empty space can be located in the first stack layer IL1 and the second stack layer IL2. The third stack layer IL3 can be located on the second stack layer IL2. The third stack layer IL3 can not be cut by the trenches TRC, and can cover the second stack layer IL2 in each of the trenches TRC. That is, in the triple series structure, each of the plurality of trenches TRC can be a structure of the first stack layer IL1 and the second stack layer IL2, the first charge generation layer, and the second charge generation layer for cutting the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3. In addition, in the double series structure, each of the trenches TRC can be a structure for cutting the charge generation layer located between the lower intermediate layer and the upper intermediate layer and the lower intermediate layer.

[0157] In order to stably cut the first stack layer IL1 and the second stack layer IL2 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, a height of each of the plurality of trenches TRC can be greater than a height of the pixel definition film PDL. The height of each of the plurality of trenches TRC refers to a length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel definition film PDL refers to a length of the pixel definition film PDL in the third direction DR3. In order to cut the first to third stack layers IL1, IL2, and IL3 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, another structure can exist instead of the trenches TRC. For example, instead of the trenches TRC, an inverted taper-shaped partition wall can be located on the pixel definition film PDL.

[0158] The number of the stack layers IL1, IL2, and IL3 emitting different light is not limited to Figure 7The light emitting stack IL can include two or more intermediate layers in addition to the first stack layer IL1. For example, the light emitting stack IL can include two intermediate layers in addition to the first stack layer IL1. In this case, one of the two intermediate layers can be substantially the same as the first stack layer IL1, and the other can include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one of the intermediate layers and for supplying holes to the other of the intermediate layers can be located between the two intermediate layers.

[0159] In addition, Figure 7 It is illustrated that the first to third stack layers IL1, IL2, and IL3 are all located in the first, second, and third light emitting areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. For example, the first stack layer IL1 can be located in the first light emitting area EA1, and can be omitted from the second and third light emitting areas EA2 and EA3. Also, the second stack layer IL2 can be located in the second light emitting area EA2, and can be omitted from the first and third light emitting areas EA1 and EA3. Also, the third stack layer IL3 can be located in the third light emitting area EA3, and can be omitted from the first and second light emitting areas EA1 and EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0160] The second electrode CAT can be located on the third stack layer IL3. The second electrode CAT can be located on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT can be formed of a transparent conductive material (TCO) such as ITO or IZO, which transmits light, or a semi-transmissive metal material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive metal material, light emission efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to a microcavity effect.

[0161] The encapsulation layer TFE can be located on the display element layer EML. The encapsulation layer TFE can include at least one inorganic film TFE1 and TFE2 to reduce or prevent penetration of oxygen or moisture into the display element layer EML. For example, the encapsulation layer TFE can include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0162] The first encapsulation inorganic film TFE1 can be located on the second electrode CAT. The first encapsulation inorganic film TFE1 can be formed as a multilayer in which one or more inorganic films selected from silicon nitride (SiN x ), silicon oxynitride (SiON), and silicon oxide (SiO x ) are alternately stacked. The first encapsulation inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0163] The second encapsulation inorganic film TFE2 can be located on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can be formed of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The second encapsulation inorganic film TFE2 can be formed through an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0164] The organic film APL can be a layer for improving the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL can be an organic film including, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0165] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a fill layer FIL. The plurality of color filters CF1, CF2, and CF3 can include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 can be located on the organic film APL.

[0166] The first color filter CF1 can overlap the first light emitting area EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit first light (e.g., light of a blue wavelength band). The blue wavelength band can be about 370 nm to about 460 nm. Accordingly, the first color filter CF1 can transmit the first light among the light emitted from the first light emitting area EA1.

[0167] The second color filter CF2 can overlap the second light emitting area EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit second light (e.g., light of a green wavelength band). The green wavelength band can be about 480 nm to about 560 nm. Accordingly, the second color filter CF2 can transmit the second light among the light emitted from the second light emitting area EA2.

[0168] The third color filter CF3 can overlap the third light emitting area EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit third light (e.g., light of a red wavelength band). The red wavelength band can be about 600 nm to about 750 nm. Accordingly, the third color filter CF3 can transmit the third light among the light emitted from the third light emitting area EA3.

[0169] The plurality of lenses LNS can be located on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS can be a structure for increasing the ratio of light directed to the front side of the display device 10. Each of the plurality of lenses LNS can have a cross-sectional shape that is convex in the upward direction.

[0170] The fill layer FIL can be located on the plurality of lenses LNS. The fill layer FIL can have a refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at an interface between the fill layer FIL and the plurality of lenses LNS. Further, the fill layer FIL can be a planarization layer. The fill layer FIL can be an organic film including, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0171] The cover layer CVL can be located on the fill layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the fill layer FIL. In this case, the fill layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly applied to the fill layer FIL.

[0172] The polarizing plate POL can be located on one surface of the cover layer CVL. The polarizing plate POL can be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (a quarter wave plate), but the present disclosure is not limited thereto. However, when visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, the polarizing plate POL can be omitted.

[0173] Figure 8 is a perspective view illustrating a head-mounted display according to one or more embodiments. Figure 9 is an exploded perspective view illustrating an example of the head-mounted display of Figure 8 .

[0174] Referring to Figure 8 and Figure 9 , the head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0175] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Because each of the first display device 10_1 and the second display device 10_2 is combined with the first eyepiece 1210 and the second eyepiece 1220, respectively, the first display device 10_1 and the second display device 10_2 can provide the images to the left eye and the right eye of the user, respectively. Figure 1 and Figure 2The display devices 10 described are substantially the same, so descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0176] The first optical member 1510 may be located between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be located between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0177] The middle frame 1400 may be located between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0178] The control circuit board 1600 may be located between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via the connector.

[0179] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0180] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is positioned to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 8 and Figure 9 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are positioned separately, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0181] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, a user can view an image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view an image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0182] The head-mounted band 1300 serves to fix the display device housing 1100 to a user's head such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively maintained on the user's left and right eyes. When the display device housing 1100 is implemented to be light in weight and compact, the head-mounted display 1000 can be provided with a spectacle frame instead of the head-mounted band 1300 as shown in Figure 10

[0183] In addition, the head-mounted display 1000 can further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port for receiving an image source and a wireless communication module. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi Fi ® module or a Bluetooth ® module (Wi Fi ® is a registered trademark of the Bluetooth Sig, Inc. of Kirkland, Washington). ®

[0184] Figure 10 is a perspective view showing a head-mounted display according to one or more embodiments.

[0185] Referring to Figure 10 , the head-mounted display 1000_1 according to one or more embodiments can be a spectacle-type display device in which the display device housing 1200_1 is implemented in a light-weight and compact manner. The head-mounted display 1000_1 according to one or more embodiments can include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple legs 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0186] ​​The display device housing 1200_1 can accommodate the display device 10_3, the optical member 1060, and the optical path changing member 1070. An image displayed on the display device 10_3 can be enlarged by the optical member 1060, and can be provided to the right eye of the user through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image seen through the right-eye lens 1020 are combined through the right eye.

[0187] Figure 10 It is shown that the display device housing 1200_1 is located at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 can be located at the left end of the support frame 1030, and in this case, an image of the display device 10_3 can be provided to the left eye of the user. Alternatively, the display device housing 1200_1 can be located at both the left end and the right end of the support frame 1030, and in this case, the user can view an image displayed on the display device 10_3 through both the left eye and the right eye.

[0188] Figure 11 is a cross-sectional view showing a display element layer of a display panel according to one or more embodiments.

[0189] Unlike one or more embodiments corresponding to Figure 7 , in one or more embodiments corresponding to Figure 11 , in each of the first, second, and third sub-pixels SP1, SP2, and SP3, the distance between the first electrode AND and the reflective electrode layer RL can be the same.

[0190] As described above, in one or more embodiments corresponding to Figure 7 , in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main peak wavelength of light emitted in each of the first, second, and third sub-pixels SP1, SP2, and SP3, it is determined whether the tenth and eleventh insulating films INS10 and INS11 are present in each of the first, second, and third sub-pixels SP1, SP2, and SP3. In one or more embodiments corresponding to Figure 7 , it is exemplified that the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. In one or more embodiments corresponding toFigure 7 In such one or more embodiments of the above, when the first electrode AND is titanium nitride (TiN), in the resonant structure using the eleventh insulating film INS11, the light emission efficiency of the third sub-pixel SP3 that displays red light can be lower than the light emission efficiency of each of the first sub-pixel SP1 and the second sub-pixel SP2. The reduction in the light emission efficiency in the third sub-pixel SP3 can be due to a relatively large amount of light in the red wavelength band being affected by the absorption coefficient of the first electrode AND made of titanium nitride (TiN).

[0191] In one or more embodiments corresponding to Figure 11 , the distance between the first electrode AND and the reflective electrode layer RL can be designed to be the same in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, so that the reduction in the light emission efficiency in the third sub-pixel SP3 is reduced or prevented. Hereinafter, only features different from one or more embodiments corresponding to Figure 11 will be described. Features not described with reference to one or more embodiments corresponding to Figure 7 will be replaced with the description of one or more embodiments corresponding to Figure 7 . Figure 11

[0192] With reference to Figure 11 , the display element layer EML according to one or more embodiments includes the reflective electrode layer RL, the first electrode AND located on the reflective electrode layer RL and directly contacting the reflective electrode layer RL, and the light-emitting stack IL and the second electrode CAT sequentially stacked on the first electrode AND. Thus, the display element layer EML according to one or more embodiments differs in that the tenth insulating film INS10 and the eleventh insulating film INS11 described in one or more embodiments corresponding to Figure 7 are omitted. Because the tenth insulating film INS10 and the eleventh insulating film INS11 (see Figure 7 ) are omitted, the first electrode AND directly contacts the reflective electrode layer RL. In such one or more embodiments corresponding to Figure 11 , by reducing the effect of the absorption coefficient of the first electrode AND made of titanium nitride (TiN), the reduction in the light emission efficiency in the third sub-pixel SP3 can be reduced or prevented.

[0193] The reflective electrode layer RL includes a first reflective electrode RL1, a second reflective electrode RL2 located on the first reflective electrode RL1, a third reflective electrode RL3 located on the second reflective electrode RL2, and a fourth reflective electrode RL4 located on the third reflective electrode RL3. At this time, the first electrode AND is located on the fourth reflective electrode RL4 and directly contacts the fourth reflective electrode RL4.

[0194] ​The display element layer EML includes a pixel definition film PDL that covers edges of the first electrode AND and divides a first light emitting region EA1 that is a light emitting region of the first sub-pixel SP1, a second light emitting region EA2 that is a light emitting region of the second sub-pixel SP2, and a third light emitting region EA3 that is a light emitting region of the third sub-pixel SP3.

[0195] The pixel definition film PDL includes a first pixel definition film PDL1, a second pixel definition film PDL2 on the first pixel definition film PDL1, and a third pixel definition film PDL3 on the second pixel definition film PDL2. The first to third pixel definition films PDL1, PDL2, and PDL3 can include a cross-sectional structure having a stepped portion.

[0196] The display element layer EML includes / defines at least one trench TRC that penetrates the first to third pixel definition films PDL1, PDL2, and PDL3. The at least one trench TRC penetrates a portion of the insulating film (e.g., the ninth insulating film INS9) of the light emitting element backplane EBP between adjacent reflective electrode layers RL.

[0197] The at least one trench TRC includes at least one pair of trenches TRC that penetrate a portion of the pixel definition film PDL and the insulating film (e.g., the ninth insulating film INS9) of the light emitting element backplane EBP between adjacent sub-pixels SP1, SP2, and SP3.

[0198] Figures 12 to 17 is a cross-sectional view illustrating a processing operation of a method of manufacturing a display element layer of a display panel according to one or more embodiments. For example, Figures 12 to 17 illustrates steps of manufacturing at least some layers of a display element layer EML according to one or more embodiments shown in Figure 11

[0199] A method of manufacturing a display device 10 according to one or more embodiments includes forming a semiconductor backplane SBP including a plurality of pixel transistors on a semiconductor substrate SSUB (see Figure 7 ), forming a light emitting element backplane EBP including a plurality of conductive layers, a plurality of vias, and a plurality of insulating films on the semiconductor backplane SBP, and forming a display element layer EML including light emitting elements that emit light on the light emitting element backplane EBP. Here, forming the display element layer EML can include the same manufacturing process as the manufacturing process shown in Figures 12 to 17

[0200] Referring to Figure 12 ​​The first metal layer for the reflective electrode layer RL and the second metal layer for the first electrode AND can be sequentially stacked. For example, titanium nitride (TiN) can be deposited as the first metal layer for the first reflective electrode RL1. Aluminum (Al) can be deposited as the first metal layer for the second reflective electrode RL2. Titanium nitride (TiN) can be deposited as the first metal layer for the third reflective electrode RL3. Aluminum (Al) can be deposited as the first metal layer for the fourth reflective electrode RL4. Titanium nitride (TiN) can be deposited as the second metal layer for the first electrode AND.

[0201] The titanium nitride (TiN) for the first electrode AND can directly contact the first metal layer for the reflective electrode layer RL. Thus, the first electrode AND directly contacts the reflective electrode layer RL. For example, the reflective electrode layer RL includes the first reflective electrode RL1, the second reflective electrode RL2 on the first reflective electrode RL1, the third reflective electrode RL3 on the second reflective electrode RL2, and the fourth reflective electrode RL4 on the third reflective electrode RL3. In this case, the first electrode AND is on the fourth reflective electrode RL4 and directly contacts the fourth reflective electrode RL4.

[0202] Referring to Figure 13 , the second metal layer for the first electrode AND and the first metal layer for the reflective electrode layer RL are patterned, thereby forming the reflective electrode layer RL and the first electrode AND corresponding to each of the sub-pixels SP1, SP2, and SP3. At this time, the portion of the ninth insulating film INS9 (see Figure 7 ) between the adjacent reflective electrode layers RL can be removed.

[0203] Referring to Figure 14 , an insulating film for the pixel definition film PDL can be deposited on the reflective electrode layer RL and the first electrode AND. For example, the insulating film for the pixel definition film PDL can be a silicon oxide (SiO x )-based inorganic film or a silicon nitride (SiN x )-based inorganic film. In one or more embodiments corresponding to Figure 14 , a state in which a silicon nitride (SiN x )-based inorganic film is deposited as the insulating film 1811 for the first pixel definition film PDL1 and in which a silicon oxide (SiO x )-based inorganic film is deposited thereon as the insulating film 1812 for the second pixel definition film PDL2 is shown.

[0204] Referring to Figures 15 to 17The patterned insulating films 1811 and 1812 are formed to form a pixel definition film PDL that covers edges of the first electrode AND, and divide a first light emitting region EA1 that is a light emitting region of the first sub-pixel SP1, a second light emitting region EA2 that is a light emitting region of the second sub-pixel SP2, and a third light emitting region EA3 that is a light emitting region of the third sub-pixel SP3.

[0205] For example, Figure 15 A state in which a process of planarizing the silicon oxide (SiO x ) based insulating film 1812 deposited for the second pixel definition film PDL2 is performed is shown.

[0206] Figure 16 A state in which, after planarizing the silicon oxide (SiO x ) based insulating film 1812 deposited for the second pixel definition film PDL2, a silicon nitride (SiN x ) based inorganic film is deposited as an insulating film 1813 for a third pixel definition film PDL3 is shown.

[0207] Figure 17 A state in which the silicon nitride (SiN x ) based insulating film 1811 (see Figure 16 ), the silicon oxide (SiO x ) based insulating film 1812 (see Figure 16 ), and the silicon nitride (SiN x ) based insulating film 1813 (see Figure 16 ) that are sequentially stacked during the process are selectively etched to form an opening of the pixel definition film PDL that exposes a portion of the first electrode AND is shown.

[0208] Referring to Figure 17 , forming the opening of the pixel definition film PDL also includes forming at least one trench TRC that penetrates the first to third pixel definition films PDL1, PDL2, and PDL3. At this time, the at least one trench TRC penetrates a portion of the insulating film (e.g., the ninth insulating film INS9) of the light emitting element back plate EBP located between adjacent reflective electrode layers RL.

[0209] Figure 18 is a layout diagram showing a display region according to a comparative example. For example, Figure 18 may be a layout diagram showing a display region of the display panel shown in Figure 7 .

[0210] Referring to Figure 18Each of the plurality of pixels PX includes a first light emitting region EA1 that is a light emitting region of the first sub-pixel SP1, a second light emitting region EA2 that is a light emitting region of the second sub-pixel SP2, and a third light emitting region EA3 that is a light emitting region of the third sub-pixel SP3.

[0211] In each of the plurality of pixels PX, the first light emitting region EA1 and the second light emitting region EA2 can be adjacent to each other in a horizontal direction. Further, the first light emitting region EA1 and the third light emitting region EA3 can be adjacent to each other in a vertical direction. Further, the second light emitting region EA2 and the third light emitting region EA3 can be adjacent to each other in the vertical direction. The area of the first light emitting region EA1, the area of the second light emitting region EA2, and the area of the third light emitting region EA3 can be different.

[0212] Figure 18 A layout diagram showing a display region DAA of the display panel 100 shown in Figure 7 is depicted, and the tenth via VA10 is located at a periphery of each of the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3. The tenth via VA10 penetrates the eleventh insulating film INS11 to electrically connect the first electrode AND (see Figure 7 ) and the reflective electrode layer RL (see Figure 7 ).

[0213] In a comparative example according to Figure 7 and Figure 18 , because the tenth via VA10 is located at the periphery of each of the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, the aperture ratio can decrease.

[0214] Figure 19 is a layout diagram showing a display region according to one or more embodiments. For example, Figure 19 may be a layout diagram showing a display region of the display panel shown in Figure 11 .

[0215] Unlike the comparative example of Figure 7 and Figure 18 , in one or more embodiments corresponding to Figure 19 , by omitting the tenth via VA10, the aperture ratio can be improved by about 10%. That is, in one or more embodiments according to Figures 11 to 19 , because the first electrode AND directly contacts the reflective electrode layer RL, a via for connecting the first electrode AND and the reflective electrode layer RL is not needed. Therefore, in one or more embodiments according to Figures 11 to 19 , compared to the comparative example according to Figure 7 and Figure 18Compared with the comparative example, the pixel opening rate can be increased, and thus the light efficiency can be improved.

[0216] In summary of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and are not for the purpose of limitation.

Claims

1. A display device comprising: a semiconductor backplane comprising a pixel transistor; a light emitting element backplane over the semiconductor backplane and comprising a conductive layer, a via, and an insulating film; and a display element layer over the light emitting element backplane, wherein a light emitting element for emitting light is provided, and comprising: a reflective electrode layer; a first electrode over the reflective electrode layer and directly contacting the reflective electrode layer; and a stack layer and a second electrode sequentially stacked over the first electrode. The reflective electrode layer comprises:

2. The display device of claim 1, wherein, a first reflective electrode; a second reflective electrode over the first reflective electrode; a third reflective electrode over the second reflective electrode; and a fourth reflective electrode over the third reflective electrode. The first electrode is over the fourth reflective electrode and directly contacts the fourth reflective electrode.

3. The display device of claim 2, wherein, The display element layer comprises a pixel defining film covering edges of the first electrode and defining a first light emitting region of a first sub-pixel, a second light emitting region of a second sub-pixel, and a third light emitting region of a third sub-pixel.

4. The display device of claim 3, wherein, The pixel defining film comprises:

5. The display device of claim 4, wherein, a first pixel defining film; a second pixel defining film over the first pixel defining film; and a third pixel defining film over the second pixel defining film, wherein the pixel defining film has a cross-sectional structure with a stepped portion. The display element layer defines at least one trench penetrating the first pixel defining film to the third pixel defining film.

6. The display device of claim 5, wherein, The at least one trench penetrates some of the insulating film of the light emitting element backplane between the reflective electrode layer and an adjacent reflective electrode layer.

7. The display device of claim 6, wherein, The at least one trench comprises a pair of trenches between adjacent sub-pixels of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

8. The display device of claim 7, wherein, 9. A method of manufacturing a display device, the method comprising: forming a semiconductor backplane comprising a pixel transistor over a semiconductor substrate; forming a light emitting element backplane comprising a conductive layer, a via, and an insulating film over the semiconductor backplane; and forming a display element layer over the light emitting element backplane, the display element layer comprising a light emitting element for emitting light, the display element layer being formed by: sequentially stacking a first metal layer for a reflective electrode layer and a second metal layer for a first electrode; forming the reflective electrode layer and the first electrode corresponding to each of sub-pixels by patterning the second metal layer and the first metal layer; depositing an other insulating film for a pixel defining film over the reflective electrode layer and the first electrode; and patterning the other insulating film to form the pixel defining film covering edges of the first electrode and defining a first light emitting region of a first sub-pixel, a second light emitting region of a second sub-pixel, and a third light emitting region of a third sub-pixel. The first electrode directly contacts the reflective electrode layer. The reflective electrode layer comprises: a first reflective electrode; 10. The method of claim 9, wherein, a second reflective electrode over the first reflective electrode; 11. The method of claim 10, wherein, a third reflective electrode over the second reflective electrode; and a fourth reflective electrode over the third reflective electrode. The first electrode is over the fourth reflective electrode and directly contacts the fourth reflective electrode. ​ ​ 12. The method of claim 11, wherein, The first electrode is over the fourth reflective electrode and directly contacts the fourth reflective electrode.

13. The method of claim 12, wherein, The pixel-defining film includes a first pixel-defining film, a second pixel-defining film over the first pixel-defining film, and a third pixel-defining film over the second pixel-defining film, and The step of forming the pixel-defining film includes selectively patterning the other insulating film so that the pixel-defining film has a cross-sectional structure with a stepped portion.

14. The method of claim 13, wherein, The step of forming the display element layer further includes forming at least one trench that penetrates the first pixel-defining film, the second pixel-defining film, and the third pixel-defining film.

15. The method of claim 14, wherein, The at least one trench penetrates some of the insulating films of the light-emitting element backplane between the reflective electrode layer and an adjacent reflective electrode layer.

16. An electronic device including a display panel over a semiconductor substrate, the display panel including: a semiconductor backplane including a pixel transistor; a light-emitting element backplane over the semiconductor backplane and including a conductive layer, a via, and an insulating film; and a display element layer over the light-emitting element backplane, in which a light-emitting element for emitting light is provided, and including a reflective electrode layer, a first electrode over the reflective electrode layer and directly contacting the reflective electrode layer, and a stack layer and a second electrode sequentially stacked over the first electrode.

17. The electronic device of claim 16, wherein, The reflective electrode layer includes: a first reflective electrode; a second reflective electrode over the first reflective electrode; a third reflective electrode over the second reflective electrode; and a fourth reflective electrode over the third reflective electrode.

18. The electronic device of claim 17, wherein, The first electrode is over the fourth reflective electrode and directly contacts the fourth reflective electrode.

19. The electronic device of claim 18, wherein, The display element layer includes a pixel-defining film that covers edges of the first electrode and defines a first light-emitting region of a first sub-pixel, a second light-emitting region of a second sub-pixel, and a third light-emitting region of a third sub-pixel.

20. The electronic device of claim 19, wherein, The pixel-defining film includes: a first pixel-defining film; a second pixel-defining film over the first pixel-defining film; and a third pixel-defining film over the second pixel-defining film, wherein the pixel-defining film has a cross-sectional structure with a stepped portion.

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