Radio frequency chip, chip cascade structure, radar device and electronic equipment

Abstract

The invention relates to the technical field of wireless communication, in particular to a radio frequency chip, a chip cascade structure, a radar device and electronic equipment. Wherein the radio frequency chip is integrated with a signal transmission link and a signal conditioning circuit, and comprises a cascade input end and a cascade output end; the signal transmission link is connected with the cascade input end and the cascade output end; in any cascade mode of the radio frequency chip, the signal transmission link is used for transmitting a cascade synchronization signal, the cascade input end is used for receiving the cascade synchronization signal from the outside of the radio frequency chip, and the cascade output end is used for transmitting the cascade synchronization signal to the outside of the radio frequency chip; the signal conditioning circuit is arranged in a signal transmission link, and the signal conditioning circuit is configured to compensate cascade mismatch of amplitude and phase of a cascade synchronization signal caused by inter-board transmission; by adjusting the phase and amplitude / power of the cascade synchronization signal received by the cascade signal, the amplitude and phase consistency of the cascade synchronization signal in each cascade chip is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of wireless communication technology, and in particular to a radio frequency chip, a chip cascade structure, a radar device, and an electronic device. Background Technology

[0002] FMCW (Frequency Modulated Continuous Wave) radar refers to radar whose transmission frequency is modulated by a specific signal. FMCW radar obtains the radial velocity information of a target by comparing the difference between the frequency of the echo signal at any given time and the frequency of the transmitted signal at that time.

[0003] Compared with other ranging and speed measuring radars, FMCW radar has a simpler structure. In addition, FMCW radar has more technical experience, requires lower peak transmit power, is easy to modulate, has low cost, and simple signal processing, making it a commonly used radar system in automotive radar.

[0004] In practical applications, the number of channels in an FMCW radar has a significant impact on its performance; it affects not only the radar's angular resolution but also its transmit power, and consequently, its detection range. Therefore, increasing the number of channels in an FMCW radar can effectively improve its performance. Specifically, the higher the number of channels, the higher the radar's angular resolution and the longer its detection range. Summary of the Invention

[0005] This disclosure provides an RF chip, a chip cascade structure, a radar device, and an electronic device. It provides a structure for the RF chip, and the cascade chip structure based on the RF chip can ensure the amplitude and phase consistency of the cascaded synchronization signal in each cascade chip.

[0006] One embodiment of this disclosure provides a chip structure, including: an integrated signal transmission link and a signal conditioning circuit, and including a cascaded input terminal and a cascaded output terminal; the signal transmission link connects the cascaded input terminal and the cascaded output terminal; in any mode of cascading RF chips, the signal transmission link is used to transmit a cascaded synchronization signal, the cascaded input terminal is used to receive a cascaded synchronization signal from outside the RF chip, and the cascaded output terminal is used to transmit the cascaded synchronization signal to outside the RF chip; the signal conditioning circuit is disposed in the signal transmission link, and the signal conditioning circuit is configured to: compensate for the cascaded mismatch of amplitude and phase caused by inter-board transmission of the cascaded synchronization signal.

[0007] The radio frequency chip provided in this embodiment uses an additional signal conditioning circuit to adjust the phase and amplitude / power of the cascaded synchronization signal received by the cascaded signal, thereby ensuring the consistency of amplitude and phase of the cascaded synchronization signal in each cascaded chip.

[0008] In some embodiments, the signal conditioning circuit includes: a time delay circuit and a variable gain amplifier circuit arranged in series; the time delay circuit is used to delay the cascaded synchronization signal; the variable gain amplifier circuit has an adjustable amplification factor to adjust the power / amplitude of the cascaded synchronization signal.

[0009] In some embodiments, the radio frequency chip further includes: a signal generation circuit connected to a signal transmission link, used to generate an on-chip oscillation signal and output it to the signal transmission link; and a radio frequency transceiver circuit connected to the signal transmission link, used to perform radar detection using the cascaded synchronization signal or the on-chip oscillation signal output from the signal transmission link.

[0010] In some embodiments, the signal conditioning circuit is disposed in at least one of the following paths: the path between the signal generation circuit and the RF transceiver circuit connected by the signal transmission link; the path between the signal generation circuit and the cascaded output terminal connected by the signal transmission link; the path between the cascaded input terminal and the cascaded output terminal connected by the signal transmission link; and the path between the RF transceiver circuit and the cascaded input terminal connected by the signal transmission link.

[0011] In some embodiments, the cascading modes of the radio frequency chip include at least one of the following: cascading master mode, first cascading slave mode, and second cascading slave mode.

[0012] In some embodiments, the cascaded synchronization signal includes at least one of the following: a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal.

[0013] In some embodiments, the local oscillator signal is a continuously modulated frequency signal.

[0014] Another embodiment of this disclosure provides a chip cascade structure, including at least two cascaded chips, wherein at least one of the chips is the radio frequency chip provided in the above embodiment.

[0015] Another embodiment of this disclosure provides a radar device, which includes the chip cascade structure provided in the above embodiments.

[0016] Another embodiment of this disclosure provides an electronic device, which includes at least the radar device provided in the above embodiments. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of several radio frequency chips provided in an embodiment of the present disclosure;

[0019] Figure 2 This is a schematic diagram of the structure of a signal transmission link provided in an embodiment of the present disclosure;

[0020] Figure 3 Provided for an embodiment of this disclosure Figure 2 The diagram shows the structure of the signal transmission link when the RF chip is in different modes.

[0021] Figure 4 This is a schematic diagram of a signal transmission link connected by a switch according to an embodiment of the present disclosure;

[0022] Figure 5 Provided for an embodiment of this disclosure Figure 4 The diagram shows the structure of the signal transmission link when the RF chip is in different modes.

[0023] Figure 6 This is a schematic diagram of a chip cascade structure provided in one embodiment of the present disclosure;

[0024] Figure 7 This is a schematic diagram of another chip cascade structure provided in an embodiment of the present disclosure;

[0025] Figure 8 A schematic diagram of another chip cascade structure provided in an embodiment of this disclosure;

[0026] Figure 9 A schematic diagram illustrating the connection relationship between various signal conditioning circuits and signal transmission links provided in an embodiment of this disclosure;

[0027] Figure 10 This is a schematic diagram of the structure of two signal conditioning circuits provided in one embodiment of the present disclosure;

[0028] Figure 11 A type of signal conditioning circuit provided in an embodiment of this disclosure and Figure 2 A schematic diagram illustrating the setup of an example signal transmission link;

[0029] Figure 12 Another type of signal conditioning circuit provided in an embodiment of this disclosure and Figure 2 A schematic diagram illustrating the setup of an example signal transmission link;

[0030] Figure 13 A schematic diagram of the structure of a radio frequency chip with self-testing function provided in an embodiment of this disclosure;

[0031] Figure 14 Provided as an embodiment of this disclosure Figure 2 Example: Schematic diagram of the self-test circuit;

[0032] Figure 15 This is a schematic diagram of the radio frequency signal structure under the first coupler structure provided in an embodiment of the present disclosure;

[0033] Figure 16 This is a schematic diagram of the radio frequency signal structure under the second ohmic coupler structure provided in an embodiment of this disclosure. Detailed Implementation

[0034] As is known from the background art, the number of channels in an FMCW radar has a significant impact on its performance; it affects not only the radar's angular resolution but also its transmission power, and consequently, its detection range. Therefore, increasing the number of channels in an FMCW radar can effectively improve its performance; specifically, the higher the number of channels, the higher the radar's angular resolution and the longer its detection range.

[0035] The number of channels in an FMCW radar can be increased directly within the chip, but an excessive number of channels complicates the design, increases the difficulty of chip manufacturing, and makes it impossible to meet differentiated requirements. Therefore, cascaded chip structures composed of multi-stage radio frequency chips have become a common practice for increasing the number of channels in FMCW radars.

[0036] The first embodiment of this disclosure provides a radio frequency chip, and more radio frequency chips can be cascaded in a cascaded chip structure based on this radio frequency chip, thereby increasing the number of channels in the FMCW radar.

[0037] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0038] The radio frequency chip provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0039] It should be noted that, in the various embodiments of this disclosure, the radio frequency (RF) chip can be exemplified as a radar chip, and the RF chip has at least an operating mode and a calibration mode. Specifically, the operating mode is used to enable the RF chip to operate and achieve real-time collection of physical data; the operating mode may include: cascaded master mode, first cascaded slave mode, second cascaded slave mode, or single-chip mode, etc., to adapt to the needs of different application scenarios. Specifically, the calibration mode can be used for factory calibration of the chip in a test environment, or for self-calibration or self-testing during use; the calibration mode may include: cascaded calibration mode or single-chip calibration mode, etc., to determine whether the RF chip can work normally, and even to determine the compensation parameters of the RF chip.

[0040] The radio frequency chip provided in this embodiment integrates a signal transmission link, and the radio frequency chip includes a cascaded input terminal and a cascaded output terminal.

[0041] In some embodiments, reference Figure 1 (A) The signal transmission link 111 connects the cascade input terminal MuxIN and the cascade output terminal MuxOUT to form a first signal path. Specifically, the first signal path refers to the signal path through which the off-chip cascade synchronization signal of the RF chip 100 is input into the RF chip 100 through the cascade input terminal MuxIN, passes through the signal transmission link 111 within the RF chip 100, and is output at the cascade output terminal MuxOUT.

[0042] More specifically, when the RF chip 100 is in the first cascade slave mode, the first signal path receives the cascade synchronization signal from outside the RF chip 100 and outputs the cascade synchronization signal to outside the RF chip 100 through the first signal path.

[0043] In this context, the first-level cascaded slave mode represents the RF chip 100 as a non-first- or non-last-level chip in the cascaded structure. For example, in a three-level cascaded structure, the second-level RF chip 100 is in the first-level cascaded slave mode; in a multi-level cascaded structure, the first-level RF chip 100 is the first-level chip, and the last-level RF chip 100 is the last-level chip. Except for the first-level and last-level chips, all other RF chips 100 are in the first-level cascaded slave mode.

[0044] The radio frequency chip provided in this embodiment is additionally equipped with a first cascade slave mode, and the first cascade slave mode can output a cascade synchronization signal through the cascade output terminal MuxOUT, so that more radio frequency chips 100 can be connected in the cascade structure based on the radio frequency chip, thereby increasing the number of channels in the FMCW radar.

[0045] In some embodiments, reference Figure 1 (B), with Figure 1 (A) The difference is that the RF chip 100 also includes an RF transceiver circuit 103. The RF transceiver circuit 103 is configured to generate RF signals based on the cascaded synchronization signals transmitted through the signal transmission link 121, so as to enable the RF chip 100 to transmit and receive RF signals. This enables the RF chip to work collaboratively in a certain cascaded mode of multiple chips, such as enabling the RF chip to collect physical data in real time in cascaded mode.

[0046] Signal transmission link 121 connects the cascaded input terminal MuxIN and the radio frequency transceiver circuit 103 to form a second signal path. Specifically, the second signal path refers to the signal path through which the radio frequency chip 100 transmits the cascaded synchronization signal to the radio frequency transceiver circuit 103 based on signal transmission link 121, and the radio frequency transceiver circuit 103 performs radar detection based on the cascaded synchronization signal.

[0047] When the RF chip 100 is in the first cascade slave mode or the second cascade slave mode, the second signal path is used by the RF chip 100 to perform radar detection using the cascade synchronization signal.

[0048] Taking a two-stage cascaded structure as an example, Figure 1 The RF chip 100 shown in (B) is in a second cascaded slave mode, receiving the cascaded synchronization signal from the MuxIN interface via signal transmission link 121 and transmitting it to the RF transceiver circuit 103. Taking the cascaded synchronization signal as a local oscillator signal as an example, the RF transceiver circuit 103 can convert the local oscillator signal into a radar detection signal for transmission. Taking the cascaded synchronization signal as a clock synchronization signal as an example, the RF transceiver circuit 103 can use the clock synchronization signal to perform digital conversion on the received signal containing the echo signal, etc. Furthermore, in a three-stage cascaded structure, Figure 1 The RF chip 100 shown in (B) is in either a first cascade slave mode or a second cascade slave mode. Taking the RF chip 100 in the first cascade slave mode as an example, its cascade input terminal MuxIn receives the cascade synchronization signal from the chip in the cascade master mode and transmits it to the cascade output terminal MUXOUT and the RF transceiver circuit 103 via the signal transmission link 121. Taking the RF chip 100 in the second cascade slave mode as an example, its cascade input terminal MuxIn receives the cascade synchronization signal from the chip in the cascade master mode and transmits it to the RF transceiver circuit 103 via the signal transmission link 121.

[0049] In some embodiments, reference Figure 1 (C), with Figure 1 Unlike (A) and (B), the RF chip 100 also includes a signal generation circuit 102 and an RF transceiver circuit 113. The description of the RF transceiver circuit 113 is the same as... Figure 1(B), which will not be elaborated here. The signal generation circuit 102 is configured to generate an on-chip oscillation signal, which can be used as a cascade synchronization signal in any cascade mode.

[0050] Signal transmission link 131 connects signal generation circuit 102 and radio frequency transceiver circuit 113 to form a third signal path. Specifically, the third signal path refers to the signal path through which the radio frequency chip 100 uses the on-chip oscillation signal generated by signal generation circuit 102 for radar detection.

[0051] More specifically, when the RF chip 100 is in single-chip mode, the third signal path is used for the RF chip 100 to perform radar detection using the on-chip oscillation signal. Here, single-chip mode indicates that the RF chip 100 is in a non-cascaded state, operating as a single chip working independently.

[0052] Signal transmission link 131 connects signal generation circuit 102 and cascade output terminal MuxOUT, forming a fourth signal path. Specifically, the fourth signal path represents the signal path through which the RF chip 100 outputs its on-chip oscillation signal as a cascaded synchronization signal to the outside of the RF chip 100.

[0053] More specifically, when the RF chip 100 is in cascaded master mode, the fourth signal path is used by the RF chip 100 to output the on-chip oscillation signal as a cascaded synchronization signal to the outside of the RF chip 100.

[0054] For the first signal path, second signal path, third signal path, and fourth signal path transmitted via signal transmission link 111 (121, 131), in some embodiments, signal transmission link 111 can be configured with mutually independent circuits to form the first signal path, second signal path, third signal path, and fourth signal path; in other embodiments, signal transmission link 111 can also be configured with partially multiplexed circuits to form the first signal path, second signal path, third signal path, and fourth signal path.

[0055] The signal transmission link 111 can also be configured to form a first signal path, a second signal path, a third signal path, and a fourth signal path by partially multiplexing circuitry. In some embodiments, the signal transmission link 111 includes multiplexed electrical components to conduct a target signal path, which is at least one of the first signal path, the second signal path, the third signal path, and the fourth signal path.

[0056] In one example, refer to Figure 2The signal transmission link 111 includes: a first amplifier A1, with its input terminal connected to a signal generation circuit and its output terminal connected to a first node A; a second amplifier A2, with its input terminal connected to the first node A and its output terminal connected to a second node B; a third amplifier A3, with its input terminal connected to the second node B and its output terminal connected to an RF transceiver circuit; a fourth amplifier A4, with its input terminal connected to a cascaded input terminal MuxIN and its output terminal connected to the second node B; a fifth amplifier A5, with its input terminal connected to the second node B and its output terminal connected to the first node A; and a sixth amplifier A6, with its input terminal connected to the first node A and its output terminal connected to a cascaded output terminal MuxOUT.

[0057] for Figure 2 The structure of the signal transmission link 111 shown is referenced. Figure 3 (A) A first amplifier A1 is connected to a second amplifier A2, and the second amplifier A2 is connected to a third amplifier A3 to form a third signal path; Reference Figure 3 (B) The first amplifier A1 is connected to the sixth amplifier A6 to form the fourth signal path; Reference Figure 3 (C) The fourth amplifier A4 is connected to the fifth amplifier A5, and the fifth amplifier A5 is connected to the sixth amplifier A6 to form the first signal path; Reference Figure 3 (B) Figure 3 (C) and Figure 3 (D) The fourth amplifier A4 is connected to the third amplifier A3 to form a second signal path.

[0058] Specifically, Figure 3 (A) A schematic diagram representing the amplifier connection of the RF chip 100 in single-chip mode. Figure 3 (B) Schematic diagram of amplifier connection for RF chip 100 in cascaded main mode. Figure 3 (C) Schematic diagram of amplifier connection of RF chip 100 in first cascade slave mode. Figure 3 (D) A schematic diagram of amplifier access in the second cascade slave mode of the radio frequency chip 100.

[0059] It should be noted that, in Figure 3 (A)~ Figure 3 In the example drawing (D), amplifiers represented by solid lines indicate amplifiers that are actually connected, and amplifiers represented by dashed lines indicate amplifiers that are not connected. In some embodiments, the connection of an amplifier to a circuit can be controlled by controlling whether power is supplied to the amplifier. In other embodiments, the connection of an amplifier to a circuit can be controlled by switching on the corresponding path.

[0060] In some embodiments of a scheme that controls whether an amplifier is connected to a circuit by switching on a corresponding path, the signal transmission link 111 includes a gating switch to control a target signal path, which is at least one of a first signal path, a second signal path, a third signal path, and a fourth signal path. The gating switch is, for example, a MOSFET or any device having a high impedance state.

[0061] refer to Figure 4 The signal transmission link 111 includes: a first amplifier B1, whose input is connected to a signal generation circuit and whose output is connected to the first terminal of a fourth gating switch S04, the second terminal of which is connected to a first node A; a third gating switch S03, whose first terminal is connected to the first node A and whose second terminal is connected to the input of a second amplifier B2, the output of which is connected to a second node B; a third amplifier B3, whose input is connected to the second node B and whose output is connected to an RF transceiver circuit; a fourth amplifier B4, whose input is connected to a cascaded input terminal MuxIN and whose output is connected to the second node B; a first gating switch S01, whose first terminal is connected to the second node B and whose second terminal is connected to the input of a fifth amplifier B5, the output of which is connected to the first node A; and a second gating switch S02, whose first terminal is connected to the first node A and whose second terminal is connected to the input of a sixth amplifier B6, the output of which is connected to a cascaded output terminal MuxOUT.

[0062] for Figure 4 The structure of the signal transmission link 111 shown is referenced. Figure 5 (A) When the first gating switch S01 and the second gating switch S02 are off, and the third gating switch S03 and the fourth gating switch S04 are closed, the third signal path is activated; Reference Figure 5 (B) When the first gating switch S01 and the third gating switch S03 are off, and the second gating switch S02 and the fourth gating switch S04 are closed, the second signal path and the fourth signal path are connected; Reference Figure 5 (C) When the first gating switch S01 and the second gating switch S02 are closed, and the third gating switch S03 and the fourth gating switch S04 are open, the first signal path and the second signal path are connected; Reference Figure 5 (D) When the first gating switch S01, the second gating switch S02, the third gating switch S03 and the fourth gating switch S04 are disconnected, the second signal path is connected.

[0063] Specifically, Figure 5 (A) A schematic diagram representing the amplifier connection of the RF chip 100 in single-chip mode. Figure 5 (B) Schematic diagram of amplifier connection for RF chip 100 in cascaded main mode. Figure 5(C) Schematic diagram of amplifier connection of RF chip 100 in first cascade slave mode. Figure 5 (D) A schematic diagram of amplifier access in the second cascade slave mode of the radio frequency chip 100.

[0064] It should be noted that, in Figure 5 (A)~ Figure 5 In the example diagram of (D), amplifiers represented by solid lines indicate amplifiers that are actually connected, while amplifiers represented by dashed lines indicate amplifiers that are not connected. Specifically, for the fourth amplifier B4, when the cascade input terminal MuxIN has no input, the fourth amplifier B4 can be considered as being in an unconnected state.

[0065] It should be noted that configuring at least one amplifier on each signal path not only helps the RF chip provide effective signal gain in different operating modes, but also facilitates impedance matching during mode switching. Furthermore, amplifiers configured on the signal transmission links allow for greater flexibility in the arrangement of off-chip circuitry within the cascaded structure, regardless of the RF chip's cascade configuration. For example, using amplifiers to increase the swing of the cascade synchronization signal allows for a more sparse arrangement of multiple RF chips on the PCB, thus improving signal isolation between boards.

[0066] Taking the RF chip 100 as an example of a radar chip, in cascaded mode, multiple synchronization signals in the radar chip are cascaded and synchronized. For example, the cascaded synchronization signals include at least one of the following: a local oscillator signal, a clock signal from the analog-to-digital converter (ADC), or a local oscillator control signal. The local oscillator control signal is used to start / stop the transceiver circuits of the cascaded radar chips, controlling the radar's transceiver circuits to operate synchronously with the transceiver circuits of other cascaded radars. Using the cascaded synchronized local oscillator signal, the cascaded radar chips synchronously convert and amplify the local oscillator signal to form a radar signal (i.e., an RF signal) and transmit it into free space; or, the cascaded synchronized local oscillator signal is used to down-convert the received reflected signal to obtain an intermediate frequency (IF) signal. The cascaded synchronized clock signal enables the ADCs in the cascaded radar chips to synchronously convert the IF signal into a digital signal, thus reducing the phase difference of the IF signals of each chip and lowering the possibility of false target detection. This achieves a wide-range, high-precision detection capability.

[0067] In some embodiments, the local oscillator signal is a frequency modulated continuous wave (FMCW).

[0068] The radio frequency chip provided in this embodiment is additionally equipped with a first cascade slave mode, and the first cascade slave mode can output a cascade synchronization signal through the cascade output terminal, so that more radio frequency chips can be connected in the cascade structure based on the radio frequency chip, thereby increasing the number of channels in the FMCW radar.

[0069] It should be noted that the features disclosed in the radio frequency chip provided in the above embodiments can be arbitrarily combined without conflict to obtain new radio frequency chip embodiments.

[0070] The second embodiment of this disclosure also provides a chip cascade structure, in which more radio frequency chips can be connected, thereby increasing the number of channels in the FMCW radar.

[0071] The chip cascade structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0072] The chip cascade structure includes a master chip and multiple slave chips; wherein, at least one of the multiple slave chips is configured as a first type of slave chip, the first type of slave chip is the RF chip described in the first embodiment above, and the RF chip is in a first cascade slave mode; the cascade output terminal MuxOUT of the master chip is connected to the cascade input terminal MuxIN of the master chip, the first type of slave chip is cascaded with the master chip, and is also cascaded with any other slave chip.

[0073] In one example, refer to Figure 6 The RF chip (B) is the master chip. Its cascade output terminal MuxOUT is connected to the cascade input terminal MuxIN of the master chip and the cascade input terminal MuxIN of the RF chip (C) through the first external power divider. The RF chip (C) is a first-class slave chip. Its cascade output terminal MuxOUT is connected to the cascade input terminal MuxIN of multiple RF chips (D) through the second external power divider. The RF chips (D) are other slave chips that are not first-class slave chips.

[0074] Among them, the radio frequency chip (B) transmits the cascaded synchronization signal to the radio frequency chip (C) based on the on-chip oscillation signal. The radio frequency chip (B) generates radio frequency signals based on the returned cascaded synchronization signal. The radio frequency chip (C) generates radio frequency signals based on the cascaded synchronization signal and outputs the cascaded synchronization signal through the cascaded output terminal to provide to multiple radio frequency chips (D). The multiple radio frequency chips (D) generate multiple radio frequency signals based on the cascaded synchronization signal respectively.

[0075] It should be noted that in the following figures, the off-chip power divider is no longer shown between the cascaded RF chips; those skilled in the art can understand this based on... Figure 6 Configure the external power divider as shown.

[0076] In one example, refer to Figure 7 The RF chip (B) serves as the main chip. Its cascade output terminal MuxOUT is connected to the cascade input terminal MuxIN of the main chip and the cascade input terminal MuxIN of the RF chip (C). The cascade output terminal MuxOUT of the RF chip (C) is connected to the cascade input terminal MuxIN of the next stage RF chip (C) to form a series structure of multiple RF chips (C). The cascade output terminal MuxOUT of the last stage RF chip (C) is connected to the cascade input terminal MuxIN of multiple RF chips (D).

[0077] In one example, refer to Figure 8 The RF chip (B) serves as the main chip, and its cascade output terminal MuxOUT is connected to the cascade input terminal MuxIN of the main chip and the cascade input terminal MuxIN of multiple RF chips (C) to form a parallel structure of multiple RF chips (C). The cascade output terminal MuxOUT of each stage of the RF chip (C) is connected to the cascade input terminal MuxIN of multiple RF chips (D).

[0078] In one example, the radio frequency chip (C) can be combined with Figure 7 and Figure 8 The configuration involves both series and parallel connections, forming a chip cascade structure. It should be noted that... Figures 6 to 8 In the example, the radio frequency chip (C) is connected to two radio frequency chips (D), which is only for illustrative purposes; in actual applications, the number of radio frequency chips (D) connected to the radio frequency chip (C) can be any number.

[0079] It should be noted that, in order to ensure that the cascaded synchronization signals received by each chip are synchronized, the parallel signal lines are of the same length. For example, for Figure 6 As shown, the cascaded output terminal MuxOUT of the RF chip (B) is connected to the cascaded input terminal MuxIN of the RF chip (B) as the first signal line, and the cascaded output terminal MuxOUT of the RF chip (B) is connected to the cascaded input terminal MuxIN of the RF chip (C) as the second signal line. The first signal line and the second signal line are parallel signal lines, that is, the lengths of the first signal line and the second signal line are equal.

[0080] In some embodiments, the main chip is the radio frequency (RF) chip provided in the first embodiment described above, and the RF chip is in a cascaded main mode. That is, the RF chip (B) is configured based on the RF chip provided in the first embodiment described above, and the RF chip is in a cascaded main mode.

[0081] In some embodiments, at least one of the plurality of slave chips is configured as a second type of slave chip, the second type of slave chip being the RF chip provided in the first embodiment described above, and the RF chip is in a second cascaded slave mode, the second type of slave chip being cascaded with the first type of slave chip. That is, some or all of the RF chips (D) are configured based on the RF chip provided in the first embodiment described above, and the RF chip is in a second cascaded slave mode.

[0082] refer to Figures 6 to 8 As can be seen from the example, the RF chip (D) is the tail chip in the chip cascade structure, and its cascade output terminal MuxOUT no longer outputs the cascade synchronization signal, that is, the empty port of the cascade output terminal MuxOUT of the second type of slave chip; in some embodiments, the cascade input terminal MuxIN and the cascade output terminal MuxOUT of the second type of slave chip share the same port to reduce the layout area of ​​the chip cascade structure.

[0083] It is not difficult to see that this embodiment can be implemented in conjunction with the radio frequency chip provided in the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and will not be repeated here to reduce repetition. In addition, the features disclosed in the chip cascade structure provided in the above embodiments can be arbitrarily combined without conflict to obtain new chip cascade structure embodiments.

[0084] The third embodiment of this disclosure provides a chip packaging structure applied to the packaging of the radio frequency chip provided in the above embodiments. The chip packaging structure includes multiple output solder balls, each output solder ball is connected to the cascaded output terminal MuxOUT through a corresponding first transmission line, and the lengths of the first transmission lines corresponding to the multiple output solder balls are the same.

[0085] Specifically, since the output solder balls are connected to the cascaded output terminal MuxOUT, multiple output solder balls can be regarded as multiple cascaded output terminals MuxOUT of the packaged RF chip, and the output solder balls are distributed in different positions to simplify the wiring in the RF chip cascading process.

[0086] In some embodiments, the chip package structure further includes a plurality of input solder balls, each input solder ball being connected to the cascaded input terminal MuxIN via a corresponding second transmission line, and the second transmission lines corresponding to the plurality of input solder balls having the same length.

[0087] Specifically, since the input solder balls are connected to the cascade input terminal MuxIN, multiple input solder balls can be regarded as multiple cascade input terminals MuxIN of the packaged RF chip, and the input solder balls are distributed in different positions to simplify the wiring in the RF chip cascading process.

[0088] In practical applications, the input and output solder balls located in different positions allow for the minimization of routing "bends" during the cascading of RF chips to form a chip cascade structure, thereby simplifying the wiring process in the RF chip cascading process.

[0089] As discussed above, the higher the number of channels in an FMCW radar, the higher its angular resolution. A cascaded chip structure composed of multi-stage radio frequency chips is advantageous for detecting long and wide ranges, thus improving radar efficiency. The fourth embodiment of this disclosure provides a radio frequency chip, and based on this cascaded chip structure, the amplitude and phase consistency of the cascaded synchronization signals in each stage of the cascaded chip can be guaranteed.

[0090] The radio frequency chip provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0091] The radio frequency chip integrates a signal transmission link and a signal conditioning circuit, and includes cascaded input terminals and cascaded output terminals. The description of the signal transmission link can be found in the first embodiment of this disclosure, and will not be repeated in this embodiment.

[0092] Specifically, the signal transmission link connects the cascade input terminal and the cascade output terminal. In any cascade mode of the RF chip, the signal transmission link is used to transmit the cascade synchronization signal. The cascade input terminal is used to receive the cascade synchronization signal from outside the RF chip, and the cascade output terminal is used to transmit the cascade synchronization signal to outside the RF chip. The signal conditioning circuit is set in the signal transmission link and is configured to compensate for the cascade adaptation of amplitude and phase caused by inter-board transmission of the cascade synchronization signal.

[0093] Specifically, cascade mismatch includes: the phase of the cascade synchronization signal received by the RF chip in cascade mode does not conform to the preset cascade phase error, or the phase group delay of the cascade synchronization signal received by the RF chip in cascade mode does not conform to the preset cascade group delay deviation, or the amplitude of the cascade synchronization signal received by the RF chip in cascade mode is lower than the preset threshold.

[0094] The radio frequency chip provided in this embodiment uses an additional signal conditioning circuit to adjust the phase and amplitude / power of the cascaded synchronization signal received by the cascaded signal, thereby ensuring the consistency of amplitude and phase of the cascaded synchronization signal in each cascaded chip.

[0095] The cascading modes of the radio frequency (RF) chips include at least one of the following: cascading master mode, first cascading slave mode, and second cascading slave mode. The first cascading slave mode represents an RF chip that is not the first or last stage chip in the cascaded structure. The cascading master mode represents an RF chip that is the first stage chip in the cascaded structure. The second cascading slave mode represents an RF chip that is the last stage chip in the cascaded structure.

[0096] Since the signal transmission link connects the cascaded input terminal MuxIN and the cascaded output terminal MuxOUT, and the signal conditioning circuit is located in the signal transmission link, refer to Figure 9 (B) and Figure 9 (D) The signal conditioning circuit 212 can be set at the input port of the signal transmission link 201 and the cascaded input terminal MuxIN, and the signal conditioning circuit 232 can also be set at the output port of the signal transmission link 201 and the cascaded output terminal MuxOUT.

[0097] Specifically, the signal conditioning circuit 212 (232) is used to adjust the amplitude and phase of the cascaded synchronization signal transmitted by the RF chip to ensure the consistency of the amplitude and phase of the cascaded synchronization signal in each cascaded chip. (See reference) Figure 9 (B) If the signal conditioning circuit 212 is located at the input port of the signal transmission link 201 and the cascaded input terminal MuxIN, the signal conditioning circuit 212 is used to adjust the consistency of the amplitude and phase of the cascaded synchronization signal input to the RF chip; Reference Figure 9 (D) If the signal conditioning circuit 232 is set at the output port of the signal transmission link 201 and the cascade output terminal MuxOUT, the signal conditioning circuit 232 is used to adjust the consistency of the amplitude and phase of the cascaded synchronization signal output by the RF chip to the outside chip.

[0098] As can be seen from the content of the first embodiment, in some embodiments, the radio frequency chip further includes: a signal generation circuit and a radio frequency transceiver circuit. The signal generation circuit, connected to the signal transmission link 201, is used to generate an on-chip oscillation signal and output it to the signal transmission link 201; the radio frequency transceiver circuit, connected to the signal transmission link 201, uses the cascaded synchronization signal or the on-chip oscillation signal output from the signal transmission link 201 for radar detection.

[0099] refer to Figure 9 (A) and Figure 9 (C) The signal conditioning circuit 202 can be set at the input port where the signal transmission link 201 is connected to the signal generation circuit, and the signal conditioning circuit 222 can also be set at the output port where the signal transmission link 201 is connected to the radio frequency transceiver circuit.

[0100] Specifically, the signal conditioning circuit 202 (222) is used to adjust the amplitude and phase of the cascaded synchronization signal transmitted by the RF chip to ensure the consistency of the amplitude and phase of the cascaded synchronization signal in each cascaded chip. (See reference) Figure 9 (A) If the signal conditioning circuit 202 is located at the input port where the signal transmission link 201 connects to the signal generation circuit, the signal conditioning circuit 202 adjusts the amplitude and phase of the on-chip oscillation signal generated by the signal generation circuit to adjust the consistency of the amplitude and phase of the cascaded synchronization signal; Reference Figure 9(C) If the signal conditioning circuit 222 is located at the output port of the signal transmission link 201 connected to the radio frequency transceiver circuit, the signal conditioning circuit 222 is used to adjust the consistency of the amplitude and phase of the cascaded synchronization signal used for radio frequency signal operation.

[0101] Since the purpose of the radio frequency chip is to utilize cascaded synchronization signals for radar detection, preferably, the signal conditioning circuit is as follows: Figure 9 (C) Configuration to enable the cascaded synchronization signal for radar detection to be synchronized before detection.

[0102] Signal conditioning circuits 202 (212, 222, 232) are used to adjust the amplitude and phase of the cascaded synchronization signal. In some embodiments, refer to... Figure 10 The signal conditioning circuit includes a time delay circuit 205 and a variable gain amplifier circuit 206 arranged in series.

[0103] Specifically, in one example, refer to Figure 10 (A) The input terminal of the variable gain amplifier circuit 206 serves as the input terminal of the signal conditioning circuit, and the output terminal of the variable gain amplifier circuit 206 is connected to the input terminal of the delay circuit 205. The output terminal of the delay circuit 205 serves as the output terminal of the signal conditioning circuit. In another example, refer to... Figure 10 (B) The input terminal of the delay circuit 205 serves as the input terminal of the signal conditioning circuit, and the output terminal of the delay circuit 205 is connected to the input terminal of the variable gain amplifier circuit 206. The output terminal of the variable gain amplifier circuit 206 serves as the output terminal of the signal conditioning circuit.

[0104] More specifically, the delay circuit 205 is used to perform group delay on the cascaded synchronization signal to adjust the phase and / or delay of the cascaded synchronization signal, and the variable gain amplifier circuit 206 has an adjustable amplification factor to adjust the power / amplitude of the cascaded synchronization signal. In some embodiments, the delay circuit 205 may be configured as an IQ phase shifter or a transmission line phase shifter, etc. In some embodiments, the variable gain amplifier circuit 206 can change its amplification factor based on adjusting the power supply voltage, or based on adjusting the access circuit in the circuit.

[0105] Combination Figure 2 and Figure 9 For examples, see reference Figure 11 and Figure 12The signal conditioning circuit 301 is disposed in at least one of the following paths: the path between the signal generation circuit and the RF transceiver circuit connected by the signal transmission link 201, i.e., the third signal path; the path between the signal generation circuit and the cascaded output terminal MuxOUT connected by the signal transmission link 201, i.e., the fourth signal path; the path between the cascaded input terminal MuxIN and the cascaded output terminal MuxOUT connected by the signal transmission link 201, i.e., the first signal path; and the path between the RF transceiver circuit and the cascaded input terminal MuxIN connected by the signal transmission link 201, i.e., the second signal path.

[0106] If the signal conditioning circuit 301 is located in the first signal path, refer to Figure 11 (B) The signal transmission link 201 includes: a first amplifier A1, with its input connected to a signal generation circuit and its output connected to a first node A; a second amplifier A2, with its input connected to the first node A and its output connected to a second node B; a third amplifier A3, with its input connected to the second node B and its output connected to an RF transceiver circuit; a fourth amplifier A4, with its input connected to a cascaded input terminal MuxIN and its output connected to the input terminal of a signal conditioning circuit 301, the output of which is connected to the second node B; a fifth amplifier A5, with its input connected to the second node B and its output connected to the first node A; and a sixth amplifier A6, with its input connected to the first node A and its output connected to a cascaded output terminal MuxOUT. (Reference) Figure 12 (B) The signal transmission link 201 includes: a first amplifier A1, with its input terminal connected to a signal generation circuit and its output terminal connected to a first node A; a second amplifier A2, with its input terminal connected to the first node A and its output terminal connected to a second node B; a third amplifier A3, with its input terminal connected to the second node B and its output terminal connected to an RF transceiver circuit; a fourth amplifier A4, with its input terminal connected to the output terminal of a signal conditioning circuit 301, the input terminal of the signal conditioning circuit 301 connected to a cascaded input terminal MuxIN, and its output terminal connected to the second node B; a fifth amplifier A5, with its input terminal connected to the second node B and its output terminal connected to the first node A; and a sixth amplifier A6, with its input terminal connected to the first node A and its output terminal connected to a cascaded output terminal MuxOUT.

[0107] If the signal conditioning circuit 301 is located in the second signal path, refer to Figure 11(C) The signal transmission link 201 includes: a first amplifier A1, with its input connected to a signal generation circuit and its output connected to a first node A; a second amplifier A2, with its input connected to the first node A and its output connected to a second node B; a third amplifier A3, with its input connected to the output of a signal conditioning circuit 301, the input of which is connected to the second node B, and its output connected to an RF transceiver circuit; a fourth amplifier A4, with its input connected to a cascaded input terminal MuxIN and its output connected to the second node B; a fifth amplifier A5, with its input connected to the second node B and its output connected to the first node A; and a sixth amplifier A6, with its input connected to the first node A and its output connected to a cascaded output terminal MuxOUT. (Reference) Figure 12 (C) The signal transmission link 201 includes: a first amplifier A1, whose input is connected to a signal generation circuit and whose output is connected to a first node A; a second amplifier A2, whose input is connected to the first node A and whose output is connected to a second node B; a third amplifier A3, whose input is connected to the second node B and whose output is connected to the input of a signal conditioning circuit 301, the output of which is connected to a radio frequency transceiver circuit; a fourth amplifier A4, whose input is connected to a cascaded input terminal MuxIN and whose output is connected to the second node B; a fifth amplifier A5, whose input is connected to the second node B and whose output is connected to the first node A; and a sixth amplifier A6, whose input is connected to the first node A and whose output is connected to a cascaded output terminal MuxOUT.

[0108] If the signal conditioning circuit 301 is located in the third signal path, refer to Figure 11 (A) The signal transmission link 201 includes: a first amplifier A1, with its input connected to a signal generation circuit and its output connected to the input of a signal conditioning circuit 301, the output of which is connected to a first node A; a second amplifier A2, with its input connected to the first node A and its output connected to a second node B; a third amplifier A3, with its input connected to the second node B and its output connected to an RF transceiver circuit; a fourth amplifier A4, with its input connected to a cascaded input terminal MuxIN and its output connected to the second node B; a fifth amplifier A5, with its input connected to the second node B and its output connected to the first node A; and a sixth amplifier A6, with its input connected to the first node A and its output connected to a cascaded output terminal MuxOUT. (Reference) Figure 12(A) The signal transmission link 201 includes: a first amplifier A1, whose input is connected to the output of a signal conditioning circuit 301, whose input is connected to a signal generation circuit, and whose output is connected to a first node A; a second amplifier A2, whose input is connected to the first node A and whose output is connected to a second node B; a third amplifier A3, whose input is connected to the second node B and whose output is connected to an RF transceiver circuit; a fourth amplifier A4, whose input is connected to a cascaded input terminal MuxIN and whose output is connected to the second node B; a fifth amplifier A5, whose input is connected to the second node B and whose output is connected to the first node A; and a sixth amplifier A6, whose input is connected to the first node A and whose output is connected to a cascaded output terminal MuxOUT.

[0109] If the signal conditioning circuit 301 is located in the fourth signal path, refer to Figure 11 (D) The signal transmission link 201 includes: a first amplifier A1, with its input connected to a signal generation circuit and its output connected to a first node A; a second amplifier A2, with its input connected to the first node A and its output connected to a second node B; a third amplifier A3, with its input connected to the second node B and its output connected to an RF transceiver circuit; a fourth amplifier A4, with its input connected to a cascaded input terminal MuxIN and its output connected to the second node B; a fifth amplifier A5, with its input connected to the second node B and its output connected to the first node A; and a sixth amplifier A6, with its input connected to the output terminal of a signal conditioning circuit 301, the input terminal of which is connected to the first node A, and the output terminal of the sixth amplifier A6 connected to a cascaded output terminal MuxOUT. (Reference) Figure 12 (D) The signal transmission link 201 includes: a first amplifier A1, whose input is connected to the signal generation circuit and whose output is connected to the first node A; a second amplifier A2, whose input is connected to the first node A and whose output is connected to the second node B; a third amplifier A3, whose input is connected to the second node B and whose output is connected to the radio frequency transceiver circuit; a fourth amplifier A4, whose input is connected to the cascaded input MuxIN and whose output is connected to the second node B; a fifth amplifier A5, whose input is connected to the second node B and whose output is connected to the first node A; and a sixth amplifier A6, whose input is connected to the first node A and whose output is connected to the input of the signal conditioning circuit 301, and whose output is connected to the cascaded output MuxOUT.

[0110] Taking the RF chip 100 as an example of a radar chip, in cascaded mode, multiple synchronization signals in the radar chip are cascaded and synchronized. For example, the cascaded synchronization signals include at least one of the following: a local oscillator signal, a clock signal from the analog-to-digital converter (ADC), or a local oscillator control signal. The local oscillator control signal is used to start / stop the transceiver circuits of the cascaded radar chips, controlling the radar's transceiver circuits to operate synchronously with the transceiver circuits of other cascaded radars. Using the cascaded synchronized local oscillator signal, the cascaded radar chips synchronously convert and amplify the local oscillator signal to form a radar signal (i.e., an RF signal) and transmit it into free space; or, the cascaded synchronized local oscillator signal is used to down-convert the received reflected signal to obtain an intermediate frequency (IF) signal. The cascaded synchronized clock signal enables the ADCs in the cascaded radar chips to synchronously convert the IF signal into a digital signal, thus reducing the phase difference of the IF signals of each chip and lowering the possibility of false target detection. This achieves a wide-range, high-precision detection capability.

[0111] In some embodiments, the local oscillator signal is a frequency modulated continuous wave (FMCW).

[0112] The radio frequency chip provided in this embodiment uses an additional signal conditioning circuit to adjust the phase and amplitude / power of the cascaded synchronization signal received by the cascaded signal, thereby ensuring the consistency of amplitude and phase of the cascaded synchronization signal in each cascaded chip.

[0113] It should be noted that the features disclosed in the RF chip provided in the above embodiments can be arbitrarily combined without conflict to obtain new RF chip embodiments. Furthermore, this embodiment can be implemented in conjunction with the RF chip provided in the first embodiment. The relevant technical details mentioned in the first embodiment remain valid in this embodiment, and will not be repeated here to reduce repetition.

[0114] The fifth embodiment of this disclosure also provides a chip cascade structure, in which the radio frequency chip of the chip cascade structure adjusts the phase and amplitude / power of the cascade synchronization signal received by the cascade signal through an additional signal conditioning circuit, thereby ensuring the consistency of amplitude and phase of the cascade synchronization signal in each cascade chip.

[0115] Specifically, the chip cascade structure includes at least two cascaded chips, wherein at least one chip is the radio frequency chip provided in the fourth embodiment above.

[0116] More specifically, assuming the chip cascade structure includes cascaded radio frequency chip A and radio frequency chip B, if radio frequency chip A is the radio frequency chip provided in the above embodiment, then radio frequency chip A adjusts the phase and amplitude / power of the internal cascaded synchronization signal so that the phase and amplitude / power of the cascaded synchronization signal in radio frequency chip A and radio frequency chip B are the same.

[0117] In some embodiments, the cascaded chip structure provided in this embodiment can also be applied to the second embodiment, that is, at least one master chip or slave chip in the second embodiment is the radio frequency chip provided in the fourth embodiment above.

[0118] That is, while ensuring the amplitude and phase consistency of the cascaded synchronization signals in each cascaded chip, more radio frequency chips can be connected in the chip cascaded structure, thereby increasing the number of channels in the FMCW radar.

[0119] In addition, based on the cascading requirements of radio frequency (RF) chips, the sixth embodiment of this disclosure also provides an RF chip that enables the RF chip to perform functional self-tests in cascading mode in single-chip mode, thereby ensuring the accuracy of the chip cascading structure based on the RF chip.

[0120] The radio frequency chip provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0121] refer to Figure 13 The radio frequency chip integrates a signal transmission link 401 and a self-test circuit 402, and includes a cascaded input terminal MuxIN and a cascaded output terminal MuxOUT. The description of the signal transmission link 401 can be found in the first embodiment of this disclosure, and will not be repeated in this embodiment.

[0122] Signal transmission link 401 connects the cascade input terminal MuxIN and the cascade output terminal MuxOUT to receive cascade synchronization signals from outside the chip and / or output cascade synchronization signals to outside the chip. In the self-test mode of the RF chip, the self-test circuit 402 is coupled to the signal transmission link 401. The self-test circuit 402 is configured to collect the cascade synchronization signals transmitted in the RF chip and detect whether the working state of the RF chip in cascade mode is abnormal based on the cascade synchronization signals.

[0123] In one example, combined Figure 2 Example, Reference Figure 14 The self-test circuit 402 includes at least an impedance circuit 412. Specifically, the impedance circuit 412 is configured to simulate the off-chip loss of the cascaded synchronization signal when the RF chip is in cascaded mode, acquire the cascaded synchronization signal received by the RF chip, and detect whether the operating state in cascaded mode is abnormal based on the amplitude / phase of the cascaded synchronization signal.

[0124] More specifically, since the impedance circuit 412 is used to simulate the off-chip transmission loss of the cascade synchronization signal in cascade mode, if the amplitude / phase loss of the cascade synchronization signal received by the RF chip meets the expected loss in cascade mode, it proves that the RF chip can work normally in cascade mode; if the amplitude / phase loss of the cascade synchronization signal received by the RF chip does not meet the expected loss in cascade mode, it proves that the RF chip cannot work normally in cascade mode.

[0125] The RF chip provided in this embodiment uses a self-test circuit to simulate the off-chip transmission loss of the cascaded synchronization signal in cascaded mode, enabling the RF chip to perform functional self-tests in cascaded mode in single-chip mode, thus ensuring the accuracy of the chip cascaded structure based on this RF chip.

[0126] In some embodiments, the impedance circuit 412 is configured as an adjustable impedance circuit, i.e., the self-test circuit includes an adjustable impedance circuit, wherein the input terminal of the adjustable impedance circuit is coupled to the cascaded output terminal MuxOUT, and the output terminal is coupled to the cascaded input terminal MuxIN. The adjustable impedance circuit 412 is configured to adjust the loss of the cascaded synchronization signal at the cascaded output terminal MuxOUT and / or the cascaded input terminal MuxIN. The adjustable impedance of the impedance circuit 412 makes it easier to match the loss of the cascaded synchronization signal between the impedance circuit 412 and the external impedance connected to the cascaded output terminal MuxOUT and / or the cascaded input terminal MuxIN.

[0127] In some embodiments, the adjustable impedance circuit is configured as a variable gain amplifier circuit. The variable gain amplifier circuit changes the amplitude / power of the output cascaded synchronization signal by adjusting the amplification factor, that is, by adjusting the amplification factor, it changes the impedance of the impedance circuit 412, thereby simulating the loss of the cascaded synchronization signal by the external impedance connected to the cascaded output terminal MuxOUT and / or the cascaded input terminal MuxIN.

[0128] In some embodiments, the self-test circuit 402 further includes a switching circuit coupled to a signal transmission link and configured to controllably connect the self-test circuit 402 and the signal transmission link 401 in self-test mode; and disconnect the self-test circuit 402 and the signal transmission link 401 in non-self-test mode.

[0129] In one example, combined Figure 2 Example, Reference Figure 14 Specifically, the self-test circuit 402, which includes a switching circuit, includes at least: a first switch K1, with its first terminal connected to the cascaded output terminal MuxOUT, and its second terminal connected to the input terminal of the impedance circuit 412. The output terminal of the impedance circuit 412 is connected to the first terminal of the second switch K2, and the second terminal of the second switch K2 is connected to the cascaded input terminal MuxIN. Figure 14In the example, when both the first switch K1 and the second switch K2 are closed, the self-test circuit 402 is turned on, and the impedance circuit 412 adjusts the amplitude / power of the cascaded synchronization signal to simulate the loss of the cascaded synchronization signal transmitted off-chip in cascaded mode.

[0130] In some embodiments, reference Figure 15 and Figure 16 The self-test circuit includes a signal acquisition circuit and a processor. The signal acquisition circuit is coupled to the signal transmission link and is configured to acquire cascaded synchronization signals in self-test mode to output a detection signal. The processor is coupled to the signal acquisition circuit and is configured to detect the detection signal and output abnormal information when the RF chip is in abnormal working state in cascade mode.

[0131] In some embodiments, the signal acquisition circuit includes a coupler 403 and a power detection circuit (PDT, Powerdetection test) 404; wherein the coupler 403 is coupled to the signal transmission link 401 and is configured to output an acquisition signal corresponding to the cascaded synchronization signal; the power detection circuit 404 is coupled to the coupler 403 and is configured to convert the acquisition signal into a detection signal reflecting the power of the cascaded synchronization signal.

[0132] Specifically, the detection signal acquired by the power detection circuit 404 is acquired by the processor. Based on the power of the detection signal and the power of the cascaded signal required for the cascaded mode to determine whether the RF chip is malfunctioning in the cascaded mode, the processor outputs abnormal information when the working state is abnormal.

[0133] Coupler 403 includes any one of the following: (1) a series capacitor circuit with an output terminal connected between the signal transmission link 401 and the signal ground, the output terminal of which outputs the acquired signal. (2) an induction component, such as a coil component or an induction coupling line component, which induction couples the signal transmission link and outputs the acquired signal.

[0134] refer to Figure 15 In some embodiments, if the coupler 403 is based on a series capacitor circuit with an output terminal, the series capacitor circuit includes a first capacitor C1 and a second capacitor C2, wherein the first terminal of the first capacitor C1 is coupled to the cascaded input terminal MuxIN, and the second terminal is connected to the output terminal of the coupler 403, and the first terminal of the second capacitor C2 is coupled to the second terminal of the first capacitor C1, and the second terminal is coupled to signal ground.

[0135] refer to Figure 16In some embodiments, if the coupler 403 is configured based on a coil assembly, the coil assembly includes four mutually coupled sub-coils, hereinafter referred to as the first coil, the second coil, the third coil, and the fourth coil. The first coil is connected to the cascaded input terminal MuxIN, the second coil is connected to the output terminal of the coupler 403, the third coil is coupled to the signal transmission link 401, and the fourth coil is coupled to the impedance circuit 412.

[0136] Taking the RF chip 100 as an example of a radar chip, in cascaded mode, multiple synchronization signals in the radar chip are cascaded and synchronized. For example, the cascaded synchronization signals include at least one of the following: a local oscillator signal, a clock signal from the analog-to-digital converter (ADC), or a local oscillator control signal. The local oscillator control signal is used to start / stop the transceiver circuits of the cascaded radar chips, controlling the radar's transceiver circuits to operate synchronously with the transceiver circuits of other cascaded radars. Using the cascaded synchronized local oscillator signal, the cascaded radar chips synchronously convert and amplify the local oscillator signal to form a radar signal (i.e., an RF signal) and transmit it into free space; or, the cascaded synchronized local oscillator signal is used to down-convert the received reflected signal to obtain an intermediate frequency (IF) signal. The cascaded synchronized clock signal enables the ADCs in the cascaded radar chips to synchronously convert the IF signal into a digital signal, thus reducing the phase difference of the IF signals of each chip and lowering the possibility of false target detection. This achieves a wide-range, high-precision detection capability.

[0137] In some embodiments, the local oscillator signal is a frequency modulated continuous wave (FMCW).

[0138] The RF chip provided in this embodiment uses a self-test circuit to simulate the off-chip transmission loss of the cascaded synchronization signal in cascaded mode, enabling the RF chip to perform functional self-tests in cascaded mode in single-chip mode, thus ensuring the accuracy of the chip cascaded structure based on this RF chip.

[0139] It should be noted that the features disclosed in the RF chips provided in the above embodiments can be arbitrarily combined without conflict to obtain new RF chip embodiments. Furthermore, this embodiment can be implemented in conjunction with the RF chips provided in the first embodiment and / or the fourth embodiment. The relevant technical details mentioned in the first embodiment and / or the fourth embodiment remain valid in this embodiment, and will not be repeated here to reduce repetition.

[0140] The seventh embodiment of this disclosure also provides a chip cascade structure. In the chip cascade structure, the radio frequency chip simulates the off-chip transmission loss of the cascade synchronization signal in the cascade mode through a self-test circuit, so that the radio frequency chip can perform functional self-test in the cascade mode in the single-chip mode, ensuring the accuracy of the chip cascade structure based on the radio frequency chip.

[0141] Specifically, the chip cascade structure includes a master chip and at least one slave chip, wherein at least one of the master chip and at least one slave chip is the radio frequency chip provided in the sixth embodiment above.

[0142] In some embodiments, the cascaded chip structure provided in this embodiment can also be applied to the second embodiment, that is, at least one master chip or slave chip in the second embodiment is the radio frequency chip provided in the sixth embodiment above.

[0143] That is, while ensuring the chip's self-test function, more radio frequency chips can be connected in the chip cascade structure, thereby increasing the number of channels in the FMCW radar.

[0144] In some embodiments, the cascaded chip structure provided in this embodiment can also be applied to the fourth embodiment, that is, at least one chip in the fourth embodiment is the radio frequency chip provided in the sixth embodiment above.

[0145] That is, while ensuring the chip's self-test function, it also ensures the amplitude and phase consistency of the cascade synchronization signal in each cascade chip.

[0146] In some embodiments, the cascaded chip structure provided in this embodiment can also be implemented together with the second and fourth embodiments to form a chip cascaded structure with the functions of all three.

[0147] The eighth embodiment of this disclosure provides a radar device. In one example, the radar device includes the chip cascade structure provided in the second embodiment described above. In another example, the radar device includes the chip cascade structure provided in the fifth embodiment described above. In yet another example, the radar device includes the chip cascade structure provided in the seventh embodiment described above.

[0148] Specifically, the radar chip includes a signal generator, a local oscillator circuit, and a power amplifier circuit connected in sequence; wherein, the signal generator is used to generate signals for radar detection, such as pulse signals, FMCW signals, etc.

[0149] Among them, radar chips are circuits built based on the Doppler effect formed between electromagnetic waves and velocity, which are detection devices that convert physical quantities in physical space into electrical signals.

[0150] The circuit principle of a radar chip includes a transmitter, a receiver, an analog-to-digital converter (ADC), and digital circuitry. The transmitter comprises a signal generator, a local oscillator circuit, an RF transmitting circuit (including a power amplifier circuit), and a transmitting antenna. The receiver includes a receiving antenna, a mixer, and an ADC. The signal generator produces a continuously varying frequency signal and outputs it to the local oscillator circuit to form the LO signal for the transmitting frequency band. The RF transmitting circuit amplifies the LO signal, and may even perform phase-controlled modulation to form a chirp signal, which is then converted into an electromagnetic wave by the transmitting antenna. This electromagnetic wave is reflected by an object to form an echo. The receiving antenna converts this echo into an echo signal. The mixer uses the LO signal to down-convert the echo signal to an intermediate frequency (IF) signal. The ADC then converts this IF signal into a digital signal. The digital signal output by the ADC corresponding to each chirp is also called a digital sequence.

[0151] By using the aforementioned cascaded radar devices, more independent transceiver ports can be integrated to form MIMO channels with the antenna array. This not only enables detection over a wider area using the antenna array but also improves detection accuracy.

[0152] In addition, the cascaded radar devices described above can also ensure the consistency of the LO signals in each radar chip.

[0153] In addition, by utilizing the aforementioned cascaded radar device, the self-test function of a single radar chip can enable the radar chip to perform functional self-tests in cascade mode in single-chip mode, ensuring the accuracy of the chip cascade structure based on the radio frequency chip.

[0154] A digital signal processor (DSP) processes the accumulated digital sequences from each receiver port to determine the relative position of the target and the radar chip. The DSP can be a DSP (Digital Signal Processor) or a dedicated hardware accelerator. The DSP performs signal processing including at least one of the following: improving SNR, FFT-based signal processing, CFAR, MIMO-based target estimation, etc., to obtain the relative position.

[0155] The radar device also includes: an antenna array, wherein the transmitting antenna in the antenna array is connected to the output of a radio frequency amplifier circuit to radiate millimeter-wave signals into free space; and receiving reflected signals (also known as echo signals) reflected by objects and obtaining digital signals.

[0156] The ninth embodiment of this disclosure provides an electronic device that includes at least the radar device described in the eighth embodiment above.

[0157] In one example, electronic devices include traditional computing devices such as desktop computers, laptops, smartphones, wearable devices such as smartwatches, and internet services. However, electronic devices also include other types of computing devices, such as personal voice assistants, programmable thermostats, automotive electronic components, robots, smart devices embedded in other machines, such as refrigerators and industrial tools, and Internet of Things (IoT) devices.

[0158] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application.

Claims

1. A radio frequency chip, characterized in that, include: It integrates a signal transmission link and a signal conditioning circuit, and includes cascaded input terminals and cascaded output terminals; The signal transmission link connects the cascaded input terminal and the cascaded output terminal; In any cascading mode of the radio frequency chips, the signal transmission link is used to transmit the cascading synchronization signal, the cascading input terminal is used to receive the cascading synchronization signal from outside the radio frequency chip, and the cascading output terminal is used to transmit the cascading synchronization signal to outside the radio frequency chip. The signal conditioning circuit is disposed in the signal transmission link, and the signal conditioning circuit is configured to compensate for the cascaded mismatch in amplitude and phase caused by inter-board transmission of the cascaded synchronization signal.

2. The radio frequency chip according to claim 1, characterized in that, The signal conditioning circuit includes: A time delay circuit and a variable gain amplifier circuit arranged in series; The delay circuit is used to delay the cascaded synchronization signal; The variable gain amplifier circuit has an adjustable amplification factor to adjust the power / amplitude of the cascaded synchronization signal.

3. The radio frequency chip according to claim 1, characterized in that, Also includes: A signal generation circuit, connected to the signal transmission link, is used to generate an on-chip oscillation signal and output it to the signal transmission link. The radio frequency transceiver circuit is connected to the signal transmission link and uses the cascaded synchronization signal output by the signal transmission link or the on-chip oscillation signal for radar detection.

4. The radio frequency chip according to claim 3, characterized in that, The signal conditioning circuit is disposed in at least one of the following paths: The signal transmission link is located on the path connecting the signal generation circuit and the radio frequency transceiver circuit. The path connecting the signal transmission link to the signal generation circuit and the cascaded output terminal; The path on which the signal transmission link connects the cascaded input terminal and the cascaded output terminal; The signal transmission link is connected to the path of the radio frequency transceiver circuit and the cascaded input terminal.

5. The radio frequency chip according to any one of claims 1 to 4, characterized in that, The cascading modes of the radio frequency chip include at least one of the following: cascading master mode, first cascading slave mode, and second cascading slave mode.

6. The radio frequency chip according to any one of claims 1 to 4, characterized in that, The cascaded synchronization signal includes at least one of the following: a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal.

7. The radio frequency chip according to claim 6, characterized in that, The local oscillator signal is a continuously modulated frequency signal.

8. A chip cascade structure, characterized in that, It includes at least two cascaded chips, wherein at least one of the chips is a radio frequency chip as described in any one of claims 1 to 7.

9. A radar device, characterized in that, The radar device includes the chip cascade structure as described in claim 8.

10. An electronic device, characterized in that, The electronic device includes at least the radar device as described in claim 9.

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