Channel parameter management method and apparatus, electronic device, and storage medium

Abstract

The application provides a channel parameter management method and device, electronic equipment and storage medium, belonging to the technical field of solid state disks, comprising: monitoring the bit error rate of a NAND flash memory; adjusting the step size of frequency scanning according to the bit error rate; writing first data to the NAND flash memory at a first frequency and reading the first data from the NAND flash memory at a second frequency; if the first data is written incorrectly, determining that the write data path of the NAND flash memory is faulty; adjusting the drive strength of the NAND flash memory, the terminal resistance of the NAND flash memory and the write delay clock of the controller of the solid state disk in sequence based on the bit error rate; writing second data to the NAND flash memory at the second frequency and reading the second data from the NAND flash memory at the first frequency; if the second data is read incorrectly, determining that the read data path of the NAND flash memory is faulty; adjusting the terminal resistance of the NAND flash memory, the reference voltage of the controller of the solid state disk and the sampling delay of the controller of the solid state disk in sequence based on the bit error rate. The read and write data path faults can be automatically distinguished and parameter collaborative management can be performed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solid state disks, and particularly relates to a channel parameter management method and device, electronic equipment and a storage medium. BACKGROUND

[0002] With the continuous rise of the working frequency of a solid state disk (SSD), signal integrity problems, including signal attenuation, timing offset and impedance mismatch, have become a key bottleneck restricting the further improvement of the performance of the SSD. These phenomena deteriorate exponentially with the frequency and easily lead to abnormal operation of the SSD. At present, the debugging methods for the above problems mainly have the following limitations and defects:

[0003] Differentiation of read and write data path characteristics is not performed: the prior art fails to differentiate and process the different electrical characteristics of the read data path and the write data path, leading to confusion of the fault phenomena of the two paths. This makes the debugging direction possibly wrong, which not only fails to solve the problem, but also possibly aggravates the fault of the SSD at high frequency due to the wrong adjustment of parameters.

[0004] There is a lack of parameter coordination mechanism: there are many channel parameters for controlling the read and write directions of the SSD, and there is a significant coupling effect between the parameters. The current technology lacks a systematic parameter coordination adjustment mechanism, and each parameter is often adjusted in isolation, ignoring the mutual influence, leading to poor debugging effect and difficulty in achieving the overall optimal transmission performance.

[0005] Therefore, there is an urgent need in the art for a solution that is automated and intelligent and can differentiate and manage the fault of the read and write data paths and the parameters in coordination, to efficiently solve the signal integrity problem in the high-speed SSD. SUMMARY

[0006] The present disclosure provides a channel parameter management method and device, electronic equipment and a storage medium to at least solve the above technical problems in the prior art.

[0007] In a first aspect, an embodiment of the present application provides a channel parameter management method, which comprises:

[0008] monitoring the error code rate of a NAND flash memory;

[0009] adjusting the step size of frequency scanning according to the error code rate of the NAND flash memory; the frequency is the operating frequency of a channel between the NAND flash memory and a solid state disk;

[0010] writing first data to the NAND flash memory at a first frequency and reading the first data from the NAND flash memory at a second frequency; if the first data is written incorrectly, it is determined that the write data path of the NAND flash memory is faulty;

[0011] if the write data path of the NAND flash memory is faulty, adjusting the drive strength of the NAND flash memory, the termination resistance of the NAND flash memory and the write delay clock of the controller of the solid state drive in turn based on the error rate of the NAND flash memory;

[0012] writing second data to the NAND flash memory at the second frequency and reading the second data from the NAND flash memory at the first frequency; if the second data is read incorrectly, determining that the read data path of the NAND flash memory is faulty;

[0013] if the read data path of the NAND flash memory is faulty, adjusting the termination resistance of the NAND flash memory, the reference voltage of the controller of the solid state drive and the sampling delay of the controller of the solid state drive in turn based on the error rate of the NAND flash memory.

[0014] In an implementation, the adjusting the step of the frequency scanning based on the error rate of the NAND flash memory comprises:

[0015] if the error rate of the NAND flash memory is less than or equal to a first threshold value, adjusting the step of the frequency scanning to be a first value;

[0016] if the error rate of the NAND flash memory is greater than the first threshold value and less than or equal to a second threshold value, adjusting the step of the frequency scanning to decay exponentially;

[0017] if the error rate of the NAND flash memory is greater than the second threshold value, adjusting the step of the frequency scanning to be a second value.

[0018] In an implementation, the adjusting the step of the frequency scanning to decay exponentially comprises:

[0019] adjusting the step of the frequency scanning to be equal to the product of the first value and a first index;

[0020] wherein the base of the first index is a constant e and the index is the error rate of the NAND flash memory divided by a third value.

[0021] In an implementation, the determining that the write data path of the NAND flash memory is faulty if the first data is written incorrectly comprises:

[0022] if the error rate of writing the first data is greater than M times the error rate of reading the first data, determining that the write data path of the NAND flash memory is faulty.

[0023] In an embodiment, the adjusting the drive strength of the NAND flash memory, the termination resistance of the NAND flash memory and the write delay clock of the controller of the solid state drive in sequence based on the bit error rate of the NAND flash memory comprises:

[0024] adjusting the drive strength of the NAND flash memory ;

[0025] adjusting the termination resistance of the NAND flash memory ;

[0026] adjusting the write delay clock of the controller of the solid state drive ;

[0027] wherein, is the bit error rate.

[0028] In an embodiment, if the second data is read incorrectly, it is determined that the read data path of the NAND flash memory is faulty, comprising:

[0029] If the bit error rate of reading the second data is greater than N times of the bit error rate of writing the second data, it is determined that the read data path of the NAND flash memory is faulty.

[0030] In an embodiment, the adjusting the termination resistance of the NAND flash memory, the reference voltage of the controller of the solid state drive and the sampling delay of the controller of the solid state drive in sequence based on the bit error rate of the NAND flash memory comprises:

[0031] adjusting the termination resistance of the NAND flash memory ;

[0032] adjusting the reference voltage of the controller of the solid state drive ;

[0033] adjusting the sampling delay of the controller of the solid state drive , T is the ambient temperature, is the bit error rate.

[0034] In an embodiment, the monitoring the bit error rate of the NAND flash memory comprises:

[0035] The hardware accelerator calculates the ratio of the number of error bits to the number of transmission bits every 1 millisecond to obtain the bit error rate of the NAND flash memory.

[0036] In a second aspect, the embodiments of the present application provide a channel parameter management device, comprising:

[0037] a monitoring module configured to monitor the bit error rate of the NAND flash memory;

[0038] The adjusting module is configured to adjust a step of frequency scanning according to a bit error rate of the NAND flash memory; the frequency is a running frequency of a channel between the NAND flash memory and the solid state disk;

[0039] The processing module is configured to write first data to the NAND flash memory at a first frequency and read the first data from the NAND flash memory at a second frequency; if the first data is written incorrectly, it is determined that a write data path of the NAND flash memory is faulty.

[0040] The adjusting module is configured to, if the write data path of the NAND flash memory is faulty, sequentially adjust a driving strength of the NAND flash memory, a terminal resistance of the NAND flash memory and a write delay clock of a controller of the solid state disk based on the bit error rate of the NAND flash memory.

[0041] The processing module is further configured to write second data to the NAND flash memory at the second frequency and read the second data from the NAND flash memory at the first frequency; if the second data is read incorrectly, it is determined that a read data path of the NAND flash memory is faulty.

[0042] The adjusting module is further configured to, if the read data path of the NAND flash memory is faulty, sequentially adjust the terminal resistance of the NAND flash memory, a reference voltage of the controller of the solid state disk and a sampling delay of the controller of the solid state disk based on the bit error rate of the NAND flash memory.

[0043] In some embodiments, the adjusting module is specifically configured to, if the bit error rate of the NAND flash memory is less than or equal to a first threshold value, adjust the step of frequency scanning to be a first numerical value.

[0044] If the bit error rate of the NAND flash memory is greater than the first threshold value and less than or equal to a second threshold value, the step of frequency scanning is exponentially attenuated.

[0045] If the bit error rate of the NAND flash memory is greater than the second threshold value, the step of frequency scanning is adjusted to be a second numerical value.

[0046] In some embodiments, the adjusting module is specifically configured to adjust the step of frequency scanning to be a product of the first numerical value and a first index.

[0047] The base of the first index is a constant e, and the index is the bit error rate of the NAND flash memory divided by a third numerical value.

[0048] In some embodiments, the processing module is specifically configured to, if the bit error rate of writing the first data is greater than M times the bit error rate of reading the first data, determine that the write data path of the NAND flash memory is faulty.

[0049] In some embodiments, the adjusting module is specifically configured to adjust driving strength of the NAND flash memory

[0050] adjusting termination resistance of the NAND flash memory

[0051] adjusting write delay clock of the controller of the solid state disk

[0052] wherein, is the bit error rate.

[0053] In some embodiments, the processing module is specifically configured to determine that a read data path of the NAND flash memory is faulty if the bit error rate of reading the second data is greater than N times of the bit error rate of writing the second data.

[0054] In some embodiments, the adjusting module is specifically configured to adjust termination resistance variation of the NAND flash memory

[0055] adjusting reference voltage variation of the controller of the solid state disk

[0056] adjusting sampling delay variation of the controller of the solid state disk T is the ambient temperature, is the bit error rate.

[0057] In some embodiments, the monitoring module is specifically configured to calculate a ratio of the number of error bits to the number of transmission bits every 1 millisecond to obtain the bit error rate of the NAND flash memory.

[0058] In a third aspect, an embodiment of the present application provides an electronic device, comprising:

[0059] a processor and a memory connected with the processor in communication, the memory storing instructions, the instructions being executed by the processor to enable the processor to perform the channel parameter management method.

[0060] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium storing executable instructions for being executed by a processor to implement the channel parameter management method.

[0061] In a fifth aspect, an embodiment of the present application provides a computer program product comprising computer programs / instructions, the computer programs / instructions being executed by a processor to implement the channel parameter management method.

[0062] ​​​​​The channel parameter management method provided by the embodiment of the application comprises: monitoring the error code rate of the NAND flash memory; adjusting the step length of frequency scanning according to the error code rate; writing first data to the NAND flash memory at a first frequency and reading the first data from the NAND flash memory at a second frequency; if the first data is written incorrectly, determining that the write data path of the NAND flash memory is faulty; adjusting the drive strength of the NAND flash memory, the terminal resistance of the NAND flash memory and the write delay clock of the controller of the solid state disk in sequence based on the error code rate; writing second data to the NAND flash memory at the second frequency and reading the second data from the NAND flash memory at the first frequency; if the second data is read incorrectly, determining that the read data path of the NAND flash memory is faulty; adjusting the terminal resistance of the NAND flash memory, the reference voltage of the controller of the solid state disk and the sampling delay of the controller of the solid state disk in sequence based on the error code rate. The read and write data path faults can be automatically distinguished, and the parameters can be managed in coordination. The embodiment of the application can automatically distinguish the read and write data path faults, and can manage the channel parameters between the solid state disk and the NAND flash memory in coordination. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 A processing flow schematic diagram of the channel parameter management method provided by the embodiment of the application is shown;

[0064] Figure 2 A flow schematic diagram of optimizing the write data path fault provided by the embodiment of the application is shown;

[0065] Figure 3 A flow schematic diagram of optimizing the read data path fault provided by the embodiment of the application is shown;

[0066] Figure 4 A whole processing flow schematic diagram of the channel parameter management method provided by the embodiment of the application is shown;

[0067] Figure 5 A component structure schematic diagram of the channel parameter management device provided by the embodiment of the application is shown;

[0068] Figure 6 A structure schematic diagram of the electronic device provided by the embodiment of the application is shown. DETAILED DESCRIPTION

[0069] In order to make the objectives, features and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure.

[0070] In the following description, reference is made to "some embodiments", which describe only a subset of all possible embodiments, and which can be understood as a description of a subset of all possible embodiments, or as a description of a different subset of all possible embodiments, and which can be combined with each other, without contradiction.

[0071] In the following description, the terms "first\second" are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that the "first\second" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0073] It should be understood that in various embodiments of the present application, the size of the serial number of each implementation process does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0074] The processing flow diagram of a channel parameter management method provided by the embodiments of the present application is shown in FIG. 1, which can be applied to an architecture system including at least two processor cores (a first processor core and a second processor core), and at least includes the following steps: Figure 1

[0075] Step S101, monitoring the bit error rate of the NAND flash memory.

[0076] In some embodiments, the bit error rate of the NAND flash memory is monitored in real time by a fully automatic control engine. Specifically, the control engine can process the bit error rate of the NAND flash memory corresponding to 100,000 times of data transmission per second; the control engine can update the data in units of milliseconds to avoid missing transient faults. Wherein, the bit error rate is equal to the ratio of the number of error bits to the total number of transmission bits.

[0077] Step S102, adjusting the step size of frequency scanning according to the bit error rate of the NAND flash memory; the frequency is the operating frequency of the channel between the NAND flash memory and the solid state disk.

[0078] ​In some embodiments, if the error rate of the NAND flash memory is less than or equal to a first threshold value, the step size of the frequency scan is adjusted to a first value; wherein the first threshold value can also be referred to as a safety threshold value, representing that the error rate of the NAND flash memory is within a normal range, and neither the read data path nor the write data path of the NAND flash memory has failed; the first threshold value can be 10 -13 . The first value can be the maximum value of the step size of the frequency scan, such as 200 MHz. By adjusting the step size of the frequency scan to the maximum value, the operating frequency of the channel between the NAND flash memory and the solid state disk can be quickly increased to speed up the debugging process.

[0079] In other embodiments, if the error rate of the NAND flash memory is greater than the first threshold value and less than or equal to a second threshold value, the step size of the frequency scan is adjusted exponentially. The second threshold value can be 10 -12 . In this scenario, adjusting the step size of the frequency scan exponentially includes adjusting the step size of the frequency scan to be equal to the product of the first value and a first exponential; wherein the first value can be 200, and the base of the first exponential is a constant e, and the exponent is the error rate of the NAND flash memory divided by a third value. Specifically, the third value can be 10 -12 , and the first exponential can be: , where BER represents the error rate of the NAND flash memory.

[0080] Therefore, when the error rate of the NAND flash memory is greater than the first threshold value and less than or equal to the second threshold value, the step size of the frequency scan is adjusted to: .

[0081] In the embodiments of the present application, the step size of the frequency scan is adjusted according to the exponential decay type step size algorithm, and at a frequency of 2400 MHz, a positioning accuracy of 5 MHz is achieved, which can reduce errors compared to the fixed step size adjustment method.

[0082] In the embodiments of the present application, when the error rate is greater than the first threshold value and less than or equal to the second threshold value, it represents that the error rate is between normal and failure of the read data path or the write data path of the NAND flash memory. If the error rate continues to increase, it represents that the read data path or the write data path of the NAND flash memory has failed, and if the error rate continues to decrease, it represents that the read data path or the write data path of the NAND flash memory is normal. Therefore, when the error rate is greater than the first threshold value and less than or equal to the second threshold value, the step size of the frequency scan is automatically reduced to ensure accurate capture of the failure critical point of the read data path or the write data path of the NAND flash memory.

[0083] In yet other embodiments, if the error rate of the NAND flash memory is greater than the second threshold value, the step size of the frequency scan is adjusted to a second value. The second threshold value can be 10-12 The second value can be 100 MHz.

[0084] In the embodiments of the present application, the step size of frequency scanning is dynamically adjusted according to the value of the error rate of the NAND flash memory, so that the operating frequency of the channel between the NAND flash memory and the solid state disk can be quickly increased to speed up the debugging process, and the failure critical point of the read data path or the write data path of the NAND flash memory can be accurately captured.

[0085] In step S103, first data is written to the NAND flash memory at a first frequency, and the first data is read from the NAND flash memory at a second frequency; if the first data is written incorrectly, it is determined that the write data path of the NAND flash memory is faulty.

[0086] In some embodiments, the first frequency can refer to the current failure frequency; for example, if the error rate of the NAND flash memory is greater than a second threshold value (for example, 10 -12 ), it indicates that the read data path and / or the write data path of the current NAND flash memory are faulty, and the current frequency can be referred to as the failure frequency. The first frequency can also be any one of the verified failure frequencies, such as 2000 MHz. In the embodiments of the present application, the value of the failure frequency is higher than the second frequency; wherein the second frequency can also be referred to as the reference frequency, and the reference frequency is the frequency at which the read data path and the write data path of the NAND flash memory can normally work.

[0087] In the embodiments of the present application, first data is written to the NAND flash memory at a high frequency (failure frequency), and the first data is read from the NAND flash memory at a low frequency (reference frequency); if the first data is written incorrectly, it is determined that the write data path of the NAND flash memory is faulty. Wherein, the first data written incorrectly can refer to: the error rate of writing the first data to the NAND flash memory is greater than 10 -12 times the error rate of reading the first data, and N can be 10; then it is determined that the read data path of the NAND flash memory is faulty.

[0088] In step S104, if the write data path of the NAND flash memory is faulty, the drive strength of the NAND flash memory, the terminal resistance of the NAND flash memory, and the write delay clock of the controller of the solid state disk are sequentially adjusted based on the error rate of the NAND flash memory.

[0089] In some embodiments, if the write data path of the NAND flash memory is faulty, the flowchart for optimizing the write data path failure is as follows: Figure 2The drive strength of the NAND flash memory is first adjusted based on the error rate of the NAND flash memory, then the termination resistance of the NAND flash memory is adjusted based on the error rate of the NAND flash memory, and finally the write delay clock of the controller of the solid state disk is adjusted based on the error rate of the NAND flash memory. If the error rate of the NAND flash memory meets a preset value, a parameter combination is recorded, and the parameter combination includes the drive strength of the NAND flash memory, the termination resistance of the NAND flash memory, and the write delay clock of the controller of the solid state disk. If the error rate of the NAND flash memory does not meet the preset value, the parameters of the write data path are iteratively optimized.

[0090] In some embodiments, the drive strength of the NAND flash memory is first adjusted to:

[0091] ; wherein the change of the drive strength is denoted by , and the unit is ohm; and the error rate is denoted by BER.

[0092] After the drive strength of the NAND flash memory is adjusted, the termination resistance of the NAND flash memory is then adjusted to: ; wherein the change of the termination resistance of the NAND flash memory is denoted by , and the unit is ohm.

[0093] After the termination resistance of the NAND flash memory is adjusted, the change of the write delay clock of the controller of the solid state disk is finally adjusted to: ; wherein the change of the write delay clock of the controller of the solid state disk is denoted by , and the unit is picosecond.

[0094] In the embodiments of the present application, the increase of the drive strength of the NAND flash memory and the advance of the write clock form a synergistic effect, solving the problem of timing deterioration caused by signal enhancement. The embodiments of the present application enhance the drive strength of the NAND flash memory in a logarithmic relationship, solving the problem of insufficient driving capacity of the write data path; increase the termination resistance of the NAND flash memory in a linear proportion, and adjust the write delay clock of the controller of the solid state disk in a reverse logarithm, optimizing the data synchronization timing.

[0095] In step S105, second data is written to the NAND flash memory at the second frequency, and the second data is read from the NAND flash memory at the first frequency; if the second data is read incorrectly, it is determined that the read data path of the NAND flash memory is faulty.

[0096] In some embodiments, the first frequency can refer to the current fault frequency; for example, the error rate of the NAND flash memory is greater than a second threshold value (such as 10 -12), it is determined that the read data path of the current NAND flash memory is faulty, and the current frequency can be referred to as a faulty frequency. The first frequency can also be any verified faulty frequency, such as 2000 MHz. In an embodiment of the present application, the value of the faulty frequency is higher than the second frequency; the second frequency can also be referred to as a reference frequency, and the reference frequency is a frequency at which the read data path and the write data path of the NAND flash memory can normally work.

[0097] In an embodiment of the present application, the second data is written into the NAND flash memory at a low frequency (reference frequency) and read from the NAND flash memory at a high frequency (faulty frequency); if the error rate of reading the second data is greater than N times the error rate of writing the second data, it is determined that the read data path of the NAND flash memory is faulty. Wherein N can be 10, if the error rate of reading the second data is greater than 10 times the error rate of writing the second data, it is determined that the read data path of the NAND flash memory is faulty.

[0098] In step S106, if the read data path of the NAND flash memory is faulty, the termination resistance of the NAND flash memory, the reference voltage of the controller of the solid state disk, and the sampling delay of the controller of the solid state disk are sequentially adjusted based on the error rate of the NAND flash memory.

[0099] In some embodiments, if the read data path of the NAND flash memory is faulty, the flowchart for optimizing the read data path fault is as shown in Figure 3 : first, the termination resistance of the NAND flash memory is adjusted based on the error rate of the NAND flash memory, then the reference voltage of the controller of the solid state disk is adjusted based on the error rate of the NAND flash memory, and finally the sampling delay of the controller of the solid state disk is adjusted based on the error rate of the NAND flash memory. If the error rate of the NAND flash memory meets a preset value, a parameter combination is recorded, the parameter combination includes: the driving strength of the NAND flash memory, the reference voltage of the controller of the solid state disk, and the sampling delay of the controller of the solid state disk. If the error rate of the NAND flash memory does not meet the preset value, the parameters of the write data path are iteratively optimized.

[0100] In some embodiments, the termination resistance of the NAND flash memory is first adjusted to: ; wherein the change of the termination resistance of the NAND flash memory is represented by , and the error rate is represented by BER.

[0101] After adjusting the termination resistance of the NAND flash memory, the reference voltage change of the controller of the solid state disk is then adjusted to: ; wherein the reference voltage of the controller of the solid state disk is represented by , and T is the ambient temperature.

[0102] After the reference voltage of the controller of the solid state disk is adjusted, the sampling delay of the controller of the solid state disk is finally adjusted as: T is the ambient temperature.

[0103] In the embodiments of the present application, the item related to the error rate and the item related to the temperature are designed separately to avoid parameter conflicts.

[0104] In the embodiments of the present application, when adjusting the reference voltage of the controller of the solid state disk and the sampling delay of the controller of the solid state disk, the temperature compensation mechanism is introduced in combination with the change of the ambient temperature to synchronously offset the low-temperature timing contraction effect, so that the adjustment accuracy is higher.

[0105] In the embodiments of the present application, by writing data at a high frequency, reading data at a low frequency, or writing data at a low frequency and reading data at a high frequency, the write data path failure and the read data path failure can be independently judged.

[0106] In the embodiments of the present application, in the case that the error rate of the NAND flash memory is greater than the second threshold value, except that the error rate of the read data is greater than N times of the error rate of the write data and the error rate of the write data is greater than N times of the error rate of the read data, other cases are confirmed as the simultaneous occurrence of the write data path failure and the read data path failure.

[0107] It should be noted that in the embodiments of the present application, step S103 and step S105 can be executed simultaneously; or step S103 can be executed first, and then step S105 can be executed; or step S105 can be executed first, and then step S103 can be executed.

[0108] The overall processing flow of the channel parameter management method provided by the embodiments of the present application is shown in FIG. 1. Figure 4 As shown in FIG. 1, the overall processing flow of the channel parameter management method provided by the embodiments of the present application at least includes:

[0109] Step S201, the error rate of the NAND flash memory is monitored in real time.

[0110] Step S202, if the error rate exceeds the preset threshold value, frequency freezing is triggered.

[0111] The frequency freezing refers to that the running frequency of the channel between the solid state disk and the NAND flash memory is no longer changed.

[0112] Step S203, it is judged whether the read data path and the write data path fail; if any one of the read data path and the write data path fails, the channel parameter optimization of the failure path is performed.

[0113] The processing process of the channel parameter optimization of the read data path is the same as that of step S106; the processing process of the channel parameter optimization of the write data path is the same as that of step S104; and here, the details are not described again.

[0114] Step S204, judging whether the error rate of the NAND flash memory meets the threshold value; if the error rate of the NAND flash memory meets the threshold value, the configuration of the channel parameter is saved; if the error rate of the NAND flash memory does not meet the threshold value, the channel parameter optimization of the read data path and the channel parameter optimization of the write data path are continuously executed.

[0115] It should be noted that the read data path of the NAND flash memory or the write data path of the NAND flash memory involved in the embodiments of the present application can also be referred to as the read data path of the solid state disk or the write data path of the solid state disk.

[0116] Next, taking the write data path fault repair of a 2000MHZ enterprise-level SSD as an example, the working frequency is 2000MHZ, and the initial BER of the NAND flash memory is At a certain moment, the error rate of the write data path is detected to be , and the error rate of the read data path is . Since , the write data path fails and the channel parameter adjustment of the write data path is required:

[0117] 1) , the DS is improved from 0.8 ohm to 0.992 ohm.

[0118] 2) , the ODT is improved by 0.83 ohm.

[0119] 3) , the write delay clock of the controller of the solid state disk is reduced from 20 ps to 16.16 ps.

[0120] Through the adjustment of the channel parameter of the write data path, the error rate BER of the write data path is reduced to , the write speed is improved from 5 GB / s to 7.2 GB / s, and 1PB of continuous writing data has zero error.

[0121] Next, taking the write data path fault and read data path fault repair of a 1800MHZ enterprise-level SSD as an example, the working frequency is 1800MHZ, and the environmental temperature is 85 degrees Celsius; the initial BER of the NAND flash memory is At a certain moment, the error rate of the write data path is detected to be , and the error rate of the read data path is . Since , the write data path and the read data path both fail. The channel parameter adjustment of the write data path and the channel parameter adjustment of the read data path are required.

[0122] The channel parameter adjustment for the write data path includes:

[0123] 1) , so that the drive strength is increased by 0.272 ohms, to .

[0124] 2) , the terminal resistance of the NAND flash is increased by 5.2 ohms, to .

[0125] 3) , the write delay clock of the controller of the solid state disk is reduced from 22ps to 16.56ps, to .

[0126] The channel parameter adjustment for the read data path includes:

[0127] 1) Expand the sampling window:

[0128] ,

[0129] After increasing the temperature compensation: , so from 24ps to 18.04ps. to .

[0130] 2) Increase the reference voltage V of the controller of the solid state disk:

[0131] = 0.002V.

[0132] After increasing the temperature compensation: , so from 0.52V to 0.474V, to .

[0133] The channel parameter management device provided by the embodiment of the application, the component structure schematic diagram of the channel parameter management device is as shown in Figure 5 , comprising:

[0134] The monitoring module 501 is used for monitoring the error rate of the NAND flash memory;

[0135] The adjustment module 502 is used for adjusting the step length of frequency scanning according to the error rate of the NAND flash memory; the frequency is the operating frequency of the channel between the NAND flash memory and the solid state disk;

[0136] The processing module 503 is configured to write first data to the NAND flash at a first frequency and read the first data from the NAND flash at a second frequency; and determine that a write data path of the NAND flash is faulty if the first data is written incorrectly.

[0137] The adjusting module 502 is configured to sequentially adjust a drive strength of the NAND flash, a termination resistance of the NAND flash, and a write delay clock of a controller of the solid state disk based on a bit error rate of the NAND flash if the write data path of the NAND flash is faulty.

[0138] The processing module 503 is further configured to write second data to the NAND flash at the second frequency and read the second data from the NAND flash at the first frequency; and determine that a read data path of the NAND flash is faulty if the second data is read incorrectly.

[0139] The adjusting module 502 is further configured to sequentially adjust a termination resistance of the NAND flash, a reference voltage of the controller of the solid state disk, and a sampling delay of the controller of the solid state disk based on the bit error rate of the NAND flash if the read data path of the NAND flash is faulty.

[0140] In some embodiments, the adjusting module 502 is specifically configured to adjust a step length of frequency scanning to be a first value if the bit error rate of the NAND flash is less than or equal to a first threshold value.

[0141] If the bit error rate of the NAND flash is greater than the first threshold value and less than or equal to a second threshold value, the step length of the frequency scanning is adjusted to be exponentially attenuated.

[0142] If the bit error rate of the NAND flash is greater than the second threshold value, the step length of the frequency scanning is adjusted to be a second value.

[0143] In some embodiments, the adjusting module 502 is specifically configured to adjust the step length of the frequency scanning to be a product of the first value and a first index.

[0144] The base of the first index is a constant e, and the index is the bit error rate of the NAND flash divided by a third value.

[0145] In some embodiments, the processing module 503 is specifically configured to determine that the write data path of the NAND flash is faulty if a bit error rate of writing the first data is greater than M times a bit error rate of reading the first data.

[0146] In some embodiments, the adjusting module 502 is specifically configured to adjust the drive strength of the NAND flash ;

[0147] adjusting a termination resistance of the NAND flash ;

[0148] adjusting a write latency clock of a controller of the solid state drive ;

[0149] wherein, is a bit error rate.

[0150] In some embodiments, the processing module 503 is specifically configured to determine that a read data path of the NAND flash is faulty if the bit error rate of reading the second data is greater than N times of the bit error rate of writing the second data.

[0151] In some embodiments, the adjusting module 502 is specifically configured to adjust a termination resistance of the NAND flash ;

[0152] adjusting a reference voltage of a controller of the solid state drive ;

[0153] adjusting a sampling delay of a controller of the solid state drive , T is an ambient temperature, is a bit error rate.

[0154] In some embodiments, the monitoring module 501 is specifically configured to calculate a ratio of a number of error bits to a number of transmission bits every 1 millisecond to obtain the bit error rate of the NAND flash.

[0155] Embodiments of the present application also provide an electronic device, a structural schematic diagram of the electronic device is shown in Figure 6 , and the electronic device includes a processor 410 and a memory 450 connected with the processor 410 in communication, and the electronic device further includes a bus 440; each module in the electronic device is coupled together through the bus 440. Wherein, the processor core can include multiple processor cores, such as the first processor core and the second processor core in the above embodiments. It can be understood that the bus 440 is used to realize the connection and communication between the modules. The bus 440 includes not only a data bus, but also a power bus, a control bus and a state signal bus. However, in order to clearly illustrate, all kinds of buses are marked as the bus 440 in Figure 6 .

[0156] The processor 410 has a signal processing capability, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware models, etc. Wherein, the general-purpose processor can be a microprocessor or any conventional processor.

[0157] The memory 450 stores executable instructions for implementing the cache coherency processing method provided by the embodiments of the present application. The memory 450 can be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memories, hard disk drives, optical disk drives, and the like. The memory 450 optionally includes one or more storage devices physically removed from the processor 410.

[0158] In some embodiments, the memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or a subset or superset thereof.

[0159] In some embodiments, the electronic device can further include:

[0160] An operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks;

[0161] A network communication module 452 for reaching other computing devices via one or more (wired or wireless) network interfaces 420, exemplary network interfaces 420 including Bluetooth, Wireless Fidelity (WiFi), and Universal Serial Bus (USB), and the like.

[0162] The embodiments of the present application provide a computer-readable storage medium storing executable instructions, wherein the executable instructions, when executed by a processor, will trigger the processor to execute the management method of the interrupt controller provided by the embodiments of the present application, for example, as shown in the channel parameter management method. Figures 1 to 4 The channel parameter management method.

[0163] In some embodiments, the computer-readable storage medium can be a Ferroelectric RAM (FRAM), a Read-Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a CD-ROM, and the like memory; it can also be various devices including one or any combination of the above memories.

[0164] In some embodiments, executable instructions can take the form of programs, software, software modules, scripts, or code, written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and they can be deployed in any form, including as a stand-alone program or as a module, model, subroutine, or other unit suitable for use in a computing environment.

[0165] By way of example, executable instructions can be deployed in one computing device or across multiple computing devices located in one site or distributed across multiple sites and interconnected by a communication network.

[0166] Embodiments of the present application provide a computer program product, which comprises computer programs / instructions, and the computer programs / instructions, when executed by a processor, implement the management method of the interrupt controller.

[0167] The above merely provides an example of the embodiments of the present application, but is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, and improvement within the spirit and scope of the present application shall be included in the protection scope of the present application.

Claims

1. A channel parameter management method, characterized in that, The method includes: Monitor the bit error rate of NAND flash memory; The step size of the frequency scan is adjusted according to the bit error rate of the NAND flash memory; the frequency is the operating frequency of the path between the NAND flash memory and the solid-state drive. Write first data to the NAND flash memory at a first frequency, and read the first data from the NAND flash memory at a second frequency; if the writing of the first data is incorrect, then the write data path of the NAND flash memory is determined to be faulty. If the write data path of the NAND flash memory fails, the drive strength of the NAND flash memory, the termination resistance of the NAND flash memory, and the write latency clock of the solid-state drive controller are adjusted sequentially based on the bit error rate of the NAND flash memory. Write second data to the NAND flash memory at the second frequency, and read the second data from the NAND flash memory at the first frequency; if the second data is read incorrectly, then determine that the read data path of the NAND flash memory is faulty; If the read data path of the NAND flash memory fails, the termination resistor of the NAND flash memory, the reference voltage of the solid-state drive controller, and the sampling delay of the solid-state drive controller are adjusted sequentially based on the bit error rate of the NAND flash memory. The step of adjusting the frequency scan step size according to the bit error rate of the NAND flash memory includes: If the bit error rate of the NAND flash memory is less than or equal to a first threshold, the step size of the frequency scan is adjusted to a first value; if the bit error rate of the NAND flash memory is greater than the first threshold and less than or equal to a second threshold, the step size of the frequency scan is adjusted to decrease exponentially; if the bit error rate of the NAND flash memory is greater than the second threshold, the step size of the frequency scan is adjusted to a second value. The step of adjusting the drive strength of the NAND flash memory, the termination resistance of the NAND flash memory, and the write latency clock of the solid-state drive controller based on the bit error rate of the NAND flash memory includes: Adjusting the drive strength of the NAND flash memory ; Adjust the termination resistance of the NAND flash memory ; Adjust the write latency clock of the solid-state drive controller ; The step of sequentially adjusting the termination resistance of the NAND flash memory, the reference voltage of the solid-state drive controller, and the sampling delay of the solid-state drive controller based on the bit error rate of the NAND flash memory includes: Adjust the termination resistance of the NAND flash memory ; Adjust the reference voltage of the solid-state drive controller ; Adjust the sampling delay of the solid-state drive controller T represents the ambient temperature. This refers to the bit error rate.

2. The method according to claim 1, characterized in that, The adjustment of the frequency scan step size by exponential decay includes: The step size of the frequency scan is adjusted to be equal to the product of the first value and the first exponent; Wherein, the base of the first exponent is a constant e, and the exponent is the bit error rate of the NAND flash memory divided by the third value.

3. The method according to claim 1, characterized in that, If an error occurs while writing the first data, determining that the NAND flash memory has a write path failure includes: If the bit error rate of writing the first data is greater than M times the bit error rate of reading the first data, then the write data path of the NAND flash memory is determined to be faulty.

4. The method according to claim 1, characterized in that, If an error occurs while reading the second data, the step of determining a read data path failure in the NAND flash memory includes: If the bit error rate of reading the second data is greater than N times the bit error rate of writing the second data, then the read data path of the NAND flash memory is determined to be faulty.

5. The method according to any one of claims 1 to 4, characterized in that, The monitored bit error rate of NAND flash memory includes: The hardware accelerator calculates the ratio of the number of error bits to the number of transmitted bits in 1-millisecond intervals to obtain the bit error rate of the NAND flash memory.

6. A channel parameter management device, characterized in that, The channel parameter management device includes: The monitoring module is used to monitor the bit error rate of NAND flash memory; An adjustment module is used to adjust the step size of the frequency scan according to the bit error rate of the NAND flash memory; the frequency is the operating frequency of the path between the NAND flash memory and the solid-state drive. The processing module is configured to write first data to the NAND flash memory at a first frequency and read the first data from the NAND flash memory at a second frequency; if an error occurs in writing the first data, the write data path of the NAND flash memory is determined to be faulty. An adjustment module is used to adjust the drive strength of the NAND flash memory, the termination resistance of the NAND flash memory, and the write latency clock of the solid-state drive controller in sequence based on the bit error rate of the NAND flash memory if the write data path of the NAND flash memory fails. The processing module is further configured to write second data to the NAND flash memory at the second frequency and read the second data from the NAND flash memory at the first frequency; if an error occurs when reading the second data, the read data path of the NAND flash memory is determined to be faulty. The adjustment module is also used to adjust the termination resistor of the NAND flash memory, the reference voltage of the solid-state drive controller, and the sampling delay of the solid-state drive controller in sequence based on the bit error rate of the NAND flash memory if the read data path of the NAND flash memory fails. Specifically, the adjustment module is used to adjust the frequency scanning step size to a first value if the bit error rate of the NAND flash memory is less than or equal to a first threshold; adjust the frequency scanning step size exponentially if the bit error rate of the NAND flash memory is greater than the first threshold and less than or equal to a second threshold; and adjust the frequency scanning step size to a second value if the bit error rate of the NAND flash memory is greater than the second threshold. The adjustment module is specifically used to adjust the drive strength of the NAND flash memory. Adjust the termination resistor of the NAND flash memory. Adjust the write latency clock of the solid-state drive controller. ; The adjustment module is also specifically used to adjust the termination resistance of the NAND flash memory. Adjust the reference voltage of the solid-state drive controller. Adjust the sampling delay of the solid-state drive's controller. T represents the ambient temperature. This refers to the bit error rate.

7. The channel parameter management device according to claim 6, characterized in that, The adjustment module is specifically used to adjust the step size of the frequency scan to be equal to the product of the first value and the first exponent; Wherein, the base of the first exponent is a constant e, and the exponent is the bit error rate of the NAND flash memory divided by the third value.

8. The channel parameter management device according to claim 6, characterized in that, The processing module is specifically configured to determine that the NAND flash memory has a write data path failure if the bit error rate of writing the first data is greater than M times the bit error rate of reading the first data.

9. The channel parameter management device according to claim 6, characterized in that, The processing module is specifically used to determine that the read data path of the NAND flash memory is faulty if the bit error rate of reading the second data is greater than N times the bit error rate of writing the second data.

10. The channel parameter management device according to any one of claims 6 to 9, characterized in that, The monitoring module is specifically used to calculate the ratio of the number of error bits to the number of transmitted bits in a 1-millisecond period to obtain the bit error rate of the NAND flash memory.

11. An electronic device, characterized in that, include: A processor and a memory communicatively connected to the processor, the memory storing instructions that, when executed by the processor, enable the electronic device to perform the channel parameter management method according to any one of claims 1 to 5.

12. A computer-readable storage medium, characterized in that, It stores executable instructions for implementing the channel parameter management method according to any one of claims 1 to 5 when executed by a processor.

13. A computer program product, characterized in that, The computer program product includes a computer program / instruction, which, when executed by a processor, implements the channel parameter management method according to any one of claims 1 to 5.

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