Method and device for managing instructions, electronic device and storage medium

Abstract

At least one embodiment of the invention provides an instruction management method and device, an electronic device and a storage medium. The method for managing the instruction comprises the following steps: in response to a received target operation request for target equipment, obtaining a first type of instruction for operating the target equipment from a storage array; a hardware logic module outside the storage array generates a second type instruction used for operating the target equipment; inserting the second type of instructions into an instruction stream formed by the first type of instructions; and sending the instruction stream to the target device. According to the instruction management method, when the first type instruction and the second type instruction are needed for operating the target equipment, the storage array can only store the first type instruction, storage resources of the storage array are saved, and the chip area is saved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to methods and apparatus for managing instructions, memory controllers, electronic devices, and storage media. Background Technology

[0002] Computer systems can interact with various target devices (such as memory, network interfaces, or other external devices) through instructions. For example, instructions issued by a computer system can control read and write operations on memory, enabling data to be stored or retrieved efficiently. Similarly, instructions issued by a computer system can manipulate network interfaces to facilitate data transfer between the computer and external networks. This instruction-driven interaction mechanism allows computers to effectively manage target devices, thereby enabling complex operations and data processing. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a method for managing instructions, comprising: in response to receiving a target operation request for a target device, obtaining a first type of instruction for operating the target device from a storage array; generating a second type of instruction for operating the target device from a hardware logic module outside the storage array; inserting the second type of instruction into an instruction stream formed by the first type of instruction; and sending the instruction stream to the target device.

[0004] At least one embodiment of this disclosure provides an apparatus for managing instructions, including a first type instruction acquisition module, a hardware logic module, a storage array, an instruction insertion module, and an instruction sending module. The first type instruction acquisition module is configured to: acquire a first type instruction for operating the target device from the storage array in response to receiving a target operation request for the target device; the hardware logic module is configured to: generate a second type instruction for operating the target device; the instruction insertion module is configured to: insert the second type instruction into the instruction stream formed by the first type instruction; and the instruction sending module is configured to: send the instruction stream to the target device.

[0005] At least one embodiment of this disclosure provides a memory controller, including: means for managing instructions as described above, wherein the target device is a double data rate memory, the first type of instructions are functional instructions related to the power consumption configuration of the double data rate memory, the second type of instructions are refresh instructions for refreshing the double data rate memory, and the target operation request is a power conversion request.

[0006] At least one embodiment of this disclosure provides an electronic device, including: at least one processor; at least one memory storing instructions thereon, wherein, when executed by the at least one processor, the instructions cause the at least one processor to perform the method for managing instructions as described above.

[0007] At least one embodiment of this disclosure provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein, when executed by a processor, the computer-readable instructions cause the processor to perform the method for managing instructions as described above. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Clearly, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure.

[0009] Figure 1 An exemplary storage array is shown;

[0010] Figure 2 A flowchart of a method for managing instructions according to at least one embodiment of the present disclosure is shown;

[0011] Figure 3 A schematic diagram of an apparatus for managing instructions according to at least one embodiment of the present disclosure is shown;

[0012] Figure 4 A schematic diagram of a memory controller according to at least one embodiment of the present disclosure is shown;

[0013] Figure 5 A schematic diagram illustrating an example application scenario according to at least one embodiment of the present disclosure is shown;

[0014] Figure 6 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0015] Figure 7 A schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure is shown;

[0016] Figure 8 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0017] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0018] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0020] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0021] This disclosure uses flowcharts to illustrate the operations performed by a system according to embodiments of this disclosure. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0022] First, the abbreviations and related terms involved in this disclosure are defined and explained.

[0023] DDR (Double Data Rate): A technology used in computer memory that transmits data on both the rising and falling edges of the clock.

[0024] DRAM (Dynamic Random Access Memory): Dynamic random access memory.

[0025] SDRAM (Synchronous Dynamic Random Access Memory): SDRAM is an evolution of DRAM and can be considered a type of DRAM. SDRAM operates synchronously with the CPU's clock signal. In each clock cycle, the CPU issues a clock signal, and the SDRAM responds on the rising or falling edge of this clock signal to read or write data. Common types of SDRAM include SDR SDRAM and DDR SDRAM. DDR SDRAM (Double Data Rate SDRAM) has a data transfer rate twice that of SDR SDRAM.

[0026] SRE (Self-Refresh Entry): Enters by refreshing the page.

[0027] SRX: (Self-Refresh Exit) - Exit by refreshing.

[0028] BANK: A memory bank, consisting of multiple storage units.

[0029] RANK: A memory queue, often consisting of a group of BANKs, allowing read and write operations to be performed on the same RANK at the same time.

[0030] REF: Refresh.

[0031] REFAB (All Bank Refresh): A single refresh operation completes all storage units in a RANK.

[0032] REFSB (Same Bank Refresh): A single refresh operation completes the same bank number across different bank groups within a RANK.

[0033] 3DS (Three-Dimensional Stacking): also known as three-dimensional stacking or multi-layer stacking structure, is an advanced semiconductor packaging technology widely used in memory modules (such as DRAM) and other integrated circuits (ICs). Its core concept is to improve integration, performance, and save space by stacking multiple chips or layers together, while reducing power consumption.

[0034] CS: Physical RANK, a concept found in DDR. Logical RANK is a concept within the 3DS stacked chips. For example, a physical RANK contains up to 8 logical RANKs. A single CPU access will select a physical RANK via the chip select signal CS, and within the 3DS stacked structure, a logical RANK within that physical RANK will be selected via the chip identifier (CID) to obtain, for example, 64 bits of data.

[0035] PHY (Physical Layer Interface): Physical layer interface.

[0036] TRANING: Training.

[0037] PDA (Per DRAM Access): Per DRAM accessibility refers to the number of accesses or access efficiency to, for example, a single DRAM memory cell or chip.

[0038] It is understood that the terms defined above are merely exemplary definitions for specific application scenarios to better understand this disclosure, and this disclosure is not limited thereto. For example, the various terms described above for memory can be mapped or extended to other types of memory.

[0039] A processor in a computer system can access target devices (such as memory, network interfaces, or other target devices) within or outside the computer system through instructions, thereby managing and using the target devices. In some cases, operations on a target device often require the coordinated execution of multiple instructions or multiple types of instructions. For example, it is important to send instructions containing multiple instructions or multiple types of instructions to the target device in an appropriate order to achieve the desired operation or function of the target device.

[0040] For example, the following description uses an application scenario of power conversion or power conversion operation for DDR SDRAM as an example; of course, the embodiments of this disclosure are not limited thereto. In the application scenario of power conversion operation for DDR SDRAM, DDR SDRAM is the target device, and multiple types of instructions, including functional instructions related to the power configuration of DDR SDRAM and refresh instructions for refreshing DDR SDRAM, are described as an example.

[0041] For example, DDR SDRAM, used as the main memory of a computer system, can support various low-power modes for low-power operation and improved performance. A DDR controller system includes a DDR controller, a PHY, and DDR chips. The DDR controller system is designed to support various DDR frequencies and low-power state transitions. The DDR controller can receive low-power request signals as input and outputs for memory operations. Each frequency or low-power state corresponds to a different configuration, and the DDR controller can pre-store the required chip configurations using a memory array. For example, the memory array can include multiple entries, each containing multiple coded fields. During low-power operation, the hardware automatically reads at least one entry stored in the memory array, converts it into the corresponding coded output, and sends it to the DRAM.

[0042] During DRAM configuration, in addition to low-power related configuration instructions (referred to as functional instructions), REF instructions need to be periodically inserted to maintain the current data in the DRAM. For example, when power conversion is achieved through frequency conversion, each frequency point corresponds to a unique set of PHY TRAINING configuration parameters (e.g., data / instruction line latency, DRAM read / write frequency, voltage, etc.). This requires many functional instructions or their descriptions (e.g., memory read / write instructions (MRW), frequency values, latency values, etc.) to be stored in the memory array. Therefore, when executing the entries corresponding to each frequency point in the memory array, the execution state of the memory array with PHY TRAINING parameters takes longer, requiring more REF instructions to maintain the data.

[0043] During the process of the DDR controller accessing the memory array and generating functional instructions in a non-SRE state (i.e., non-self-refreshing DDR state), refresh instructions need to be manually generated by software.

[0044] Figure 1 An exemplary storage array is shown.

[0045] like Figure 1 As shown, the memory array is illustrated as including memory array 1 and memory array 2. Memory array 1 and memory array 2 store a first type of instruction and a second type of instruction for operating the target device. For example, in an application scenario involving power conversion operations for DDR SDRAM, the first type of instruction could be a functional instruction related to the power configuration of the DDR SDRAM, such as... Figure 1 The diagram shows functional instructions 1, 2, 3, and 4, etc., while the second type of instruction can be a refresh instruction used to refresh DDR SDRAM, for example... Figure 1 The REF instruction in [the context of the text].

[0046] The inventors of this disclosure have discovered that storing first-type instructions and second-type instructions via a memory array is inefficient. For example, see... Figure 1 Software methods require the storage space of the memory array to store REF instructions, which consumes the memory array's storage resources. For example, manually controlling the insertion of REF instructions during memory array execution necessitates constant adjustments to the order of REF instructions and other functional instructions under varying power consumption, which is unfriendly to software. Furthermore, manual control methods cannot precisely control the interval between sent instructions, such as the interval between two adjacent instructions in the memory array. Additionally, in some 3DS stacked packages, such as an 8H structure with 4 CSs in a single channel, where 8H corresponds to 8 logical RANKs, each logical RANK needs to be refreshed separately. Each RANK requires at least one refresh instruction, resulting in 4*8 instructions per refresh. A large number of refresh instructions can overwhelm the memory array, and expanding the memory array would increase the chip area.

[0047] At least one embodiment of the present invention provides a method and apparatus for managing instructions, an electronic device, and a storage medium. A hardware logic module outside a storage array, from which first-type instructions for operating a target device can be obtained, generates second-type instructions for operating the target device. An instruction stream including both first-type and second-type instructions is then sent to the target device to achieve a target operation. Thus, the storage array stores only the first-type instructions, rather than both, thereby saving storage resources and chip area.

[0048] Figure 2 A flowchart of a method for managing instructions according to at least one embodiment of the present disclosure is shown. Figure 3 A schematic diagram of an apparatus for managing instructions according to at least one embodiment of the present disclosure is shown.

[0049] See Figure 2 The method 200 for managing instructions and its additional aspects described herein can be found below. Figure 3 The described means of implementing management instructions, electronic devices, hardware structures, software structures, or a combination of hardware and software structures.

[0050] See Figure 2 The method 200 for managing instructions includes steps S210, S220, S230 and S240.

[0051] In step S210, in response to receiving a target operation request for the target device, a first type of instruction for operating the target device is obtained from the storage array.

[0052] The target device can be any device on which a target operation is performed via instructions. For example, the target device may include memory, a network interface, etc. A target operation request can be a request to operate the target device to achieve a certain function and / or to manage the target device. A target operation request can be represented as data and / or instructions.

[0053] For example, a storage array can be a collection of storage units used to store data.

[0054] In some embodiments, the storage array may directly store one or more first-type instructions. In some embodiments, the storage array may store encoded information of one or more first-type instructions, and the encoded information may be decoded into the corresponding first-type instructions.

[0055] In step S220, a second type of instruction for operating the target device is generated by the hardware logic module outside the storage array.

[0056] The hardware logic module can be a hardware component, such as a circuit component, that can be used to generate a second type of instruction for operating the target device, and may include, for example, digital circuits and / or logic circuits.

[0057] In step S230, the second type of instruction is inserted into the instruction stream formed by the first type of instruction.

[0058] Since implementing the corresponding target operation in response to the target operation request of the target device requires at least first type instructions and second type instructions, the insertion operation can form an instruction stream including first type instructions and second type instructions. In some embodiments, for example, depending on the timing of the operation on the target device and / or the different target operation requests, the first type instructions and second type instructions may each include one or more instructions.

[0059] In step S240, the instruction stream is sent to the target device.

[0060] For example, the instruction stream here may include first-type instructions and second-type instructions, which can be executed by the target device to achieve the target operation corresponding to the target operation request.

[0061] As described above, the method for managing instructions according to at least one embodiment of this disclosure generates a second type of instruction for operating the target device through a hardware logic module outside the memory array from which a first type of instruction for operating the target device can be obtained, thereby sending an instruction stream including the first type of instruction and the second type of instruction to the target device to achieve the target operation for the target device. Thus, the memory array only stores the first type of instruction instead of both the first type of instruction and the second type of instruction, saving memory array resources and chip area.

[0062] Additional aspects of a method for managing instructions according to another embodiment of this disclosure are described below.

[0063] For example, according to at least one embodiment of the present disclosure, the method for managing instructions, in which a hardware logic module outside the storage array generates a second type of instruction for operating a target device, may include: generating a second type of instruction in response to a preset time elapsed after the target device exits the execution of the second type of instruction; and inserting the second type of instruction into the instruction stream formed by the first type of instruction, including: in response to the generation of the second type of instruction, inserting the second type of instruction before the first type of instruction currently transmitted from the storage array in the instruction stream.

[0064] The inventors of this disclosure, through further research, have found that it may be necessary to insert second-type instructions into the instruction stream formed by first-type instructions at appropriate times to ensure that the order of the first-type and second-type instructions in the instruction stream achieves the corresponding target operation for the target device, for example, when the second-type instructions need to be re-executed after a preset time following their initial execution. For instance, in an application scenario involving power conversion operations for DDR SDRAM, it is necessary to issue a refresh instruction (an example of a second-type instruction) every preset time to refresh the DDR SDRAM and maintain data.

[0065] Therefore, the method for managing instructions according to at least one embodiment of the present disclosure can generate a second type of instruction at an appropriate time and insert it into the instruction stream through a hardware logic module, which is suitable for application scenarios that require the execution of a first type of instruction at a preset time.

[0066] For example, according to at least one embodiment of the method for managing instructions, generating a second type of instruction for operating a target device by a hardware logic module outside the storage array may include: generating a second type of instruction; and inserting the second type of instruction into an instruction stream formed by a first type of instruction, including: in response to a preset time elapsed after the target device exits the execution of the second type of instruction, inserting the second type of instruction into the instruction stream before the first type of instruction currently transmitted from the storage array.

[0067] For example, when both a first type of instruction and a second type of instruction are received simultaneously, the first type of instruction can be transmitted first and then the second type of instruction, thus placing the second type of instruction before the first type of instruction in the instruction stream.

[0068] Compared to the above-described method of generating and inserting a second type of instruction into the instruction stream at an appropriate time, in this embodiment, one or more second type of instructions can be pre-generated by a hardware logic module, and the second type of instructions can be inserted into the instruction stream at a preset time. Therefore, the method for managing instructions according to at least one embodiment of this disclosure is also applicable to application scenarios where a first type of instruction needs to be executed at a preset time. Compared to the above embodiments, this embodiment requires an additional caching unit (e.g., a first-in-first-out (FIFO) caching unit) to cache the pre-generated second type of instructions, but omits the logic of the hardware logic module determining when the execution of the second type of instruction by the target device reaches the preset time.

[0069] For example, according to at least one embodiment of the present disclosure, the method for managing instructions, in response to the generation of a second type of instruction, inserting the second type of instruction before the currently transmitted first type of instruction from the memory array in the instruction stream may include: in response to the number of second type instructions being generated reaching a threshold, inserting all of that number of second type instructions before the currently transmitted first type of instruction from the memory array in the instruction stream.

[0070] Thus, the method for managing instructions according to at least one embodiment of this disclosure can support the setting of a threshold, by comparing the number of second-type instructions generated with the threshold to insert all of that number of second-type instructions into the instruction stream. For example, this embodiment can support a shortage of a predetermined number (e.g., 5 or other values) of second-type instructions, which can be replenished in a subsequent process. This is suitable for the bundled transmission of a predetermined number of second-type instructions, reducing the number of times second-type instructions are inserted into the instruction stream and thus reducing overhead.

[0071] For example, the method for managing instructions according to at least one embodiment of the present disclosure may further include: in response to receiving a target operation request for a target device, determining the operation state of the target device, wherein the operation state includes the target device exiting the execution of a second type of instruction.

[0072] Thus, the method for managing instructions according to at least one embodiment of the present disclosure can support the determination of the operating state of the target device in order to monitor the state of the target device exiting the execution of the second type of instruction, for example, it can facilitate the determination of the time when the target device exits the execution of the second type of instruction.

[0073] For example, in the method for managing instructions according to at least one embodiment of the present disclosure, the preset time can be a preset time interval, and generating the second type instruction in response to the target device exiting the execution of the second type instruction reaching the preset time may include: timing the exit time in response to the target device exiting the execution of the second type instruction; and generating the second type instruction in response to the timing reaching the preset time interval.

[0074] The inventors of this disclosure, through research, have found that in application scenarios such as power conversion operations for DDR SDRAM or other application scenarios, refresh instructions, as second-type instructions, are generally periodic, i.e., they need to be executed at predetermined time intervals. In at least one embodiment, the time when the target device exits the execution of the second-type instruction can be timed, for example, by a timer, to determine whether the target device has reached a preset time to exit the execution of the second-type instruction.

[0075] Thus, the method for managing instructions according to at least one embodiment of the present disclosure can be applied to application scenarios that require the periodic execution of second-type instructions at preset time intervals.

[0076] For example, according to at least one embodiment of the method for managing instructions, generating a second type of instruction in response to a preset time interval being reached may include: generating and sending an instruction generation request in response to a preset time interval corresponding to a target mode among a plurality of modes being reached; and generating a corresponding instruction in the target mode as a second type of instruction in response to receiving the instruction generation request.

[0077] Thus, the method for managing instructions according to at least one embodiment of this disclosure can support multiple modes of the entire system involving instructions. Since different modes can have different preset time intervals, the method for managing instructions according to at least one embodiment of this disclosure can be applied to different operating conditions or application scenarios.

[0078] For example, the method for managing instructions according to at least one embodiment of the present disclosure may further include: obtaining pre-configured second type of instruction configuration information to select a target mode from a plurality of modes.

[0079] Thus, the method for managing instructions according to at least one embodiment of the present disclosure can select a target mode from multiple modes in a pre-configured manner, supporting on-demand configuration of the target mode.

[0080] For example, according to at least one embodiment of the method for managing instructions, sending an instruction stream to a target device may include: sending the instruction stream to the target device with predetermined timing control.

[0081] The inventors of this disclosure have found through research that precise control of the timing of instruction transmission (e.g., the timing interval between two adjacent instructions in a memory array) is advantageous. For example, an appropriate timing interval can ensure the smooth execution of instructions, avoiding instruction conflicts or data errors caused by inaccurate timing, thereby improving system execution efficiency. Furthermore, multiple instructions may access shared resources simultaneously; if the timing interval is inaccurate, it may lead to data contention and inconsistency, affecting data integrity. Therefore, an appropriate timing interval can ensure data integrity.

[0082] Thus, the method for managing instructions according to at least one embodiment of the present disclosure can support sending instruction streams to target devices with predetermined timing control, ensuring the effectiveness of instruction execution and the integrity of data, thereby improving system performance.

[0083] For example, a method for managing instructions according to at least one embodiment of the present disclosure, which sends an instruction stream to a target device with predetermined timing control, may include: sending adjacent instructions to the target device with corresponding timing based on combinations between adjacent instructions in the instruction stream.

[0084] In some embodiments, the combination of adjacent instructions can be a combination of a first type of instruction and a second type of instruction (e.g., Figure 1 (A combination of adjacent functional instructions and REF instructions), or a combination of two subtype instructions or two instructions from the first type and / or the second type (e.g., Figure 1 The combination of adjacent functional instructions 1 and functional instruction 2 in the code. Additionally or alternatively, the combination of adjacent instructions may include more than two types of instructions or more than two instructions (such as...). Figure 1 (The combination of adjacent functional instructions 1, functional instructions 2, and REF instructions). Different adjacent instructions can correspond to different timing sequences. Therefore, once the adjacent instructions to be sent to the target device are determined, they can be sent to the target device for execution based on the timing sequence corresponding to the adjacent instructions.

[0085] Thus, the method for managing instructions according to at least one embodiment of the present disclosure can improve system performance by supporting the effectiveness of instruction execution and the integrity of data through preset combinations of adjacent instructions and their corresponding timing.

[0086] For example, the method for managing instructions according to at least one embodiment of the present disclosure may further include: obtaining pre-configured timing configuration information to generate and store combinations of adjacent instructions in the instruction stream and their corresponding timing.

[0087] Thus, the method for managing instructions according to at least one embodiment of the present disclosure can support the combination of adjacent instructions and the pre-configuration and storage of their corresponding timings, and the corresponding timings can be reused when subsequent adjacent instructions are sent, thereby improving the utilization efficiency of timing information.

[0088] For example, in a method for managing instructions according to at least one embodiment of the present disclosure, the storage array may store one or more extended instruction information, wherein each extended instruction information can be decoded into a plurality of second-type instructions.

[0089] Thus, the method for managing instructions according to at least one embodiment of this disclosure can facilitate the generation of multiple second-type instructions with less storage space, i.e., it supports instruction extension functionality and effectively saves storage space of the storage array. For example, the method for managing instructions according to at least one embodiment of this disclosure can be applied to application scenarios where second-type instructions are generated based on the storage array when there are few second-type instructions required.

[0090] For example, according to at least one embodiment of the method for managing instructions in this disclosure, the target device may be a double data rate memory, the first type of instruction may be a functional instruction related to the power consumption configuration of the double data rate memory, the second type of instruction may be a refresh instruction for refreshing the double data rate memory, and the target operation request may be a power conversion request.

[0091] Of course, the embodiments disclosed herein are not limited thereto. For example, depending on the target device and / or the target operation request, the first type of instructions and the second type of instructions may be changed accordingly. As another example, the double data rate memory may be extended to other types of memory.

[0092] Thus, the method for managing instructions according to at least one embodiment of this disclosure can be applied to application scenarios involving power conversion of double data rate memory.

[0093] For example, according to at least one embodiment of the method for managing instructions in this disclosure, a power conversion request may include at least one of the following requests: a conversion frequency request, a light sleep request, and a deep sleep request.

[0094] Thus, the method for managing instructions according to at least one embodiment of this disclosure can be applied to application scenarios such as specific switching frequencies, shallow sleep and / or deep sleep operations under power conversion of double data rate memory.

[0095] Of course, the embodiments disclosed herein are not limited thereto, and power conversion requests may also include other requests, as long as they involve the conversion of power consumption of the target device.

[0096] Corresponding to the method 200 for managing instructions according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides an apparatus for managing instructions.

[0097] See Figure 3 The apparatus 300 for managing instructions includes: a first type instruction fetching module 310, a hardware logic module 320, a storage array 330, an instruction insertion module 340, and an instruction sending module 350. The description of the apparatus 300 may be at least partially referenced to the description of the method for managing instructions described above.

[0098] The first type instruction acquisition module 310 is configured to: in response to receiving a target operation request for a target device, acquire a first type instruction for operating the target device from the storage array 330.

[0099] Hardware logic module 320 is configured to generate a second type of instruction for operating the target device.

[0100] The instruction insertion module 340 is configured to insert a second type of instruction into the instruction stream formed by the first type of instruction.

[0101] The instruction sending module 350 is configured to send an instruction stream to the target device.

[0102] As described above, the apparatus for managing instructions according to at least one embodiment of this disclosure generates a second type of instruction for operating the target device through a hardware logic module outside the memory array from which a first type of instruction for operating the target device can be obtained, thereby sending an instruction stream including the first type of instruction and the second type of instruction to the target device to achieve the target operation for the target device. Thus, the memory array only stores the first type of instruction instead of both the first type of instruction and the second type of instruction, saving memory resources and chip area.

[0103] The following describes exemplary additional aspects of an apparatus for managing instructions according to another embodiment of the present disclosure.

[0104] For example, in the apparatus for managing instructions according to at least one embodiment of the present disclosure, the hardware logic module may be further configured to: generate a second type instruction in response to a preset time elapsed after the target device exits the execution of the second type instruction; and the insertion module includes: an arbitration logic module configured to: insert the second type instruction before the first type instruction currently being transmitted from the memory array in the instruction stream in response to the generation of the second type instruction.

[0105] For example, in the apparatus for managing instructions according to at least one embodiment of the present disclosure, the hardware logic module may be further configured to: generate a second type of instruction; and the insertion module includes: an arbitration logic module, which may be configured to: insert the second type of instruction before the first type of instruction currently being transmitted from the memory array in the instruction stream in response to a preset time elapsed after the target device exits the execution of the second type of instruction.

[0106] For example, in an apparatus for managing instructions according to at least one embodiment of the present disclosure, the arbitration logic module may be further configured to include: in response to a threshold number of second type instructions being generated, inserting all of the second type instructions into the instruction stream before the first type instructions currently being transmitted from the memory array.

[0107] For example, an apparatus for managing instructions according to at least one embodiment of the present disclosure may further include: a power conversion module configured to: determine the operating state of the target device in response to receiving a target operation request for the target device, wherein the operating state includes the target device exiting the execution of a second type of instruction.

[0108] For example, in the apparatus for managing instructions according to at least one embodiment of the present disclosure, the preset time can be a preset time interval, and the hardware logic module can include: a timing module configured to: time the exit time in response to the target device exiting the execution of the second type of instruction; and a second type of instruction generation module configured to: generate a second type of instruction in response to the timing reaching the preset time interval.

[0109] For example, in the apparatus for managing instructions according to at least one embodiment of the present disclosure, the timing module may be further configured to: generate and send an instruction generation request in response to the timing reaching a preset time interval corresponding to a target mode among a plurality of modes; and the second type instruction generation module may be further configured to: generate a corresponding instruction in the target mode as a second type instruction in response to receiving the instruction generation request.

[0110] For example, an apparatus for managing instructions according to at least one embodiment of the present disclosure may further include: a mode selection module configured to: acquire pre-configured second type instruction configuration information to select a target mode from a plurality of modes.

[0111] For example, in the apparatus for managing instructions according to at least one embodiment of the present disclosure, the instruction sending module may be further configured to send the instruction stream to the target device with predetermined timing control.

[0112] For example, the apparatus for managing instructions according to at least one embodiment of the present disclosure may further include: a timing control module configured to: store combinations of adjacent instructions in an instruction stream and their corresponding timing, wherein the instruction sending module is further configured to: send adjacent instructions to a target device based on the combinations of adjacent instructions in the instruction stream and their corresponding timing.

[0113] For example, in the apparatus for managing instructions according to at least one embodiment of the present disclosure, the timing control module may be further configured to: acquire pre-configured timing configuration information to generate and store combinations of adjacent instructions in the instruction stream and their corresponding timing.

[0114] For example, in a device for managing instructions according to at least one embodiment of the present disclosure, the storage array may store one or more extended instruction information, wherein each extended instruction information can be decoded into a plurality of second type instructions.

[0115] For example, in the apparatus for managing instructions according to at least one embodiment of the present disclosure, the target device may be a double data rate memory, the first type of instruction may be a functional instruction related to the power consumption configuration of the double data rate memory, the second type of instruction may be a refresh instruction for refreshing the double data rate memory, and the target operation request may be a power conversion request.

[0116] For example, in a management instruction apparatus according to at least one embodiment of the present disclosure, a power conversion request may include: a conversion frequency request, a light sleep request, and a deep sleep request.

[0117] Other additional aspects of the apparatus 300 for managing instructions according to at least one embodiment of the present disclosure may correspond to additional aspects of the method 200 for managing instructions according to at least one embodiment of the present disclosure. Furthermore, the technical effects of the additional aspects of the method 200 for managing instructions according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the apparatus 300 for managing instructions according to at least one embodiment of the present disclosure, and will not be elaborated further here.

[0118] Additionally, it should be noted that, unless otherwise specified, the above modules or units can be implemented through software, hardware, firmware, or combinations thereof.

[0119] At least one embodiment of the present invention also provides a memory controller. Figure 4 A schematic diagram of a memory controller 400 according to at least one embodiment of the present disclosure is shown.

[0120] See Figure 4 The memory controller 400 includes, for example, see [reference] Figure 3 The described apparatus 300 is for managing instructions. In at least one example of this embodiment, the target device is a double data rate memory, the first type of instruction is a functional instruction related to the power consumption configuration of the double data rate memory, the second type of instruction is a refresh instruction for refreshing the double data rate memory, and the target operation request is a power conversion request.

[0121] Thus, the memory controller according to at least one embodiment of the present disclosure can be adapted to perform power conversion on the memory.

[0122] The following describes the above combination with example application scenarios. Figures 2 to 4 One or more exemplary aspects are described. It is understood that the example application scenarios described below are merely examples and not limitations, intended to achieve the above combinations in specific application scenarios. Figures 2 to 4 One or more aspects, and the aspects described below in conjunction with example application scenarios can be combined with the above. Figures 2 to 4 One or more aspects are combined.

[0123] Figure 5 A schematic diagram illustrating an example application scenario according to at least one embodiment of the present disclosure is shown. For example, see... Figure 5 The example application scenario involves power conversion operations for DDR SDRAM, where the target device can be a double data rate memory, the first type of instruction can be a functional instruction related to the power configuration of the double data rate memory, the second type of instruction can be a refresh instruction for refreshing the double data rate memory, and the target operation request can be a power conversion request.

[0124] Figure 5 The application scenario shown can provide a refresh circuit that saves storage resources of the storage array (e.g.) Figure 5 The refresh logic module 2.10, arbitration logic module 2.12, instruction sending module 2.13, etc. are responsible for the timely generation of REF instructions and periodic sending to the DDR memory to maintain the DRAM data without changing the order of functional instructions stored in the memory array. In situations such as low-power transitions or multiple frequency point transitions, the configuration sequence of the current frequency point can be reused. Software personnel only need to change the configurations that differ between different frequencies, which is user-friendly, can save storage resources of the memory array, and can precisely control the interval of REF instruction sending.

[0125] Understandable, depending on the needs of use, see [link / reference]. Figure 5 Not all described units or modules are necessary, and some units or modules can be omitted. Additionally, it is possible to... Figure 5 It includes more units or modules.

[0126] The following combination Figure 5 To describe each module.

[0127] The configuration bus 2.1 primarily configures the configuration module 2.2 in a user-defined manner through operations such as external software. For example, the configuration bus can use the AXI protocol in the AMBA bus protocol, or other configuration buses; this disclosure is not limited to these.

[0128] Configuration module 2.2 primarily receives configuration information sent from configuration bus 2.1. This configuration information may include functional command configuration, refresh command configuration, and timing configuration.

[0129] The functional instruction configuration involves configuring functional instructions for the programmable memory array 2.3 (e.g., the memory array described above). These functional instructions may correspond to the first type of instructions described above, such as functional instructions related to low power consumption. For example, low-power related functional instructions may include the index of the functional instruction in the memory array, the name of the functional instruction, timing requirements between functional instructions required by the DDR protocol, etc. Alternatively, the programmable memory array 2.3 may be replaced with other memory arrays, such as a non-programmable memory array, as long as it is capable of storing the relevant data and / or instructions.

[0130] The refresh instruction configuration involves configuring refresh instructions (e.g., instructions corresponding to the second type of instructions described above) for the refresh logic module 2.10 (e.g., the hardware logic module described above). For example, the refresh instruction to be inserted can be configured to be either REFAB or REFSB, depending on user requirements.

[0131] Timing configuration involves configuring the timing parameters between instructions for the timing control module 2.11 (e.g., the timing control module described above). For example, timing parameters conforming to the protocol between functional instructions and refresh instructions, between functional instructions, or between refresh instructions at different frequencies configured by the user can be stored in advance.

[0132] The programmable memory array 2.3 primarily stores functional instructions and data related to, for example, low-power functions (shown as functional instructions 1 to n). A specific number of instruction entries can be generated according to the functional instructions configuration. Each instruction entry can carry information such as the instruction's index, the current instruction's nature (e.g., specific function, type), the target address of the DRAM to which the current instruction operates, the data information to be written to the target DRAM, and the timing interval between the current functional instruction and the next functional instruction.

[0133] Power conversion requests 2.4 (e.g., corresponding to the target operation requests for the target device described above) are primarily issued via, for example, the AMBA bus or other bus. For instance, a power conversion request may include a request for frequency conversion, light sleep, deep sleep, or some other power state.

[0134] The power conversion module 2.5 can be a state machine, such as a single-threaded state machine. After receiving the power conversion request 2.4, the power conversion module 2.5 first performs some preparatory work, such as clearing the instruction queue (e.g., instructions currently being executed or about to be executed). Then, it executes the instructions in the memory array that need to be executed before SRE, such as some configurations related to frequency switching. Then, it sends SRE to the DRAM to put the DRAM into a self-refresh state. After completing the corresponding power conversion operation, it sends SRX to the DRAM to put the DRAM out of the self-refresh state. Then, it executes the memory operation state, configuring, for example, some voltage-related configurations at the new frequency point. When executing the memory operation state, the power conversion module 2.5 waits for the instruction decoding module 2.6 (described below) to finish continuously reading the contents of the programmable memory array 2.3 and converting them into operation instructions.

[0135] The input portion of the instruction decoding module 2.6 can receive the SRE, SRX, and memory operation status flags issued by module 2.5. When SRX is detected, it can send a flag to the refresh timing module 2.8 (e.g., the timing module described above) to start timing. During memory operation, the instruction decoding module 2.6 can automatically read at least one entry in the programmable memory array 2.3 sequentially and decode it into the corresponding functional instruction. It obtains information such as the target address to be sent for the functional instruction, the interval between the functional instruction and the next instruction, and sends it to the arbitration logic module 2.12 according to the interval requirements of the functional instructions. Additionally, when the instruction decoding module 2.6 reads an empty entry in the programmable memory array 2.3, it can stop decoding and send a flag indicating that the functional instruction transmission of the memory array is complete to the refresh timing module 2.8, which will be described below.

[0136] The refresh mode selection module 2.7 (e.g., the mode selection module described above) can configure the current refresh mode according to the refresh command generated by the configuration module 2.2. For example, the refresh mode can include three types of refresh operations: one is issuing a REFAB command in the normal refresh mode; the second is issuing a REFAB command in the fine-grained refresh mode; and the third is issuing a REFSB command in the fine-grained refresh mode.

[0137] The refresh timing module 2.8 may include a clock counter or a timer. When it detects that the DRAM has exited the self-refresh state, the timing starts. The refresh mode selection module 2.7 generates a refresh instruction request (e.g., the instruction generation request described above) according to the refresh interval configured in different modes and sends it to the refresh instruction generation module 2.9 (e.g., the second type of instruction generation module described above) which will be described below.

[0138] Regarding refresh intervals, for example, when issuing a REFAB command in normal refresh mode, the refresh interval configured is 3.9µs when the temperature is below 85°C, and 1.95µs when the temperature is above 85°C. When issuing a REFAB command in fine-grained refresh mode, the refresh interval set is 1.95µs when the temperature is below 85°C, and 0.975µs when the temperature is above 85°C. When issuing a REFSB command in fine-grained refresh mode, the required refresh interval is (1.95 / n)µs when the temperature is below 85°C, and (0.975 / n)µs when the temperature is above 85°C, where n represents the number of banks in a BankGroup. The temperature here can refer to the ambient temperature of the DRAM. For example, storage devices including DRAM generate heat during use, leading to temperature increases and requiring a higher refresh rate.

[0139] In addition, when the refresh timing module 2.8 receives a flag indicating that the functional instructions for the storage array have been sent by the instruction decoding module 2.6, it can send a request for the last compensation refresh instruction and then stop timing.

[0140] The refresh instruction generation module 2.9 can generate refresh instructions based on the mode configuration of the refresh mode selection module 2.7 when it receives a request from the refresh timing module 2.8. For example, the refresh instruction types that can be generated include REFAB or REFSB.

[0141] See Figure 5 The refresh logic module 2.10 may include a refresh mode selection module 2.7, a refresh timing module 2.8, and a refresh instruction generation module 2.9. The refresh instruction generation module 2.9 can ultimately send the generated refresh instruction to the arbitration logic module 2.12, which will be described below (e.g., the instruction insertion module described above).

[0142] The timing control module 2.11 can be generated based on the timing configuration of module 2.2, and can include information about each instruction combination and its corresponding timing, such as the timing interval from a functional instruction to a refresh instruction, the timing interval from a refresh instruction to the next functional instruction, and the timing interval between refresh instructions, etc., for query by the instruction sending module 2.13 (e.g., the instruction sending module described above) which will be described below.

[0143] When the arbitration logic module 2.12 receives only the functional instruction stream from the instruction decoding module 2.6, it can directly send the functional instruction out, such as to the memory. When the arbitration logic module 2.12 receives both the functional instruction from the instruction decoding module 2.6 and the refresh instruction (i.e., the REF instruction) from module 2.10, it can pause the sending of the functional instruction, prioritize the sending of the refresh instruction, and resume the sending of the functional instruction after the refresh instruction has been sent.

[0144] The instruction sending module 2.13 can query the instruction combinations and corresponding timing sequences in the timing control module 2.11, and send out the received functional instruction streams and refresh instructions according to the configured timing sequences.

[0145] See Figure 5 The described example application scenarios can achieve one or more of the following advantages: For example, by having a dedicated refresh logic module outside the storage array responsible for generating refresh instructions, the storage array can store only low-power configuration-related functional instructions or associated data, saving storage resources and chip area; for another example, the refresh timing module can precisely control the generation time of refresh instructions, and the arbitration logic module can transmit refresh instructions with high priority, thereby promoting the timely delivery of refresh instructions to the memory and ensuring that DRAM data is not lost; for another example, through timing configuration, the transmission timing of functional instructions and refresh instructions is efficiently provided, ensuring the effective execution of instructions; for another example, the redundant software operation of adjusting the configuration order of the storage array at different frequency points is eliminated, increasing the portability of configuration conversion between different frequency points; for another example, the method of using the refresh logic module to control the generation of refresh instructions in the frequency switching process can completely solve the bottleneck caused by the need for excessive refresh instructions when the number of 3DS stacking layers continues to increase, which is technologically forward-looking; for another example, software engineers can only write functional instructions in the storage array, thereby improving work efficiency; for another example, the refresh logic module is a pure hardware structure with high operating efficiency.

[0146] In addition, the storage array can support the expansion of refresh instructions. For example, the storage array can store refresh instructions or their associated data in its entries, and the instruction decoding module can decode them into multiple refresh instructions. In this way, multiple refresh instructions can be retrieved using less storage space in the storage array. This expansion can be used, for example, when only a few refresh instructions are needed.

[0147] The state and timing of the memory can be reused from other units or modules of the memory system. For example, the refresh timing module 2.8 can be omitted, and its corresponding timing function can be provided by other units or modules of the memory system.

[0148] Although the above example application scenario only shows the refresh command, the refresh command can be extended to other commands, such as commands that need to be sent periodically.

[0149] The refresh logic module can support setting multiple thresholds. For example, by comparing the number of refresh commands to be sent with multiple thresholds, control signals are generated to influence the arbitration logic's selection of which command to issue. For instance, a threshold number of refresh commands can be pre-generated; if the number of refresh commands exceeds the threshold, all refresh commands within that threshold number can be sent to the arbitration module.

[0150] Figure 6 A schematic diagram of an electronic device 600 according to at least one embodiment of the present disclosure is shown.

[0151] like Figure 6 As shown, the electronic device 600 includes at least one processing unit 620 and a memory 610. The memory 610 stores computer-readable instructions and is communicatively connected to the processing unit 620. The processing unit 620 executes the computer-readable instructions stored in the memory 610 to implement a method for managing instructions and additional aspects thereof according to at least one embodiment of the present disclosure.

[0152] For example, the memory 610 and the processing unit 620 can communicate with each other directly or indirectly. For example, in some examples, such as... Figure 6 As shown, the electronic device 600 may also include a system bus 630, through which the memory 610 and the processing unit 620 can communicate with each other. For example, the processing unit 620 can access the memory 610 through the system bus 630. For example, in other examples, components such as the memory 610 and the processing unit 620 can communicate through a network on-chip (NOC) connection.

[0153] For example, the processing unit 620 can control other components in the electronic device 600 to perform desired functions. The processing unit 620 can be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), tensor processor (TPU), network processor (NP), or graphics processor (GPU), or it can be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0154] For example, memory 610 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0155] For example, one or more computer-readable instructions can be stored on memory 610, and processing unit 620 can execute computer-readable instructions to perform various functions. Various application programs and various data, such as instruction processing code and various data used and / or generated by the application programs, can also be stored in the computer-readable storage medium.

[0156] For example, when some computer instructions stored in memory 610 are executed by processing unit 620, they can perform one or more steps of the method for managing instructions described above.

[0157] For example, such as Figure 6 As shown, the electronic device 600 may further include an input interface 640 that allows external devices to communicate with the electronic device 600. For example, the input interface 640 may be used to receive instructions from external computer devices, users, etc. The electronic device 600 may also include an output interface 650 that enables the electronic device 600 to connect to one or more external devices. For example, the electronic device 600 can communicate via the output interface 650, etc.

[0158] It should be noted that the electronic device 600 according to at least one embodiment of the present disclosure is exemplary and not restrictive. Depending on the actual application needs, the electronic device 600 may also include other conventional components or structures. For example, in order to realize the necessary functions of the electronic device, those skilled in the art can set other conventional components or structures according to the specific application scenario. The embodiments of the present disclosure do not limit this.

[0159] At least one embodiment of this disclosure also provides a computer-readable storage medium. Figure 7 A schematic diagram of a computer-readable storage medium 700 according to at least one embodiment of the present disclosure is shown.

[0160] For example, such as Figure 7 As shown, the computer-readable storage medium 700 stores computer-readable instructions 710, which, when executed by a computer (including a processor), can implement a method for managing instructions and its additional aspects according to at least one embodiment of the present disclosure.

[0161] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 700. Some of the computer-readable instructions stored on the computer-readable storage medium 700 may be, for example, instructions for implementing one or more steps in the method for managing instructions described above.

[0162] For example, a computer-readable storage medium may include the storage component of a tablet computer, a hard disk of a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical disc read-only memory (CD-ROM), flash memory, or any combination of the above computer-readable storage media, or other suitable storage media. For example, computer-readable storage medium 700 may include the memory 610 in the electronic device 600 described above.

[0163] Figure 8 A schematic diagram of another electronic device 800 according to at least one embodiment of the present disclosure is shown.

[0164] The electronic device according to at least one embodiment of the present disclosure can be implemented as, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs, desktop computers, etc.

[0165] Figure 8 The electronic device 800 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0166] For example, such as Figure 8 As shown, in some examples, electronic device 800 includes a processor 801, which can act as a controller for, for example, storage device 808, and can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 802 or a program loaded from storage device 808 into random access memory (RAM) 803. RAM 803 also stores various programs and data required for the operation of the computer system. Processor 801, ROM 802, and RAM 803 are connected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0167] For example, the following components can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809, such as network interface cards like LAN cards and modems, etc. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 810 is also connected to I / O interface 805 as needed. Removable media 811, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 810 as needed so that computer programs read from them can be installed into storage device 808 as needed. Although Figure 8 An electronic device 800 including various means is shown; however, it should be understood that implementation or inclusion of all the means shown is not required. More or fewer means may be implemented or included alternatively.

[0168] For example, the electronic device 800 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 809 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0169] In addition to the exemplary descriptions above, the following points should be noted regarding this disclosure:

[0170] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0171] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0172] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A method for managing instructions, comprising: In response to receiving a target operation request for a target device, a first type of instruction for operating the target device is obtained from the storage array; A second type of instruction for operating the target device is generated by a hardware logic module outside the storage array; Insert the second type of instruction into the instruction stream formed by the first type of instruction; as well as The instruction stream is sent to the target device.

2. The method according to claim 1, wherein, The second type of instructions generated by the hardware logic module outside the storage array for operating the target device includes: In response to the target device exiting the execution of the second type of instruction after a preset time, the second type of instruction is generated; and The step of inserting the second type of instruction into the instruction stream formed by the first type of instruction includes: In response to the generation of the second type of instruction, the second type of instruction is inserted before the first type of instruction currently being transmitted from the memory array in the instruction stream.

3. The method according to claim 1, wherein, The second type of instructions generated by the hardware logic module outside the storage array for operating the target device includes: Generate the second type of instruction; and The step of inserting the second type of instruction into the instruction stream formed by the first type of instruction includes: In response to the target device exiting the execution of the second type of instruction after a preset time, the second type of instruction is inserted before the first type of instruction currently being transmitted from the storage array in the instruction stream.

4. The method according to claim 2, wherein, The step of inserting the second type instruction before the first type instruction currently being transmitted from the memory array in the instruction stream in response to the generation of the second type instruction includes: In response to the number of second-type instructions being generated reaching a threshold, all of the second-type instructions are inserted before the first-type instructions currently being transmitted from the memory array in the instruction stream.

5. The method according to claim 2, further comprising: In response to receiving a target operation request for a target device, the operation status of the target device is determined, wherein the operation status includes the target device exiting the execution of the second type of instruction.

6. The method according to claim 2, wherein, The preset time is a preset time interval, and the second type of instruction is generated in response to the target device exiting the execution of the second type of instruction after the preset time has elapsed, including: In response to the execution of the second type of instruction by the target device, the time of the exit is timed; and In response to the timing reaching the preset time interval, the second type of instruction is generated.

7. The method according to claim 6, wherein, The response to the timing reaching the preset time interval, generating the second type of instruction, includes: In response to the timing reaching a preset time interval corresponding to the target mode among multiple modes, a command generation request is generated and sent; and In response to receiving the instruction generation request, the corresponding instruction in the target mode is generated as the second type of instruction.

8. The method according to claim 7, further comprising: Obtain pre-configured second type of instruction configuration information to select the target mode from the plurality of modes.

9. The method according to claim 1, wherein, Sending the instruction stream to the target device includes: The instruction stream is sent to the target device with predetermined timing control.

10. The method according to claim 9, wherein, Sending the instruction stream to the target device with predetermined timing control includes: Based on the combination of adjacent instructions in the instruction stream, the adjacent instructions are sent to the target device in a corresponding timing sequence.

11. The method of claim 10, further comprising: Obtain pre-configured timing configuration information to generate and store combinations of adjacent instructions in the instruction stream and their corresponding timing.

12. The method according to claim 1, wherein, The storage array stores one or more extended instruction information, wherein each extended instruction information can be decoded into multiple second-type instructions.

13. The method according to any one of claims 1 to 12, wherein, The target device is a double data rate memory. The first type of instruction is a functional instruction related to the power consumption configuration of the double data rate memory. The second type of instruction is a refresh instruction used to refresh the double data rate memory, and The target operation request is a power conversion request.

14. The method according to claim 13, wherein, The power conversion requests include: frequency conversion requests, light sleep requests, and deep sleep requests.

15. An apparatus for managing instructions, comprising a first type of instruction fetching module, a hardware logic module, a storage array, an instruction insertion module, and an instruction sending module, wherein... The first type of instruction acquisition module is configured to: in response to receiving a target operation request for a target device, acquire a first type of instruction for operating the target device from the storage array; The hardware logic module is configured to generate a second type of instruction for operating the target device; The instruction insertion module is configured to: insert the second type of instruction into the instruction stream formed by the first type of instruction; and The instruction sending module is configured to send the instruction stream to the target device.

16. The apparatus according to claim 15, wherein, The hardware logic module is also configured to: In response to the target device exiting the execution of the second type of instruction after a preset time, the second type of instruction is generated; and The insertion module includes: The arbitration logic module is configured to, in response to the generation of the second type of instruction, insert the second type of instruction before the first type of instruction currently being transmitted from the memory array in the instruction stream.

17. The apparatus of claim 16, further comprising: The timing control module is configured to store combinations of adjacent instructions in the instruction stream and their corresponding timing sequences, wherein... The instruction sending module is further configured to send the adjacent instructions to the target device based on the combination of adjacent instructions in the instruction stream and the corresponding timing.

18. A memory controller, comprising: The apparatus for managing instructions as claimed in any one of claims 16 to 17, wherein, The target device is a double data rate memory. The first type of instruction is a functional instruction related to the power consumption configuration of the double data rate memory. The second type of instruction is a refresh instruction used to refresh the double data rate memory, and The target operation request is a power conversion request.

19. An electronic device comprising: At least one processor; At least one memory, on which instructions are stored, When the instruction is executed by the at least one processor, it causes the at least one processor to perform the method as described in any one of claims 1 to 14.

20. A computer-readable storage medium having computer-readable instructions stored thereon, in, When executed by a processor, the computer-readable instructions cause the processor to perform the method as described in any one of claims 1 to 14.

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