PCIe Lane dynamic configuration and board-level management method based on Loongson architecture

Abstract

The invention relates to a PCIe Lane dynamic configuration and board-level management method based on a Loongson architecture, and relates to the technical field of computer hardware, and the method comprises the following steps: S1, constructing a hardware architecture, employing a Loongson processor and a matched chipset to form a computing platform, enabling the processor to integrate a controller supporting a plurality of PCIe Lanes, and connecting an external device through a PCIe exchange chip; the board card integrates a voltage sensor, a temperature sensor, a current sensor and a board-level management controller; and S2, state data acquisition. According to the method, the PCIe Lane resource is dynamically configured, so that the problem of inflexible resource utilization in a traditional static configuration mode is effectively solved, Lane allocation can be automatically adjusted according to the actual load and demand of the equipment, resource idleness of high-performance equipment in a light load scene is avoided, the overall resource utilization rate of a system is improved, and the system performance is improved. State data acquisition and board-level collaborative management mechanisms are integrated, key parameters such as equipment temperature and bandwidth utilization rate can be sensed in real time, and the stability of the system is enhanced.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, and in particular to a method for dynamic configuration and board-level management of PCIe Lanes based on the Loongson architecture. Background Technology

[0002] In the field of computer hardware design, the PCIe interface, as a high-speed transmission channel connecting the CPU with external devices such as graphics cards, solid-state drives, and network cards, plays a crucial role in system performance and resource utilization due to the rationality of its lane configuration. Currently, most mainstream PCIe lane configuration methods adopt a static configuration mode, that is, the number of lanes, bandwidth, and allocation mode are pre-set during the hardware design stage or the initial system startup. This method is difficult to flexibly adjust when facing diverse application scenarios and changes in device load. In computing platforms based on the Loongson architecture, although Loongson processors such as the 3A5000 and 3C5000 have abundant PCIe resources, the traditional static configuration method has obvious limitations. It may lead to idle PCIe lane resources occupied by high-performance devices in light-load scenarios, and it lacks a real-time perception and dynamic adjustment mechanism for device link errors, overheating, or high load, affecting system stability and reliability.

[0003] Furthermore, in existing technologies, the board-level management system and the PCIe configuration module are relatively independent, lacking an effective coordination mechanism. Although the board-level management system can monitor hardware status, it is difficult to directly participate in the dynamic adjustment of PCIe lanes, and the PCIe configuration process cannot obtain real-time hardware operation data in a timely manner, resulting in a disconnect between configuration strategies and actual needs, thus limiting the full utilization of computing platform performance. To address this, we propose a dynamic PCIe lane configuration and board-level management method based on the Loongson architecture. Summary of the Invention

[0004] The purpose of this application is to provide a method for dynamic configuration and board-level management of PCIe Lanes based on the Loongson architecture. This technical solution solves the problems mentioned above, where statically configuring PCIe Lanes makes it difficult to dynamically adjust according to scenarios and loads, leading to wasted resources on the Loongson platform and a lack of real-time status awareness and adjustment mechanisms, affecting system stability. Furthermore, the board-level management system and the PCIe configuration module are independent, lacking coordination, and the configuration strategy is disconnected from actual needs.

[0005] The PCIe Lane dynamic configuration and board-level management method based on the Loongson architecture provided in this application adopts the following technical solution: The method for dynamic configuration and board-level management of PCIe lanes based on the Loongson architecture includes the following steps: S1. Hardware architecture construction: The computing platform is composed of Loongson processor and matching chipset. The processor integrates a controller that supports multiple PCIe lanes and connects to external devices through PCIe switching chips. The board integrates voltage sensor, temperature sensor, current sensor and board-level management controller. S2. Status data acquisition: The board-level management controller reads sensor data periodically through the bus, and at the same time obtains the bandwidth utilization, error count and link training status of the PCIe device through the PCIe configuration space. S3. Configuration strategy decision: The board-level management controller's built-in dynamic policy library performs the following judgments: When the bandwidth utilization of a PCIe device remains below a set threshold and the bandwidth demand of other devices exceeds the threshold, Lane reallocation is triggered. When the device temperature exceeds the primary safety threshold, it triggers a reduction in the device's PCIe Lane transfer rate to the first throttling mode. When the device temperature exceeds the secondary safety threshold, it triggers a reduction in the number of available PCIe lanes to a preset reduction ratio and activates an enhanced heat dissipation mechanism. S4. Configuration Command Execution: The board-level management controller sends commands to the firmware through the system management interface, and the firmware performs operations including: splitting or aggregating lanes; adjusting lane transmission rates; enabling / disabling specific lanes. S5, board-level collaborative management, triggers an early warning and starts dynamic configuration when link errors exceed limits or devices overheat. Before reconfiguring, it shuts down the target device and suspends data transmission. After configuration, it monitors bandwidth utilization and temperature changes and optimizes the strategy library based on feedback data.

[0006] Preferably, in the hardware architecture construction described in step S1, the deployment schemes for various sensors include: The current sensor monitors the ripple coefficient of the power supply rail, which is the percentage value of the ripple voltage to the nominal voltage; The eye diagram monitoring module acquires signal integrity parameters in real time, which is the ratio of signal amplitude to noise standard deviation. When the ripple coefficient is detected to be greater than 5% or the signal integrity parameter is lower than 0.3 unit interval, the link automatic speed reduction and hardware diagnostic process are triggered.

[0007] Preferably, the board-level management controller in step S1 performs the following operations during the collaborative management process: By accessing the configuration space of the PCIe endpoint device, the PCI Express Capability structure in the PCIe capability structure linked list of the endpoint device can be directly parsed to obtain the maximum link width and speed supported by the device. Continuously monitor the pin level signals of PCIe devices. When a low-to-high transition is detected and the duration exceeds a preset range, it is determined to be a hot removal event. The occupied lane is immediately reclaimed to the dynamic hot standby pool, and the policy library is updated via alarm interrupt through the system management bus. The cooling system coordinates operations by sending cooling adjustment commands to the chassis controller via a multi-level management bus.

[0008] Preferably, the bandwidth utilization rate mentioned in step S2 is monitored by the following method: The board-level management controller periodically reads the link status register of the PCIe configuration space to obtain the actual amount of data transmitted by the target device per unit time. Calculate the bandwidth utilization rate based on the theoretical maximum bandwidth of the link where the device is located; Based on the calculated bandwidth utilization, determine whether the conditions for triggering reallocation are met: A first utilization threshold is set for the graphics processing device, and a second utilization threshold is set for the storage device; When the bandwidth utilization of the graphics processing device is lower than the first utilization threshold for N consecutive sampling periods, and the bandwidth demand of the storage device continues to exceed the second utilization threshold, a Lane reallocation operation is triggered. The sampling period is dynamically set through the link control register in the PCIe configuration space.

[0009] Preferably, the dynamic policy library mentioned in step S3 includes: In scenarios where real-time requirements exceed a preset threshold, lock the Lane configuration of critical devices; For non-critical equipment, the following dynamic adjustment strategy will be implemented: When the system idle time reaches or exceeds 60%, its Lane rate is reduced to the lowest generation. Increase the lane width when the system interrupt response delay exceeds 200 microseconds; The reconfiguration is performed by avoiding the system's preset high-load periods through the real-time clock module.

[0010] Preferably, in step S3, the temperature difference between the primary safety threshold and the secondary safety threshold must be greater than or equal to the minimum temperature buffer zone, which is set based on the equipment's thermal time constant. The first speed reduction mode is the second highest transmission rate level supported by the current PCIe protocol; The preset reduction ratio is achieved through binary division.

[0011] Preferably, the Lane splitting operation in step S4 includes: The processor output lanes are divided into three groups by using the switch chip port bonding function: Graphics processing dedicated group: contains at least x16 lanes; Storage array group: contains at least x8 lanes; Dynamic hot standby pool: must contain at least x4 lanes; During dynamic allocation, the Lane in the hot standby pool is aggregated with the Lane in the target group to form a preset width for allocation to the newly added device.

[0012] Preferably, the dynamic configuration described in step S5 includes the following security measures during the configuration process: Before reconfiguration, the device is forced into D3cold power state via an electrical idle signal; The clock signal of the target device is paused by a clock gating circuit; After configuration, the following operations are executed sequentially: de-gating the clock and waiting for the minimum settling time; sending a PCIe hot reset command to the device's bridge control register; and enabling data transmission after verifying that the device state machine's link training state has entered the initialization phase.

[0013] Preferably, the strategy library based on feedback data mentioned in step S5 includes: An evaluation value is established, which is composed of the bandwidth change multiplied by the first weighting coefficient, the temperature change multiplied by the second weighting coefficient, and the error rate change multiplied by the third weighting coefficient. When the evaluation value exceeds the first optimization threshold, the current strategy is marked as the preferred strategy; When the error rate change exceeds the second optimization threshold, the configuration is automatically rolled back and a device compatibility alarm log is generated.

[0014] Preferably, in an embedded device: The processor integrates a fixed number of PCIe 2.0 lanes; Configuration commands are passed via memory-mapped registers, with a firmware response time of no more than 50 milliseconds. The feedback data is stored using a differential compression algorithm with a compression ratio of no less than 4:1.

[0015] In summary, this application includes at least one of the following beneficial technical effects: This invention effectively solves the problem of inflexible resource utilization in the traditional static configuration mode by dynamically configuring PCIe Lane resources. It can automatically adjust Lane allocation according to the actual load and demand of the device, avoiding resource idleness of high-performance devices in light load scenarios, improving the overall resource utilization of the system. It integrates status data acquisition and board-level collaborative management mechanisms, which can sense key parameters such as device temperature and bandwidth utilization in real time, and trigger early warnings and dynamic configuration in time when the device overheats or the link fails, significantly enhancing the stability and reliability of the system. Through the built-in dynamic strategy library and feedback data optimization mechanism, this method can continuously optimize the configuration strategy to ensure that the configuration decision closely matches the actual needs, further improving the performance and efficiency of the computing platform. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0017] The following is combined with Figure 1 , further details of this application are given.

[0018] Example: A method for dynamic configuration and board-level management of PCIe lanes based on the Loongson architecture, referring to... Figure 1 As shown, its implementation process first depends on a specific hardware architecture.

[0019] This architecture uses the Loongson processor and its supporting chipset to build the core computing platform. The processor integrates controllers that support multiple PCIe lanes. These controllers can be connected to various external devices through PCIe switching chips.

[0020] To achieve comprehensive system status monitoring, the board integrates various sensors, including voltage sensors for monitoring power quality, temperature sensors for environmental sensing, and current sensors for power management. All sensor data is acquired and processed by a dedicated board-level management controller. In the sensor deployment scheme, current sensors are precisely configured on critical power supply tracks to monitor the ripple factor, which is the percentage of ripple voltage to nominal voltage—a crucial indicator for evaluating power supply stability. Its calculation formula is: In the formula, R is the ripple factor, which is the percentage value of ripple voltage to nominal voltage, V 纹波 V is the AC ripple voltage output by the power supply. 标称 This is the nominal DC output voltage of the power supply.

[0021] Simultaneously, the eye diagram monitoring module is integrated into the high-speed signal path to acquire signal integrity parameters in real time. These parameters are defined as the ratio of signal amplitude to the noise standard deviation. The expression is: In the formula, S is the signal-to-noise ratio, and A is... 信号 σ represents the actual amplitude of the high-speed signal. 噪声 This represents the standard deviation of the noise.

[0022] When the ripple coefficient is detected to exceed the threshold of 5%, or the signal integrity parameter is lower than 0.3 unit interval, the system will immediately trigger the link automatic speed reduction mechanism and start the hardware diagnostic process to prevent data errors caused by signal degradation.

[0023] Status data acquisition is fundamental to management decisions. The board-level management controller periodically reads real-time data from various physical sensors, including temperature, voltage, and current values, via a dedicated system bus. More importantly, it also obtains critical performance and status information by accessing the configuration space of PCIe devices. This includes reading link status registers to calculate the actual amount of data transmitted by the target device per unit time, and then combining this with the theoretical maximum bandwidth of the link to which the device resides to accurately calculate the current bandwidth utilization. The formula is: In the formula, U represents bandwidth utilization, and D... 实际 B represents the actual amount of data transmitted by the target device within time T. 理论 Where T is the theoretical maximum bandwidth of the link, and T is the sampling period. In addition, the error counter status and the link training status are also continuously monitored.

[0024] The board-level management controller performs more in-depth operations during collaborative management. It accurately obtains the maximum link width and speed capabilities supported by the device by parsing the PCIe Capability structure linked list in the PCIe configuration space of the endpoint device. It also continuously monitors the pin level signals of the PCIe device. When a low-to-high transition is detected and the high-level state lasts for more than a preset range, the system determines that a hot-removal event has occurred. The specific determination logic is as follows: Let V(t) be the pin level signal (0 represents low level, 1 represents high level), and t0 be the level transition time. t max The upper limit of the preset high-level duration is defined when there exists t1>t0 such that (t1>t0)>t max and When this occurs, it is determined to be a hot removal event. The system will immediately reclaim the PCIeLane resources occupied by the device, release them to the dynamic hot spare pool, and trigger an alarm interrupt through the system management bus to update the policy library.

[0025] The board-level management controller can also send thermal adjustment commands to the chassis controller via a multi-level management bus, enabling coordinated thermal management across the entire system. Bandwidth utilization monitoring is a key criterion for triggering reallocation. The system sets differentiated utilization thresholds for different types of devices; for example, a first utilization threshold is set for graphics processing devices, and a second utilization threshold is set for storage devices.

[0026] When the system detects that the bandwidth utilization of the graphics processing device is below the first utilization threshold for N consecutive sampling periods, while the bandwidth demand of the storage device continuously exceeds its second utilization threshold, a lane resource reallocation operation will be triggered. The length of the sampling period can be dynamically set by configuring the PCIe link control register to adapt to the needs of different monitoring granularities.

[0027] The core of configuration strategy decision-making lies in the dynamic strategy library built into the board-level management controller.

[0028] This policy library contains a series of intelligent judgment logic: when it is detected that the bandwidth utilization of a certain PCIe device is continuously lower than the preset threshold, while other devices have bandwidth requirements exceeding the threshold, the system will trigger the dynamic reallocation of Lane resources.

[0029] In terms of temperature management, the policy library defines primary and secondary safety thresholds. Between these two thresholds, a minimum temperature buffer greater than or equal to the device's thermal time constant is set to avoid frequent state switching.

[0030] When the device temperature exceeds the primary safety threshold, the system will trigger the first throttling mode, which reduces the transmission rate of the PCIe lane connected to the device to the second-highest transmission rate level supported by the current PCIe protocol. If the device temperature rises further and exceeds the more stringent secondary safety threshold, the system will take more severe measures, quickly determining and executing a preset reduction ratio through binary division to reduce the number of available PCIe lanes for the device, while simultaneously activating an enhanced cooling mechanism.

[0031] The dynamic policy library also includes adjustment strategies for different device priorities and system states: For core critical devices with real-time requirements exceeding a preset threshold, their Lane configuration will be locked and dynamic adjustment will be prohibited to ensure performance stability; for non-critical devices, flexible dynamic adjustment strategies will be enabled, such as automatically reducing their Lane rate to the lowest generation supported by the device when the system idle time reaches or exceeds 60% to save power. When the system interrupt response latency exceeds the tolerance limit of 200 microseconds, the system attempts to increase its lane width to improve bandwidth and mitigate latency. Furthermore, the policy library uses a real-time clock module to identify and avoid performing reconfiguration operations during preset high-load periods, reducing the impact on critical business operations.

[0032] The configuration command execution phase translates policy decisions into hardware actions. The board-level management controller sends precise operation commands to the firmware through a standard system management interface.

[0033] The firmware is responsible for performing specific low-level operations, including complex splitting or aggregating lane resources, fine-tuning lane transmission rates, and enabling or disabling specific lane channels. In the specific operation of splitting lanes, the system utilizes the port bonding function of the PCIe switch chip to divide the total lane resources output by the processor into three functional groups: a dedicated graphics processing group, ensuring at least x16 lanes to meet high bandwidth requirements; a storage device array group, allocating at least x8 lanes for connecting storage subsystems; and a dynamic hot spare pool, reserving at least x4 lanes as a flexibly allocable resource pool. When resources need to be allocated to a new device, the dynamic allocation mechanism calls upon lanes in the hot spare pool and aggregates them with a portion of lanes from the target functional group (such as the storage group), combining them into a preset width (such as x4, x8) for allocation to the new device.

[0034] Board-level collaborative management is implemented throughout the entire process to ensure the security and effectiveness of dynamic configuration. When the link error count exceeds the safety limit or the device temperature rises abnormally, the system triggers an alert and initiates the dynamic configuration process. Before actually performing the physical layer reconfiguration operation, the system implements strict security measures: First, it forces the target device into a deep sleep D3cold power state by sending an electrical idle signal, cutting off its active power consumption; second, it suspends the supply of clock signals to the target device through a clock gating circuit, making its logic completely static. After the configuration command is executed, the system resumes device operation in a strict sequence: first, it de-gates the clock and waits for a minimum time window to ensure signal stability; then, it sends a PCIe hot reset command to the device's bridge control register; finally, it continuously verifies the device status until it confirms that its link training state has successfully entered the initialization phase before finally enabling the data transmission channel.

[0035] After configuration, the system continuously monitors changes in key metrics, particularly bandwidth utilization and device temperature trends. Based on this feedback data, the system continuously optimizes the dynamic strategy library. The optimization process is achieved by establishing a comprehensive evaluation value, which is calculated by multiplying the bandwidth change by a first weighting coefficient, subtracting the temperature change by a second weighting coefficient, and then subtracting the error rate change by a third weighting coefficient. The formula is as follows: E=(ΔU×w1)-(ΔT×w2)-(ΔE×w3) In the formula, E represents the overall performance evaluation score of the device, ΔU represents the change in bandwidth utilization, ΔT represents the change in device temperature, ΔE represents the change in error rate, and w1, w2, and w3 are the weighting coefficients for bandwidth, temperature, and error rate, respectively. When this evaluation value exceeds the preset first optimization threshold, the system will mark the currently executed strategy as the priority strategy for subsequent similar scenarios. Conversely, if the error rate change value exceeds the preset second optimization threshold, it indicates that the configuration may cause compatibility issues, and the system will automatically roll back to the previous stable configuration and generate detailed device compatibility alarm logs for analysis.

[0036] In specific application scenarios of embedded devices, this method must also adapt to its constraints. Processors typically integrate a fixed number of PCIe 2.0 lanes, resulting in relatively limited resources. Configuration instructions are transmitted via direct access to memory-mapped registers, requiring firmware response times to be strictly controlled within 50 milliseconds to meet real-time requirements. To save limited storage space, feedback monitoring data generated during system operation is stored using an efficient differential compression algorithm, ensuring a compression ratio of at least 4:1, thereby maintaining sufficient historical data for analysis and strategy optimization within limited resources.

[0037] Through real-time acquisition and in-depth analysis of sensor data and PCIe device status (including bandwidth utilization, link training status, and error count) by the board-level management controller, the system can accurately perceive the actual operating load and environmental conditions of the devices. The built-in dynamic policy library makes autonomous decisions based on preset multi-dimensional thresholds (such as differentiated device bandwidth thresholds and temperature safety thresholds), enabling on-demand and precise allocation of PCIe Lane resources. For example, when it detects that graphics processor resources are idle while storage device bandwidth is tight, the system can quickly trigger Lane reallocation, transferring resources from inefficient areas to bottleneck areas, overcoming the fundamental defects of traditional fixed configuration modes where resources are rigid and unable to respond to load fluctuations.

[0038] It employs a multi-layered protection mechanism to ensure system stability and equipment safety. At the hardware level, deployed current, voltage, and temperature sensors, along with an eye diagram monitoring module, provide direct monitoring capabilities for key physical parameters. Once a power supply ripple coefficient exceeding the standard (>5%) or signal integrity parameter degradation (<0.3UI) is detected, link deceleration and diagnostics are immediately triggered, preventing signal failures at the source. The temperature management strategy employs a two-tiered threshold with buffer intervals (based on the device's thermal time constant), combined with a stepped response (decelerating to the second-highest level, proportionally reducing the lane, and enhancing heat dissipation), effectively avoiding the risk of equipment overheating and preventing hardware damage or system crashes caused by sudden temperature increases. The collaborative management mechanism further enhances security. Before reconfiguration, the device is forced into D3cold state and the clock is paused. After configuration, a strict reset and status verification process is executed, minimizing the risk of link instability or data errors that may arise from the configuration operation itself.

[0039] This method deeply optimizes system energy efficiency and long-term operational adaptability. For non-critical devices, the policy library introduces an automatic lane rate degradation mechanism based on system idle rate (≥60%) and a lane width enhancement strategy based on interrupt latency (>200μs), achieving dynamic energy saving while ensuring basic performance requirements. The feedback-driven policy optimization engine continuously evaluates the configuration effect and marks priority policies or triggers rollbacks by constructing comprehensive evaluation values ​​(weighted bandwidth, temperature, and error rate changes), enabling the system configuration to evolve self-evolving and continuously adapt to the actual operating environment and device characteristics. Special optimizations for embedded scenarios (such as memory-mapped register instruction passing and differential compression storage of feedback data) ensure efficient execution and low-overhead operation of this method in resource-constrained environments.

[0040] It has achieved a fundamental transformation in computing platform resource management from static and passive to dynamic and adaptive, demonstrating substantial breakthroughs in several key dimensions, including improving hardware utilization efficiency, ensuring safe and reliable operation, optimizing system energy consumption, and enhancing long-term adaptability.

[0041] The examples of this specific embodiment are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, any equivalent changes made based on the structure, shape, and principle of this application should be included in the scope of protection of this application.

Claims

1. A method for dynamic configuration and board-level management of PCIe lanes based on Loongson architecture, characterized in that, Includes the following steps: S1. Hardware architecture construction: The computing platform is composed of Loongson processor and matching chipset. The processor integrates a controller that supports multiple PCIe lanes and connects to external devices through PCIe switching chips. The board integrates voltage sensor, temperature sensor, current sensor and board-level management controller. S2. Status data acquisition: The board-level management controller reads sensor data periodically through the bus, and at the same time obtains the bandwidth utilization, error count and link training status of the PCIe device through the PCIe configuration space. S3. Configuration strategy decision: The board-level management controller's built-in dynamic policy library performs the following judgments: When the bandwidth utilization of a PCIe device remains below a set threshold and the bandwidth demand of other devices exceeds the threshold, Lane reallocation is triggered. When the device temperature exceeds the primary safety threshold, it triggers a reduction in the device's PCIe Lane transfer rate to the first throttling mode. When the device temperature exceeds the secondary safety threshold, it triggers a reduction in the number of available PCIe lanes to a preset reduction ratio and activates an enhanced heat dissipation mechanism. S4. Configuration Command Execution: The board-level management controller sends commands to the firmware through the system management interface, and the firmware performs operations including: splitting or aggregating lanes; adjusting lane transmission rates; enabling / disabling specific lanes. S5, board-level collaborative management, triggers an early warning and starts dynamic configuration when link errors exceed limits or devices overheat. Before reconfiguring, it shuts down the target device and suspends data transmission. After configuration, it monitors bandwidth utilization and temperature changes and optimizes the strategy library based on feedback data.

2. The method for dynamic configuration and board-level management of PCIe Lanes based on Loongson architecture according to claim 1, characterized in that, In the hardware architecture construction described in step S1, the deployment schemes for various sensors include: The current sensor monitors the ripple coefficient of the power supply rail, which is the percentage value of the ripple voltage to the nominal voltage; The eye diagram monitoring module acquires signal integrity parameters in real time, which is the ratio of signal amplitude to noise standard deviation. When the ripple coefficient is detected to be greater than 5% or the signal integrity parameter is lower than 0.3 unit interval, the link automatic speed reduction and hardware diagnostic process are triggered.

3. The PCIe Lane dynamic configuration and board-level management method based on Loongson architecture according to claim 1, characterized in that, The board-level management controller mentioned in step S1 performs the following operations during the collaborative management process: By accessing the configuration space of the PCIe endpoint device, the PCIExpress Capability structure in the PCIe capability structure linked list of the endpoint device can be directly parsed to obtain the maximum link width and speed supported by the device. Continuously monitor the pin level signals of PCIe devices. When a low-to-high transition is detected and the duration exceeds a preset range, it is determined to be a hot removal event. The occupied lane is immediately reclaimed to the dynamic hot standby pool, and the policy library is updated via alarm interrupt through the system management bus. The cooling system coordinates operations by sending cooling adjustment commands to the chassis controller via a multi-level management bus.

4. The PCIe Lane dynamic configuration and board-level management method based on Loongson architecture according to claim 1, characterized in that, The bandwidth utilization rate mentioned in step S2 is monitored using the following method: The board-level management controller periodically reads the link status register of the PCIe configuration space to obtain the actual amount of data transmitted by the target device per unit time. Calculate the bandwidth utilization rate based on the theoretical maximum bandwidth of the link where the device is located; Based on the calculated bandwidth utilization, determine whether the conditions for triggering reallocation are met: A first utilization threshold is set for the graphics processing device, and a second utilization threshold is set for the storage device; When the bandwidth utilization of the graphics processing device is lower than the first utilization threshold for N consecutive sampling periods, and the bandwidth demand of the storage device continues to exceed the second utilization threshold, a Lane reallocation operation is triggered. The sampling period is dynamically set through the link control register in the PCIe configuration space.

5. The PCIe Lane dynamic configuration and board-level management method based on Loongson architecture according to claim 1, characterized in that, The dynamic policy library mentioned in step S3 includes: In scenarios where real-time requirements exceed a preset threshold, lock the Lane configuration of critical devices; For non-critical equipment, the following dynamic adjustment strategy will be implemented: When the system idle time reaches or exceeds 60%, its Lane rate is reduced to the lowest generation. Increase the lane width when the system interrupt response delay exceeds 200 microseconds; The reconfiguration is performed by avoiding the system's preset high-load periods through the real-time clock module.

6. The PCIe Lane dynamic configuration and board-level management method based on Loongson architecture according to claim 1, characterized in that, In step S3, the temperature difference between the primary safety threshold and the secondary safety threshold must be greater than or equal to the minimum temperature buffer zone, which is set based on the equipment's thermal time constant. The first speed reduction mode is the second highest transmission rate level supported by the current PCIe protocol; The preset reduction ratio is achieved through binary division.

7. The method for dynamic configuration and board-level management of PCIe Lanes based on Loongson architecture according to claim 1, characterized in that, The Lane splitting operation in step S4 includes: The processor output lanes are divided into three groups by using the switch chip port bonding function: Graphics processing dedicated group: contains at least x16 lanes; Storage array group: contains at least x8 lanes; Dynamic hot standby pool: must contain at least x4 lanes; During dynamic allocation, the Lane in the hot standby pool is aggregated with the Lane in the target group to form a preset width for allocation to the newly added device.

8. The PCIe Lane dynamic configuration and board-level management method based on Loongson architecture according to claim 1, characterized in that, The dynamic configuration described in step S5 includes the following security measures during the configuration process: Before reconfiguration, the device is forced into D3cold power state via an electrical idle signal; The clock signal of the target device is paused by a clock gating circuit; After configuration, the following operations are executed sequentially: de-gating the clock and waiting for the minimum settling time; sending a PCIe hot reset command to the device's bridge control register; and enabling data transmission after verifying that the device state machine's link training state has entered the initialization phase.

9. The method for dynamic configuration and board-level management of PCIe Lanes based on Loongson architecture according to claim 1, characterized in that, The strategy library based on feedback data optimization mentioned in step S5 includes: An evaluation value is established, which is composed of the bandwidth change multiplied by the first weighting coefficient, the temperature change multiplied by the second weighting coefficient, and the error rate change multiplied by the third weighting coefficient. When the evaluation value exceeds the first optimization threshold, the current strategy is marked as the preferred strategy; When the error rate change exceeds the second optimization threshold, the configuration is automatically rolled back and a device compatibility alarm log is generated.

10. The PCIe Lane dynamic configuration and board-level management method based on Loongson architecture according to claim 1, characterized in that, In embedded devices: The processor integrates a fixed number of PCIe 2.0 lanes; Configuration commands are passed via memory-mapped registers, with a firmware response time of no more than 50 milliseconds. The feedback data is stored using a differential compression algorithm with a compression ratio of no less than 4:1.

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