A memory address allocation method and an electronic device

Abstract

This application discloses a memory address allocation method and electronic device, relating to the field of memory management technology. The method includes: determining the memory requirements of a chipset in a target device based on the base address requirements of a target memory address space that meets preset high-order address judgment conditions according to memory-mapped input / output; determining a first memory address that meets the memory requirements based on the total memory capacity of the target device; and determining a second memory address based on the target memory buffer and the first memory address; assigning the second memory address to a target global variable defined in the target code of the basic input / output system as the target base, and determining the corresponding memory address space to allocate to each computing device. This application can predefine global variables in the target code of the basic input / output system, read the total memory capacity of the device, and assign values ​​to the global variables according to chip design requirements and buffers, thereby dynamically allocating memory resources and improving memory resource utilization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory management, and particularly relates to a memory address allocation method and an electronic device. BACKGROUND

[0002] PCI / PCIE (Peripheral Component Interconnect Express bus, high-speed serial computer expansion bus standard) devices need a certain number of MMIO (Memory Mapped I / O, memory-mapped input / output) resources to work, and the type and size of the MMIO resources need to be allocated by the BIOS (Base Input / Output System, basic input / output system). When the current BIOS allocates MMIO resources, a number of fixed-size gears are set for the high-end MMIO base address MMIO HighBase (high-end MMIO start address) of the device for users to choose, but due to the large span between different setting values of the MMIO HighBase, this setting method will cause serious resource waste. SUMMARY

[0003] The present application provides a memory address allocation method and an electronic device, which defines a global variable in advance in the object code of the basic input / output system, reads the total capacity of the device memory, assigns the global variable according to the chip design requirements and the buffer interval, and then dynamically allocates memory resources, thereby avoiding resource waste caused by selecting the base address through fixed gears and improving the utilization rate of memory resources.

[0004] The present application provides a memory address allocation method, which comprises:

[0005] determining the memory requirement of a chip set in a target device; the memory requirement is determined based on the base address requirement of a memory-mapped input / output to a target memory address space, and the memory address in the target memory address space is a memory address meeting a preset high-bit address determination condition;

[0006] determining a first memory address meeting the memory requirement based on the total capacity of the memory of the target device, and determining a second memory address based on the target memory buffer interval and the first memory address; the target memory buffer interval is the memory buffer interval corresponding to the target device;

[0007] assigning the second memory address to a target global variable defined in advance in the object code, and taking the target global variable as the target base address of the memory-mapped input / output of the target device; the object code is the code of the basic input / output system of the target device;

[0008] The corresponding memory address space is determined based on the target base address, and the determined memory address space is allocated to each computing device.

[0009] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing any of the above-described memory address allocation methods when executing the computer program.

[0010] In this application, the memory requirements of the chipset in the target device can first be determined based on the base address requirements of the target memory address space for memory-mapped input / output. The memory address in the target memory address space is the memory address that meets the preset high-order address judgment condition. Then, based on the total memory capacity of the target device, a first memory address that meets the memory requirements is determined, and a second memory address is determined based on the memory buffer space of the target device and the first memory address. The second memory address is assigned to a target global variable predefined in the target code of the basic input / output system, and the target global variable is used as the target base address of the memory-mapped input / output of the target device. Based on the target base address, the corresponding memory address space is determined, and the determined memory address space is allocated to each computing device.

[0011] This application allows for the pre-definition of global variables in the target code of a basic input / output system (BIS), reading the total memory capacity of the target device, and assigning appropriate buffer values ​​to the global variables according to the chip design requirements of the target device. This enables dynamic resource allocation, avoiding the resource waste caused by large parameter ranges when the BIS provides fixed-level base address selection through the interface. It also avoids the risk of server and device malfunctions or even system crashes due to improper manual settings. Furthermore, it can dynamically and automatically analyze and calculate the most suitable high-order base address parameter values ​​for the user based on different memory configurations and other influencing factors on the server, improving memory resource utilization and device compatibility, and enabling compatibility with more resource-intensive devices. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart of a memory address allocation method provided in an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of a memory address allocation device provided in an embodiment of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] Currently, when allocating MMIO resources in PCIe devices, the BIOS code typically sets several fixed levels for the device's high MMIO base address (MMIO High Base). However, when users select the MMIO granularity through the BIOS Setup interface, the range between the MMIO High Base settings is quite large, leading to significant resource waste. This application, however, predefines global variables in the object code of the basic input / output system, reads the total device memory capacity, and assigns values ​​to the global variables according to chip design requirements and buffer intervals, thereby dynamically allocating memory resources. This avoids the resource waste caused by selecting base addresses through fixed levels and improves memory resource utilization.

[0018] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Next, this embodiment will describe the execution flow of the memory address allocation method in detail, such as... Figure 1 As shown, an embodiment of this application provides a memory address allocation method, including:

[0020] Step S11: Determine the memory requirements of the chipset in the target device; the memory requirements are determined based on the base address requirements of the target memory address space according to the memory mapping input / output, and the memory addresses in the target memory address space are memory addresses that meet the preset high-order address determination conditions.

[0021] In this embodiment, after the device boots up, the target function in the BIOS Setup tool can be removed first, and a global variable can be defined as the target global variable in the target code, i.e., the BIOS code. The target setup tool is the setup tool for the Basic Input / Output System, and the target function is the function used to set the target base address MMIOHigh Base for memory-mapped input / output. For example, in the BIOS Setup interface configuration file, the menu node corresponding to MMIO High Base is deleted, including the option name, fixed-level list, help text, etc., and the relevant code in the BIOS that reads manually selected values ​​is also deleted to avoid residual code interfering with the automatic calculation results.

[0022] It is understood that the target device in this embodiment includes, but is not limited to, PCIe devices or other firmware, software, OS (Operating System), etc., in order to perform memory resource and other types of resource allocation processing, or other parameter settings on the above-mentioned device.

[0023] In other words, this embodiment first requires removing the option setting for MMIO High Base in the BIOS Setup and defining a global variable representing MMIO High Base in the BIOS code. For example, this variable can be named MmiohVariable. It can be understood that this variable does not have a fixed value and is automatically assigned a value according to the server configuration.

[0024] Step S12: Determine the first memory address that meets the memory requirements based on the total memory capacity of the target device, and determine the second memory address based on the target memory buffer and the first memory address; the target memory buffer is the memory buffer corresponding to the target device.

[0025] In this embodiment, a first memory address that meets the memory requirements can be determined based on the total memory capacity of the target device, and a second memory address can be determined based on the target memory buffer and the first memory address; the target memory buffer is the memory buffer corresponding to the target device. Before determining the first memory address that meets the memory requirements, a target setting tool needs to scan the hardware devices in the target device and sequentially read the device parameters (SPD, or Serial Presence Detect) information of each memory in the hardware device. Then, the total memory capacity of the target device is determined based on the device parameters. For example, all memory slots of the target device can be traversed, the SPD capacity of each slot can be read, and empty slots and faulty memory with unresponsive SPD addresses can be skipped during accumulation, and corresponding processing can be performed.

[0026] Specifically, in this embodiment, when determining the total memory capacity of the target device, the memory capacity of each memory module can be determined based on the device parameters, and the capacities of each memory module are summed to obtain the total memory capacity of the target device. That is, in this embodiment, after each server boot, after the BIOS initializes and enumerates all hardware devices, including memory devices, it sequentially reads the SPD information of each memory module, parses the memory capacity from the read data, and sums the capacities of each memory module to calculate the total memory capacity of all memory on the server, for example, this value is X. It is also understood that, in addition to reading and parsing SPD information, other possible methods can also be used in this embodiment to obtain the total memory capacity of all memory on the server. In this way, in the dynamic MMIO High Base calculation scheme of this embodiment, SPD information is used to replace manual configuration. There is no need for users to manually input the memory capacity. The BIOS automatically obtains the actual capacity of each memory module by reading the SPD, avoiding errors caused by manual input. Moreover, the SPD information is written by the memory manufacturer, and the recorded capacity is the physical actual capacity of the memory (not the nominal value deviation), which can ensure the accuracy of the capacity. At the same time, when the server replaces or adds memory, the BIOS can update the total memory capacity X in real time by rereading the SPD without user intervention, thereby dynamically adjusting the MMIO High Base value.

[0027] Based on the above technical solution, in this embodiment, the second memory address is determined based on the target memory buffer space and the first memory address. Specifically, a preset memory alignment granularity corresponding to the target device can be determined, and the first memory address is adjusted according to the preset memory alignment granularity to obtain the adjusted first memory address. Then, the second memory address is determined based on the target memory buffer space and the adjusted first memory address. Furthermore, when adjusting the first memory address according to the preset memory alignment granularity, it can first be determined whether the first memory address conforms to the preset memory alignment granularity. If it does not conform to the preset memory alignment granularity, the first memory address is adjusted based on the memory requirements and the preset memory alignment granularity to obtain the adjusted first memory address. In other words, in this embodiment, the corresponding adjusted first memory address can be calculated according to the design requirements of different types of server chip platforms for MMIO High Base. For example, in a specific embodiment, the current server chip platform requires MMIO High Base to be greater than the total capacity of all memory on the server. In this case, based on this requirement and the calculated total memory capacity X on the machine, and after necessary processing according to the chipset design requirements, such as alignment at a certain granularity, including but not limited to 16M alignment, the processed data Y can be obtained. It is understood that, apart from the requirements in the specific embodiments described above, when this solution is applied to other server platforms, the total memory capacity X can be adjusted accordingly based on the requirements of the corresponding chip.

[0028] It is understandable that chipset address space allocation is an integer multiple of a certain fixed granularity. This is because the CPU / chipset address bus addresses in batches according to granularity. Unaligned addresses can lead to complex addressing logic, reduced efficiency, and even trigger hardware errors. Furthermore, if the MMIO High Base is unaligned, its address may overlap with memory addresses and other hardware resources, causing system crashes. Manufacturers explicitly require MMIO-related parameters to be aligned to a specified granularity in their chip manuals; misalignment will cause BIOS initialization failure. Therefore, in this embodiment, the alignment granularity is first determined by the chipset model and BIOS design specifications. The BIOS then loads the corresponding predefined alignment granularity based on different chipsets. Assuming the alignment granularity is determined to be G (e.g., 16M), and the total memory capacity is X, the steps to calculate Y are as follows: Ensure that Y is an integer multiple of G, and Y≥X. Assuming the total memory capacity X=100GB and the alignment granularity G=16M, first, convert X and G to the same unit and determine if they are aligned. Calculate the remainder of X÷G. If the remainder is 0, it means X itself is an integer multiple of G, and Y=X directly. If the remainder ≠ 0, round up to the nearest integer multiple of G. Furthermore, in this embodiment, the alignment process can be automatically executed by the BIOS code during the hardware initialization phase without user intervention. First, the BIOS reads the SPD information of each memory module, parses the capacity of a single module, accumulates it to obtain X, and loads the predefined alignment granularity to perform the alignment calculation. Then, the validity of Y can be verified by checking whether Y meets the preset conditions. If not, an error is triggered.

[0029] Furthermore, by determining the second memory address based on the target memory buffer and the adjusted first memory address, the target memory buffer corresponding to the target device can be identified. The memory space corresponding to the target memory buffer is then added to the adjusted first memory address to obtain the second memory address. In other words, based on the data Y obtained in the above steps, a buffer of an appropriate size can be added, such as, but not limited to, 10G. This ensures that the chip's functional design needs are met and that memory space conflicts are avoided. It is important to understand that the buffer size needs to meet a preset range to avoid resource waste due to an excessively large buffer. In this way, the most suitable MMIO High Base parameter value can be dynamically and automatically analyzed and calculated for the user based on different memory configurations and other influencing factors on the server. For example, if the machine has different numbers and sizes of memory modules connected, the total memory will be different, and therefore the available MMIO High Base value will also be different. The aforementioned buffer can be determined based on the chipset's memory MMIO isolation requirements, future memory expansion margins, or device redundancy needs.

[0030] It should be noted that, in determining the target memory buffer space corresponding to the target device, it is also possible to determine whether the target device has a reserved memory range based on its memory requirements; if a reserved memory range exists, the target memory buffer space is determined based on the reserved memory range and the preset memory buffer space. The aforementioned reserved memory range is memory space that is prohibited from being allocated to computing devices. In this way, the data corresponding to the second memory address can be obtained as Z.

[0031] Step S13: Assign the second memory address to the target global variable predefined in the target code, and use the target global variable as the target base address of the memory-mapped input / output of the target device; the target code is the code of the basic input / output system of the target device.

[0032] In this embodiment, the second memory address can be assigned to the target global variable MmiohVariable, which is predefined in the target code, and the target global variable can be used as the target base address MMIOHighBase for the memory-mapped input / output of the target device. The target code is the code of the target device's basic input / output system. Through the above technical solution, in this embodiment, after the server boots up, the BIOS first initializes and enumerates all hardware, reads the SPD information of each memory module, parses and accumulates it to obtain the total memory capacity X, and then aligns X with granularity according to the target chipset design requirements to obtain data Y. Then, a reasonable buffer is added to Y to finally obtain the MMIO High Base value Z. Furthermore, MMIO High Base is the starting point of the device address; therefore, it must be ensured that the device address falls completely outside the memory address range. That is, for the current server chip platform, the MMIO High Base value Z must be greater than the total capacity X of all server memory to ensure normal memory initialization and avoid conflicts between memory and MMIOH resource addresses.

[0033] Step S14: Determine the corresponding memory address space based on the target base address, and allocate the determined memory address space to each computing device.

[0034] In this embodiment, the target address corresponding to the target device can be determined. Then, based on the memory address between the target address and the target base address, the corresponding memory address space is determined, and the determined memory address space is allocated to each computing device. The target address is the maximum address of the memory-mapped input / output in the target device. Specifically, in this embodiment, Z can be assigned to a predefined global variable MmiohVariable representing MMIO High Base, and the value Z of MmiohVariable is used as the base value of MMIO High Base. Based on this base value, resources are allocated to all devices requiring MMIOH resources according to the original functional design. It is also understood that for other chipsets, the design requirements of the MMIO High Base parameters can be investigated separately, and memory allocation and dynamic setting can be implemented according to the above scheme. Furthermore, if some devices or chips have other special design requirements for the MMIO High Base parameters, corresponding processing can be performed during the above assignment of MMIO High Base parameters, and finally, all design requirements are summarized and aligned for assignment.

[0035] Furthermore, in this embodiment, the memory address space MMIOH allocated to each computing device is a dedicated resource for PCIe devices. It is an address space, not a physical memory chip, located in the high address space above 4GB supported by the CPU. This address space can be mapped to hardware registers, onboard caches, and other hardware units of the PCIe device. When the CPU accesses this address space, it does not operate on physical memory but communicates directly with the hardware units of the PCIe device. In this way, the BIOS allocates the high address space above 4GB to each PCIe device according to rules, allowing the CPU to control the device through an efficient memory addressing method.

[0036] In this way, by dynamically analyzing and calculating the MMIO High Base value as described above, instead of manually setting it through BIOS Setup as in the original solution, manual settings are no longer required when allocating memory addresses. This avoids impacting the operation of upper-layer services. Furthermore, the system can dynamically and automatically analyze and calculate the most suitable MMIO High Base parameter value based on factors such as different memory configurations on the server. For example, if the machine has different numbers and sizes of memory modules, the total memory will be different, and the available MMIO High Base value will also be different. In this way, compared to the large granularity of the original BIOS options (e.g., the next configurable level after 40T is 56T), and because the MMIOH range in the Memory Space is between MMIO High Base and MMIOH Resource Limit, the MMIOH Resource Limit remains unchanged while the MMIO High Base value decreases. There is no waste caused by the large granularity of the configurable value, so the available resource range (MMIOH Resource Limit – MMIO High Base) is maximized. This provides the server with the maximum amount of MMIOH resources for devices to use, thus enabling compatibility with more PCIe devices.It is understood that in this embodiment, MMIO HighGranularity Size is a fixed MMIOH address block size allocated by the BIOS to each independent unit stack of the CPU. This simplifies stack resource management and avoids address conflicts between stacks. MMIOH Resource Limit is the upper limit of high-granularity MMIO resource addresses, representing the highest physical address supported by the CPU and chipset that can be used for MMIOH resources. The MMIOH addresses of all PCIe devices cannot exceed this value. MMIOH Resource Limit and MMIO High Base together determine the total amount of MMIOH resources that the server can allocate. This limits the maximum range of MMIOH resources, preventing addresses from exceeding the CPU's addressing capabilities. Furthermore, some high-order addresses can be reserved for CPU security encryption functions. Limit can deduct these reserved addresses to ensure functional compatibility. The value of Limit is determined by the CPU hardware capabilities and high-end feature configuration. Accordingly, in this embodiment, the total amount of allocatable MMIOH resources = MMIOH Resource Limit - MMIO High Base. By dynamically optimizing MMIO High Base and maximizing MMIOH Resource Limit, the total amount of allocatable MMIOH resources can be maximized. Limit maximizes the total resources, enabling support for more high-demand PCIe devices and resolving current issues of resource waste and poor device compatibility.

[0037] In this embodiment, the memory requirements of the chipset in the target device are first determined based on the base address requirements of the target memory address space for memory-mapped input / output. The memory addresses in the target memory address space are memory addresses that meet the preset high-order address determination conditions. Then, based on the total memory capacity of the target device, a first memory address that meets the memory requirements is determined, and a second memory address is determined based on the memory buffer space of the target device and the first memory address. The second memory address is assigned to a target global variable predefined in the target code of the basic input / output system, and the target global variable is used as the target base address of the memory-mapped input / output of the target device. Based on the target base address, the corresponding memory address space is determined, and the determined memory address space is allocated to each computing device. The above technical solution allows for the pre-definition of global variables in the target code of the basic input / output system, reading the total memory capacity of the target device, adding appropriate buffers according to the chip design requirements of the target device, and assigning values ​​to the global variables. This enables dynamic resource allocation, avoiding the resource waste caused by large parameter ranges when the basic input / output system provides fixed-level base address selection through the interface. It also avoids the risk of server and device malfunctions or even system crashes due to improper manual settings. Furthermore, it can dynamically and automatically analyze and calculate the most suitable high-order base address parameter values ​​for the user based on different memory configurations and other influencing factors on the server, improving memory resource utilization and device compatibility, and enabling compatibility with more resource-intensive devices.

[0038] like Figure 2 As shown, embodiments of this application also provide a memory address allocation device, including:

[0039] The requirement determination module 11 is used to determine the memory requirement of the chipset in the target device. The memory requirement is determined based on the base address requirement of the target memory address space according to the memory mapping input and output. The memory address in the target memory address space is the memory address that meets the preset high-order address judgment condition.

[0040] Address determination module 12 is used to determine a first memory address that meets the memory requirements based on the total memory capacity of the target device, and to determine a second memory address based on the target memory buffer and the first memory address; the target memory buffer is the memory buffer corresponding to the target device.

[0041] The variable assignment module 13 is used to assign the second memory address to a target global variable predefined in the target code, and use the target global variable as the target base address of the memory-mapped input / output of the target device; the target code is the code of the basic input / output system of the target device;

[0042] Address allocation module 14 is used to determine the corresponding memory address space based on the target base address and allocate the determined memory address space to each computing device.

[0043] In some specific embodiments, the memory address allocation device further includes:

[0044] The scalar setting unit is used to remove the target function from the target setting tool and define a global variable in the target code as the target global variable; where the target setting tool is the setting tool for the basic input / output system, and the target function is the function used to set the target base address for implementing memory-mapped input / output.

[0045] In some specific embodiments, the memory address allocation device further includes:

[0046] The parameter reading module is used to scan the hardware devices in the target device using the target setting tool, and read the device parameters of each memory in the hardware device in turn;

[0047] The capacity determination module is used to determine the total memory capacity of the target device based on the device parameters.

[0048] In some specific embodiments, the capacity determination module specifically includes:

[0049] The capacity determination unit is used to determine the memory capacity corresponding to each memory module based on the device parameters.

[0050] The capacity accumulation unit is used to accumulate the capacity of each memory unit to obtain the total memory capacity of the target device.

[0051] In some specific embodiments, the address determination module 12 specifically includes:

[0052] The address adjustment submodule is used to determine the preset memory alignment granularity corresponding to the target device, and adjust the first memory address according to the preset memory alignment granularity to obtain the adjusted first memory address;

[0053] The address determination submodule is used to determine the second memory address based on the target memory buffer and the adjusted first memory address.

[0054] In some specific embodiments, the address adjustment submodule specifically includes:

[0055] The address determination unit is used to determine whether the first memory address conforms to the preset memory alignment granularity.

[0056] The memory adjustment unit is used to adjust the first memory address based on memory requirements and the preset memory alignment granularity if the memory does not meet the preset memory alignment granularity, so as to obtain the adjusted first memory address.

[0057] In some specific embodiments, the address determination submodule specifically includes:

[0058] The interval determination unit is used to determine the target memory buffer space corresponding to the target device;

[0059] The address increment unit is used to increment the memory space corresponding to the target memory buffer to the adjusted first memory address to obtain the second memory address.

[0060] In some specific embodiments, the interval determination unit is specifically used to determine whether the target device has a reserved memory interval based on the memory requirements of the target device; the reserved memory interval is the memory space that is prohibited from being allocated to the computing device; if the reserved memory interval exists, the target memory buffer interval is determined based on the reserved memory interval and the preset memory buffer interval.

[0061] In some specific embodiments, the address allocation module 14 specifically includes:

[0062] The address determination unit is used to determine the target address corresponding to the target device; the target address is the maximum address of the memory-mapped input / output in the target device.

[0063] The space allocation unit is used to determine the corresponding memory address space based on the memory address between the target address and the target base address, and to allocate the determined memory address space to each computing device.

[0064] For a description of the features in the embodiment corresponding to the memory address allocation device, please refer to the relevant description in the embodiment corresponding to the memory address allocation method, which will not be repeated here.

[0065] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0066] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described memory address allocation method embodiments.

[0067] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described memory address allocation method embodiments at runtime.

[0068] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0069] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described memory address allocation method embodiments.

[0070] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described memory address allocation method embodiments.

[0071] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0072] The foregoing has provided a detailed description of a memory address allocation method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory address allocation method, characterized by, The method comprises the following steps: determining the memory requirement of a chipset in a target device; the memory requirement is determined based on the base address requirement of a target memory address space for memory-mapped input / output, the memory address in the target memory address space being a memory address meeting a preset high-bit address determination condition; determining a first memory address meeting the memory requirement based on the total memory capacity of the target device, and determining a second memory address based on a target memory buffer interval and the first memory address; the target memory buffer interval being a memory buffer interval corresponding to the target device; assigning the second memory address to a target global variable defined in advance in a target code, and taking the target global variable as a target base address for memory-mapped input / output of the target device; the target code being a code of a basic input / output system of the target device; determining a corresponding memory address space based on the target base address, and allocating the determined memory address space to each computing device; before the step of assigning the second memory address to the target global variable defined in advance in the target code, the method further comprises the following steps: removing a target function in a target setting tool, and defining a global variable in the target code as the target global variable; wherein the target setting tool is a setting tool of the basic input / output system, and the target function is a function for setting the target base address for memory-mapped input / output; before the step of determining the first memory address meeting the memory requirement based on the total memory capacity of the target device, the method further comprises the following steps: scanning hardware devices in the target device by using the target setting tool, and reading device parameters of each memory in the hardware devices in sequence; the device parameters being serial presence detect information of each memory read by the basic input / output system; determining the total memory capacity of the target device according to the device parameters; the step of determining the total memory capacity of the target device according to the device parameters comprises the following steps: determining the memory capacity corresponding to each memory according to the device parameters; accumulating each memory capacity to obtain the total memory capacity of the target device; the step of determining the second memory address based on the target memory buffer interval and the first memory address comprises the following steps: determining a preset memory alignment granularity corresponding to the target device, adjusting the first memory address according to the preset memory alignment granularity to obtain an adjusted first memory address; verifying the adjusted first memory address by using the basic input / output system, and determining the second memory address based on the target memory buffer interval and the adjusted first memory address after verification; the step of adjusting the first memory address according to the preset memory alignment granularity to obtain the adjusted first memory address comprises the following steps: determining whether the first memory address meets the preset memory alignment granularity; if the first memory address does not meet the preset memory alignment granularity, adjusting the first memory address based on the memory requirement and the preset memory alignment granularity to obtain the adjusted first memory address. The second memory address is determined based on the target memory buffer interval and the adjusted first memory address, including: determining the target memory buffer interval corresponding to the target device; increasing the memory space corresponding to the target memory buffer interval to the adjusted first memory address to obtain the second memory address; The target memory buffer interval corresponding to the target device is determined, including: determining whether there is a reserved memory interval based on the memory requirement of the target device; the reserved memory interval is a memory space that is prohibited to be allocated to the computing device; if there is the reserved memory interval, determining the target memory buffer interval based on the reserved memory interval and a preset memory buffer interval.

2. The memory address allocation method of claim 1, wherein, The corresponding memory address space is determined based on the target base address, and the determined memory address space is allocated to each computing device, including: determining a target address corresponding to the target device; the target address is the maximum address of memory-mapped input / output in the target device; determining the corresponding memory address space based on the memory address between the target address and the target base address, and allocating the determined memory address space to each computing device.

3. An electronic device, comprising: including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the memory address allocation method according to claim 1 or 2.

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