Low-power-consumption bridging chip and electronic equipment
By introducing a power management module into the bridge chip, the power consumption status of the second functional module is monitored and adjusted, thus solving the problem of high power consumption in existing PCIe to SATA bridge chips and achieving low-power design and high-efficiency operation.
Patent Information
- Application Number
- CN202511070585.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-10-28
AI Technical Summary
Existing PCIe to SATA bridge chips consume a lot of power, making it difficult to meet low-power design requirements.
Design a low-power bridge chip that monitors the power consumption status changes of the first functional module through a power management module, generates target instructions, and sends them to the second functional module through a bus interface module. This enables power consumption linkage between the first and second functional modules, avoiding waste or inefficiency caused by power consumption mismatch.
Optimize and save power consumption of bridge chips, improve operating efficiency, and meet low-power design requirements.
Smart Images
Figure CN120849326A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chips, and more specifically, to a low-power bridging chip and electronic device. Background Technology
[0002] With the rapid development of computer technology and the continuous improvement of hardware performance, the demand for data transmission speed is increasing. High-speed serial computer expansion bus (Peripheral Component Interconnect express, or PCIe) has become mainstream due to its high bandwidth and low latency. However, due to the interface differences between different devices and the PCIe bus, direct connection is often difficult to achieve. To fully utilize the high-speed performance of the PCIe bus while also accommodating the advantages of other interface devices, PCIe bridge chips have emerged.
[0003] With the explosive growth of computing power, the upgrade cycle of mainstream Central Processing Unit (CPU) platforms has accelerated, primarily focusing on improving computing power and processing speed. Many new-generation CPU platforms have reduced support for Serial ATA (SATA) ports or directly adopted PCIe interfaces. As user demands for computing power increase, so too does the demand for storage capacity. Since the number of SATA ports supported by CPUs cannot meet the needs of users for more storage devices, hardware systems such as servers, desktops, and industrial control computers urgently require more SATA ports. Therefore, PCIe-to-SATA bridge chips have become an effective solution for expanding SATA ports.
[0004] A PCIe-to-SATA bridge chip is a chip used to convert a PCIe bus into a SATA interface, allowing motherboards or expansion cards to expand to multiple SATA storage device interfaces through the PCIe channel. Existing PCIe-to-SATA bridge chips suffer from high power consumption, making it difficult to meet low-power design requirements. Summary of the Invention
[0005] The purpose of this invention is to provide a low-power bridging chip and electronic device to improve the above-mentioned problems.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a low-power bridge chip, the low-power bridge chip comprising: a first functional module, a second functional module, a bus interface module, and a power management module; The bus interface module is connected to the first functional module, the second functional module, and the power management module, respectively. The first functional module is used to connect to its matched upstream device; The second functional module is used to connect to its matched downstream devices; When the low-power bridge chip is in automatic power management mode, the power management module is used to send a power state adjustment command to the second functional module through the bus interface module when it detects a change in the power state of the first functional module.
[0007] By adjusting the power consumption state of the second functional module, power consumption linkage between the first and second functional modules is achieved, avoiding power waste or low operating efficiency caused by power consumption mismatch between the first and second functional modules, thus optimizing and saving the power consumption of the bridge chip.
[0008] Optionally, when a change in the power consumption state of the first functional module is detected, the power consumption management module generates a target instruction and sends the target instruction to the bus interface module; wherein, the target instruction is a power consumption state adjustment instruction that matches the current power consumption state of the first functional module. The bus interface module is used to send the target instruction to the second functional module; The second functional module is used to adjust the power consumption state according to the target instruction.
[0009] By generating a target instruction that matches the current power consumption state of the first functional module, the second functional module is precisely adjusted to achieve power consumption linkage between the first and second functional modules, enabling the power consumption states of the first and second functional modules to be quickly matched.
[0010] Optionally, the first functional module is used to send a first type of interrupt signal to the power management module when the power consumption state changes; The power management module is used to read the power status register in the first functional module through the bus interface module when it receives the first type of interrupt signal, obtain the current power status of the first functional module, generate a target instruction, and send the target instruction to the second functional module. The target instruction is a power consumption state adjustment instruction that matches the current power consumption state of the first functional module.
[0011] By sending a first type of interrupt signal when the power consumption state of the first functional module changes, the power management module is notified as soon as the power consumption state of the first functional module changes, thereby ensuring the timeliness of the power consumption state switching of the second functional module.
[0012] Optionally, the power management module is further configured to read the power status register in the first functional module through the bus interface module at a preset period to obtain the current power status of the first functional module, generate a target instruction when the power status of the first functional module changes, and send the target instruction to the second functional module.
[0013] When the power consumption state changes, even if the first functional module fails to send a first type of interrupt signal to the power management module in a timely manner due to hardware or software reasons, it can still adjust the power consumption state of the second functional module in a timely manner to avoid the power consumption state of the second functional module being mismatched with that of the first functional module for a long time.
[0014] Optionally, the second functional module is used to send a second type of interrupt signal to the power management module when the power consumption state changes; When the second type of interrupt signal is received, the power management module reads the power status register in the second functional module through the bus interface module to obtain the current power status of the second functional module, and determines whether the current power status of the first functional module matches the current power status of the second functional module.
[0015] By reading the current state of the second functional module, we can further verify whether the power consumption state of the first functional module matches the power consumption state of the second functional module, thus ensuring the accuracy of the power consumption state linkage adjustment.
[0016] Secondly, embodiments of the present invention provide an electronic device including the aforementioned low-power bridging chip.
[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is one of the structural schematic diagrams of a low-power bridge chip provided in an embodiment of the present invention.
[0020] Figure 2 This is the second schematic diagram of the structure of the low-power bridging chip provided in the embodiment of the present invention.
[0021] Figure 3 This is a schematic diagram of the PCIe to SATA bridge chip provided in an embodiment of the present invention. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0025] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0026] To achieve power consumption linkage between the first and second functional modules in a bridging chip and avoid power waste or low operating efficiency caused by power mismatch between the first and second functional modules, this invention provides a low-power bridging chip. Please refer to [link / reference]. Figure 1 , Figure 1 This is one of the structural schematic diagrams of a low-power bridge chip provided in an embodiment of the present invention.
[0027] The low-power bridge chip includes: a first functional module, a second functional module, a bus interface module, and a power management module.
[0028] The first functional module may be, but is not limited to, a PCIe module and a ComputeExpress Link (CXL) module; the second functional module may be, but is not limited to, a SATA module and a USB module; the bus interface module may be, but is not limited to, an Advanced Microcontroller Bus Architecture (AMBA); and the power management module may be, but is not limited to, an RTL hardware circuit module.
[0029] The bus interface module is connected to the first functional module, the second functional module, and the power management module via a bus. The power management module is also connected to the first functional module and the second functional module via an interrupt signal line.
[0030] The first functional module is used to connect to its matching upstream device. The upstream device corresponding to the PCIe module is a PCIe device.
[0031] The second functional module is used to connect to its matching downstream devices. The upstream device corresponding to the SATA module is a SATA device.
[0032] In one optional implementation, the first functional module includes a first controller and a first physical layer, and the second functional module includes a second controller and a second physical layer. For example, the first controller is a PCIe controller, the first physical layer is a PCIe physical layer, the second controller is a SATA controller, and the second physical layer is a SATA physical layer.
[0033] The first controller is connected to the upstream device through the first physical layer, and the second controller is connected to the downstream device through the second physical layer. The first and second controllers are connected to the bus interface module through a bus, and the first and second controllers are respectively connected to the power management module (and the processing module below) through corresponding interrupt signal lines.
[0034] The first functional module receives first-type protocol downlink data (e.g., PCIe protocol data) transmitted from upstream devices, converts it into bus protocol downlink data corresponding to the bus interface module, and then transmits the bus protocol downlink data to the bus interface module. The bus interface module transmits the bus protocol downlink data to the second functional module. The second functional module converts the bus protocol downlink data into second-type protocol downlink data (e.g., SATA protocol data) and transmits the second-type protocol downlink data to downstream devices.
[0035] The second functional module receives second-type protocol uplink data (e.g., SATA protocol data) transmitted from downstream devices, converts it into bus protocol uplink data corresponding to the bus interface module, and then transmits the bus protocol uplink data to the bus interface module. The bus interface module transmits the bus protocol uplink data to the first functional module. The first functional module converts the bus protocol uplink data into first-type protocol uplink data (e.g., PCIe protocol data) and transmits the first-type protocol uplink data to the upstream device.
[0036] The first functional module, the second functional module, and the bus interface module can serve as read / write channels between upstream and downstream devices. Simultaneously, upstream devices can also configure various modules in the bridge chip through these channels.
[0037] For details on how to achieve power consumption linkage between the first and second functional modules in the bridging chip, please refer to the following text.
[0038] When the low-power bridge chip is in automatic power management mode, the power management module sends a power state adjustment command to the second functional module through the bus interface module when it detects a change in the power state of the first functional module, so that the adjusted power state of the second functional module matches the current power state of the first functional module.
[0039] When the first functional module enters a low-power state, the second functional module remains in a high-power state, which results in unnecessary power waste and does not meet the low-power design requirements. When the first functional module is in a high-power state, if the second functional module is in a low-power state, it will affect the operating efficiency of the bridge chip.
[0040] In the low-power bridging chip provided in this embodiment of the invention, by adjusting the power consumption state of the second functional module, the power consumption linkage between the first functional module and the second functional module is realized, avoiding the problem of power waste or low operating efficiency caused by the mismatch of power consumption states of the first functional module and the second functional module, thereby achieving the purpose of optimizing and saving the power consumption of the bridging chip.
[0041] Building upon the preceding text, this invention also provides an optional implementation method for how the power management module controls the second functional module to adjust the power consumption state, as detailed below.
[0042] When a change in the power consumption status of the first functional module is detected, the power management module generates a target instruction and sends the target instruction to the bus interface module.
[0043] The target instruction is a power consumption state adjustment instruction that matches the current power consumption state of the first functional module.
[0044] Optionally, the power management module sets a first mapping relationship between the power consumption status of the first functional module and the power consumption status of the second functional module. The first mapping relationship may be, but is not limited to, a power consumption status mapping table. When the current power consumption status of the first functional module is determined, the first mapping relationship is queried to determine the target status corresponding to the second functional module, and the corresponding target instruction is generated based on the target status.
[0045] Please refer to Table 1 below. Table 1 is a power consumption state mapping table provided in the embodiments of the present invention.
[0046] Table 1
[0047] Table 1 uses PCIe module as the first functional module and SATA module as the second functional module as an example to illustrate the power consumption state mapping table. The mapping table can be adjusted adaptively when the first and second functional modules change, but it will not be listed here.
[0048] The bus interface module is used to send target instructions to the second function module.
[0049] The second functional module is used to adjust the power consumption state according to the target instruction, so that the adjusted power consumption state matches the current power consumption state of the first functional module.
[0050] Specifically, the second functional module can adjust the power consumption status register in the second functional module according to the target instruction, and then manage the clock circuit accordingly based on the adjusted value in the power consumption status register in the second functional module to complete the power consumption status switching.
[0051] By generating a target instruction that matches the current power consumption state of the first functional module, the second functional module is precisely adjusted to achieve power consumption linkage between the first and second functional modules, enabling the power consumption states of the first and second functional modules to be quickly matched.
[0052] Building upon the preceding text, this embodiment of the invention also provides an optional implementation method for ensuring the timeliness of power consumption state adjustment of the second functional module, as detailed below.
[0053] The first functional module is used to send a first type of interrupt signal to the power management module through the first interrupt signal line when the power consumption state changes.
[0054] The first interrupt signal line is the interrupt signal line between the first functional module and the power management module.
[0055] When a first type of interrupt signal is received, the power management module reads the power status register in the first functional module through the bus interface module, obtains the current power status of the first functional module, generates a target instruction, and sends the target instruction to the second functional module.
[0056] The target instruction is a power consumption state adjustment instruction that matches the current power consumption state of the first functional module.
[0057] Specifically, the power management module sends a first type of read instruction to the bus interface module. When the bus interface module receives the first type of read instruction, it reads the first type of current value of the power status register in the first functional module. The bus interface module feeds back the read first type of current value to the power management module so that the power management module can determine the current power status of the first functional module based on the first type of current value.
[0058] By sending a first type of interrupt signal when the power consumption state of the first functional module changes, the power management module is notified as soon as the power consumption state of the first functional module changes, thereby ensuring the timeliness of the power consumption state switching of the second functional module.
[0059] Based on the foregoing, this embodiment of the invention also provides an optional implementation method, which is described below.
[0060] The power management module is also used to read the power status register in the first functional module from the bus interface module according to a preset period, obtain the current power status of the first functional module, generate a target instruction when the power status of the first functional module changes, and send the target instruction to the second functional module.
[0061] The change in the power consumption state of the first functional module refers to the fact that the current power consumption state of the first functional module is different from the historical state read last time.
[0062] When the power consumption state changes, even if the first functional module fails to send a first type of interrupt signal to the power management module in a timely manner due to hardware or software reasons, it can still adjust the power consumption state of the second functional module in a timely manner to avoid the power consumption state of the second functional module being mismatched with that of the first functional module for a long time.
[0063] Building upon the preceding text, this invention also provides an optional implementation method to ensure the accuracy of power consumption state linkage adjustment, as detailed below.
[0064] The second functional module is used to send a second type of interrupt signal to the power management module through the second interrupt signal line when the power consumption state changes.
[0065] The second interrupt signal line is the interrupt signal line between the second functional module and the power management module.
[0066] When a second type of interrupt signal is received, the power management module reads the power status register in the second functional module through the bus interface module to obtain the current power status of the second functional module and determine whether the current power status of the first functional module matches the current power status of the second functional module.
[0067] Specifically, the power management module sends a second type of read instruction to the bus interface module. When the bus interface module receives the second type of read instruction, it reads the second type of current value of the power status register in the second functional module. The bus interface module feeds back the read second type of current value to the power management module so that the power management module can determine the current power status of the second functional module based on the second type of current value.
[0068] If the current power consumption status of the first functional module does not match the current power consumption status of the second functional module, the target instruction can be sent repeatedly or an exception can be handled.
[0069] Because the power consumption state of the second functional module changes passively under the control of the adjustment instruction, a second type of interrupt signal will definitely be sent when its power consumption state changes. If a second type of interrupt signal is not received for a preset time after the target instruction is sent, it indicates that there is an abnormality and abnormality handling can be performed.
[0070] By reading the current state of the second functional module, we can further verify whether the power consumption state of the first functional module matches the power consumption state of the second functional module, thus ensuring the accuracy of the power consumption state linkage adjustment.
[0071] Please refer to Figure 2 , Figure 2 This is a second schematic diagram of the structure of a low-power bridging chip provided in an embodiment of the present invention. In an optional embodiment, the low-power bridging chip further includes a processing module, which may be, but is not limited to, a microcontroller unit (MCU), and the microcontroller unit may run based on software code.
[0072] When the current power consumption state of the first functional module matches the current power consumption state of the second functional module, the power management module sends the current operating mode to the processing module, which enables the processing module to operate based on the current operating mode.
[0073] The current operating mode is the bridge chip operating mode that matches the current power consumption state of the first functional module.
[0074] This invention also provides an optional implementation method for manually managing power consumption status; please refer to [link / reference needed]. Figure 2 The low-power bridge chip also includes a processing module, which is connected to the bus interface module via a bus.
[0075] The processing module is used to send power consumption state adjustment instructions to the first functional module and the second functional module through the bus interface module according to the target operating mode specified by the user, so that the power consumption state adjusted by the second functional module and the power consumption state adjusted by the first functional module are matched with the target operating mode.
[0076] Alternatively, when the low-power bridging chip is in manual power management mode, the processing module sends power state adjustment instructions to the first and second functional modules through the bus interface module according to the target operating mode specified by the user, so that the power state adjusted by the second functional module and the power state adjusted by the first functional module match the target operating mode.
[0077] The target operating mode can be any operating mode specified by the user through the upstream device.
[0078] In manual power management mode, the option to manage chip power consumption through configuration disables automatic power management. Users can flexibly configure the chip to enter low-power mode as needed to save power. Conversely, by selecting automatic power management, the chip can automatically switch power modes according to the usage scenario, thereby saving chip power.
[0079] In one optional implementation, the processing module is used to generate configuration instructions according to the target operating mode specified by the user, and send the configuration instructions to the bus interface module; wherein, the configuration instructions are power consumption state adjustment instructions that match the target operating mode.
[0080] The processing module establishes a second mapping relationship between various operating modes and the power consumption states of the first and second functional modules. This second mapping relationship can be, but is not limited to, a power consumption state mapping table (as shown in Table 1), and can be the same as the first mapping relationship. When determining the target operating mode, this second mapping relationship is queried to determine the power consumption states of the first and second functional modules that match the target operating mode. Based on the power consumption states that match the target operating mode, corresponding configuration instructions are generated.
[0081] The bus interface module is used to send configuration commands to the first functional module and the second functional module.
[0082] The first and second functional modules are used to adjust the power consumption state according to the configuration instructions, so that the power consumption state adjusted by the second functional module and the power consumption state adjusted by the first functional module match the target operating mode.
[0083] Building upon the preceding text, this invention also provides an optional implementation method for determining whether the power consumption state is successful; please refer to the following text.
[0084] When the current power consumption state of the first functional module matches the current power consumption state of the second functional module, the power management module sends the current operating mode to the processing module.
[0085] The current operating mode is the bridge chip operating mode that matches the current power consumption state of the first functional module.
[0086] The process by which the power management module obtains the current power consumption status of the first functional module and the second functional module is described in the relevant description above and will not be repeated here.
[0087] The processing module compares the current operating mode with the target operating mode to determine whether the power consumption state adjustment was successful. If successful, it can send feedback to the upstream device.
[0088] If the current operating mode is inconsistent with the target operating mode, or if the current operating mode is not received from the power management module, exception handling can be performed.
[0089] In one optional implementation, the processing module is also connected to a first functional module and a second functional module, which are further configured to send a fault interrupt signal to the processing module in the event of a fault.
[0090] The processing module is used to control the bridge chip to perform relevant fault interruption processing when a fault interruption signal is received.
[0091] When the first functional module is a PCIe module and the second functional module is a SATA module, the low-power bridge chip is a PCIe to SATA bridge chip. Please refer to [reference needed]. Figure 3 , Figure 3 This is a schematic diagram of the PCIe to SATA bridge chip provided in an embodiment of the present invention. Figure 3 The processing module uses an MCU as an example.
[0092] This invention also provides an electronic device including the aforementioned low-power bridge chip.
[0093] In summary, the present invention provides a low-power bridging chip and electronic device. The low-power bridging chip includes: a first functional module, a second functional module, a bus interface module, and a power management module. The bus interface module is connected to the first functional module, the second functional module, and the power management module. The first functional module is used to connect to a matched upstream device. The second functional module is used to connect to a matched downstream device. When the low-power bridging chip is in automatic power management mode, when the power management module detects a change in the power consumption state of the first functional module, it sends a power consumption state adjustment command to the second functional module through the bus interface module. By adjusting the power consumption state of the second functional module, power consumption linkage between the first and second functional modules is achieved, avoiding power waste or low operating efficiency caused by power consumption mismatch between the first and second functional modules, thus optimizing and saving the power consumption of the bridging chip.
[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
[0095] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A low-power bridging chip, characterized in that, The low-power bridge chip includes: a first functional module, a second functional module, a bus interface module, and a power management module; The bus interface module is connected to the first functional module, the second functional module, and the power management module, respectively. The first functional module is used to connect to its matched upstream device; The second functional module is used to connect to its matched downstream devices; When the low-power bridge chip is in automatic power management mode, the power management module is used to send a power state adjustment command to the second functional module through the bus interface module when it detects a change in the power state of the first functional module.
2. The low-power bridging chip as described in claim 1, characterized in that, When the power consumption status of the first functional module changes, the power consumption management module generates a target instruction and sends the target instruction to the bus interface module. The target instruction is a power consumption state adjustment instruction that matches the current power consumption state of the first functional module. The bus interface module is used to send the target instruction to the second functional module; The second functional module is used to adjust the power consumption state according to the target instruction.
3. The low-power bridging chip as described in claim 1, characterized in that, The first functional module is used to send a first type of interrupt signal to the power management module when the power consumption state changes; The power management module is used to read the power status register in the first functional module through the bus interface module when it receives the first type of interrupt signal, obtain the current power status of the first functional module, generate a target instruction, and send the target instruction to the second functional module. The target instruction is a power consumption state adjustment instruction that matches the current power consumption state of the first functional module.
4. The low-power bridging chip as described in claim 3, characterized in that, The power management module is also used to read the power status register in the first functional module through the bus interface module at a preset period to obtain the current power status of the first functional module. When the power status of the first functional module changes, the module generates a target instruction and sends the target instruction to the second functional module.
5. The low-power bridging chip as described in claim 1, characterized in that, The second functional module is used to send a second type of interrupt signal to the power management module when the power consumption state changes; When the second type of interrupt signal is received, the power management module reads the power status register in the second functional module through the bus interface module to obtain the current power status of the second functional module, and determines whether the current power status of the first functional module matches the current power status of the second functional module.
6. The low-power bridging chip as described in claim 5, characterized in that, The low-power bridging chip also includes a processing module; When the current power consumption state of the first functional module matches the current power consumption state of the second functional module, the power management module is used to send the current working mode to the processing module. The current operating mode is the bridge chip operating mode that matches the current power consumption state of the first functional module.
7. The low-power bridging chip as described in claim 1, characterized in that, The low-power bridge chip also includes a processing module, which is connected to the bus interface module. The processing module is used to send power consumption status adjustment instructions to the first functional module and the second functional module through the bus interface module according to the target working mode specified by the user.
8. The low-power bridging chip as described in claim 7, characterized in that, The processing module is used to generate configuration instructions according to the target working mode specified by the user, and send the configuration instructions to the bus interface module; The configuration instruction is a power consumption state adjustment instruction that matches the target operating mode; The bus interface module is used to send the configuration instructions to the first functional module and the second functional module; The first functional module and the second functional module are used to adjust the power consumption state according to the configuration instructions.
9. The low-power bridging chip as described in claim 7, characterized in that, When the current power consumption state of the first functional module matches the current power consumption state of the second functional module, the power management module is used to send the current working mode to the processing module. The current working mode is the bridge chip working mode that matches the current power consumption state of the first functional module. The processing module is used to compare whether the current working mode is consistent with the target working mode.
10. An electronic device, characterized in that, Includes the low-power bridge chip according to any one of claims 1-9.