Wave recording method based on FPGA and wave recording system based on FPGA

Abstract

The invention is suitable for the technical field of electronic power, and provides a wave recording method based on an FPGA and a wave recording system based on the FPGA, and the wave recording method based on the FPGA comprises the following steps: carrying out the parallel real-time sampling of a plurality of paths of driving signals through the FPGA; circularly writing the sampled driving signal into a data cache module; in response to a preset triggering condition, stopping writing the driving signal into the data caching module, and freezing cached data of the data caching module; adding a timestamp to the cache data, and analyzing the cache data to generate analysis protocol data; and transferring the cache data added with the timestamps and the analysis protocol data to an external nonvolatile storage module and transmitting the cache data and the analysis protocol data to an upper computer. According to the technical scheme of the invention, continuous high-fidelity wave recording, fault backtracking and long-term data storage can be carried out on transient signals.

Description

Technical Field

[0001] This invention belongs to the field of electronic power technology, and particularly relates to an FPGA-based waveform recording method and an FPGA-based waveform recording system. Background Technology

[0002] As the core power control device in a power electronic conversion system, the inverter's drive signal stability and accuracy are crucial to the system's energy conversion efficiency and operational safety. Currently, the industry commonly uses waveform recording devices based on general-purpose processors such as DSPs and ARM processors to monitor drive signals. However, these general-purpose processor-based waveform recording devices have the following problems: 1. Due to the limitations of the processing speed and sampling frequency of general-purpose processors, it is impossible to fully capture the microsecond-level transient signals of power devices during the switching process, resulting in the loss of detailed signals during high-frequency switching; 2. Limited storage resources result in short recording times or missing data; 3. The system response speed is slow, making it impossible to quickly locate faults and capture dynamic processes. Summary of the Invention

[0003] This invention provides an FPGA-based waveform recording method that enables continuous high-fidelity waveform recording of transient signals, fault tracing, and long-term data storage.

[0004] This invention is implemented as follows: an FPGA-based waveform recording method, comprising the following steps: Parallel real-time sampling of multiple drive signals is performed using FPGA; The sampled drive signals are cyclically written into the data cache module; In response to a preset trigger condition, the writing of the drive signal to the data cache module is stopped, and the cached data of the data cache module is frozen; Add a timestamp to the cached data and parse the cached data to generate parsing protocol data; The cached data with added timestamps and the parsing protocol data are transferred to an external non-volatile storage module and then transmitted to the host computer.

[0005] Furthermore, the step of cyclically writing the sampled drive signal into the data buffer module includes: The sampled drive signal is written into a data cache module based on Block RAM on the FPGA chip; The historical cached data in the data cache module is cyclically overwritten using a first-in, first-out (FIFO) mechanism.

[0006] Furthermore, the step of stopping the writing of the drive signal to the data cache module and freezing the cached data of the data cache module in response to a preset trigger condition includes: The activation status of the preset triggering conditions is detected in real time, and the preset triggering conditions include fault signals and host computer triggering signals; In response to the detection that any of the preset trigger conditions is activated, the write enable signal of the data cache module is turned off to stop writing to the drive signal, and the current write address pointer is frozen to lock the cached data.

[0007] Furthermore, the steps of adding a timestamp to the cached data and parsing the cached data to generate parsing protocol data include: Read cached data from the data cache module in the order it was written; Add a timestamp with microsecond precision to the read cached data; The cached data with timestamps is parsed to generate parsed protocol data containing timestamp fields, fault information fields, and file number fields.

[0008] Furthermore, after the step of transferring the timestamped cached data and the parsing protocol data to an external non-volatile storage module and transmitting them to the host computer, the method further includes: Reset the write address pointer and write enable signal of the data cache module, and return to the step of parallel real-time sampling of multiple drive signals through the FPGA.

[0009] This invention also provides an FPGA-based waveform recording system, the FPGA-based waveform recording system comprising: The signal sampling module is used to sample multiple drive signals in parallel in real time via the FPGA; The data writing module is used to cyclically write the sampled drive signal into the data buffer module; A freeze control module is used to stop writing the drive signal to the data cache module and freeze the cached data of the data cache module in response to a preset trigger condition. The protocol generation module is used to add timestamps to the cached data and parse the cached data to generate parsed protocol data; The storage and transmission module is used to transfer the cached data with added timestamps and the parsing protocol data to an external non-volatile storage module and transmit them to the host computer.

[0010] Furthermore, the data writing module includes: The writing unit is used to write the sampled drive signal into a data cache module based on Block RAM on the FPGA chip; The overlay unit is used to cyclically overwrite the historical cached data in the data cache module using a first-in-first-out (FIFO) mechanism.

[0011] Furthermore, the freeze control module includes: The detection unit is used to detect the activation status of the preset triggering conditions in real time. The preset triggering conditions include fault signals and host computer triggering signals. The freeze unit is used to, in response to the detection that any of the preset trigger conditions are activated, turn off the write enable signal of the data cache module to stop writing to the drive signal, and freeze the current write address pointer to lock the cached data.

[0012] Furthermore, the protocol generation module includes: A read unit is used to read cached data from the data cache module in the order of writing. An addition unit is used to add a timestamp with microsecond precision to the read cached data; The generation unit is used to parse the cached data with timestamps and generate parsing protocol data containing timestamp fields, fault information fields, and file number fields.

[0013] Furthermore, the FPGA-based waveform recording system also includes: The reset control module is used to reset the write address pointer and write enable signal of the data cache module, and return to the step of parallel real-time sampling of multiple drive signals through the FPGA.

[0014] The technical solution of this invention, by employing an FPGA to perform parallel real-time sampling of multiple driving signals, can capture high-frequency transient signals without loss; by cyclically writing the sampled data into the data buffer module, it achieves a dynamic balance between continuous waveform recording and limited storage resources, avoiding data overflow; by freezing the buffer data in response to preset trigger conditions, it can accurately lock the complete waveform of the fault transient, avoiding the loss of critical data; by adding timestamps to the frozen buffer data and parsing it to generate parsing protocol data, it preserves the integrity of the data, thus meeting the needs of data analysis and fault diagnosis; by synchronously transferring the buffer data and parsing protocol data to an external non-volatile storage module and uploading it to the host computer, it achieves permanent data storage and real-time interaction, providing dual protection for fault backtracking and system optimization. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the first embodiment of the FPGA-based waveform recording method provided by the present invention. Figure 2 yes Figure 1 A flowchart illustrating an embodiment of step S2; Figure 3 yes Figure 1 A flowchart illustrating an embodiment of step S3; Figure 4 yes Figure 1 A flowchart illustrating an embodiment of step S4; Figure 5 A flowchart illustrating the second embodiment of the FPGA-based waveform recording method provided by this invention; Figure 6 The structural block diagram of the first embodiment of the FPGA-based waveform recording system provided by the present invention; Figure 7 The structural block diagram of the second embodiment of the FPGA-based waveform recording system provided by the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0017] Existing waveform recording technologies primarily rely on general-purpose processors to serially sample drive signals, and their software response is often sluggish, leading to signal distortion and loss of critical data. Furthermore, limitations in storage resources result in short recording times and incomplete data storage. In contrast, this invention utilizes an FPGA to achieve parallel real-time sampling of multiple drive signals and cyclically writes the sampled data to a data buffer module, thus overcoming limitations in sampling rate and storage duration. By freezing the buffered data in response to preset trigger conditions, the complete waveform of fault transients can be accurately locked, preventing the loss of critical data. Timestamps are added to the buffered data, and parsing protocol data is generated. The buffered data and parsing protocol data are then synchronously transferred to an external non-volatile storage module and uploaded to a host computer, achieving permanent data backup and real-time interaction, providing dual protection for fault backtracking and system optimization.

[0018] Example 1 Reference Figure 1 This invention provides a waveform recording method based on FPGA, comprising the following steps: Step S1: Parallel real-time sampling of multiple drive signals is performed using the FPGA; In this embodiment, the FPGA (Field-Programmable Gate Array) is a programmable logic device with parallel processing capabilities, enabling microsecond-level real-time parallel sampling, cyclic buffering, and trigger control of multiple drive signals. Multiple drive signals refer to the multiple electrical signals used in power electronic devices to control the on / off state of power devices. In specific applications, this can be manifested as the drive signals of each arm of an inverter, such as the six drive signals for each of the three phases of a photovoltaic inverter, i.e., three signals for each upper and lower arm of each phase, for a total of six signals. The multi-channel synchronous ADC controller configured within the FPGA can be used to perform parallel real-time sampling of the multiple drive signals.

[0019] Step S2: The sampled drive signals are cyclically written into the data buffer module; After the FPGA performs parallel real-time sampling of multiple drive signals, the sampled data will be continuously written to the data cache module built on the FPGA's on-chip Block RAM.

[0020] Reference Figure 2 In one specific embodiment, step S2 includes: Step S21: Write the sampled drive signal into the data cache module composed of Block RAM on the FPGA chip; Step S22: The historical cached data in the data cache module is cyclically overwritten using a first-in-first-out (FIFO) mechanism.

[0021] The data cache module is a high-speed cache unit built using the Block RAM (Block Random Access Memory) integrated on the FPGA. Block RAM is a dedicated hardware storage resource inside the FPGA, with microsecond-level read and write speeds, which can meet the real-time storage requirements of microsecond-level signals. The sampled multi-channel drive signals are written to the data cache module through the FPGA's parallel sampling logic to achieve real-time temporary storage of data.

[0022] First-In-First-Out (FIFO) refers to a management mechanism where cached data is read out sequentially according to the order it was written. When the storage capacity of the data cache module reaches its limit, newly written drive signals will automatically overwrite the oldest historical cached data according to the FIFO principle, forming a cyclic overwrite effect. This ensures that the acquisition process of drive signals is not interrupted due to insufficient storage space. With this setting, the system can continuously and uninterruptedly record microsecond-level high-frequency drive signals, providing complete timing waveform data for subsequent cache data freezing and fault analysis in the event of a fault.

[0023] Step S3: In response to a preset trigger condition, stop writing the drive signal to the data cache module and freeze the cached data of the data cache module; The preset trigger conditions include fault signals detected by the system, such as overcurrent signals, overvoltage signals, overheat signals, or trigger commands sent by the user through the host computer. When a preset trigger condition is detected to be activated, i.e., when any fault signal or host computer trigger command is detected, the write enable signal of the data cache module is turned off to stop the subsequent sampled drive signals from being written to the data cache module, and the write address pointer of the data cache module is locked, so that the cached data already stored is locked to prevent subsequent new data from overwriting critical waveform data.

[0024] Reference Figure 3 In one specific embodiment, step S3 includes: step S31, real-time detection of the activation status of the preset triggering condition, wherein the preset triggering condition includes a fault signal and a host computer triggering signal; Step S32: In response to detecting that any of the preset trigger conditions are activated, the write enable signal of the data cache module is turned off to stop writing to the drive signal; and the current write address pointer is frozen to lock the cached data.

[0025] Fault signals refer to abnormal state signals that occur during the operation of power electronic equipment such as inverters, such as overcurrent signals, overvoltage signals, overheating signals, or power device failure signals. These signals can be generated by sensors or corresponding detection circuits inside the equipment and transmitted to the FPGA. The host computer trigger signal refers to a trigger command manually sent through the human-machine interface to actively initiate the waveform recording process in non-fault scenarios. The write enable signal is a control logic signal used to control the data cache module to perform write operations. Once the write enable signal is turned off, the data cache module will stop receiving new drive signals to prevent critical waveforms from being overwritten. The write address pointer represents the index value of the current write position in the data cache module, used to mark the timing order of data storage. After the write address pointer is frozen, the write position of the data cache module is locked, thus ensuring that the stored cached data remains unchanged.

[0026] Specifically, the built-in logic control unit scans the input signal channels in real time to determine whether a fault signal or a host computer trigger signal is received. Once a fault signal or host computer trigger signal is detected, it is determined that the preset trigger condition has been activated. At this time, the system shuts down the write enable signal of the data cache module and freezes the current write address pointer, thus locking the complete signals within the data cache module and forming static data available for analysis. This provides accurate raw data for subsequent generation of protocol data and transfer of cached data. This configuration enables a rapid response to the detection of fault signals or host computer trigger signals and the freezing of cached data, ensuring that the drive signal state at the moment of fault or manual trigger is completely captured, meeting the high-precision requirements of power electronic systems for fault tracing and dynamic process analysis.

[0027] Step S4: Add a timestamp to the cached data and parse the cached data to generate parsing protocol data; The timestamp is a microsecond-precision time stamp generated by the FPGA's internal logic, used to record the sampling time of each set of cached data. The parsing protocol data refers to structured data containing key information needed for fault analysis, specifically including timestamps, parsing file numbers, fault information, and parsing schemes.

[0028] After stopping the writing of drive signals and freezing the cached data in the data cache module, the current time is read from the real-time clock module through built-in logic, and a timestamp corresponding to the cached data is generated to achieve precise alignment between data and time. The frozen cached data is then analyzed and processed to extract key features such as signal amplitude and frequency change trends before and after the trigger time, and preset trigger condition types, and combined with the system's preset logic rules to generate parsing protocol data.

[0029] Reference Figure 4 In one specific embodiment, step S4 includes: Step S41: Read cached data from the data cache module in the writing order; Step S42: Add a timestamp with microsecond precision to the read cached data; Step S43: Parse the cached data with timestamps to generate parsing protocol data containing timestamp field, fault information field and file number field.

[0030] In this embodiment, the timestamp field is used to record the precise moment when the cached data is sampled; the fault information field is used to identify the reason for triggering waveform recording, such as overcurrent, overvoltage, overheating, or manual triggering command from the host computer; the file number field is used to uniquely identify the file number of the current waveform recording task for data management and traceability.

[0031] After stopping the write drive signal and freezing the buffered data, the FPGA switches the operating mode of the data buffer module from cyclic write to sequential read. The FPGA reads the current time from the built-in real-time clock module and, combined with the write address pointer of the data buffer module, generates a corresponding microsecond-precision timestamp for each set of read buffered data. Then, feature extraction is performed on the timestamped buffered data, such as analyzing whether the signal amplitude exceeds a preset threshold, determining the fault type, and generating a fault information field; a unique file number field is generated based on the system's preset waveform recording task numbering rules, such as the timestamp and device ID. This ensures that the waveform recording data has complete time traceability and fault diagnosis value.

[0032] Step S5: The cached data with added timestamps and the parsing protocol data are transferred to an external non-volatile storage module and transmitted to the host computer.

[0033] External non-volatile storage modules refer to storage media independent of the FPGA, used for long-term storage of waveform recording data. These modules can be FLASH memory or EEPROM, and are designed to ensure data integrity even after power failure, meeting the reliability requirements for storing fault data in power electronic equipment. The host computer refers to a terminal device with data processing and analysis capabilities. It can connect to the FPGA via an SPI interface to receive and parse the waveform recording data, allowing users to view signal waveforms, fault information, and statistical analysis results through a graphical interface.

[0034] The FPGA packages the timestamped cached data and parsing protocol data into a pre-defined format to form a complete waveform recording file, and then sends the packaged waveform recording file to the non-volatile storage module. The stored waveform recording file is then transmitted to the host computer via the SPI interface, fulfilling the requirements for reliable data storage and remote analysis.

[0035] The technical solution of this invention uses FPGA to perform parallel real-time sampling of multiple driving signals to achieve lossless capture of high-frequency transient signals. The sampled data is cyclically written to a data buffer module to achieve continuous waveform recording. The buffer data is frozen in response to preset trigger conditions to accurately lock the complete waveform of the fault moment or critical event, avoiding the loss of critical data. A timestamp is added to the frozen data and parsing is used to generate parsing protocol data, preserving the integrity of the original data and the readability of the parsed data, meeting the needs of fault analysis. The timestamped buffer data and parsing protocol data are synchronously transferred to an external non-volatile storage module and uploaded to the host computer to achieve permanent data storage and real-time interaction, providing dual protection for fault backtracking and system optimization.

[0036] Example 2 Reference Figure 5 In this embodiment, after step S5, the method further includes: Step S6: Reset the write address pointer and write enable signal of the data cache module, and return to the step of parallel real-time sampling of multiple drive signals through FPGA.

[0037] The FPGA sends a reset signal to the data cache module through its internal logic control unit, forcibly setting the write address pointer of the data cache module to its initial value to unlock the write address pointer from the freeze operation. Simultaneously, the write enable signal is reactivated, releasing the blockade on write operations to the data cache module and allowing new drive signals to be written. After the reset, the system automatically restarts parallel real-time sampling of multiple drive signals and enters the next recording cycle. Through the reset operation, the system can quickly restore its initial state after a recording cycle, supporting long-term uninterrupted monitoring of power electronic equipment. This configuration eliminates the need for the data cache module to reinitialize its hardware after each recording cycle; only the write address pointer and write enable signal need to be reset via software logic, significantly improving the utilization efficiency of FPGA resources and reducing system power consumption. The reset mechanism also clears invalid data generated by abnormal triggers in the data cache module, ensuring the accuracy of subsequent recording data and enhancing the system's anti-interference capability.

[0038] Example 3 Reference Figure 6 The present invention also provides an FPGA-based waveform recording system, the FPGA-based waveform recording system comprising: The signal sampling module 100 is used to sample multiple drive signals in parallel in real time via FPGA; In this embodiment, the FPGA (Field-Programmable Gate Array) is a programmable logic device with parallel processing capabilities, enabling microsecond-level real-time parallel sampling, cyclic buffering, and trigger control of multiple drive signals. Multiple drive signals refer to the multiple electrical signals used in power electronic devices to control the on / off state of power devices. In specific applications, this can be manifested as the drive signals of each arm of an inverter, such as the six drive signals for each of the three phases of a photovoltaic inverter, i.e., three signals for each upper and lower arm of each phase, for a total of six signals. The multi-channel synchronous ADC controller configured within the FPGA can be used to perform parallel real-time sampling of the multiple drive signals.

[0039] The data writing module 200 is used to cyclically write the sampled driving signal into the data buffer module; After the FPGA performs parallel real-time sampling of multiple drive signals, the sampled data will be continuously written to the data cache module built on the FPGA's on-chip Block RAM.

[0040] In one specific embodiment, the data writing module 200 includes: The writing unit is used to write the sampled drive signal into a data cache module composed of Block RAM on the FPGA chip; The overlay unit is used to cyclically overwrite the historical cached data in the data cache module using a first-in-first-out (FIFO) mechanism.

[0041] The data cache module is a high-speed cache unit built using the Block RAM (Block Random Access Memory) integrated on the FPGA. Block RAM is a dedicated hardware storage resource inside the FPGA, with microsecond-level read and write speeds, which can meet the real-time storage requirements of microsecond-level signals. The sampled multi-channel drive signals are written to the data cache module through the FPGA's parallel sampling logic to achieve real-time temporary storage of data.

[0042] First-In-First-Out (FIFO) refers to a management mechanism where cached data is read out sequentially according to the order it was written. When the storage capacity of the data cache module reaches its limit, newly written drive signals will automatically overwrite the oldest historical cached data according to the FIFO principle, forming a cyclic overwrite effect. This ensures that the acquisition process of drive signals is not interrupted due to insufficient storage space. With this setting, the system can continuously and uninterruptedly record microsecond-level high-frequency drive signals, providing complete timing waveform data for subsequent cache data freezing and fault analysis in the event of a fault.

[0043] The freeze control module 300 is used to stop writing the drive signal to the data cache module and freeze the cached data of the data cache module in response to a preset trigger condition. The preset trigger conditions include fault signals detected by the system, such as overcurrent signals, overvoltage signals, overheat signals, or trigger commands sent by the user through the host computer. When a preset trigger condition is detected to be activated, i.e., when any fault signal or host computer trigger command is detected, the write enable signal of the data cache module is turned off to stop the subsequent sampled drive signals from being written to the data cache module, and the write address pointer of the data cache module is locked, so that the cached data already stored is locked to prevent subsequent new data from overwriting critical waveform data.

[0044] In one specific embodiment, the freeze control module 300 includes: The detection unit is used to detect the activation status of the preset triggering conditions in real time. The preset triggering conditions include fault signals and host computer triggering signals. The freeze unit is used to, in response to the detection that any of the preset trigger conditions are activated, turn off the write enable signal of the data cache module to stop writing to the drive signal; and freeze the current write address pointer to lock the cached data.

[0045] Fault signals refer to abnormal state signals that occur during the operation of power electronic equipment such as inverters, such as overcurrent signals, overvoltage signals, overheating signals, or power device failure signals. These signals can be generated by sensors or corresponding detection circuits inside the equipment and transmitted to the FPGA. The host computer trigger signal refers to a trigger command manually sent through the human-machine interface to actively initiate the waveform recording process in non-fault scenarios. The write enable signal is a control logic signal used to control the data cache module to perform write operations. Once the write enable signal is turned off, the data cache module will stop receiving new drive signals to prevent critical waveforms from being overwritten. The write address pointer represents the index value of the current write position in the data cache module, used to mark the timing order of data storage. After the write address pointer is frozen, the write position of the data cache module is locked, thus ensuring that the stored cached data remains unchanged.

[0046] Specifically, the built-in logic control unit scans the input signal channels in real time to determine whether a fault signal or a host computer trigger signal is received. Once a fault signal or host computer trigger signal is detected, it is determined that the preset trigger condition has been activated. At this time, the system shuts down the write enable signal of the data cache module and freezes the current write address pointer, thus locking the complete signals within the data cache module and forming static data available for analysis. This provides accurate raw data for subsequent generation of protocol data and transfer of cached data. This configuration enables a rapid response to the detection of fault signals or host computer trigger signals and the freezing of cached data, ensuring that the drive signal state at the moment of fault or manual trigger is completely captured, meeting the high-precision requirements of power electronic systems for fault tracing and dynamic process analysis.

[0047] The protocol generation module 400 is used to add timestamps to the cached data and parse the cached data to generate parsed protocol data; The timestamp is a microsecond-precision time stamp generated by the FPGA's internal logic, used to record the sampling time of each set of cached data. The parsing protocol data refers to structured data containing key information needed for fault analysis, specifically including timestamps, parsing file numbers, fault information, and parsing schemes.

[0048] After stopping the writing of drive signals and freezing the cached data in the data cache module, the current time is read from the real-time clock module through built-in logic, and a timestamp corresponding to the cached data is generated to achieve precise alignment between data and time. The frozen cached data is then analyzed and processed to extract key features such as signal amplitude and frequency change trends before and after the trigger time, and preset trigger condition types, and combined with the system's preset logic rules to generate parsing protocol data.

[0049] In one specific embodiment, the protocol generation module 400 includes: A read unit is used to read cached data from the data cache module in the order of writing. An addition unit is used to add a timestamp with microsecond precision to the read cached data; The generation unit is used to parse the cached data with timestamps and generate parsing protocol data containing timestamp fields, fault information fields, and file number fields.

[0050] In this embodiment, the timestamp field is used to record the precise moment when the cached data is sampled; the fault information field is used to identify the reason for triggering waveform recording, such as overcurrent, overvoltage, overheating, or manual triggering command from the host computer; the file number field is used to uniquely identify the file number of the current waveform recording task for data management and traceability.

[0051] After stopping the write drive signal and freezing the buffered data, the FPGA switches the operating mode of the data buffer module from cyclic write to sequential read. The FPGA reads the current time from the built-in real-time clock module and, combined with the write address pointer of the data buffer module, generates a corresponding microsecond-precision timestamp for each set of read buffered data. Then, feature extraction is performed on the timestamped buffered data, such as analyzing whether the signal amplitude exceeds a preset threshold, determining the fault type, and generating a fault information field; a unique file number field is generated based on the system's preset waveform recording task numbering rules, such as the timestamp and device ID. This ensures that the waveform recording data has complete time traceability and fault diagnosis value.

[0052] The storage and transmission module 500 is used to transfer the cached data with added timestamps and the parsing protocol data to an external non-volatile storage module and transmit them to the host computer.

[0053] External non-volatile storage modules refer to storage media independent of the FPGA, used for long-term storage of waveform recording data. These modules can be FLASH memory or EEPROM, and are designed to ensure data integrity even after power failure, meeting the reliability requirements for storing fault data in power electronic equipment. The host computer refers to a terminal device with data processing and analysis capabilities. It can connect to the FPGA via an SPI interface to receive and parse the waveform recording data, allowing users to view signal waveforms, fault information, and statistical analysis results through a graphical interface.

[0054] The FPGA packages the timestamped cached data and parsing protocol data into a pre-defined format to form a complete waveform recording file, and then sends the packaged waveform recording file to the non-volatile storage module. The stored waveform recording file is then transmitted to the host computer via the SPI interface, fulfilling the requirements for reliable data storage and remote analysis.

[0055] The technical solution of this invention uses FPGA to perform parallel real-time sampling of multiple driving signals to achieve lossless capture of high-frequency transient signals. The sampled data is cyclically written to a data buffer module to achieve continuous waveform recording. The buffer data is frozen in response to preset trigger conditions to accurately lock the complete waveform of the fault moment or critical event, avoiding the loss of critical data. A timestamp is added to the frozen data and parsing is used to generate parsing protocol data, preserving the integrity of the original data and the readability of the parsed data, meeting the needs of fault analysis. The timestamped buffer data and parsing protocol data are synchronously transferred to an external non-volatile storage module and uploaded to the host computer to achieve permanent data storage and real-time interaction, providing dual protection for fault backtracking and system optimization.

[0056] Example 4 Reference Figure 7 Compared with the above embodiments, the FPGA-based waveform recording system provided in this embodiment also includes a reset control module 600.

[0057] The reset control module 600 is used to reset the write address pointer and write enable signal of the data cache module, and return to the step of parallel real-time sampling of multiple drive signals through the FPGA.

[0058] The FPGA sends a reset signal to the data cache module through its internal logic control unit, forcibly setting the write address pointer of the data cache module to its initial value to unlock the write address pointer from the freeze operation. Simultaneously, the write enable signal is reactivated, releasing the blockade on write operations to the data cache module and allowing new drive signals to be written. After the reset, the system automatically restarts parallel real-time sampling of multiple drive signals and enters the next recording cycle. Through the reset operation, the system can quickly restore its initial state after a recording cycle, supporting long-term uninterrupted monitoring of power electronic equipment. This configuration eliminates the need for the data cache module to reinitialize its hardware after each recording cycle; only the write address pointer and write enable signal need to be reset via software logic, significantly improving the utilization efficiency of FPGA resources and reducing system power consumption. The reset mechanism also clears invalid data generated by abnormal triggers in the data cache module, ensuring the accuracy of subsequent recording data and enhancing the system's anti-interference capability.

[0059] It is understood that those skilled in the art can combine various implementation methods in the above embodiments under the guidance of the above examples to obtain technical solutions with multiple implementation methods.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A waveform recording method based on FPGA, characterized in that, The FPGA-based waveform recording method includes the following steps: Parallel real-time sampling of multiple drive signals is performed using FPGA; The sampled drive signals are cyclically written into the data cache module; In response to a preset trigger condition, the writing of the drive signal to the data cache module is stopped, and the cached data of the data cache module is frozen; Add a timestamp to the cached data and parse the cached data to generate parsing protocol data; The cached data with added timestamps and the parsing protocol data are transferred to an external non-volatile storage module and then transmitted to the host computer.

2. The FPGA-based waveform recording method as described in claim 1, characterized in that, The step of cyclically writing the sampled drive signal into the data buffer module includes: The sampled drive signal is written into a data cache module based on Block RAM on the FPGA chip; The historical cached data in the data cache module is cyclically overwritten using a first-in, first-out (FIFO) mechanism.

3. The FPGA-based waveform recording method as described in claim 1, characterized in that, The steps of stopping the writing of the drive signal to the data cache module and freezing the cached data of the data cache module in response to a preset trigger condition include: The activation status of the preset triggering conditions is detected in real time, and the preset triggering conditions include fault signals and host computer triggering signals; In response to the detection that any of the preset trigger conditions is activated, the write enable signal of the data cache module is turned off to stop writing to the drive signal, and the current write address pointer is frozen to lock the cached data.

4. The FPGA-based waveform recording method as described in claim 1, characterized in that, The steps of adding a timestamp to the cached data and parsing the cached data to generate parsing protocol data include: Read cached data from the data cache module in the order it was written; Add a timestamp with microsecond precision to the read cached data; The cached data with timestamps is parsed to generate parsed protocol data containing timestamp fields, fault information fields, and file number fields.

5. The FPGA-based waveform recording method as described in any one of claims 1 to 4, characterized in that, After the step of transferring the cached data with added timestamps and the parsing protocol data to an external non-volatile storage module and transmitting them to the host computer, the method further includes: Reset the write address pointer and write enable signal of the data cache module, and return to the step of parallel real-time sampling of multiple drive signals through the FPGA.

6. A waveform recording system based on FPGA, characterized in that, The FPGA-based waveform recording system includes: The signal sampling module is used to sample multiple drive signals in parallel in real time via the FPGA; The data writing module is used to cyclically write the sampled drive signal into the data buffer module; A freeze control module is used to stop writing the drive signal to the data cache module and freeze the cached data of the data cache module in response to a preset trigger condition. The protocol generation module is used to add timestamps to the cached data and parse the cached data to generate parsed protocol data; The storage and transmission module is used to transfer the cached data with added timestamps and the parsing protocol data to an external non-volatile storage module and transmit them to the host computer.

7. The FPGA-based waveform recording system as described in claim 6, characterized in that, The data writing module includes: The writing unit is used to write the sampled drive signal into a data cache module composed of Block RAM on the FPGA chip; The overlay unit is used to cyclically overwrite the historical cached data in the data cache module using a first-in-first-out (FIFO) mechanism.

8. The FPGA-based waveform recording system as described in claim 6, characterized in that, The freeze control module includes: The detection unit is used to detect the activation status of the preset triggering conditions in real time. The preset triggering conditions include fault signals and host computer triggering signals. The freeze unit is used to, in response to the detection that any of the preset trigger conditions are activated, turn off the write enable signal of the data cache module to stop writing to the drive signal, and freeze the current write address pointer to lock the cached data.

9. The FPGA-based waveform recording system as described in claim 6, characterized in that, The protocol generation module includes: A read unit is used to read cached data from the data cache module in the order of writing. An addition unit is used to add a timestamp with microsecond precision to the read cached data; The generation unit is used to parse the cached data with timestamps and generate parsing protocol data containing timestamp fields, fault information fields, and file number fields.

10. The FPGA-based waveform recording system as described in any one of claims 6 to 9, characterized in that, The FPGA-based waveform recording system also includes: The reset control module is used to reset the write address pointer and write enable signal of the data cache module, and return to the step of parallel real-time sampling of multiple drive signals through the FPGA.

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