Organic light emitting diode display panel and image display method thereof

Abstract

The invention discloses an organic light emitting diode display panel and an image display method thereof. The organic light-emitting diode display panel comprises at least one first power line, at least one second power line and a plurality of pixel units, each pixel unit comprises a light-emitting module, a driving module and a black frame insertion control module, and the light-emitting modules are electrically connected between the first power lines and the second power lines. The driving module is electrically connected between the first power line and the light-emitting module and used for driving the light-emitting module to emit light in the light-emitting stage, one end of the black insertion control module is electrically connected with the driving module, and the other end of the black insertion control module is electrically connected with the second power line. The black frame insertion control module is used for closing the driving module in a plurality of different time periods in the light-emitting stage, so that the driving module stops driving the light-emitting module to emit light, and the light-emitting pulse width of the light-emitting module is divided into a plurality of non-equal molecular fields. According to the display panel, the display frame is uniform, the display effect is improved, and the gray scale digit is increased.

Description

Technical Field

[0001] This application relates to the field of display panel driving technology, specifically to an organic light-emitting diode display panel and its image display method. Background Technology

[0002] In recent years, organic light-emitting diode (OLED) display panels have gradually become the subject of research due to their high color gamut and high contrast characteristics. Based on the driving method, OLED display panels can be divided into passive-matrix OLED (PMOLED) and active-matrix OLED (AMOLED). AMOLED is widely used because of its low transient current and ease of achieving high-resolution displays.

[0003] However, the TFTs (Thin film transistors) in traditional active-drive organic electroluminescent display panels are prone to threshold voltage shift under long-term current pressure, which causes the light-emitting device in the organic electroluminescent display panel to lose brightness and result in uneven display images. Summary of the Invention

[0004] This application provides an organic light-emitting diode (OLED) display panel and its image display method, which solves the technical problem that threshold voltage shift occurs under long-term current pressure, resulting in uneven display images on the organic electroluminescent display panel.

[0005] In a first aspect, embodiments of this application provide an organic light-emitting diode (OLED) display panel, the OLED display panel including a first power line, a second power line, and a pixel circuit, the pixel circuit including:

[0006] A light-emitting module electrically connected to the second power line;

[0007] A driving module electrically connected between the first power line and the light-emitting module, the driving module being used to drive the light-emitting module to emit light; and

[0008] A black-insertion control module is provided, one end of which is electrically connected to the driving module and the other end of which is electrically connected to the second power line. The black-insertion control module is used to turn off the driving module a predetermined number of times during the light-emitting stage, so that the driving module stops driving the light-emitting module to emit light for the predetermined number of times. At least two of the predetermined number of times the black-insertion control module turns off the driving module have different durations.

[0009] In some embodiments, the organic light-emitting diode display panel further includes a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a data signal line, a light emission control signal line, a read signal line, and a detection signal line;

[0010] The light-emitting module includes at least one light-emitting device;

[0011] The driving module includes:

[0012] A capacitor, wherein the first plate of the capacitor is electrically connected to the anode end of the light-emitting device;

[0013] A first transistor, wherein the gate of the first transistor is electrically connected to the second plate of the capacitor, and one of the source and drain of the first transistor is electrically connected to the anode of the light-emitting device.

[0014] A second transistor, the gate of which is electrically connected to the read signal line, one of the source and drain of the second transistor being electrically connected to the other of the source and drain of the first transistor, and the other of the source and drain of the second transistor being electrically connected to the detection signal line.

[0015] A third transistor, wherein the gate of the third transistor is electrically connected to the first scan signal line, one of the source and drain of the third transistor is electrically connected to the data signal line, and the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor.

[0016] A fourth transistor, wherein the gate of the fourth transistor is electrically connected to the second scan signal line, one of the source and drain of the fourth transistor is electrically connected to the other of the source and drain of the first transistor, and the other of the source and drain of the fourth transistor is electrically connected to the gate of the first transistor.

[0017] A fifth transistor, wherein the gate of the fifth transistor is electrically connected to the light-emitting control signal line, one of the source and drain of the fifth transistor is electrically connected to the first power supply line, and the other of the source and drain of the fifth transistor is electrically connected to the other of the source and drain of the first transistor; and

[0018] A sixth transistor, wherein the gate of the sixth transistor is electrically connected to the third scan signal line, one of the source and drain of the sixth transistor is electrically connected to the second power supply line, and the other of the source and drain of the sixth transistor is electrically connected to the anode of the light-emitting device.

[0019] The black-insertion control module includes:

[0020] A seventh transistor, the gate of which is electrically connected to the fourth scan signal line, one of the source and drain of which is electrically connected to the second power supply line, and the other of the source and drain of which is electrically connected to the gate of the first transistor.

[0021] During the light-emitting phase of the light-emitting device, the seventh transistor is used to pull down the gate voltage of the first transistor a predetermined number of times under the control of the scan signal transmitted by the fourth scan signal line, wherein at least two of the predetermined number of times the seventh transistor pulls down the gate voltage of the first transistor have different durations.

[0022] In some embodiments, the light emission stage includes multiple sub-time periods, and one of the sub-time periods includes a light emission control sub-time period and a light emission insertion sub-time period;

[0023] During the light emission control sub-period, the light emission control signal transmitted by the light emission control signal line is at a high potential, while the threshold voltage read signal transmitted by the read signal line, the data signal transmitted by the data signal line, the first scan signal transmitted by the first scan line, the second scan signal transmitted by the second scan line, the third scan signal transmitted by the third scan line, and the fourth scan signal transmitted by the fourth scan line are all at a low potential.

[0024] During the period of light emission and black spot insertion, the light emission control signal and the fourth scan signal are both at high potentials, the threshold voltage reading signal, the data signal, the first scan signal are at high potentials, and the second scan signal and the third scan signal are all at low potentials.

[0025] In some embodiments, the duration of the (n+1)th light-emitting black-insertion sub-segment is equal to twice the duration of the nth light-emitting black-insertion sub-segment, and the durations of any two sub-segments are equal, where n is a positive integer.

[0026] In some embodiments, during the light emission phase, the light emission control sub-period and the light emission insertion sub-period alternate, and the light emission control sub-period and the light emission insertion sub-period are continuous;

[0027] In the sub-time period, the light emission control sub-time period precedes the light emission insertion sub-time period.

[0028] Secondly, embodiments of this application also provide an image display method for an organic light-emitting diode (OLED) display panel. The pixel circuit of the OLED display panel includes a light-emitting module, a driving module, and a black-insertion control module. The driving cycle for the OLED display panel to display one frame of an image includes a light-emitting phase.

[0029] The image display method includes the following steps:

[0030] During the light-emitting phase, the driving module drives the light-emitting module to emit light;

[0031] During the light-emitting phase, the black-insertion control module shuts down the driving module a predetermined number of times, causing the driving module to stop driving the light-emitting module to emit light for the predetermined number of times. At least two of the predetermined number of times the black-insertion control module shuts down the driving module have different durations.

[0032] In some embodiments, the organic light-emitting diode display panel includes a first power line, a second power line, a first scan line, a second scan line, a third scan line, and a fourth scan line; the driving module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor; the black-insertion control module includes a seventh transistor, the gate of which is electrically connected to the fourth scan signal line; one of the source and drain of the seventh transistor is electrically connected to the second power line; and the other of the source and drain of the seventh transistor is electrically connected to the gate of the first transistor.

[0033] During the light-emitting phase, the black-insertion control module shuts down the driving module a predetermined number of times, causing the driving module to stop driving the light-emitting module to emit light. The predetermined number of times includes:

[0034] During the light-emitting phase, the seventh transistor, under the control of the scan signal transmitted by the fourth scan signal line, pulls down the gate voltage of the first transistor a predetermined number of times, wherein at least two of the predetermined number of times the seventh transistor pulls down the gate voltage of the first transistor have different durations.

[0035] In some embodiments, the light emission stage includes multiple sub-time periods, and one of the sub-time periods includes a light emission control sub-time period and a light emission insertion sub-time period;

[0036] During the light emission control sub-period, the light emission control signal transmitted by the light emission control signal line is at a high potential, while the threshold voltage read signal transmitted by the read signal line, the data signal transmitted by the data signal line, the first scan signal transmitted by the first scan line, the second scan signal transmitted by the second scan line, the third scan signal transmitted by the third scan line, and the fourth scan signal transmitted by the fourth scan line are all at a low potential.

[0037] During the period of light emission and black spot insertion, the light emission control signal and the fourth scan signal are both at high potentials, while the threshold voltage reading signal, the data signal, the first scan signal are at high potentials, and the second scan signal and the third scan signal are all at low potentials.

[0038] In some embodiments, the duration of the (n+1)th light-emitting black-insertion sub-segment is equal to twice the duration of the nth light-emitting black-insertion sub-segment, and the durations of any two sub-segments are equal, where n is a positive integer.

[0039] In some embodiments, during the light emission phase, the light emission control sub-period and the light emission insertion sub-period alternate, and the light emission control sub-period and the light emission insertion sub-period are continuous;

[0040] In the sub-time period, the light emission control sub-time period precedes the light emission insertion sub-time period.

[0041] This application provides an organic light-emitting diode (OLED) display panel and its image display method. The OLED display panel includes at least one first power line, at least one second power line, and multiple pixel circuits. Each pixel circuit includes the first power line, the second power line, a light-emitting module, a driving module, and a black-pinning control module. The light-emitting module is electrically connected between the first power line and the second power line. The driving module is electrically connected between the first power line and the light-emitting module and is used to drive the light-emitting module to emit light during the light-emitting phase. One end of the black-pinning control module is electrically connected to the driving module, and the other end is electrically connected to the second power line. The black-pinning control module is used to turn off the driving module for multiple different durations after the light-emitting phase, thereby stopping the driving module from driving the light-emitting module to emit light, and dividing the pulse width of the light-emitting module's emission into multiple non-uniform molecular fields. The black-pinning control module provided in this application can control the switching of the driving module, thereby reducing the current pressure on the transistors in the driving module, making the displayed image on the display panel uniform, and thus improving the display effect of the display panel. In addition, by setting a black insertion control module to insert black into the light-emitting module, the pulse width of the light-emitting module is adjusted from an iso-molecular field to a non-iso-molecular field, thereby increasing the number of gray levels. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of an organic light-emitting diode display panel provided in an embodiment of this application.

[0043] Figure 2 This is a circuit diagram of an organic light-emitting diode display panel provided in an embodiment of this application.

[0044] Figure 3 A timing diagram of an organic light-emitting diode display panel provided in an embodiment of this application.

[0045] Figure 4 The organic light-emitting diode display panel provided in the embodiments of this application is in Figure 3 The diagram shows the path of the initialization phase under the driving timing.

[0046] Figure 5 The organic light-emitting diode display panel provided in the embodiments of this application is in Figure 3 The diagram shows the path of the threshold voltage detection stage under the driving timing.

[0047] Figure 6 The organic light-emitting diode display panel provided in the embodiments of this application is in Figure 3 The diagram shows the path for the threshold voltage reading stage under the driving timing.

[0048] Figure 7 The organic light-emitting diode display panel provided in the embodiments of this application is in Figure 3 The diagram shows the data writing stage path under the driving timing.

[0049] Figure 8 The organic light-emitting diode display panel provided in the embodiments of this application is in Figure 3 The diagram shows the path of the light emission stage under the driving timing.

[0050] Figure 9 The organic light-emitting diode display panel provided in the embodiments of this application is in Figure 3 The diagram shows the path of the black insertion stage under the driving timing.

[0051] Figure 10 This is a schematic diagram of the distribution of non-equimolecular fields in an organic light-emitting diode display panel provided in an embodiment of this application. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. The described embodiments are only used to explain the ideas of the present invention and should not be regarded as limiting the scope of protection of this application.

[0053] Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly specified.

[0054] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0055] To address the brightness decay caused by threshold voltage offset, numerous compensation circuits have been developed. However, for Mini LED and Micro LED, the voltage grayscale segmentation method can lead to uneven brightness in low grayscale displays, primarily because the light-emitting device emits light unevenly under low current.

[0056] To avoid uneven brightness and threshold voltage shift caused by low current operation of the display panel, an external compensation circuit combined with time-division grayscale PWM (Pulse Width Modulation) driving mode can be used. This ensures that the display panel's light-emitting devices always operate in a stable high-current emission phase, thus preventing uneven display and achieving threshold voltage compensation. However, the external compensation circuit combined with PWM driving mode still faces the problem of a limited number of grayscale levels, and poor light emission stability can still easily lead to poor display uniformity.

[0057] To avoid uneven brightness display caused by low current operation of the light-emitting device (LED) and threshold voltage deviation due to pressure, this application incorporates a PWM driving method into the internal compensation circuit. This ensures that the LED always operates in a stable high-current emission phase, thus preventing uneven display. Simultaneously, it compensates for the TFT threshold voltage. Furthermore, this application significantly increases the number of grayscale levels while maintaining consistent compensation range and accuracy, resulting in a more uniform display image and improved display performance.

[0058] This application illustrates the specific implementation methods of this application through the following embodiments:

[0059] Please refer to Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of the organic light-emitting diode display panel 100 provided in the embodiments of this application, as shown below. Figure 1 As shown, the organic light-emitting diode display panel 100 includes a first power line, a second power line, and a pixel circuit. The pixel circuit includes:

[0060] The light-emitting module 10 is electrically connected to the first power line;

[0061] A driving module 20 is electrically connected between the first power line and the light-emitting module 10, and the driving module 20 is used to drive the light-emitting module 10 to emit light.

[0062] A black-out control module 30 is provided, one end of which is electrically connected to the drive module 20, and the other end of which is electrically connected to the second power line. The black-out control module 30 is used to turn off the drive module 20 a predetermined number of times, so that the drive module 20 stops driving the light-emitting module 10 to emit light for the predetermined number of times. At least two of the predetermined number of times the black-out control module 30 turns off the drive module 20 have different durations.

[0063] In this embodiment, the first power line is used to transmit the first voltage VDD, and the second power line is used to transmit the second voltage VSS. The light-emitting module 10 is a pixel unit, including at least three types of pixel units: RGB.

[0064] It is understood that the black-insertion control module 30 of this application shuts down the driving module 20 during multiple different time periods in the light-emitting stage, causing the driving module 20 to stop driving the light-emitting module 10 to emit light, thereby dividing the pulse width of the light-emitting module 10 into multiple non-uniform molecular fields. This application, through the black-insertion control module 30, can control the switching of the driving module 20 to prevent the light-emitting current from flowing through the light-emitting module 10, thereby reducing the current pressure on the transistors in the driving module 20, making the display screen display uniform, and thus improving the display effect of the display panel. Furthermore, by setting the black-insertion control module 30 to control the light-emitting module 10, the display panel can achieve black-insertion during the light-emitting stage. Black-insertion means inserting a black frame between each frame of data. By controlling the timing of the black-insertion, different grayscale brightness levels can be combined, thereby adjusting the pulse width of the light-emitting module 10 from an uniform molecular field to a non-uniform molecular field, thus improving the grayscale bit depth. In this embodiment, by setting an internal black-insertion control module 30 to perform threshold compensation on the driving module 20 to improve the display effect, and without the need for an external compensation chip, the cost is reduced.

[0065] In this embodiment, the driving module 20 and the black insertion control module 30 can share the same second power line, which reduces the signal lines required by the pixel circuit, thereby reducing the space occupied by the display area and improving the aperture ratio.

[0066] In some embodiments, please refer to Figure 2 , Figure 2 This is a circuit diagram of an organic light-emitting diode display panel 100 provided in an embodiment of this application. (In conjunction with...) Figure 1 , Figure 2 As shown, the organic light-emitting diode display panel further includes a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a data signal line, a light emission control signal line, a read signal line, and a detection signal line;

[0067] The light-emitting module 10 includes at least one light-emitting device D1;

[0068] The drive module 20 includes:

[0069] A capacitor C1, wherein the first plate of the capacitor C1 is electrically connected to the anode of the light-emitting device D1;

[0070] A first transistor T1, the gate of the first transistor T1 is electrically connected to the second plate of the capacitor C1, and one of the source and drain of the first transistor T1 is electrically connected to the anode of the light-emitting device D1.

[0071] A second transistor T2, the gate of the second transistor T2 is electrically connected to the read signal line, one of the source and drain of the second transistor T2 is electrically connected to the other of the source and drain of the first transistor T1, and the other of the source and drain of the second transistor T2 is electrically connected to the detection signal line.

[0072] A third transistor T3, wherein the gate of the third transistor T3 is electrically connected to the first scan signal line, one of the source and drain of the third transistor T3 is electrically connected to the data signal line, and the other of the source and drain of the third transistor T3 is electrically connected to the gate of the first transistor T1.

[0073] A fourth transistor T4, the gate of the fourth transistor T4 being electrically connected to the second scan signal line, one of the source and drain of the fourth transistor T4 being electrically connected to the other of the source and drain of the first transistor T1, and the other of the source and drain of the fourth transistor T4 being electrically connected to the gate of the first transistor T1.

[0074] A fifth transistor T5, wherein the gate of the fifth transistor T5 is electrically connected to the light-emitting control signal line, one of the source and drain of the fifth transistor T5 is electrically connected to the first power supply line, and the other of the source and drain of the fifth transistor T5 is electrically connected to the other of the source and drain of the first transistor T1.

[0075] A sixth transistor T6, wherein the gate of the sixth transistor T6 is electrically connected to the third scan signal line, one of the source and drain of the sixth transistor T6 is electrically connected to the second power supply line, and the other of the source and drain of the sixth transistor T6 is electrically connected to the anode of the light-emitting device D1; and

[0076] The black insertion control module 30 includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the fourth scan signal line, one of the source and drain of the seventh transistor T7 is electrically connected to the second power line, and the other of the source and drain of the seventh transistor T7 is electrically connected to the gate of the first transistor T1.

[0077] During the light-emitting phase of the light-emitting device D1, the seventh transistor T7, under the control of the scan signal transmitted by the fourth scan signal line, pulls down the gate voltage of the first transistor T1 a predetermined number of times, wherein at least two of the predetermined number of times the seventh transistor T7 pulls down the gate voltage of the first transistor T1 have different durations.

[0078] In this embodiment, the light-emitting module 10 is electrically connected between a first power line and a second power line to form a light-emitting circuit. The light-emitting module 10 includes at least one light-emitting device D1. The anode of the at least one light-emitting device D1 is electrically connected to the first power line, and the cathode of the at least one light-emitting device D1 is electrically connected to the second power line. It should be noted that the at least one light-emitting device D1 can be connected in series and / or in parallel, and each light-emitting device D1 can be one of Mini-LED, Micro-LED, OLED, and QLED.

[0079] Please see Figure 2 As shown, the gate of the first transistor T1 is electrically connected to the first node A, one of the source and drain of the first transistor T1 is electrically connected to the second node B, and the anode of the light-emitting device D1 is also electrically connected to the second node B. The other of the source and drain of the first transistor T1 is electrically connected to the third node C. The first transistor T1 is used to control the current flowing through the light-emitting circuit. By controlling the on / off state of the first transistor T1, the switching between the on and off states of the light-emitting module 10 can be controlled.

[0080] Please continue reading. Figure 2 As shown, the gate of the second transistor T2 is electrically connected to the read signal line to receive the threshold voltage read signal RD. One of the source and drain of the second transistor T2 is electrically connected to the third node C, and simultaneously, one of the source and drain of the first transistor T1 is also electrically connected to the third node C. The other of the source and drain of the second transistor T2 is electrically connected to the detection signal line, which is connected to the analog-to-digital converter (ADC) module. The threshold voltage of the first transistor T1 can be detected by the ADC module.

[0081] Please continue reading. Figure 2As shown, the other of the source and drain of the third transistor T3 is electrically connected to the first node A. Additionally, the gate of the first transistor T1 and one of the source and drain of the seventh transistor T7 are also electrically connected to the first node A. The gate of the third transistor T3 is electrically connected to the first scan signal line to receive the first scan signal SCAN, and one of the source and drain of the third transistor T3 is electrically connected to the data signal line to receive the data signal DATA. After the third transistor T3 is turned on, the data signal DATA can be written to the first node A, thereby pulling up the potential of the first node A. This causes one of the source and drain of the first transistor T1 to obtain a high level, thus turning on the first transistor T1.

[0082] Please continue reading Figure 2 As shown, the control terminal of the fourth transistor T4 is electrically connected to the second scan signal line to receive the second scan line signal. The other of the source and drain of the fourth transistor T4 is electrically connected to the first node A. Additionally, the gate of the first transistor T1 and the other of the source and drain of the second transistor T2 are also electrically connected to the first node A. One of the source and drain of the fourth transistor T4 is electrically connected to the third node C, and the other of the source and drain of the first transistor T1 is also electrically connected to the third node C. The fourth transistor T4 primarily initializes the potential of the first node A during the initialization phase and forms a diode structure during the threshold voltage detection phase.

[0083] Please continue reading Figure 2 As shown, the fifth transistor T5 is used to control the light-emitting circuit to be turned on or off under the control of the light-emitting control signal EM. Specifically, the light-emitting control signal line is used to transmit or provide the light-emitting control signal EM. The on and off states of the fifth transistor T5 are related to the on or off states of the first transistor T1. When the light-emitting control signal line turns on the fifth transistor T5, the first voltage VDD connected to the first power supply line is transmitted to the first transistor T1 through the fifth transistor T5. Therefore, controlling the fifth transistor T5 can achieve potential control at the third node C.

[0084] Please continue reading Figure 2 As shown, the gate of the sixth transistor T6 is electrically connected to the third scan signal line to receive the third scan signal SCAN3. The other of the source and drain of the sixth transistor T6 is electrically connected to the second node B. Additionally, the other of the source and drain of the first transistor T1 is also electrically connected to the second node B. The sixth transistor T6 primarily initializes the potential of the second node B.

[0085] Please continue reading Figure 2As shown, the first plate of capacitor C1 is electrically connected to the second node B, the anode of light-emitting device D1 is electrically connected to the second node B, and the cathode of light-emitting device D1 is electrically connected to the second power line. The second plate of capacitor C1 is electrically connected to the first node A, and the gate of the first transistor T1 is also electrically connected to the first node A. Capacitor C1 is used to maintain the gate potential of the first transistor T1, that is, to maintain the potential at the first node A, so as to maintain the state of the light-emitting module 10. Specifically, the third transistor T3 can also charge capacitor C1 after it is turned on. It can be understood that since the gate of the first transistor T1 is electrically connected to capacitor C1, and capacitor C1 is not easy to form a leakage path, it is beneficial to maintain the stability of the current flowing through the light-emitting module 10, thereby improving the display effect of the display panel.

[0086] In the embodiments of this application, please continue to refer to Figure 2 As shown, the first transistor T1 is a driving transistor. Since the driving transistor requires precise voltage waveform and timing control to ensure the normal operation of the liquid crystal display, the first transistor T1 is a key component in the pixel circuit and experiences the greatest current pressure. After the fifth transistor T5 is turned on, the voltage of the first voltage VDD is shunted to the third node C, thereby raising the potential of the third node C. This allows one of the source and drain terminals of the first transistor T1 to obtain a high level, thus turning on the first transistor T1. When the seventh transistor T7 is turned on under the control of the fourth scan signal SCAN4, since the output terminal of the seventh transistor T7 is electrically connected to the second power line, the potential of the third node C can be pulled low by the seventh transistor T7, thereby turning off the first transistor T1. At this time, the light-emitting module 10 is also turned off, thus realizing the black-insertion operation.

[0087] The gate of the seventh transistor T7 is electrically connected to the fourth scan signal line to receive the fourth scan signal SCAN4. Under the control of the scan signal transmitted by the fourth scan signal line, the seventh transistor T7 can pull down the gate voltage of the first transistor T1, thereby controlling the number of times the first transistor T1 is turned off. The number of times it is pulled down or turned off is a predetermined number, including at least two times, and the duration of at least two of the predetermined number of times the seventh transistor T7 pulls down the gate voltage of the first transistor T1 is different. In this way, under the control of the fourth scan signal SCAN4, the seventh transistor T7 can control the off state of the first transistor T1, thereby reducing the stress on the first transistor T1 and allowing the light-emitting module 10 to be inserted into the black hole. Therefore, the seventh transistor T7 and the fourth scan signal SCAN4 provided in this application can reduce the working stress of the first transistor T1, improve the uniformity of the display screen, and thus improve the display effect of the display panel.

[0088] It should be noted that the pulse width of the fourth scan signal SCAN4 can be set as needed. The organic light-emitting diode display panel 100 provided in this application embodiment can control the time node when the seventh transistor T7 is turned on by setting the fourth scan signal SCAN4, thereby realizing the control of the black insertion time point in the light-emitting stage of the display panel. Different gray level brightness can be obtained by combining them, thereby adjusting the pulse width of the light-emitting module 10 from an equimolecular field to a non-equimolecular field, thereby realizing the improvement of the gray level bit depth.

[0089] In some embodiments, please refer to Figure 3 , Figure 3 A timing diagram of an organic light-emitting diode display panel 100 provided in an embodiment of this application. (See diagram below.) Figure 2 and Figure 3 As shown, the driving cycle T0 for displaying a frame of image in the organic light-emitting diode display panel 100 includes a light-emitting phase t5; the light-emitting phase t5 includes multiple sub-time periods, and each sub-time period includes a light-emitting control sub-time period t51_n and a light-emitting black-insertion sub-time period t51_n;

[0090] During the light emission control sub-period t51_n, the light emission control signal EM transmitted by the light emission control signal EM line is at a high potential, while the threshold voltage read signal RD transmitted by the read signal RD line, the data signal DATA transmitted by the data signal DATA line, the first scan signal SCAN transmitted by the first scan line, the second scan signal SCAN2 transmitted by the second scan line, the third scan signal SCAN3 transmitted by the third scan line, and the fourth scan signal SCAN4 transmitted by the fourth scan line are all at a low potential.

[0091] During the period t52_n when the light emission is inserted into the black spot, the light emission control signal EM and the fourth scan signal SCAN4 are at high potentials, while the threshold voltage reading signal RD, the data signal DATA, the first scan signal SCAN, the second scan signal SCAN2, and the third scan signal SCAN3 are all at low potentials.

[0092] In the embodiments of this application, such as Figure 3 As shown, the driving cycle T0 of the organic light-emitting diode display panel 100 for displaying one frame of image includes, in chronological order, an initialization phase t1, a threshold voltage detection phase t2, a threshold voltage reading phase t3, a data writing phase t4, and an emission phase t5. The emission phase t5 includes multiple sub-segments, each of which includes an emission control sub-segment t51_n and an emission insertion sub-segment t51_n.

[0093] like Figure 3 and Figure 4As shown, during the initialization phase t1, the light emission control signal EM, the second scan signal SCAN2, and the third scan signal SCAN3 are all at high potentials. The fifth transistor T5 turns on under the high potential control of the light emission control signal EM, thereby initializing the potential of the third node C, making the potential of the third node C the first voltage VDD. The fourth transistor T4 turns on under the high potential control of the second scan signal SCAN2, thereby initializing the potential of the first node A, making the potential of the first node A the first voltage VDD. The sixth transistor T6 turns on under the high potential control of the third scan signal SCAN3, thereby initializing the potential of the second node B, making the potential of the second node B the second voltage VSS. Since the data signal DATA, the threshold voltage read signal RD, the fourth scan signal SCAN4, and the first scan signal SCAN are all at low potentials, the first transistor T1, the seventh transistor T7, the second transistor T2, and the third transistor T3 are all turned off.

[0094] like Figure 3 and Figure 5 As shown, during the threshold voltage detection phase t2, since both the second scan signal SCAN2 and the third scan signal SCAN3 are at high potentials, it is known that the fourth transistor T4 and the sixth transistor T6 remain on. The fourth transistor T4 forms a diode structure during the threshold voltage detection phase t2. Furthermore, since the data signal DATA, the threshold voltage read signal RD, the fourth scan signal SCAN4, and the first scan signal SCAN are all at low potentials, the first transistor T1, the seventh transistor T7, the second transistor T2, and the third transistor T3 remain off. However, since the light emission control signal EM becomes low during the threshold voltage detection phase t2, the fifth transistor T5 is turned off under the low potential control of the light emission control signal EM, causing the potentials of the first node A and the third node C to decrease from the first voltage VDD to the second voltage VSS+Vth. Vth is the threshold voltage that turns on the first transistor T1.

[0095] like Figure 3 and Figure 6 As shown, during the threshold voltage reading stage t3, since both the second scan signal SCAN2 and the third scan signal SCAN3 are at high potentials, it is known that the fourth transistor T4 and the sixth transistor T6 remain on. Because the light emission control signal EM, the data signal DATA, the fourth scan signal SCAN4, and the first scan signal SCAN are all at low potentials, the first transistor T1, the seventh transistor T7, the fifth transistor T5, and the third transistor T3 are off. However, since the threshold voltage reading signal RD is at a high potential during the threshold voltage reading stage t3, the second transistor T2 is on, and the threshold voltage Vth of the first transistor T1, previously detected, is read by the analog-to-digital converter (ADC).

[0096] like Figure 3 and Figure 7 As shown, during the data writing phase t4, the sixth transistor T6 is turned on because the third scan signal SCAN3 is at a high level. Since both the light emission control signal EM and the fourth scan signal SCAN4 are at a low level, the seventh transistor T7 and the fifth transistor T5 are both turned off. Additionally, during the data writing phase t4, the analog-to-digital converter (ADC) collects and analyzes the threshold voltage Vth and provides the data signal DATA to the third transistor T3 via the IC. Since the data signal DATA and the first scan signal SCAN are both at a high level, the third transistor T3 is turned on. Since the second scan signal SCAN2 and the threshold voltage read signal RD are at a low level, the fourth transistor T4 and the second transistor T2 are turned off. Because the third transistor T3 is turned on and the fourth transistor T4 is turned off, the potential of the first node A becomes DATA. Since the first transistor T1 remains off and the sixth transistor T6 is turned on, the potential of the second node B remains the second voltage VSS.

[0097] like Figure 3 and Figure 8 As shown, during the light emission control sub-period t51_n of the light emission stage t5, the threshold voltage read signal RD, data signal DATA, fourth scan signal SCAN4, second scan signal SCAN2, third scan signal SCAN3, and first scan signal SCAN are all at low potentials. Therefore, the seventh transistor T7, the fourth transistor T4, the second transistor T2, the sixth transistor T6, and the third transistor T3 are all turned off. Since the light emission control signal EM is at a high potential, the first transistor T1 and the fifth transistor T5 are turned on, thus achieving compensated light emission.

[0098] like Figure 3 , Figure 4 and Figure 9 As shown, during the black dot insertion period t52_n of the light-emitting stage t5, since the voltage detection signal RD, data signal DATA, second scan signal SCAN2, third scan signal SCAN3, and first scan signal SCAN are all at low potentials, the fourth transistor T4, the second transistor T2, the sixth transistor T6, and the third transistor T3 are all turned off. Since the light-emitting control signal EM is at a high potential, the fifth transistor T5 is turned on. When the fourth scan signal SCAN4 is at a high potential during the black dot insertion period t52_n of the light-emitting stage t5, the seventh transistor T7 is turned on, and the potential of the first node A is momentarily pulled low, thereby turning off the first transistor T1. This prevents the light-emitting device D1 from conducting and emitting light, thus causing the light-emitting device D1 to change from bright to dark. Figure 4As shown, by making the fourth scanning signal SCAN4 high during the period t52_n of the light emission insertion of black spots in the light emission stage t5, the turn-on time of the seventh transistor T7 can be controlled, thereby controlling the continuous light emission time of the light-emitting device D1. This allows the light emission process of the light-emitting device D1 in one frame to be divided into multiple subfields with different durations, realizing the transformation of the grayscale from an equimolecular field to an unequal molecular field, and achieving an increase in the number of grayscale levels.

[0099] In some embodiments, during the light emission stage t5, the light emission control sub-period t51_n alternates with the light emission insertion sub-period t52_n, and the light emission control sub-period t51_n and the light emission insertion sub-period t52_n are continuous;

[0100] Within the sub-time period, the light emission control sub-time period t51_n precedes the light emission insertion sub-time period t52_n.

[0101] In this embodiment, the light-emitting stage t5 includes multiple sub-segments, each sub-segment including a light-emitting control sub-segment t51_n and a light-emitting insertion sub-segment t52_n. The multiple light-emitting control sub-segments t51_n and the multiple light-emitting insertion sub-segments t52_n are arranged alternately, and the light-emitting control sub-segment t51_n is located in the first sub-segment among the multiple sub-segments. For example, as... Figure 3 As shown, the light emission stage t5 includes, in chronological order, the first light emission control sub-period t51_1, the first light emission interpolation sub-period t52_1, the second light emission control sub-period t51_2, the second light emission interpolation sub-period t52_2, and so on, including multiple alternating light emission control sub-periods t51_n and light emission interpolation sub-periods t52_n.

[0102] In some embodiments, the duration of the (n+1)th light-emitting black-insertion sub-period t52_n+1 is equal to twice the duration of the nth light-emitting black-insertion sub-period t52_n, and the durations of any two sub-periods are equal, where n is a positive integer.

[0103] In the embodiments of this application, please refer to Figure 10 As shown, Figure 10 This is a schematic diagram illustrating the distribution of the non-equimolecular field in an organic light-emitting diode (OLED) display panel provided in an embodiment of this application. Figure 10The horizontal axis represents time (Time), and the vertical axis represents the current (ILED) flowing through the light-emitting device D1. The duration of the second light-emitting sub-period t52_2 is twice the duration of the first light-emitting sub-period t52_1, and the total duration of the first light-emitting control sub-period t51_1 and the first light-emitting sub-period t52_1 is equal to the total duration of the second light-emitting control sub-period t51_2 and the second light-emitting sub-period t52_2. The duration of the third light-emitting sub-period t52_3 is twice the duration of the second light-emitting sub-period t52_2, and the total duration of the second light-emitting control sub-period t51_2 and the second light-emitting sub-period t52_2 is equal to the total duration of the third light-emitting control sub-period t51_3 and the third light-emitting sub-period t52_3, and so on. Figure 10 As shown, n=8. Taking a 240Hz, 10-row panel as an example, assuming that threshold voltage detection and compensation require 50 microseconds, this application can control the turn-on time of the seventh transistor T7 to make the light-emitting device D1 black, thus changing the original 8 equimolecular fields into 8 non-equimolecular fields. That is, the 8 non-equimolecular fields can achieve 2 n =2 8 =256 grayscale variations, which can significantly increase the number of bits without losing the compensation range, that is, increase the number of grayscale levels.

[0104] The number of subfields per frame depends on the grayscale levels of the display panel. For example, if the display panel has 7 grayscale levels, there are 7 subfields; if it has 8 grayscale levels, there are 8 subfields. The durations of the n subfields are different, and each subfield corresponds to one bit of data. The duration of different bits indicates their contribution to the backlight brightness, i.e., their weight. The longer the duration of each subfield, the greater its weight.

[0105] For light-emitting devices such as Mini-LEDs and Micro-LEDs, using voltage-based grayscale segmentation presents challenges. At lower voltages, it becomes difficult to precisely control the luminous current, leading to uneven brightness in low-grayscale displays. To avoid uneven brightness due to low current and threshold voltage shift caused by stress, Figure 2 The internal compensation pixel circuit shown combines the time-division grayscale PWM driving method to ensure that the light-emitting device D1 always works in the high-current stable light-emitting stage, which can improve or avoid the problem of uneven display, while also realizing the threshold voltage compensation of the first transistor T1.

[0106] Wherein, the first power line is used to transmit the first voltage VDD, and the second power line is used to transmit the second voltage VSS; when the first transistor T1 is an N-channel thin film transistor, the potential of the first voltage VDD is a constant high potential, and the potential of the second voltage VSS is a constant low potential; or, when the first transistor T1 is a P-channel thin film transistor, the potential of the first voltage VDD is a constant low potential, and the potential of the second voltage VSS is a constant high potential.

[0107] In some embodiments, at least one of the first transistor T1, the seventh transistor T7, the fifth transistor T5, the fourth transistor T4, the second transistor T2, the sixth transistor T6, and the third transistor T3 may be, but is not limited to, an N-channel thin-film transistor or a P-channel thin-film transistor.

[0108] In some embodiments, the first transistor T1, the seventh transistor T7, the fifth transistor T5, the fourth transistor T4, the second transistor T2, the sixth transistor T6, and the third transistor T3 can be one or more of low-temperature polycrystalline silicon thin-film transistors, oxide semiconductor thin-film transistors, or amorphous silicon thin-film transistors. Furthermore, the transistors in the organic light-emitting diode display panel 100 provided in this application embodiment can be configured to be of the same type, thereby avoiding the impact of differences between different types of transistors on the organic light-emitting diode display panel 100.

[0109] In one embodiment, this embodiment provides an image display method, applied to Figures 1 to 10 The organic light-emitting diode (OLED) display panel 100 shown includes multiple pixel circuits, each pixel circuit including a light-emitting module 10, a driving module 20, and a black-insertion control module 30. The driving cycle for displaying one frame of an image by the OLED display panel 100 includes a light-emitting phase t5. The image display method includes the following steps:

[0110] S100, during the light-emitting stage t5, the driving module 20 drives the light-emitting module 10 to emit light;

[0111] S200, during the light-emitting stage t5, the black-insertion control module 30 shuts down the driving module 20 a predetermined number of times, causing the driving module 20 to stop driving the light-emitting module 10 to emit light for the predetermined number of times. At least two of the predetermined number of times the black-insertion control module 30 shuts down the driving module 20 have different durations.

[0112] This embodiment is a method embodiment corresponding to the above-described embodiment of the organic light-emitting diode (OLED) display panel 100. For the parts of this embodiment that are the same as those in the above-described embodiment of the OLED display panel 100, please refer to the above-described embodiment of the OLED display panel 100; they will not be described again here. It is understood that the black-insertion control module 30 provided in this embodiment can control the switching of the driving module 20, thereby reducing the current pressure on the transistors in the driving module 20. During the black-insertion period t52_n in the light-emitting phase t5 of the OLED display panel 100, the driving module 20 can be turned off multiple times, thus constructing multiple non-uniform molecular fields and exponentially increasing the number of displayable grayscale levels.

[0113] In some embodiments, the organic light-emitting diode display panel includes a first power line, a second power line, a first scan line, a second scan line, a third scan line, and a fourth scan line; the driving module includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor C1; the black dot insertion control module 30 includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the fourth scan signal line, one of the source and drain of the seventh transistor T7 is electrically connected to the second power line, and the other of the source and drain of the seventh transistor T7 is electrically connected to the gate of the first transistor T1.

[0114] During the light-emitting stage t5, the black insertion control module shuts down the driving module a predetermined number of times, causing the driving module to stop driving the light-emitting module to emit light. The predetermined number of times includes:

[0115] During the light-emitting stage t5, the seventh transistor T7, under the control of the fourth scan signal SCAN4 transmitted by the fourth scan signal line, pulls down the gate voltage of the first transistor T1 a predetermined number of times, and at least two of the predetermined number of times the seventh transistor T7 pulls down the gate voltage of the first transistor T1 have different durations.

[0116] This embodiment is a method embodiment corresponding to the above-described organic light-emitting diode display panel 100 embodiment. The parts that are the same as those in the above-described organic light-emitting diode display panel 100 embodiment can be referred to the above-described organic light-emitting diode display panel 100 embodiment, and will not be described again here.

[0117] In some embodiments, the light emission stage t5 includes multiple sub-time periods, and one of the sub-time periods includes a light emission control sub-time period t51_n and a light emission insertion sub-time period t51_n;

[0118] During the light emission control sub-period t51_n, the light emission control signal EM transmitted by the light emission control signal EM line is at a high potential, while the threshold voltage read signal RD transmitted by the read signal RD line, the data signal DATA transmitted by the data signal DATA line, the first scan signal SCAN transmitted by the first scan line, the second scan signal SCAN2 transmitted by the second scan line, the third scan signal SCAN3 transmitted by the third scan line, and the fourth scan signal SCAN4 transmitted by the fourth scan line are all at a low potential.

[0119] During the period t52_n when the light emission is inserted into the black spot, the light emission control signal EM and the fourth scan signal SCAN4 are at high potentials, while the threshold voltage reading signal RD, the data signal DATA, the first scan signal SCAN, the second scan signal SCAN2, and the third scan signal SCAN3 are all at low potentials.

[0120] This embodiment is a method embodiment corresponding to the above-described organic light-emitting diode display panel 100 embodiment. The parts that are the same as those in the above-described organic light-emitting diode display panel 100 embodiment can be referred to the above-described organic light-emitting diode display panel 100 embodiment, and will not be described again here.

[0121] In some embodiments, during the light emission stage t5, the light emission control sub-period t51_n alternates with the light emission insertion sub-period t52_n, and the light emission control sub-period t51_n and the light emission insertion sub-period t52_n are continuous;

[0122] Within the sub-time period, the light emission control sub-time period t51_n precedes the light emission insertion sub-time period t52_n.

[0123] This embodiment is a method embodiment corresponding to the above-described organic light-emitting diode display panel 100 embodiment. The parts that are the same as those in the above-described organic light-emitting diode display panel 100 embodiment can be referred to the above-described organic light-emitting diode display panel 100 embodiment, and will not be described again here.

[0124] In some embodiments, the duration of the (n+1)th light-emitting black-insertion sub-period t52_n+1 is equal to twice the duration of the nth light-emitting black-insertion sub-period t52_n, and the durations of any two sub-periods are equal, where n is a positive integer.

[0125] This embodiment is a method embodiment corresponding to the above-described organic light-emitting diode display panel 100 embodiment. The parts that are the same as those in the above-described organic light-emitting diode display panel 100 embodiment can be referred to the above-described organic light-emitting diode display panel 100 embodiment, and will not be described again here.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0127] The organic light-emitting diode display panel 100 and the display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An organic light-emitting diode display panel, characterized in that, The organic light-emitting diode display panel includes a first power line, a second power line, and a pixel circuit, wherein the pixel circuit includes: A light-emitting module electrically connected to the second power line; A driving module electrically connected between the first power line and the light-emitting module, the driving module being used to drive the light-emitting module to emit light; and A black-insertion control module is provided, one end of which is electrically connected to the driving module and the other end of which is electrically connected to the second power line. The black-insertion control module is used to turn off the driving module a predetermined number of times during the light-emitting stage, so that the driving module stops driving the light-emitting module to emit light for the predetermined number of times. At least two of the predetermined number of times the black-insertion control module turns off the driving module have different durations.

2. The organic light-emitting diode display panel as described in claim 1, characterized in that, The organic light-emitting diode display panel further includes a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a data signal line, a light emission control signal line, a read signal line, and a detection signal line; The light-emitting module includes at least one light-emitting device; The driving module includes: A capacitor, wherein the first plate of the capacitor is electrically connected to the anode end of the light-emitting device; A first transistor, wherein the gate of the first transistor is electrically connected to the second plate of the capacitor, and one of the source and drain of the first transistor is electrically connected to the anode of the light-emitting device. A second transistor, the gate of which is electrically connected to the read signal line, one of the source and drain of the second transistor being electrically connected to the other of the source and drain of the first transistor, and the other of the source and drain of the second transistor being electrically connected to the detection signal line. A third transistor, wherein the gate of the third transistor is electrically connected to the first scan signal line, one of the source and drain of the third transistor is electrically connected to the data signal line, and the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor. A fourth transistor, wherein the gate of the fourth transistor is electrically connected to the second scan signal line, one of the source and drain of the fourth transistor is electrically connected to the other of the source and drain of the first transistor, and the other of the source and drain of the fourth transistor is electrically connected to the gate of the first transistor. A fifth transistor, wherein the gate of the fifth transistor is electrically connected to the light-emitting control signal line, one of the source and drain of the fifth transistor is electrically connected to the first power supply line, and the other of the source and drain of the fifth transistor is electrically connected to the other of the source and drain of the first transistor; and A sixth transistor, wherein the gate of the sixth transistor is electrically connected to the third scan signal line, one of the source and drain of the sixth transistor is electrically connected to the second power supply line, and the other of the source and drain of the sixth transistor is electrically connected to the anode of the light-emitting device. The black-insertion control module includes: A seventh transistor, wherein the gate of the seventh transistor is electrically connected to the fourth scan signal line, one of the source and drain of the seventh transistor is electrically connected to the second power supply line, and the other of the source and drain of the seventh transistor is electrically connected to the gate of the first transistor. During the light-emitting phase of the light-emitting device, the seventh transistor is used to pull down the gate voltage of the first transistor a predetermined number of times under the control of the scan signal transmitted by the fourth scan signal line, wherein at least two of the predetermined number of times the seventh transistor pulls down the gate voltage of the first transistor have different durations.

3. The organic light-emitting diode display panel as described in claim 2, characterized in that, The light emission stage includes multiple sub-time periods, and each sub-time period includes a light emission control sub-time period and a light emission insertion sub-time period. During the light emission control sub-period, the light emission control signal transmitted by the light emission control signal line is at a high potential, while the threshold voltage read signal transmitted by the read signal line, the data signal transmitted by the data signal line, the first scan signal transmitted by the first scan line, the second scan signal transmitted by the second scan line, the third scan signal transmitted by the third scan line, and the fourth scan signal transmitted by the fourth scan line are all at a low potential. During the period of light emission and black spot insertion, the light emission control signal and the fourth scan signal are both at high potentials, while the threshold voltage reading signal, the data signal, the first scan signal are at high potentials, and the second scan signal and the third scan signal are all at low potentials.

4. The organic light-emitting diode display panel as described in claim 3, characterized in that, The duration of the (n+1)th light-emitting black-spotting sub-segment is equal to twice the duration of the nth light-emitting black-spotting sub-segment, and the durations of any two sub-segments are equal, where n is a positive integer.

5. The organic light-emitting diode display panel as described in claim 3, characterized in that, During the light emission phase, the light emission control sub-period and the light emission insertion sub-period alternate, and the light emission control sub-period and the light emission insertion sub-period are continuous; In the sub-time period, the light emission control sub-time period precedes the light emission insertion sub-time period.

6. A method for displaying images on an organic light-emitting diode (OLED) display panel, characterized in that, The pixel circuit of the organic light-emitting diode display panel includes a light-emitting module, a driving module, and a black-insertion control module. The driving cycle of the organic light-emitting diode display panel to display one frame of image includes a light-emitting phase. The image display method includes the following steps: During the light-emitting phase, the driving module drives the light-emitting module to emit light; During the light-emitting phase, the black-insertion control module shuts down the driving module a predetermined number of times, causing the driving module to stop driving the light-emitting module to emit light for the predetermined number of times. At least two of the predetermined number of times the black-insertion control module shuts down the driving module have different durations.

7. The image display method according to claim 6, characterized in that, The organic light-emitting diode display panel includes a first power line, a second power line, a first scan line, a second scan line, a third scan line, and a fourth scan line. The driving module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor. The black-insertion control module includes a seventh transistor. The gate of the seventh transistor is electrically connected to the fourth scan signal line. One of the source and drain of the seventh transistor is electrically connected to the second power line, and the other of the source and drain of the seventh transistor is electrically connected to the gate of the first transistor. During the light-emitting phase, the black-insertion control module shuts down the driving module a predetermined number of times, causing the driving module to stop driving the light-emitting module to emit light. The predetermined number of times includes: During the light-emitting phase, the seventh transistor, under the control of the scan signal transmitted by the fourth scan signal line, pulls down the gate voltage of the first transistor a predetermined number of times, wherein at least two of the predetermined number of times the seventh transistor pulls down the gate voltage of the first transistor have different durations.

8. The image display method as described in claim 7, characterized in that, The light emission stage includes multiple sub-time periods, and each sub-time period includes a light emission control sub-time period and a light emission insertion sub-time period. During the light emission control sub-period, the light emission control signal transmitted by the light emission control signal line is at a high potential, while the threshold voltage read signal transmitted by the read signal line, the data signal transmitted by the data signal line, the first scan signal transmitted by the first scan line, the second scan signal transmitted by the second scan line, the third scan signal transmitted by the third scan line, and the fourth scan signal transmitted by the fourth scan line are all at a low potential. During the period of light emission and black spot insertion, the light emission control signal and the fourth scan signal are both at high potentials, while the threshold voltage reading signal, the data signal, the first scan signal are at high potentials, and the second scan signal and the third scan signal are all at low potentials.

9. The image display method as described in claim 8, characterized in that, The duration of the (n+1)th light-emitting black-spotting sub-segment is equal to twice the duration of the nth light-emitting black-spotting sub-segment, and the durations of any two sub-segments are equal, where n is a positive integer.

10. The image display method as described in claim 8, characterized in that, During the light emission phase, the light emission control sub-period and the light emission insertion sub-period alternate, and the light emission control sub-period and the light emission insertion sub-period are continuous; In the sub-time period, the light emission control sub-time period precedes the light emission insertion sub-time period.

Images