Flash memory device and programming method thereof

Abstract

The invention provides a flash memory device and a programming method thereof. The programming method comprises the following steps of: performing programming operation on a plurality of memory cell groups in sequence; under the condition that a target storage unit group in the storage unit groups does not pass the programming verification, one or more programming verification cycles are executed on the target storage unit group, the target storage unit group is divided into M parts, and M is a positive integer larger than 1; judging whether a programming verification loop executed on the target storage unit group is a first programming verification loop or not; and sequentially programming the M portions when a first program verification cycle is performed on the target memory cell group.

Description

Technical Field

[0001] This invention relates to a control technology for a memory device, and more particularly to a flash memory device for reducing the time spent on programming operations and the programming method thereof. Background Art

[0002] Flash memory devices can be mainly divided into two types: NOR and NAND. Compared to NAND flash memory devices, NOR flash memory devices require a longer time for programming / erasing operations. However, NOR flash memory devices provide complete addressing and data buses, thus allowing access to any memory cell on the NOR flash memory device. Therefore, how to reduce the programming time of NOR flash memory devices has become one of the important issues in this field. Summary of the Invention

[0003] The present invention provides a flash memory device and a programming method thereof, which can dynamically adjust the number of memory cells that are programmed simultaneously in a programming verification loop, so as to reduce the time spent on programming operations.

[0004] The flash memory device of the present invention includes a memory array and a memory control circuit. The memory array has multiple groups of memory cells. The memory control circuit is coupled to the memory array and configured to sequentially program the groups of memory cells. If a target group of memory cells fails programming verification, the memory control circuit performs one or more programming verification loops on the target group of memory cells, wherein the target group of memory cells is divided into M parts, where M is a positive integer greater than 1. The memory control circuit determines whether the programming verification loop performed on the target group of memory cells is the first programming verification loop. When the first programming verification loop is performed on the target group of memory cells, the memory control circuit sequentially programs the M parts.

[0005] The programming method for the flash memory device of the present invention includes the following steps: sequentially performing programming operations on a plurality of memory cell groups; if a target memory cell group in the memory cell group fails programming verification, performing one or more programming verification loops on the target memory cell group, wherein the target memory cell group is divided into M parts, where M is a positive integer greater than 1; determining whether the programming verification loop performed on the target memory cell group is the first programming verification loop; and when the first programming verification loop is performed on the target memory cell group, sequentially programming the M parts.

[0006] Based on the above, the flash memory device and programming method of the present invention can program only a portion of the target memory cell group at a time during the first programming verification cycle, and perform the programming sequentially. In this way, the number of memory cells programmed simultaneously in the programming verification cycle can be dynamically adjusted to reduce the time spent on programming operations.

[0007] To make the above-mentioned features and advantages of this case more apparent and understandable, specific embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 A schematic diagram of a flash memory device according to an embodiment of the present invention is shown;

[0009] Figure 2 and Figure 3 A flowchart illustrating the steps of a programming method for a flash memory device according to some embodiments of the present invention is shown. Detailed Implementation

[0010] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0011] Please refer to Figure 1 In one embodiment of the present invention, a flash memory device 100 is, for example, a NOR type, including a memory array 110 and a memory control circuit 120. The memory array 110 includes a plurality of memory cell groups 112. Each memory cell group 112 includes a plurality of memory cells to be programmed into a specific data pattern. The memory cells are, for example, memory tunneling oxide (ETOX) structures. In this embodiment of the present invention, there is no limitation on the number of memory cell groups 112 or memory cells.

[0012] Memory control circuitry 120 is coupled to memory array 110. Memory control circuitry 120 can be configured to sequentially program all memory cell groups 112. Specifically, memory control circuitry 120 can select a target memory cell group 114 from multiple memory cell groups 112 within memory array 110 to perform programming operations based on a received selection command (CMD). In this embodiment, the target memory cell group 114 can be divided into M parts G1 to GM, where M is a positive integer greater than 1. For example, each part G1 to GM can correspond to 16 bits. Part G1 includes 16 memory cells in the target memory cell group 114 corresponding to the highest 16 bits, part G2 includes 16 memory cells in the target memory cell group 114 corresponding to the 16 bits immediately following the bits in part G1, and so on. However, the present invention does not limit the size of each part G1 to GM or the number of bits it corresponds to; those skilled in the art can make appropriate adjustments according to their actual needs.

[0013] The memory control circuit 120, besides being, for example, a state machine, a central processing unit, or other programmable general-purpose or special-purpose microprocessor, digital signal processor, programmable controller, application-specific integrated circuit, programmable logic device, or other similar device or combination thereof, can also be a hardware circuit designed using a hardware description language or any other existing digital circuit design method, and implemented using a field-programmable gate array or complex programmable logic device. Furthermore, although... Figure 1 The memory control circuit 120 is shown to be located in the flash memory device 100; however, the memory control circuit 120 may also be a device independent of the flash memory device 100.

[0014] Optionally, the flash memory device 100 further includes a flag register 130. The flag register 130 is coupled to the memory control circuitry 120 and is used to store a count flag FT. During each execution of the programming verification loop, the memory control circuitry 120 can set the initial value of the count flag FT to a first value (e.g., "0"). Furthermore, although... Figure 1 The flag register 130 is shown to be separate from the memory array 110 and the memory control circuit 120; however, the flag register 130 may also be integrated into the memory array 110 or the memory control circuit 120.

[0015] Please refer to the following at the same time Figure 1 and Figure 2 The programming method for the flash memory device in this embodiment is applicable to Figure 1 The following describes the various steps of the programming method of this embodiment of the invention in conjunction with the various components in the flash memory device 100.

[0016] First, in step S200, the memory control circuit 120 sequentially programs multiple memory cell groups 112. For example, the memory control circuit 120 may initialize and set one of the memory cell groups 112 to be programmed in the memory array 110 (e.g., the first memory cell group) as the target memory cell group 114.

[0017] Next, the memory control circuit 120 can compare the bit data (e.g., 32 bits) formed by the target memory cell group 114 with a specific data pattern (e.g., 32 bits) to determine whether the target memory cell group 114 passes programming verification. More specifically, in one example of programming verification, the memory control circuit 120 can determine whether the threshold voltage of each memory cell within the target memory cell group 114 conforms to the specified range of each bit value within the specific data pattern. For example, if the bit value in the data pattern is "0", the threshold voltage of the corresponding memory cell must be greater than the default programming verification reference voltage; if the bit value in the data pattern is "1", the threshold voltage of the corresponding memory cell must be less than the default programming verification reference voltage. The data patterns corresponding to each memory cell group 112 can be the same or different.

[0018] Therefore, in step S202, if the target memory cell group 114 fails the programming verification, the memory control circuit 120 performs one or more programming verification cycles on the target memory cell group 114.

[0019] Next, in step S204, the memory control circuit 120 determines whether the programming verification loop executed on the target memory cell group 114 is the first programming verification loop. When the first programming verification loop is executed on the target memory cell group 114, in step S206, the memory control circuit 120 sequentially programs the M parts G1 to GM of the target memory cell group 114. For example, the memory control circuit 120 can set the initial value of K to 1, and the memory control circuit 120 can determine whether the Kth part GK of the target memory cell group 114 has one or more failed memory cells. If yes, the memory control circuit 120 can apply a programming voltage Vprg to the failed memory cells of the Kth part GK and increment K (K = K + 1) to continue the judgment for the next part. If no, the memory control circuit 120 directly increments K (K = K + 1) to continue the judgment for the next part. In this embodiment, a "failed memory cell" refers to a memory cell within the target memory cell group 114 that has not passed programming verification. The programming voltage Vprg includes the voltage applied to the gate node, drain node, source node, and well region of the failed memory cell, and particularly refers to the voltage applied to the drain node. For example, the voltage applied to the gate node may be 9 volts, the voltage applied to the drain node may be 4 volts, and the voltage applied to the source node and well region may be 0 volts, but the invention is not limited thereto.

[0020] Furthermore, the memory control circuit 120 can repeat the steps of determining whether the Kth part GK has one or more failed memory cells and incrementing K, thereby continuing to determine the next part until K is greater than M (all parts G1 to GM have been determined).

[0021] When performing programming verification cycles on the target memory cell group 114 other than the first one (e.g., the second, third, etc.), in step S208, the memory control circuit 120 simultaneously programs the M portions G1 to GM of the target memory cell group 114. Specifically, the memory control circuit 120 can simultaneously apply a programming voltage Vprg to the failed memory cells of all M portions G1 to GM.

[0022] The programming operation of an NOR flash memory device requires a large amount of current and is limited by the pumping capacity in the hardware circuitry. In this embodiment, the "pumping capacity" refers to the number of bits that the memory control circuit 120 can simultaneously apply programming pulses to failed memory cells using the programming voltage Vprg (that is, the number of failed memory cells to which the programming voltage Vprg can be applied simultaneously).

[0023] In this embodiment, since the number of failed memory cells is the largest in the first programming verification cycle, the memory control circuit 120 applies the programming voltage Vprg to the failed memory cells of a portion GK of the target memory cell group 114 at a time in the first programming verification cycle, thereby preventing the number of failed memory cells to be simultaneously applied with the programming voltage Vprg from exceeding the pump capacity.

[0024] Since the number of failed memory cells in programming verification loops other than the first one decreases with the increase of the number of programming verification loops, the memory control circuit 120 can simultaneously apply the programming voltage Vprg to all the failed memory cells of all M parts G1 to GM of the target memory cell group 114 in one programming verification loop, thereby improving the speed of programming verification. In this way, the time spent on programming operations can be reduced while taking into account the pump capacity limit.

[0025] It is worth mentioning that, in this embodiment, the target storage cell group 114 is divided into M parts G1 to GM, for example, according to the pump capacity of the flash memory device 100. In other words, the size of M can depend on the pump capacity of the flash memory device 100.

[0026] The following is as follows Figure 3 The illustrated embodiments further illustrate the programming methods disclosed herein. Please also refer to... Figure 1 and Figure 3 The programming method for the flash memory device in this embodiment is applicable to Figure 1 The flash memory device 100 is described below, along with the various components in the flash memory device 100, illustrating the steps of the programming method according to an embodiment of the present invention. In this embodiment, with... Figure 2 The same or similar parts will not be repeated. In addition, for the sake of simplicity, it is assumed in this embodiment that the target storage unit group 114 is divided into two parts G1 to G2 (M equals 2).

[0027] First, in step S300, the memory control circuit 120 can be initialized and the first memory cell group in all the memory cell groups 112 to be programmed in the memory array 110 is set as the target memory cell group 114.

[0028] Next, in step S302, the memory control circuit 120 determines whether the target memory cell group 114 has passed the programming verification. If the target memory cell group 114 has failed the programming verification, in step S304, the memory control circuit 120 determines whether the count flag FT stored in the flag register 130 is a first value (e.g., "0"). Specifically, the memory control circuit 120 can determine whether the programming verification loop being executed on the current target memory cell group 114 is the first programming verification loop based on the count flag FT.

[0029] When the count flag FT is at its first value, the memory control circuit 120 determines that the programming verification loop being performed on the current target memory cell group 114 is the first programming verification loop. Therefore, in step S306, the memory control circuit 120 determines whether the first part G1 of the target memory cell group 114 has one or more failed memory cells. If yes, in step S308, the memory control circuit 120 applies a programming voltage Vprg to the failed memory cells of the first part G1, and then proceeds to S310. If no, it proceeds directly to S310 after step S306.

[0030] In step S310, the memory control circuit 120 determines whether the second portion G2 of the target memory cell group 114 has one or more failed memory cells. If yes, in step S312, the memory control circuit 120 applies a programming voltage Vprg to the failed memory cells of the second portion G2, and then proceeds to S314. If no, it proceeds directly to S314 after step S310.

[0031] After performing the first programming verification cycle on the target memory cell group 114, in step S314, the memory control circuit 120 sets the count flag FT to a second value (e.g., "1"), and then returns to step S302 to continue the second programming verification cycle.

[0032] When the memory control circuit 120 determines in step S304 that the count flag FT stored in the flag register 130 is not the first value (but the second value), the memory control circuit 120 can determine that the programming verification cycle performed on the current target memory cell group 114 is a programming verification cycle other than the first one (e.g., the second, third, etc.). Therefore, in step S316, the memory control circuit 120 simultaneously programs the two parts G1 to G2 of the target memory cell group 114. Specifically, the memory control circuit 120 can simultaneously apply the programming voltage Vprg to all the failed memory cells of the two parts G1 to G2. Then, it returns to step S302 to continue the next programming verification cycle.

[0033] On the other hand, when the memory control circuit 120 determines in step S302 that the target memory cell group 114 has passed the programming verification, in step S318, the memory control circuit 120 determines whether the target memory cell group 114 is the last memory cell group among all memory cell groups 112 to be programmed. If yes, proceed to S320 to end the programming operation of the memory array 110. If no, in step S322, the memory control circuit 120 sets the next memory cell group in the memory cell group 112 as the target memory cell group 114, and then proceeds to S302 to continue the programming operation.

[0034] In summary, the flash memory device and programming method of the present invention can dynamically adjust the number of memory cells programmed simultaneously in the programming verification cycle. This reduces the time spent on programming operations while still considering pump capacity limitations.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flash memory device, characterized in that, include: A memory array having multiple groups of memory cells; as well as A memory control circuit, coupled to the memory array, is configured to sequentially program the plurality of memory cell groups. If a target memory cell group fails the programming verification among the plurality of memory cell groups, the memory control circuit performs one or more programming verification cycles on the target memory cell group. The target storage unit group is divided into M parts, where M is a positive integer greater than 1. The memory control circuit determines whether the programming verification loop executed on the target memory cell group is the first programming verification loop. When the first programming verification loop is executed on the target memory cell group, the memory control circuit programs the M parts sequentially.

2. The flash memory device according to claim 1, characterized in that, When the first programming verification loop is performed on the target memory cell group, the memory control circuit sets the initial value of K to 1 and determines whether the Kth part of the target memory cell group has one or more failed memory cells. If so, the memory control circuit applies a programming voltage to the one or more failed memory cells in the Kth part.

3. The flash memory device according to claim 2, characterized in that, The memory control circuit increments K to continue the judgment for the next part, and repeats the steps of judging whether the Kth part has one or more failed memory cells and incrementing K until K is greater than M.

4. The flash memory device according to claim 1, characterized in that, When the programming verification loop is executed on the target memory cell group except for the first one, the memory control circuit simultaneously programs the M parts.

5. The flash memory device according to claim 1, characterized in that, The flash memory device further includes a flag register for storing a count flag, the flag register being coupled to the memory control circuit, the memory control circuit determining, based on the count flag, whether the programming verification loop executed on the target memory cell group is the first programming verification loop.

6. The flash memory device according to claim 5, characterized in that, When the count flag is a first value, the programming verification loop executed on the target storage unit group is the first programming verification loop; when the count flag is a second value, the programming verification loop executed on the target storage unit group is the programming verification loop other than the first one.

7. The flash memory device according to claim 5, characterized in that, The memory control circuit sets the initial value of the count flag to a first value, and after performing the first programming verification loop on the target memory cell group, the memory control circuit sets the count flag to a second value.

8. The flash memory device according to claim 1, characterized in that, If the target storage cell group passes the programming verification, the memory control circuit determines whether the target storage cell group is the last storage cell group. If not, the memory control circuit sets the next storage cell group as the target storage cell group for the programming operation.

9. The flash memory device according to claim 1, characterized in that, The size of M depends on the pump capacity of the flash memory device.

10. A method for programming a flash memory device, characterized in that, The flash memory device includes a memory array having multiple groups of memory cells, and the programming method includes the following steps: The programming operations are performed sequentially on the multiple groups of storage units; If a target storage unit group fails the programming verification in the plurality of storage unit groups, one or more programming verification loops are performed on the target storage unit group, wherein the target storage unit group is divided into M parts, where M is a positive integer greater than 1; Determine whether the programming verification loop executed on the target storage unit group is the first programming verification loop; as well as When the first programming verification loop is performed on the target storage unit group, the M parts are programmed sequentially.

11. The programming method according to claim 10, characterized in that, The steps for programming the M parts in sequence include: Set the initial value of K to 1; Determine whether the Kth part of the target storage unit group has one or more failed storage units; and If so, a programming voltage is applied to the one or more failed memory cells of the Kth part.

12. The programming method according to claim 11, characterized in that, The steps of sequentially programming the M parts also include: Increment K to continue the judgment for the next part; and Repeat the steps of determining whether the Kth part has one or more failed storage units and incrementing K until K is greater than M.

13. The programming method according to claim 10, characterized in that, Also includes: While the programming verification loop is executed on the target storage unit group except for the first one, the M parts are programmed simultaneously.

14. The programming method according to claim 10, characterized in that, The flash memory device further includes a flag register for storing a count flag, and the step of determining whether the programming verification loop executed on the target memory cell group is the first programming verification loop includes: Based on the count flag, determine whether the programming verification loop executed on the target storage unit group is the first programming verification loop.

15. The programming method according to claim 14, characterized in that, When the count flag is a first value, the programming verification loop executed on the target storage unit group is the first programming verification loop; when the count flag is a second value, the programming verification loop executed on the target storage unit group is the programming verification loop other than the first one.

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