A health management method for multi-channel optical fiber data receiving based on FPGA and DSP

Abstract

The application relates to the technical field of data processing, in particular to a health management method for multi-channel optical fiber data reception based on FPGA and DSP. The method combines the advantages of FPGA and DSP, can realize decoupling of the number of data channels, data rates and reception modes through parameter configuration, realizes the functions of calibration, data verification and alignment and detection information reporting of the multi-channel optical fiber data reception, is particularly suitable for a radar system with a large number of antenna array output channels and complex data rate combinations, has the characteristics of strong universality, good detection performance, wide application scenarios and the like, and can provide accurate and reliable health data for users.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data processing, in particular to a health management method for multi-channel optical fiber data reception based on FPGA and DSP. BACKGROUND

[0002] Before radar signal processing, array element data output by an antenna needs to be received. With increasing complexity of radar functions and tasks, the number of channels output by a radar front-end antenna is also increasing, and data rates also appear more variable. FPGA is very suitable for multi-channel data reception work due to its own characteristics.

[0003] In the implementation process of a radar signal processing algorithm, it is very important to be able to timely find errors in multi-channel data, because in high-speed communication, the clock frequency is very high. To meet the wiring requirements of FPGA, clock data recovery technology is usually used to ensure the accuracy and stability of data acquisition, and the accuracy and stability of input data often determine the performance of subsequent radar detection.

[0004] In the traditional method for multi-channel optical fiber data reception based on FPGA, when the number of data channels or data rates of the previous stage changes, the data reception mode is coupled, and there is no verification capability for the correctness of any one data. When data results are abnormal, it is not possible to quickly locate and report, and the problem of long debugging period is faced. Therefore, for the increasingly complex radar front-end array and the increasingly flexible and variable sampling rate, how to quickly implement health management of data reception has a great influence on the performance of radar target detection. SUMMARY

[0005] Therefore, embodiments of the present application propose a health management method for multi-channel optical fiber data reception based on FPGA and DSP. Through parameter configuration, the number of data channels, data rates and reception modes are decoupled, and through detection management, the accuracy of multi-channel data is checked and reported. The method has the characteristics of high flexibility, strong universality, complete detection performance and wide adaptation to scenarios.

[0006] In order to achieve the above object, the embodiment of the present application proposes a health management method for multi-channel optical fiber data reception based on FPGA and DSP, which is suitable for radar array antennas, and the method comprises the following steps: step 1, calling a GT high-speed transceiver module by FPGA, checking the reset code, idle code and start code in the data item content of each optical fiber channel, and generating a channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel; wherein the internal part of each transceiver of the GT high-speed transceiver module realizes data byte alignment and clock correction functions; step 2, generating a reset signal according to the reset code, re-counting the valid data length in the data item content of each optical fiber channel, generating a channel data valid flag signal when the first valid data is a frame header and the valid data length is greater than a preset reception threshold value, and counting the total number of channel data valid flag signals; step 3, inputting the data of each optical fiber channel into the corresponding buffer area, generating a read valid pulse when the total number of channel data valid flag signals meets the preset number requirement, generating a read data rate matched with the input data rate, and finally obtaining the valid data after multi-channel optical fiber alignment according to the channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel; step 4, packaging the channel GT optical fiber hardware circuit link state signal and the channel data valid flag signal of each optical fiber channel, sending them to the DSP after adding frame header information, realizing fast positioning of whether the multi-channel optical fiber data reception is valid, and realizing health management of the multi-channel optical fiber data reception.

[0007] To achieve the above object, the embodiment of the present application also proposes a health management system for multi-channel optical fiber data reception based on FPGA and DSP, which is suitable for radar array antennas, and the system comprises: a channel GT optical fiber hardware circuit link detection state signal generation module, which is configured to call a GT high-speed transceiver module through an FPGA, check a reset code, an idle code and a start code in data item content of each optical fiber channel, and generate a channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel, and the GT high-speed transceiver module is internally provided with a data byte alignment and clock correction function; a channel data valid flag signal generation module, which is configured to generate a reset signal according to the reset code, re-count the valid data length in the data item content of each optical fiber channel, generate a channel data valid flag signal when the first valid data is a frame header and the valid data length is greater than a preset reception threshold value, and count the total number of channel data valid flag signals; an effective data alignment module, which is configured to input the data of each optical fiber channel into a corresponding buffer area, generate a read valid pulse when the total number of channel data valid flag signals meets a preset number requirement, generate a read data rate matched with the input data rate, and finally obtain the valid data of the multi-channel optical fiber after alignment according to the channel GT optical fiber hardware circuit link detection state signals of each optical fiber channel; and an execution module, which is configured to uniformly pack the channel GT optical fiber hardware circuit link state signals and the channel data valid flag signals of each optical fiber channel, send the signals to a DSP after adding frame header information, quickly locate whether the multi-channel optical fiber data reception is valid, and implement health management of the multi-channel optical fiber data reception.

[0008] To achieve the above object, the embodiment of the present application also proposes an electronic device, which comprises: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the health management method for multi-channel optical fiber data reception based on FPGA and DSP as described above.

[0009] To achieve the above object, the embodiment of the present application also proposes a computer readable storage medium, which stores a computer program, and the computer program is executable by a processor to implement the health management method for multi-channel optical fiber data reception based on FPGA and DSP as described above.

[0010] The embodiment of the application proposes a health management method for multi-channel optical fiber data reception based on FPGA and DSP. The method is aimed at multi-channel data output by a radar array antenna. In order to adapt to different numbers of output channels and different output data rates, the advantages of FPGA and DSP are fully combined. Through parameter configuration, the decoupling of the number of data channels, the data rate and the reception mode is realized, and the functions of calibration, data verification and alignment and detection information reporting for multi-channel optical fiber data reception are realized. The method is especially suitable for radar systems with a large number of antenna array output channels and complex data rate combinations, has strong universality, good detection performance and wide application scenarios, and can provide accurate and reliable health data for users. The method has the functions of detection and reporting of data of each optical fiber channel, has strong detection performance and high real-time performance, realizes loose coupling of input data rate and read data rate, does not require a large number of buffer zones, saves storage resources, realizes decoupling of the number of output channels of the radar array antenna and the number of high-speed reception channel modules, and enhances the universality and applicability of the system.

[0011] Optionally, when the output channels of the radar array antenna are expanded and the data rate of the array elements changes, the number of GT high-speed transceiver modules called and the read data rate are reconfigured according to parameters, and the validity of the multi-channel data is detected and reported in real time. Steps 1 to 4 are repeated, and the health management of the multi-channel optical fiber data reception is realized.

[0012] Optionally, the maximum number of channels of the received antenna array output data of a single FPGA is N, the number of array elements of a single optical fiber channel is M, the data rate of a single array element is T, the threshold value of the number of data of a single array element is K, the total number of array elements received by a single FPGA is NXM, the input data rate of a single optical fiber channel is TXM, and the frequency F of the working clock of the FPGA satisfies F>TXM.

[0013] The FPGA calls the IP core of the GT high-speed transceiver module, instantiates N GT high-speed transceiver data channels, configures the line rate, the data bit width and the encoding mode, introduces K codes to determine the boundary of the data received by the GT high-speed transceiver module, performs byte alignment, introduces a 4-byte clock verification sequence for clock correction when the read and write rates in the IP core of the GT high-speed transceiver module are inconsistent, and when the rxdisperr signal and the rxnotintable signal output by the IP core of the GT high-speed transceiver module are both greater than zero, it is considered that the GT high-speed transceiver module is calibrated incorrectly, otherwise it is considered that the GT high-speed transceiver module is calibrated correctly.

[0014] When the FPGA checks the reset code, idle code and start code in the data item content of each fiber channel, the lower 8 bits of the reset code, idle code and start code in the issued reset code, idle code and start code are consistent with the K code, and the idle code is also consistent with the clock check sequence. When charisk is 1 and any one of the reset code, idle code and start code is incorrect, it is considered that there is a bit error when the GT high-speed transceiver module receives the fiber data, otherwise it is considered that there is no bit error. When the calibration is correct and there is no bit error, it is considered that the channel GT fiber hardware circuit link is normal.

[0015] Optionally, in the process of generating the channel data valid flag signal, when charisk is 1 and the reset code is correct, the valid data counter is cleared. When charisk is 0, the data valid enable signal is pulled high, the data valid enable signal is equal to the chariskdata signal, and the data valid counter signal is accumulated. When the data valid enable signal and the data valid counter signal are both 1, the data valid enable signal is equal to the frame header, and the data frame header valid flag is generated. When the data valid counter signal is greater than the received valid data threshold number K, the data length valid flag is generated.

[0016] The FPGA instantiates N GT high-speed transceiver data channels inside. The actual output channel number of the radar array antenna is less than or equal to N. The actual output channel number is controlled by a parameter. The total number of channel data valid flag signals is counted. When the total number of channel data valid flag signals is equal to the actual output channel number, the channel data valid flag signal of the actual output channel is pulled high.

[0017] Optionally, the data of the N fiber channels is buffered in N FIFOs. The valid enable signal of the data of the first fiber channel is the write enable signal of the first FIFO. The channel data valid flag signal of the first fiber channel is the write data signal of the first FIFO. The reset code valid signal of the first fiber channel is the reset signal of the first FIFO. The same is true for the other channels.

[0018] When the channel data valid flag signal of the actual output channel in step 2 is pulled high, the FIFO read enable signal is generated. The N FIFOs share the same read enable signal, so that the data of the N fiber channels is aligned and output at the same time. The read data rate is (T x M) / F, which ensures the balance of the input and output data rates. The buffer area of each FIFO is greater than the received valid data threshold number K. When the channel GT fiber hardware circuit link of any one fiber channel is normal, the valid data read from the FIFO corresponding to the channel is input to the next module for processing, otherwise the valid data read from the FIFO corresponding to the channel is not input to the next module.

[0019] Optionally, the detection flag signals generated by each optical fiber channel are arranged and stored, and the arrangement rule is that the first 4 bytes contain the channel GT optical fiber hardware circuit link state signal, the rxdisperr signal, the rxnotintable signal, the error code generation signal, the channel data valid flag signal, the data frame header valid flag signal and the data length valid flag signal of the first optical fiber channel, and so on, and a frame header is added at the front end of the entire data item;

[0020] The CPI count and the PRF count are stored in a memory interval agreed in advance with the DSP, and an interrupt doorbell signal is generated at the last PRF period of each CPI to inform the DSP to perform parameter receiving processing, and the DSP analyzes the data receiving correctness of any one of the multi-channel optical fibers of the FPGA in real time according to the protocol.

[0021] Optionally, when the output channels of the radar array antenna are expanded and the data rate of the array elements is changed, the effective channel number of the FPGA receiving optical fiber is configured according to the number of the array output channels, the reading rate is configured, and the data of each optical fiber channel is calibrated, checked, aligned and detected to report the information, so as to realize the data receiving management function of the new array. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the following drawings are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor, and the drawings described herein are only used to explain the present application, and not to limit the present application.

[0023] Figure 1 is a flow chart of a health management method for multi-channel optical fiber data receiving based on FPGA and DSP provided in an embodiment of the present application;

[0024] Figure 2 is a schematic diagram of the visualization details of the health management method for multi-channel optical fiber data receiving based on FPGA and DSP provided in an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of the optical fiber channel data input timing provided in an embodiment of the present application;

[0026] Figure 4 is a schematic diagram of the reading pulse generation process provided in an embodiment of the present application;

[0027] Figure 5is a schematic diagram of the cache data alignment output provided in an embodiment of the present application;

[0028] Figure 6 is a timing diagram of the information reporting interrupt signal generation provided in an embodiment of the present application;

[0029] Figure 7 is a schematic diagram of the digital array channel expansion provided in an embodiment of the present application;

[0030] Figure 8 is a schematic diagram of a health management system structure of a multi-channel optical fiber data receiving based on FPGA and DSP provided in another embodiment of the present application;

[0031] Figure 9 is a schematic diagram of an electronic device structure provided in another embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. Those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The following embodiments are classified for the convenience of description, and should not constitute any limitation on the specific implementation of the present application. The following embodiments can be combined and referenced with each other without contradiction.

[0033] An embodiment of the present application proposes a health management method of multi-channel optical fiber data receiving based on FPGA and DSP, which is suitable for radar array antennas. The implementation details of the health management method of multi-channel optical fiber data receiving based on FPGA and DSP proposed in the embodiment will be described in detail below. The following content only provides related implementation details for the convenience of understanding, and is not necessary for implementing the present solution.

[0034] The specific process of the health management method of multi-channel optical fiber data receiving based on FPGA and DSP proposed in the embodiment can be as shown in Figure 1 The specific process of the health management method of multi-channel optical fiber data receiving based on FPGA and DSP proposed in the embodiment can be as shown in Figure 2 The method comprises the following steps.

[0035] In step 11, the GT high-speed transceiver module is called by the FPGA to check the reset code, idle code and start code in the data item content of each optical fiber channel, and to generate a channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel.

[0036] In a specific implementation, the health management method proposed in the embodiment is realized based on two processing platforms of FPGA and DSP. The FPGA starts first, calls a GT high-speed transceiver module (GT high-speed transceiver) through the FPGA, checks the reset code, idle code and start code in the data item content of each fiber channel, and generates a channel GT fiber hardware circuit link detection state signal of each fiber channel. The data byte alignment and clock correction functions are realized in the internal of each transceiver of the GT high-speed transceiver module.

[0037] In one example, the number of channels of the maximum receiving antenna array output data of a single FPGA is configured as N, the number of array elements of a single fiber channel is M (N and M are both integers greater than 1), the rate of the data transmitted by a single array element is T (T is greater than 0), and the threshold value of the number of data transmitted by a single array element is K (K is also an integer greater than 1). Based on this, the total number of array elements received by a single FPGA is N×M, the input data rate of a single fiber channel is T×M, and the frequency F of the working clock of the FPGA needs to satisfy F>T×M.

[0038] In one example, the FPGA calls the IP core of the GT high-speed transceiver module, instantiates N GT high-speed transceiver data channels, configures the line rate, data bit width and encoding mode, introduces K code (K28.5 form) to determine the boundary of the data received by the GT high-speed transceiver module, so as to perform byte alignment. At the same time, a 4-byte clock check sequence is introduced to correct the clock when it is detected that the read-write rate in the internal of the IP core of the GT high-speed transceiver module is inconsistent. When it is detected that the rxdisperr signal and the rxnotintable signal output by the IP core of the GT high-speed transceiver module are both greater than zero, it is considered that the GT high-speed transceiver module calibration is incorrect, and when it is detected that at least one of the rxdisperr signal and the rxnotintable signal output by the IP core of the GT high-speed transceiver module is less than or equal to zero, it is considered that the GT high-speed transceiver module calibration is correct.

[0039] In one example, as shown in Figure 3 When checking the reset code, idle code and start code in the data item content of each fiber channel, the low 8 bits in the reset code, idle code and start code issued by the FPGA are consistent with the K code, and the idle code is also consistent with the clock check sequence. When charisk is 1 and any one of the reset code, idle code and start code is not correctly checked, it is considered that there is an error code when the GT high-speed transceiver module receives the fiber data, otherwise it is considered that there is no error code. When the calibration is correct and there is no error code, it is considered that the channel GT fiber hardware circuit link is normal, and the channel GT fiber hardware circuit link detection state signal can be generated for the fiber channel.

[0040] Step 12, reset signal is generated according to the reset code, and the length of valid data in the data item content of each fiber channel is re-counted. When the first valid data is a frame header and the length of valid data is greater than a preset receiving threshold, a channel data valid flag signal is generated, and the total number of channel data valid flag signals is counted.

[0041] In a specific implementation, after the channel GT fiber hardware circuit link detection state signal of each fiber channel is generated, a reset signal is generated according to the reset code, and the length of valid data in the data item content of each fiber channel is re-counted. When the first valid data is a frame header and the length of valid data is greater than a preset receiving threshold, a channel data valid flag signal is generated, and the total number of channel data valid flag signals is counted.

[0042] In an example, in the process of generating the channel data valid flag signal, when charisk is 1 and the reset code is correct, the valid data counter is cleared, when charisk is 0, the data valid enable signal is pulled high, the data valid enable signal is equal to the chariskdata signal, and the data valid counter signal is accumulated. When the data valid enable signal and the data valid counter signal are both 1, the data valid enable signal is equal to the frame header, at this time the data frame header valid flag is generated, otherwise it is not generated. When the data valid counter signal is greater than the receiving valid data threshold number K, the data length valid flag is generated, otherwise it is not generated.

[0043] That is, only when the data frame header valid flag is pulled high and the data length valid flag is pulled high, the channel data valid flag signal is generated, and the generation of each channel data valid flag signal is the same.

[0044] In an example, N GT high-speed transceiver data channels are instantiated in the FPGA, and the actual output channel number of the radar array antenna may be less than or equal to N. The actual output channel number can be controlled by a parameter. The total number of channel data valid flag signals is counted, and when the total number of channel data valid flag signals is equal to the actual output channel number, the channel data valid flag signal of the actual output channel is pulled high. This process can be as shown in Figure 4 .

[0045] Step 13, input the data of each fiber channel into the corresponding buffer area, when the total number of channel data valid flag signals meets the preset number requirement, generate a read valid pulse, and generate a read data rate matched with the input data rate, and finally obtain the valid data after multi-channel fiber alignment according to the channel GT fiber hardware circuit link detection state signal of each fiber channel.

[0046] In a specific implementation, after the channel data valid flag signal is generated, the data of each optical fiber channel needs to be input into the corresponding buffer area, when the total number of channel data valid flag signals meets the preset number requirement, a read valid pulse is generated, and a read data rate matching the input data rate is generated, and finally the valid data of the aligned multi-channel optical fiber is obtained according to the channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel.

[0047] In one example, the data of N optical fiber channels is buffered in N FIFOs, the valid enable signal of the data of the first optical fiber channel is the write enable signal of the first FIFO, the channel data valid flag signal of the first optical fiber channel is the write data signal of the first FIFO, the reset code valid signal of the first optical fiber channel is the reset signal of the first FIFO, and so on, the valid enable signal of the data of the Nth optical fiber channel is the write enable signal of the Nth FIFO, the channel data valid flag signal of the Nth optical fiber channel is the write data signal of the Nth FIFO, and the reset code valid signal of the Nth optical fiber channel is the reset signal of the Nth FIFO.

[0048] In one example, when the channel data valid flag signal of the actual output channel is pulled high, a FIFO read enable signal is generated, and N FIFOs share the same read enable signal, so that the data of N optical fiber channels is aligned and output at the same time. The process can be as shown in Figure 5 The read data rate is (T x M) / F, which ensures the balance of input and output data rates. At this time, the buffer area of each FIFO only needs to be greater than the received valid data threshold K, which greatly saves the storage resources.

[0049] In one example, when the channel GT optical fiber hardware circuit link of any optical fiber channel is normal, the valid data read from the FIFO corresponding to the channel is input to the next module for processing, otherwise the valid data read from the FIFO corresponding to the channel is not input to the next module.

[0050] Step 14, the channel GT optical fiber hardware circuit link state signal and the channel data valid flag signal of each optical fiber channel are packaged together, after adding frame header information, they are sent to DSP, realizing fast positioning of whether the multi-channel optical fiber data reception is valid, and realizing health management of the multi-channel optical fiber data reception.

[0051] In a specific implementation, after obtaining the valid data after the multi-channel fiber alignment, the channel GT fiber hardware circuit link state signal, the channel data valid flag signal of each fiber channel are uniformly packed, and after adding the frame header information, they are sent to the DSP, and the DSP processing platform realizes the rapid positioning of whether the multi-channel fiber data reception is valid, and realizes the health management of the multi-channel fiber data reception.

[0052] In one example, when the output channel of the radar array antenna is expanded and the data rate of the array element changes, the number of called GT high-speed transceiver modules and the read data rate can be reconfigured according to parameters, and the validity of the multi-channel data is detected and reported in real time, and the steps 11 to 14 are repeated, so as to realize the health management of the multi-channel fiber data reception.

[0053] In one example, the embodiment arranges and stores the detection flag signals generated by each fiber channel, and the arrangement rule is that the first 4 bytes contain the channel GT fiber hardware circuit link state signal, the rxdisperr signal, the rxnotintable signal, the error code generation signal, the channel data valid flag signal, the data frame header valid flag signal and the data length valid flag signal of the first fiber channel. In this way, the first 4 bytes contain the channel GT fiber hardware circuit link state signal, the rxdisperr signal, the rxnotintable signal, the error code generation signal, the channel data valid flag signal, the data frame header valid flag signal and the data length valid flag signal of the first fiber channel. Finally, the frame header is added at the front end of the entire data item.

[0054] In one example, the CPI count, PRF count and other parameters are stored in the memory interval agreed with the DSP in advance. At the last PRF period of each CPI, an interrupt doorbell signal is generated to inform the DSP to perform parameter receiving processing, as shown in Figure 6 The DSP can analyze the data reception correctness of any one of the multi-channel fiber channels of the FPGA in real time according to the protocol.

[0055] In one example, when the output channel of the radar array antenna is expanded and the data rate of the array element changes, the number of effective channels of the FPGA receiving fiber is configured according to the number of array output channels, and the read rate is also configured, and the calibration, verification, alignment and detection information reporting of each fiber channel data are performed to realize the data reception management function of the new array, as shown in Figure 7The unused channel receiving data is set to zero. When the channel is expanded, the instantiated channel number N is reconfigured to the latest channel number to meet the requirements. If the data rate needs to be adjusted, the processing platform operating frequency needs to be greater than the product of the number of elements and the single-element data rate to achieve the balance of read and write data rates. Finally, the physical layer calibration information and data validity judgment information of each channel are reported to the DSP processing platform, and the health management of the FPGA end multi-channel optical fiber receiving data is completed.

[0056] The health management method of the multi-channel optical fiber data reception based on FPGA and DSP proposed in the embodiment is suitable for the multi-channel data output by the radar array antenna. In order to adapt to different output channel numbers and different output data rates, the advantages of FPGA and DSP are fully combined. The decoupling of the data channel number, the data rate and the reception mode can be realized through parameter configuration. The functions of calibration, data verification and alignment and detection information reporting of the multi-channel optical fiber data reception are realized. The method is especially suitable for radar systems with a large number of antenna array output channels and complex data rate combinations. The method has the characteristics of strong universality, good detection performance and wide application scenarios, and can provide accurate and reliable health data for users. The method has the functions of detection and reporting of the data of each optical fiber channel. The detection is strong and the real-time performance is high. The input data rate and the read data rate are loosely coupled. A large number of buffer areas are not needed. The storage resources are saved. The decoupling of the number of output channels of the radar array antenna and the number of high-speed receiving channel modules is realized. The universality and applicability of the system are enhanced.

[0057] The steps of the above methods are only for clear description. Some steps can be combined into one step or some steps can be divided into multiple steps. As long as the same logical relationship is included, it is within the protection scope of the application. Irrelevant modifications or irrelevant designs are added to the algorithm or the flow. However, the core design of the algorithm and the flow is not changed. It is within the protection scope of the application.

[0058] Another embodiment of the application provides a health management system of multi-channel optical fiber data reception based on FPGA and DSP, which is suitable for a radar array antenna. The details of the health management system of multi-channel optical fiber data reception based on FPGA and DSP proposed in the embodiment are described below. The following content is only provided for the implementation details for easy understanding, and is not necessary for implementing the embodiment. Figure 8Fig. 1 is a structural schematic diagram of a health management system for multi-channel optical fiber data reception based on FPGA and DSP according to the embodiment, which comprises a channel GT optical fiber hardware circuit link detection state signal generation module 21, a channel data valid flag signal generation module 22, a valid data alignment module 23 and an execution module 24.

[0059] The channel GT optical fiber hardware circuit link detection state signal generation module 21 is configured to check the reset code, idle code and start code in the data item content of each optical fiber channel through the FPGA calling GT high-speed transceiver module, and generate the channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel, and the internal of each transceiver of the GT high-speed transceiver module realizes the data byte alignment and clock correction function.

[0060] The channel data valid flag signal generation module 22 is configured to generate a reset signal according to the reset code, re-count the valid data length in the data item content of each optical fiber channel, generate a channel data valid flag signal when the first valid data is a frame header and the valid data length is greater than a preset reception threshold value, and count the total number of channel data valid flag signals.

[0061] The valid data alignment module 23 is configured to input the data of each optical fiber channel into the corresponding buffer area, generate a read valid pulse when the total number of channel data valid flag signals meets the preset number requirement, generate a read data rate matched with the input data rate, and finally obtain the valid data of the multi-channel optical fiber after alignment according to the channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel.

[0062] The execution module 24 is configured to uniformly pack the channel GT optical fiber hardware circuit link state signal and the channel data valid flag signal of each optical fiber channel, send them to the DSP after adding frame header information, realize the fast positioning of whether the multi-channel optical fiber data reception is valid, and realize the health management of the multi-channel optical fiber data reception.

[0063] It is not difficult to find that the embodiment is a system embodiment corresponding to the above-mentioned method embodiment, and the embodiment can be implemented in cooperation with the above-mentioned method embodiment. The related technical details and technical effects mentioned in the above-mentioned method embodiment are still effective in the embodiment. In order to reduce repetition, they will not be described here. Correspondingly, the related technical details mentioned in the embodiment can also be applied to the above-mentioned method embodiment.

[0064] It is worth mentioning that each module and module involved in the embodiment is a logical module. In actual application, one logical unit can be one physical unit, or a part of one physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, units not closely related to solving the technical problems proposed in the present application are not introduced in the embodiment, but this does not mean that there are no other units in the embodiment.

[0065] Another embodiment of the present application provides an electronic device, such as Figure 9 As shown in the figure, comprising: at least one processor 31;And, the memory 32 connected with the at least one processor 31;Wherein, the memory 32 stores the instruction that can be executed by the at least one processor 31, the instruction is executed by the at least one processor 31, to enable the at least one processor 31 can execute the health management method of multi-channel optical fiber data reception based on FPGA and DSP as described in the above method embodiment.

[0066] Wherein, the memory and the processor are connected in a bus mode, the bus includes any number of interconnected buses and bridges, and the bus connects one or more processors and various circuits of the memory together. The bus can also connect various other circuits such as peripheral devices, voltage regulators and power management circuits together, which are well known in the art, and therefore will not be further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, which provide units for communicating with various other devices on the transmission medium.

[0067] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management and other control functions. And the memory can be used to store the data used by the processor in the execution operation.

[0068] Another embodiment of the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is executed by the processor, and can realize the health management method of multi-channel optical fiber data reception based on FPGA and DSP as described in the above method embodiment.

[0069] That is, a person skilled in the art can understand that all or part of the steps in the above method embodiments can be completed by programs instructing relevant hardware, the programs are stored in a storage medium, and the programs include a plurality of instructions for causing a device (such as a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in the method embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0070] A person skilled in the art can understand that each of the above embodiments is a specific embodiment for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. For those skilled in the art, a number of improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements are also considered within the protection scope of the present application.

Claims

1. A health management method for FPGA and DSP based multi-channel fiber optic data reception, suitable for radar array antennas, characterized in that, The method comprises: Step 1, checking the reset code, idle code and start code in the data item content of each fiber channel by calling the GT high-speed transceiver module of the FPGA, and generating a channel GT fiber hardware circuit link detection state signal of each fiber channel; wherein the data byte alignment and clock correction functions are realized in the internal of each transceiver of the GT high-speed transceiver module; Step 2, generating a reset signal according to the reset code, re-counting the valid data length in the data item content of each fiber channel, generating a channel data valid flag signal when the first valid data is a frame header and the valid data length is greater than a preset receiving threshold value, and counting the total number of the channel data valid flag signal; Step 3, inputting the data of each fiber channel into the corresponding buffer area, generating a read valid pulse when the total number of the channel data valid flag signal meets the preset number requirement, generating a read data rate matched with the input data rate, and finally obtaining the valid data of the multi-channel fiber after alignment according to the channel GT fiber hardware circuit link detection state signal of each fiber channel; Step 4, packaging the channel GT fiber hardware circuit link state signal and the channel data valid flag signal of each fiber channel, adding frame header information, and sending to the DSP to realize the fast positioning of the validity of the multi-channel fiber data reception and the health management of the multi-channel fiber data reception; In step 1, the number of channels of the maximum receiving antenna array output data of a single FPGA is N, the number of elements of a single fiber channel is M, the rate of data transmitted by a single element is T, the threshold value of the number of data transmitted by a single element is K, the total number of elements received by a single FPGA is N×M, the input data rate of a single fiber channel is T×M, and the frequency F of the working clock of the FPGA satisfies F>T×M; The FPGA calls the IP core of the GT high-speed transceiver module, instantiates N GT high-speed transceiver data channels, configures the line rate, data bit width and encoding mode, introduces K code to determine the boundary of the data received by the GT high-speed transceiver module, performs byte alignment, introduces a 4-byte clock verification sequence for clock correction when the read and write rates are inconsistent in the internal of the IP core of the GT high-speed transceiver module, considers that the GT high-speed transceiver module calibration is incorrect when the rxdisperr signal and the rxnotintable signal output by the IP core of the GT high-speed transceiver module are both greater than zero, and considers that the GT high-speed transceiver module calibration is correct otherwise; When the FPGA checks the reset code, idle code and start code in the data item content of each fiber channel, the low 8 bits in the reset code, idle code and start code in the reset code, idle code and start code sent by the FPGA are consistent with the K code, and the idle code is also consistent with the clock verification sequence; when charisk is 1 and any one of the reset code, idle code and start code is not correctly checked, it is considered that there is an error code when the GT high-speed transceiver module receives the fiber data, otherwise it is considered that there is no error code; when the calibration is correct and there is no error code, it is considered that the channel GT fiber hardware circuit link is normal.

2. The health management method for multi-channel fiber data receiving based on FPGA and DSP according to claim 1, wherein, When the output channels of the radar array antenna are expanded and the data rate of the array element changes, the number of GT high-speed transceiver modules called, the read data rate, and the validity of the multi-channel data are supported to be reconfigured according to parameters, and the validity of the multi-channel data is detected and reported in real time, and steps 1 to 4 are repeated, so that the health management of the multi-channel optical fiber data receiving can be realized. 3.The health management method for multi-channel fiber data receiving based on FPGA and DSP according to claim 1, wherein, In the process of generating the channel data validity flag signal, when charisk is 1 and the reset code is correct, the valid data counter is cleared, when charisk is 0, the data validity enable signal is pulled high, the data validity enable signal is equal to the charisk data signal, the data validity counter signal is accumulated, when the data validity enable signal and the data validity counter signal are both 1, the data validity enable signal is equal to the frame header, the data frame header validity flag is generated, and when the data validity counter signal is greater than the received valid data threshold number K, the data length validity flag is generated. The FPGA instantiates N GT high-speed transceiver data channels inside, the actual output channel number of the radar array antenna is less than or equal to N, the actual output channel number supports being controlled through parameters, and the total number of channel data validity flag signals is counted, when the total number of channel data validity flag signals is equal to the actual output channel number, the channel data validity flag signal of the actual output channel is pulled high.

4. The health management method for multi-channel fiber data receiving based on FPGA and DSP according to claim 3, characterized in that, The data of the N optical fiber channels is buffered in N FIFOs, the valid enable signal of the data of the first optical fiber channel is the write enable signal of the first FIFO, the channel data validity flag signal of the first optical fiber channel is the write data signal of the first FIFO, and the reset code validity signal of the first optical fiber channel is the reset signal of the first FIFO, and so on. When the channel data validity flag signal of the actual output channel in step 2 is pulled high, the FIFO read enable signal is generated, the N FIFOs share the same read enable signal, so that the data of the N optical fiber channels is aligned and output at the same time, until the empty signal of each FIFO is pulled high, the read data rate is (T x M) / F, the input and output data rates are balanced, and the buffer interval of each FIFO is greater than the received valid data threshold number K. When the channel GT optical fiber hardware circuit link of any one optical fiber channel is normal, the valid data read from the FIFO corresponding to the channel is input to the next module for processing, otherwise the valid data read from the FIFO corresponding to the channel is not input to the next module.

5. The health management method for multi-channel fiber data receiving based on FPGA and DSP according to claim 1, wherein, The detection flag signals generated by each optical fiber channel are arranged and stored, the arrangement rule is that the first 4 bytes contain the channel GT optical fiber hardware circuit link state signal, the rxdisperr signal, the rxnotintable signal, the error code generation signal, the channel data validity flag signal, the data frame header validity flag signal and the data length validity flag signal of the first optical fiber channel, and so on, and a frame header is added at the front end of the entire data item. CPI count, PRF count are stored in the memory area agreed with DSP in advance, at the last PRF period of each CPI, interrupt doorbell signal is generated to inform DSP to perform parameter receiving processing, DSP analyzes the data receiving correctness of any one optical fiber channel in the multi-channel optical fiber of FPGA in real time according to the protocol.

6. The health management method for multi-channel fiber data receiving based on FPGA and DSP according to claim 5, wherein, When the output channel of the radar array antenna is expanded and the data rate of the array element is changed, the effective channel number of the FPGA receiving optical fiber is configured according to the number of the array output channel, the read rate is configured at the same time, and the calibration, verification, alignment and detection information reporting of the data of each optical fiber channel are performed to realize the data receiving management function of the new array.

7. A health management system for FPGA and DSP based multi-channel fiber optic data reception, which is suitable for radar array antennas, to implement a health management method for FPGA and DSP based multi-channel fiber optic data reception as claimed in any one of claims 1 to 6, characterized in that, The system comprises: The channel GT optical fiber hardware circuit link detection state signal generation module is used for verifying the reset code, idle code and start code in the data item content of each optical fiber channel by calling the GT high-speed transceiver module of FPGA, and generating the channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel, and the data byte alignment and clock correction function are realized in each transceiver of the GT high-speed transceiver module; The channel data valid flag signal generation module is used for generating a reset signal according to the reset code, and re-counting the valid data length in the data item content of each optical fiber channel, and generating a channel data valid flag signal when the first valid data is a frame header and the valid data length is greater than a preset receiving threshold value, and counting the total number of channel data valid flag signals; The valid data alignment module is used for inputting the data of each optical fiber channel into the corresponding buffer area, generating a read valid pulse when the total number of channel data valid flag signals meets the preset number requirement, and generating a read data rate matched with the input data rate, and finally obtaining the aligned valid data of the multi-channel optical fiber according to the channel GT optical fiber hardware circuit link detection state signal of each optical fiber channel; The execution module is used for uniformly packing the channel GT optical fiber hardware circuit link state signal and the channel data valid flag signal of each optical fiber channel, sending them to DSP after adding frame header information, realizing the fast positioning of whether the multi-channel optical fiber data receiving is valid, and realizing the health management of the multi-channel optical fiber data receiving.

8. An electronic device, comprising: It comprises: At least one processor; And The memory is in communication connection with the at least one processor; wherein The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the health management method of the multi-channel optical fiber data receiving based on FPGA and DSP according to any one of claims 1-6.

9. A computer readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to realize the health management method of the multi-channel optical fiber data receiving based on FPGA and DSP according to any one of claims 1-6.

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