Semiconductor structure
Through the design of the all-around gate structure, the density of semiconductor components is increased and the size of transistor components is reduced, which solves the problem of increasing component density and enhances the current performance of transistor components.
Patent Information
- Application Number
- CN202410566575.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-18
- Filing Date
- 2024-05-09
- Publication Date
- 2025-10-28
AI Technical Summary
How to further increase the component density of semiconductor components to meet the demand for continuous size reduction.
A gate-all-around (GAA) structure is adopted, by stacking multiple separated gate layers on a substrate, each gate layer surrounds the corresponding channel layer, and a gate dielectric layer is set between adjacent channel layers to form multiple transistor elements connected in parallel.
It effectively increases the component density of semiconductor components, reduces component size, and improves the current-carrying capacity of transistor components.
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Figure CN120857484A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure comprising a gate-all-around (GAA) element. Background Technology
[0002] With advancements in semiconductor technology, the semiconductor industry continues to shrink the size of semiconductor components (such as transistors). This reduces the component footprint, thereby increasing the component density. However, further increasing the component density remains a continuous goal. Summary of the Invention
[0003] This invention provides a semiconductor structure that can effectively increase the device density of semiconductor devices.
[0004] This invention proposes a semiconductor structure comprising a substrate, multiple gate layers, multiple channel layers, and multiple gate dielectric layers. The multiple gate layers and multiple channel layers are stacked on the substrate. The multiple gate layers are separated from each other. Each gate layer surrounds a corresponding channel layer. Two adjacent gate layers are located between two adjacent channel layers. The multiple gate dielectric layers are located between the multiple gate layers and the multiple channel layers.
[0005] According to one embodiment of the present invention, in the above semiconductor structure, the substrate may be a silicon substrate or a glass substrate.
[0006] According to one embodiment of the present invention, in the above-described semiconductor structure, the materials of the plurality of gate layers may include TiN, Al, Ti, Pd, Cr, Cu, Mo, or combinations thereof.
[0007] According to one embodiment of the present invention, in the above-described semiconductor structure, the materials of the multiple channel layers may include oxide semiconductor materials or semiconductor materials.
[0008] According to one embodiment of the present invention, in the above-described semiconductor structure, the oxide semiconductor material may include InGaZnO (IGZO), InSnO, In2O3, InZnO, ZnO, GaO, ZnInSnO, or ZnSnO.
[0009] According to one embodiment of the present invention, in the above-described semiconductor structure, the semiconductor material may include Si, Ge, SiGe, GeSn, GaAs, GaSe, SiC, GaN, InP, AlGaAs, InGaP, or ZnSe.
[0010] According to one embodiment of the present invention, in the above-described semiconductor structure, a portion of the lowermost gate layer may be located between the substrate and the lowermost channel layer.
[0011] According to one embodiment of the present invention, in the above-described semiconductor structure, a portion of the lowermost gate dielectric layer may be located between the substrate and the lowermost channel layer.
[0012] According to one embodiment of the present invention, in the above-described semiconductor structure, the material of the plurality of gate dielectric layers may include a high dielectric constant dielectric material.
[0013] According to one embodiment of the present invention, in the above-described semiconductor structure, the high dielectric constant dielectric material may include Al2O3, HfO2, TiO2, ZrO2, La2O3, Y2O3, Ta2O5, or HfSiO4.
[0014] According to one embodiment of the present invention, the semiconductor structure described above may further include multiple transistor elements. The multiple transistor elements may include multiple gate layers, multiple channel layers, and multiple gate dielectric layers.
[0015] According to one embodiment of the present invention, in the above-described semiconductor structure, at least two transistor elements can be connected in parallel.
[0016] According to one embodiment of the present invention, the semiconductor structure described above may further include a plurality of first doped regions and a plurality of second doped regions. The plurality of first doped regions and the plurality of second doped regions are located in a plurality of channel layers. The plurality of first doped regions and the plurality of second doped regions may be located on opposite sides of a plurality of gate layers.
[0017] According to an embodiment of the present invention, in the above semiconductor structure, the plurality of transistor elements may further include a plurality of first doped regions and a plurality of second doped regions.
[0018] According to one embodiment of the present invention, in the above-described semiconductor structure, a plurality of transistor elements may include write transistor elements and read transistor elements.
[0019] According to one embodiment of the present invention, in the above-described semiconductor structure, the write transistor may include at least two transistor elements connected in parallel.
[0020] According to an embodiment of the present invention, in the above semiconductor structure, the first doped region of the write transistor can be electrically connected to the gate layer of the read transistor.
[0021] According to one embodiment of the present invention, the semiconductor structure described above may further include multiple sacrificial layers. The multiple sacrificial layers are located adjacent to multiple gate layers. The multiple sacrificial layers are located between multiple channel layers.
[0022] According to one embodiment of the present invention, the semiconductor structure described above may further include multiple dielectric layers. The multiple dielectric layers are located on multiple gate layers.
[0023] According to one embodiment of the present invention, in the above-described semiconductor structure, a portion of the lowermost dielectric layer may be located within a portion of the lowermost gate layer.
[0024] Based on the above, in the semiconductor structure proposed in this invention, multiple gate layers and multiple channel layers are stacked on a substrate, the multiple gate layers are separated from each other, each gate layer surrounds a corresponding channel layer, and two adjacent gate layers are located between two adjacent channel layers. Therefore, the semiconductor structure proposed in this invention can effectively increase the device density of semiconductor devices (e.g., transistor devices).
[0025] To make the above-mentioned features and advantages of the present invention readily apparent, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0026] Figure 1 This is a top view of a semiconductor structure according to some embodiments of the present invention;
[0027] Figure 2 For along Figure 1 Cross-sectional views of the semiconductor structure along sections I-I' and II-II' in the diagram;
[0028] Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0029] Figure 4 for Figure 3 A simplified circuit diagram of a semiconductor structure.
[0030] Symbol Explanation
[0031] 10: Semiconductor Structure
[0032] 100: Base
[0033] 102, 102A, 102B, 102C: Gate layers
[0034] 104, 104A, 104B, 104C: Channel layers
[0035] 106, 106A, 106B, 106C: Gate dielectric layers
[0036] 108, 108A, 108B, 108C, 110, 110A, 110B, 110C: Doped regions
[0037] 112, 112A, 112B, 112C: Sacrificial Layer
[0038] 114, 114A, 114B, 114C, 116: Dielectric layers
[0039] C1: Capacitor
[0040] IS1~IS12: Internal Wiring Structure
[0041] L1, L2, L3: Length
[0042] RBL: Read bit line
[0043] RT1: Read transistor components
[0044] RWL: Read word line
[0045] T1, T11, T12, T13: Transistor components
[0046] WBL: Write Bit Line
[0047] WT1: Write transistor element
[0048] WWL: Write to word line Detailed Implementation
[0049] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the top view are not drawn to the same scale as those in the sectional view. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.
[0050] Figure 1 This is a top view of a semiconductor structure according to some embodiments of the present invention. Figure 2 For along Figure 1 Cross-sectional views of the semiconductor structure along sections I-I' and II-II'. Figure 1 In the top view, omitted Figure 2 The cross-sectional view of some components is used to clearly illustrate... Figure 1 The positional relationship between the components.
[0051] Please refer to Figure 1 and Figure 2 The semiconductor structure 10 includes a substrate 100, a plurality of gate layers 102, a plurality of channel layers 104, and a plurality of gate dielectric layers 106. In some embodiments, the substrate 100 may be a silicon substrate or a glass substrate.
[0052] Multiple gate layers 102 and multiple channel layers 104 are stacked on a substrate 100. The multiple gate layers 102 are separated from each other. The gate layers 102 may be a single-layer structure or a multi-layer structure. In some embodiments, the materials of the multiple gate layers may include TiN, Al, Ti, Pd, Cr, Cu, Mo, or combinations thereof. In some embodiments, the materials of the multiple channel layers 104 may include oxide semiconductor materials or semiconductor materials. In some embodiments, the oxide semiconductor materials may include InGaZnO (IGZO), InSnO, In2O3, InZnO, ZnO, GaO, ZnInSnO, or ZnSnO. In some embodiments, the semiconductor materials may include Si, Ge, SiGe, GeSn, GaAs, GaSe, SiC, GaN, InP, AlGaAs, InGaP, or ZnSe.
[0053] Each gate layer 102 surrounds a corresponding channel layer 104. For example, gate layer 102A may surround channel layer 104A, gate layer 102B may surround channel layer 104B, and gate layer 102C may surround channel layer 104C. Two adjacent gate layers 102 are located between two adjacent channel layers 104. For example, gate layer 102A and gate layer 102B may be located between channel layer 104A and channel layer 104B, and gate layer 102B and gate layer 102C may be located between channel layer 104B and channel layer 104C.
[0054] In some embodiments, a portion of the lowermost gate layer 102 (e.g., gate layer 102A) may be located between the substrate 100 and the lowermost channel layer 104 (e.g., channel layer 104A). In some embodiments, the length L1 of channel layer 104A may be greater than the length L2 of channel layer 104B, and the length L2 of channel layer 104B may be greater than the length L3 of channel layer 104C. Furthermore, the number of gate layers 102 and the number of channel layers 104 are not limited to those shown in the figures. As long as there are multiple gate layers 102 and multiple channel layers 104, they fall within the scope of this invention.
[0055] Multiple gate dielectric layers 106 are located between multiple gate layers 102 and multiple channel layers 104. For example, gate dielectric layer 106A is located between gate layer 102A and channel layer 104A, gate dielectric layer 106B is located between gate layer 102B and channel layer 104B, and gate dielectric layer 106C is located between gate layer 102C and channel layer 104C. In some embodiments, the material of the multiple gate dielectric layers 106 may include a high dielectric constant dielectric material. In some embodiments, the high dielectric constant dielectric material may include Al2O3, HfO2, TiO2, ZrO2, La2O3, Y2O3, Ta2O5, or HfSiO4. Furthermore, the number of gate dielectric layers 106 is not limited to the number shown in the figure. As long as there are multiple gate dielectric layers 106, they are within the scope of this invention.
[0056] In some embodiments, a portion of the lowermost gate dielectric layer 106 (e.g., gate dielectric layer 106A) may be located between the substrate 100 and the lowermost channel layer 104 (e.g., channel layer 104A). In some embodiments, gate layer 102A and gate layer 102B may be separated from each other via gate dielectric layer 106B. In some embodiments, gate layer 102B and gate layer 102C may be separated from each other via gate dielectric layer 106C.
[0057] In some embodiments, the semiconductor structure 10 may further include a plurality of doped regions 108 and a plurality of doped regions 110. The plurality of doped regions 108 and 110 are located in a plurality of channel layers 104. The plurality of doped regions 108 and 110 may be located on opposite sides of a plurality of gate layers 102. For example, doped region 108A and a plurality of doped regions 110A may be located in channel layer 104A, and the plurality of doped regions 108A and 110A may be located on opposite sides of gate layer 102A. Doped region 108B and a plurality of doped regions 110B may be located in channel layer 104B, and the plurality of doped regions 108B and 110B may be located on opposite sides of gate layer 102B. Doped region 108C and a plurality of doped regions 110C may be located in channel layer 104C, and the plurality of doped regions 108C and 110C may be located on opposite sides of gate layer 102C.
[0058] In some embodiments, the semiconductor structure 10 may further include a plurality of sacrificial layers 112. The plurality of sacrificial layers 112 are located adjacent to a plurality of gate layers 102. The plurality of sacrificial layers 112 are located between a plurality of channel layers 104. For example, sacrificial layer 112A may be located adjacent to gate layer 102A. Sacrificial layer 112B may be located adjacent to gate layers 102A and 102B, and may be located between channel layers 104A and 104B. Sacrificial layer 112C may be located adjacent to gate layers 102B and 102C, and may be located between channel layers 104B and 104C. In some embodiments, the material of the plurality of sacrificial layers 112 is, for example, silicon oxide or silicon nitride. Furthermore, the number of sacrificial layers 112 is not limited to the number shown in the figures. Any plurality of sacrificial layers 112 falls within the scope of this invention.
[0059] In some embodiments, the semiconductor structure 10 may further include a plurality of dielectric layers 114. The plurality of dielectric layers 114 are located on a plurality of gate layers 102. For example, dielectric layer 114A may be located on gate layer 102A, dielectric layer 114B may be located on gate layer 102B, and dielectric layer 114C may be located on gate layer 102C. In some embodiments, a portion of the lowermost dielectric layer 114A may be located within a portion of the lowermost gate layer 102A. In some embodiments, the material of the plurality of dielectric layers 114 is, for example, silicon oxide.
[0060] In some embodiments, the semiconductor structure 10 may further include a dielectric layer 116. The dielectric layer 116 is located on the substrate 100, the channel layer 104, and the sacrificial layer 112. The material of the dielectric layer 116 is, for example, silicon oxide.
[0061] In some embodiments, the semiconductor structure 10 may further include interconnect structures IS1 to IS9. Interconnect structures IS1, IS2, and IS3 are electrically connected to gate layers 102A, 102B, and 102C, respectively. Interconnect structures IS4, IS5, and IS6 are electrically connected to doped regions 108A, 108B, and 108C, respectively. Interconnect structures IS7, IS8, and IS9 are electrically connected to doped regions 110A, 110B, and 110C, respectively. In some embodiments, the materials of interconnect structures IS1 to IS9 are, for example, tungsten, copper, titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.
[0062] In some embodiments, the semiconductor structure 10 may further include a plurality of transistor elements T1. In some embodiments, the plurality of transistor elements T1 may be gate-all-around (GAA) transistor elements. The plurality of transistor elements T1 may include a plurality of gate layers 102, a plurality of channel layers 104, and a plurality of gate dielectric layers 106. In some embodiments, the transistor elements T1 may further include a plurality of doped regions 108 and a plurality of doped regions 110. For example, transistor element T11 may include a gate layer 102A, a channel layer 104A, a gate dielectric layer 106A, a doped region 108A, and a doped region 110A. Transistor element T12 may include a gate layer 102B, a channel layer 104B, a gate dielectric layer 106B, a doped region 108B, and a doped region 110B. Transistor element T13 may include a gate layer 102C, a channel layer 104C, a gate dielectric layer 106C, a doped region 108C, and a doped region 110C.
[0063] As can be seen from the above embodiments, in the semiconductor structure 10, multiple gate layers 102 and multiple channel layers 104 are stacked on the substrate 100. The multiple gate layers 102 are separated from each other, each gate layer 102 surrounds a corresponding channel layer 104, and two adjacent gate layers 102 are located between two adjacent channel layers 104. Therefore, the semiconductor structure 10 can effectively increase the device density of semiconductor devices (e.g., transistor device T1).
[0064] Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention. Figure 4 for Figure 3 A simplified circuit diagram of a semiconductor structure.
[0065] Please refer to Figure 2 , Figure 3 and Figure 4 , Figure 3 Semiconductor structure 20 and Figure 2 The differences in semiconductor structure 10 are as follows. In semiconductor structure 20, interconnect structure IS10 is electrically connected to gate layer 102B and gate layer 102C, interconnect structure IS11 is electrically connected to doped region 108B and doped region 108C, and interconnect structure IS12 is electrically connected to doped region 110B and doped region 110C. Thus, two transistor elements T1 (i.e., transistor elements T12 and T13) can be connected in parallel, but the present invention is not limited thereto. Any transistor element T1 that can be connected in parallel falls within the scope of the present invention.
[0066] In semiconductor structure 20, interconnect structures IS4 and IS7 can be located in sacrificial layer 112A and substrate 100. Furthermore, in semiconductor structure 20, the length L1 of channel layer 104A can be equal to the length L2 of channel layer 104B, thereby further reducing the size of semiconductor devices (e.g., transistor device T11) and further increasing the device density of semiconductor devices (e.g., transistor device T1).
[0067] In some embodiments, the semiconductor structure 20 may be a 2-transistor-0-capacitor (2T0C) dynamic random access memory (DRAM). The plurality of transistor elements T1 may include a write transistor element WT1 and a read transistor element RT1. The write transistor WT1 may include at least two transistor elements T1 connected in parallel (e.g., transistor elements T12 and T13), whereby the write transistor WT1 may have a large current. The read transistor element RT1 may be transistor element T11.
[0068] Please refer to Figure 4 The doped regions 108B and 108C of the write transistor WT1 are electrically connected to the gate layer 102A of the read transistor RT1. The doped regions 110B and 110C of the write transistor WT1 are electrically connected to the write bit line WBL. The gate layers 102B and 102C of the write transistor WT1 are electrically connected to the write word line WWL. The doped region 108A of the read transistor element RT1 is electrically connected to the read word line RWL. The doped region 110A of the read transistor element RT1 is electrically connected to the read bit line RBL. Furthermore, the capacitor C1 can be a capacitor formed by the gate layer 102A, the gate dielectric layer 106A, and the channel layer 104A.
[0069] In addition, Figure 2 and Figure 3 In Chinese, identical or similar components are represented by the same symbol, and their descriptions are omitted.
[0070] As can be seen from the above embodiments, in the semiconductor structure 20, multiple gate layers 102 and multiple channel layers 104 are stacked on the substrate 100. The multiple gate layers 102 are separated from each other, each gate layer 102 surrounds a corresponding channel layer 104, and two adjacent gate layers 102 are located between two adjacent channel layers 104. Therefore, the semiconductor structure 20 can effectively increase the device density of semiconductor devices (e.g., transistor device T1).
[0071] In summary, the semiconductor structure of the above embodiments includes a substrate, multiple gate layers, multiple channel layers, and multiple gate dielectric layers. The multiple gate layers and multiple channel layers are stacked on the substrate, with the multiple gate layers separated from each other. Each gate layer surrounds a corresponding channel layer, and adjacent gate layers are located between adjacent channel layers. Therefore, the semiconductor structure of the above embodiments can effectively increase the device density of semiconductor devices (e.g., transistor devices).
[0072] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.
Claims
1. A semiconductor structure, comprising: Base; Multiple gate layers and multiple channel layers are stacked on the substrate, wherein the multiple gate layers are separated from each other, each gate layer surrounds a corresponding channel layer, and adjacent two gate layers are located between adjacent two channel layers; as well as Multiple gate dielectric layers are located between the multiple gate layers and the multiple channel layers.
2. The semiconductor structure of claim 1, wherein the substrate comprises a silicon substrate or a glass substrate.
3. The semiconductor structure of claim 1, wherein the material of the plurality of gate layers includes TiN, Al, Ti, Pd, Cr, Cu, Mo or a combination thereof.
4. The semiconductor structure of claim 1, wherein the material of the plurality of channel layers comprises an oxide semiconductor material or a semiconductor material.
5. The semiconductor structure of claim 4, wherein the oxide semiconductor material comprises InGaZnO, InSnO, In2O3, InZnO, ZnO, GaO, ZnInSnO or ZnSnO.
6. The semiconductor structure of claim 4, wherein the semiconductor material comprises Si, Ge, SiGe, GeSn, GaAs, GaSe, SiC, GaN, InP, AlGaAs, InGaP, or ZnSe.
7. The semiconductor structure of claim 1, wherein a portion of the lowermost gate layer is located between the substrate and the lowermost channel layer.
8. The semiconductor structure of claim 1, wherein a portion of the lowermost gate dielectric layer is located between the substrate and the lowermost channel layer.
9. The semiconductor structure of claim 1, wherein the material of the plurality of gate dielectric layers comprises a high dielectric constant dielectric material.
10. The semiconductor structure of claim 9, wherein the high dielectric constant dielectric material comprises Al2O3, HfO2, TiO2, ZrO2, La2O3, Y2O3, Ta2O5 or HfSiO4.
11. The semiconductor structure of claim 1, further comprising a plurality of transistor elements, wherein the plurality of transistor elements includes a plurality of the gate layers, a plurality of the channel layers and a plurality of the gate dielectric layers.
12. The semiconductor structure of claim 11, wherein at least two of the transistor elements are connected in parallel.
13. The semiconductor structure of claim 11, further comprising: A plurality of first doped regions and a plurality of second doped regions are located in a plurality of channel layers, wherein the plurality of first doped regions and the plurality of second doped regions are located on opposite sides of the plurality of gate layers.
14. The semiconductor structure of claim 13, wherein the plurality of transistor elements further comprises a plurality of first doped regions and a plurality of second doped regions.
15. The semiconductor structure of claim 14, wherein the plurality of transistor elements includes write transistor elements and read transistor elements.
16. The semiconductor structure of claim 15, wherein the write transistor comprises at least two of the transistor elements connected in parallel.
17. The semiconductor structure of claim 15, wherein the first doped region of the write transistor is electrically connected to the gate layer of the read transistor.
18. The semiconductor structure of claim 1, further comprising: Multiple sacrificial layers are located adjacent to the multiple gate layers and between the multiple channel layers.
19. The semiconductor structure of claim 1, further comprising: Multiple dielectric layers are located on multiple gate layers.
20. The semiconductor structure of claim 17, wherein a portion of the lowermost dielectric layer is located within a portion of the lowermost gate layer.