A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises at least two floating gate regions formed in a well region, the floating gate region comprising a floating gate layer and a floating gate dielectric layer arranged adjacently, and the floating gate layer and the floating gate dielectric layer are perpendicular to a plane in which a top surface of a substrate is located; and an isolation dielectric layer formed between the floating gate region and the well region; a voltage application end connected to the floating gate layer outside the floating gate region, used to apply a voltage on the voltage application end to adjust the electron concentration in the well region at the bottom of the polysilicon gate layer; wherein the floating gate region is located on both sides of the polysilicon gate layer, and the arrangement direction of the floating gate layer and the floating gate dielectric layer in the floating gate region is the same as the arrangement direction between the floating gate regions on both sides. The application can adjust the threshold voltage of the semiconductor device, and realizes the controllable threshold voltage of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] For metal-oxide-semiconductor field-effect transistors (MOSFETs), factors affecting their threshold voltage include the thickness of the gate oxide layer, the doping concentration of the substrate or well region, and the channel length at the bottom of the gate. In an electronic product, both high-threshold-voltage and low-threshold-voltage MOSFETs are often used simultaneously, requiring different manufacturing processes with varying parameters, thus increasing manufacturing costs. Therefore, there are areas for improvement. Summary of the Invention

[0003] This invention provides a semiconductor device and a method for manufacturing the same, thereby addressing the technical problem of requiring different process parameters to manufacture metal-oxide-semiconductor field-effect transistors with high and low threshold voltages respectively.

[0004] The present invention provides a semiconductor device comprising:

[0005] A substrate, wherein the substrate includes a well region, and the well region includes a lead-out region, a source region and a drain region disposed at intervals;

[0006] A gate dielectric layer is disposed on the surface of the well region, the gate dielectric layer is located between the source region and the drain region, and the lead-out region and the source region are located on the same side of the gate dielectric layer;

[0007] A polycrystalline silicon gate layer is disposed on the surface of the gate dielectric layer;

[0008] At least two floating gate regions are formed within the well region, each floating gate region comprising an adjacent floating gate layer and a floating gate dielectric layer, the floating gate layer and the floating gate dielectric layer being perpendicular to the plane containing the upper surface of the substrate; and

[0009] An isolation dielectric layer is formed between the floating gate region and the well region;

[0010] A voltage application terminal is connected to the floating gate layer outside the floating gate region to apply a voltage to the voltage application terminal in order to adjust the electron concentration in the well region at the bottom of the polysilicon gate layer;

[0011] The floating gate region is located on both sides of the polysilicon gate layer, and the arrangement direction of the floating gate layer and the floating gate dielectric layer in the floating gate region is the same as the arrangement direction between the two floating gate regions.

[0012] In one embodiment of the present invention, the arrangement direction of the lead-out region, the source region and the drain region is referred to as the first direction;

[0013] In the first direction, the floating gate region is provided on the side of the drain region away from the source region, and the floating gate region is provided on the side of the source region away from the drain region.

[0014] In one embodiment of the present invention, a floating gate region is provided between the source region and the lead-out region on the side of the source region away from the drain region, and / or the floating gate region is provided on the side of the lead-out region away from the drain region.

[0015] In one embodiment of the present invention, the other directions intersecting with the first direction are designated as the second direction;

[0016] In the second direction, floating gate regions are respectively provided on both sides of the polysilicon gate layer.

[0017] In one embodiment of the present invention, the floating gate region includes at least two floating gate layers, and a floating gate dielectric layer is disposed between two adjacent floating gate layers;

[0018] The inner sidewall of the isolation medium layer is adjacent to the floating grid layer.

[0019] In one embodiment of the present invention, the floating gate region is provided on the side of the drain region away from the source region, and the floating gate region includes at least four floating gate layers;

[0020] The source region is located on the side away from the drain region, and a floating gate region is provided between the source region and the lead-out region. The floating gate region includes at least two floating gate layers, and / or, the floating gate region is provided on the side of the lead-out region away from the drain region, and the floating gate region includes at least four floating gate layers.

[0021] This invention also proposes a method for fabricating a semiconductor device, comprising:

[0022] A substrate is provided in which a well region is formed, the well region having at least two trenches;

[0023] An isolation medium layer is formed in at least two trenches in the well region;

[0024] A floating gate region is formed on the surface of the isolation dielectric layer. The floating gate region includes an adjacent floating gate layer and a floating gate dielectric layer. The floating gate layer and the floating gate dielectric layer are perpendicular to the plane on the upper surface of the substrate.

[0025] Within the well region, an outlet region, a source region, and a drain region are formed at intervals.

[0026] A gate dielectric layer is formed on the surface of the well region, and a polysilicon gate layer is formed on the surface of the gate dielectric layer. The polysilicon gate layer and the gate dielectric layer are etched sequentially, such that the gate dielectric layer and the polysilicon gate layer are located between the source region and the drain region, and the lead-out region and the source region are located on the same side of the gate dielectric layer.

[0027] A voltage application terminal is connected to the floating gate layer outside the floating gate region to apply a voltage to adjust the electron concentration in the well region at the bottom of the polysilicon gate layer.

[0028] The floating gate region is located on both sides of the polysilicon gate layer, and the arrangement direction of the floating gate layer and the floating gate dielectric layer in the floating gate region is the same as the arrangement direction between the two floating gate regions.

[0029] In one embodiment of the present invention, the step of forming a floating gate region on the surface of the isolation dielectric layer, the floating gate region comprising an adjacently disposed floating gate layer and a floating gate dielectric layer, wherein the floating gate layer and the floating gate dielectric layer are perpendicular to the plane containing the upper surface of the substrate, includes:

[0030] On the surface of the isolation dielectric layer, polysilicon is deposited to form a polysilicon body, and the polysilicon body is etched to form a floating gate layer.

[0031] Between adjacent floating gate layers, a dielectric layer deposition process is performed to form a floating gate dielectric layer.

[0032] In one embodiment of the present invention, the step of forming a spaced-out lead-out region, a source region, and a drain region within the well region includes:

[0033] When there are three floating gate regions, a lead-out region is formed on the well region between the first floating gate region and the second floating gate region, and a source region and a drain region are formed on the well region between the second floating gate region and the third floating gate region.

[0034] When there are two floating gate regions, a lead-out region, a source region, and a drain region are sequentially formed on the well region between the two floating gate regions, or a source region and a drain region are formed on the well region, and a lead-out region is formed on the outside of the floating gate region.

[0035] In one embodiment of the present invention, after the step of forming the spaced-apart lead-out region, source region, and drain region within the well region, the method includes:

[0036] The arrangement direction of the lead-out region, the source region, and the drain region is denoted as the first direction, and other directions that intersect with the first direction are denoted as the second direction;

[0037] In the second direction, at least two isolation dielectric layers are formed in the well region on both sides of the polysilicon gate layer, and the isolation dielectric layers have trenches.

[0038] On the surface of the isolation dielectric layer, polysilicon is deposited to form a polysilicon body, and the polysilicon body is etched to form a floating gate layer.

[0039] Between adjacent floating gate layers, a dielectric layer deposition process is performed to form a floating gate dielectric layer.

[0040] The beneficial effects of this invention are as follows: The semiconductor device and its fabrication method proposed in this invention have the following unexpected technical effects: A lead-out region, a source region, and a drain region are formed within the well region of the substrate; a polysilicon gate layer is formed on the surface of the substrate; and adjacent floating gate layers and floating gate dielectric layers are formed within the well regions on both sides of the bottom of the polysilicon gate layer. By applying a voltage to the outermost floating gate layer, which is far from the polysilicon gate layer, the electron concentration in the electron channel within the well region at the bottom of the polysilicon gate layer can be adjusted. Furthermore, the threshold voltage of the semiconductor device formed can be adjusted, thereby achieving controllable threshold voltage of the semiconductor device. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 A schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor provided for the prior art;

[0043] Figure 2 This is a top view of a semiconductor device provided according to an embodiment of the present invention.

[0044] Figure 3 Provided for an embodiment of the present invention Figure 2 A schematic diagram of the AA cross-section of a semiconductor device.

[0045] Figure 4 This is a schematic diagram of the structure of a floating gate region provided in an embodiment of the present invention.

[0046] Figure 5 Provided for an embodiment of the present invention Figure 3 A schematic diagram of applying a positive voltage to the floating gate region.

[0047] Figure 6Provided for an embodiment of the present invention Figure 3 A schematic diagram of applying a negative voltage to the floating gate region.

[0048] Figure 7 Provided for an embodiment of the present invention Figure 2 A schematic diagram of the BB cross-section of a semiconductor device.

[0049] Figure 8 Provided for an embodiment of the present invention Figure 7 A schematic diagram of applying a positive voltage to the floating gate region.

[0050] Figure 9 Provided for an embodiment of the present invention Figure 7 A schematic diagram of applying a negative voltage to the floating gate region.

[0051] Figure 10 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0052] Figure 11 This is a schematic diagram of a structure in which trenches are formed on a substrate, according to an embodiment of the present invention.

[0053] Figure 12 This is a schematic diagram of a structure in which an isolation dielectric layer is formed in a trench in a substrate, according to an embodiment of the present invention.

[0054] Figure 13 This is a schematic diagram of a structure in which a floating gate layer is formed on an isolation medium layer, according to an embodiment of the present invention.

[0055] Figure 14 This is a schematic diagram of the structure for etching the floating gate layer according to an embodiment of the present invention.

[0056] Figure 15 This is a schematic diagram of a structure in which a floating gate dielectric layer is formed between floating gate layers, according to an embodiment of the present invention.

[0057] Figure 16 This is a schematic diagram of the structure for etching the floating gate dielectric layer according to an embodiment of the present invention.

[0058] Figure 17 This is a schematic diagram of a structure for forming a floating gate layer between floating gate dielectric layers, according to an embodiment of the present invention.

[0059] Figure 18 This is a schematic diagram of a structure in which a floating gate dielectric layer is formed between floating gate layers, according to an embodiment of the present invention.

[0060] Figure 19 This is a schematic diagram of a structure in which an extraction region, a source region, and a drain region are formed in a well region, according to an embodiment of the present invention.

[0061] Figure 20 This is a schematic diagram of a structure in which a gate dielectric layer is formed on a well region, according to an embodiment of the present invention.

[0062] Figure 21 This is a schematic diagram of a structure for forming a polysilicon gate layer on a gate dielectric layer, according to an embodiment of the present invention.

[0063] Figure 22 This is a schematic diagram of the structure after etching the polysilicon gate layer and gate dielectric layer according to an embodiment of the present invention.

[0064] Figure 23 This is a schematic diagram of a structure in which trenches are formed on a substrate, according to another embodiment of the present invention.

[0065] Figure 24 This is a schematic diagram of a structure in which an isolation dielectric layer is formed in a trench in a substrate, according to another embodiment of the present invention.

[0066] Figure 25 This is a schematic diagram of a structure in which a floating gate layer is formed on an isolation medium layer, according to another embodiment of the present invention.

[0067] Figure 26 This is a schematic diagram of the structure for etching the floating gate layer according to another embodiment of the present invention.

[0068] Figure 27 This is a schematic diagram of a structure in which a floating gate dielectric layer is formed between floating gate layers, according to another embodiment of the present invention.

[0069] Figure 28 This is a schematic diagram of the structure for etching the floating gate dielectric layer, provided in another embodiment of the present invention.

[0070] Figure 29 This is a schematic diagram of a structure in which a floating gate layer is formed between floating gate dielectric layers, according to another embodiment of the present invention.

[0071] Figure 30 This is a schematic diagram of the structure for etching the floating gate layer according to another embodiment of the present invention.

[0072] Figure 31 This is a schematic diagram of a structure in which a floating gate dielectric layer is formed between floating gate layers, according to another embodiment of the present invention.

[0073] Explanation of icon numbers

[0074] 10. Substrate; 100. Trench; 110. Well region; 20. Lead-out region; 30. Source region; 310. Lightly doped source region; 40. Drain region; 410. Lightly doped drain region; 50. Polysilicon gate layer; 510. Gate dielectric layer; 60. Floating gate region; 610. Floating gate layer; 620. Floating gate dielectric layer; 630. Voltage application terminal; 70. Isolation dielectric layer; 80. Positive voltage; 90. Negative voltage. Detailed Implementation

[0075] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0076] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0077] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0078] Please see Figure 1 This is a metal-oxide-semiconductor (MOSFET) field-effect transistor (MOSFET) in the prior art. Because its process parameters, such as the thickness of the gate oxide layer, the doping concentration of the substrate 10 or well region 110, and the channel length at the bottom of the gate, are relatively fixed and do not vary significantly, its threshold voltage is also relatively fixed and does not vary widely. However, the relatively fixed threshold voltage of a prior art MOSFET makes it impossible to adjust between high and low threshold voltages. Please refer to [link / reference]. Figures 2 to 31 This invention proposes a semiconductor device and its fabrication method, applicable to semiconductor integrated circuits, such as the design circuit of a metal-oxide-semiconductor field-effect transistor. Under applied voltage, this invention can adjust the ion concentration in the electron channel at the bottom of the gate, allowing more electrons to enter the channel or causing electrons to flow out, thereby adjusting the threshold voltage of the semiconductor device and achieving controllable threshold voltage. Specific embodiments are described in detail below.

[0079] Please see Figure 2 , Figure 3 and Figure 7In one embodiment of the present invention, a semiconductor device is proposed, which can be obtained by forming a well region 110, a lead-out region 20, a source region 30, a drain region 40, a polysilicon gate layer 50, a gate dielectric layer 510, a floating gate region 60, a voltage application terminal 630 and an isolation dielectric layer 70 on a substrate 10 of a wafer.

[0080] In one embodiment of the present invention, the substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide, gallium nitride, aluminum nitride, indium nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire, silicon wafers, or other III / V compound semiconductor materials, and also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, and germanium-on-insulator, etc. The substrate 10 serves to support the well region 110, the lead-out region 20, the source region 30, the drain region 40, the polysilicon gate layer 50, the gate dielectric layer 510, the floating gate region 60, and the isolation dielectric layer 70.

[0081] In one embodiment of the present invention, such as Figure 2 , Figure 3 and Figure 7 As shown, a well region 110 can be formed in the substrate 10, and a lead-out region 20, a source region 30 and a drain region 40 can be formed in the well region 110, and the lead-out region 20, the source region 30 and the drain region 40 can be spaced apart from each other.

[0082] Specifically, a well region 110 is formed within the substrate 10, and the threshold voltage can be adjusted by regulating the doping concentration in the well region 110. For example, the substrate 10 is a P-type substrate 10, and the well region 110 is a P-type well region 110. The lead-out region 20, the source region 30, and the drain region 40 are formed by ion implantation on the well region 110, respectively, to form the substrate, source, and drain of the metal-oxide-semiconductor field-effect transistor.

[0083] Specifically, when the substrate 10 is a P-type substrate 10 and the well region 110 is a P-type well region 110, the lead-out region 20 is a P-type lead-out region 20, the source region 30 is an N-type source region 30, and the drain region 40 is an N-type drain region 40.

[0084] In one embodiment of the present invention, such as Figure 2 , Figure 3 and Figure 7 As shown, the gate dielectric layer 510 can be disposed on the surface of the well region 110, and the gate dielectric layer 510 is located between the source region 30 and the drain region 40. The lead-out region 20 and the source region 30 are located on the same side of the gate dielectric layer 510. The polysilicon gate layer 50 can be disposed on the surface of the gate dielectric layer 510.

[0085] Specifically, the polysilicon gate layer 50 is used to form the gate of the metal-oxide-semiconductor field-effect transistor, and the gate dielectric layer 510 is located between the polysilicon gate layer 50 and the surface of the well region 110 to isolate the polysilicon gate layer 50.

[0086] In one embodiment of the present invention, such as Figure 2 , Figure 3 and Figure 7 As shown, there are at least two floating gate regions 60, and at least two floating gate regions 60 are formed within the well region 110. Each floating gate region 60 includes an adjacent floating gate layer 610 and a floating gate dielectric layer 620, which are perpendicular to the plane containing the upper surface of the substrate 10. An isolation dielectric layer 70 is formed between the floating gate regions 60 and the well region 110.

[0087] Specifically, the floating gate region 60 is located on both sides of the polysilicon gate layer 50, such as... Figure 3 , Figure 4 As shown, the arrangement direction of the floating gate layer 610 and the floating gate dielectric layer 620 within the floating gate region 60 is the same as the arrangement direction between the floating gate regions 60 on both sides. Here, the specific positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 is not limited; it is only required that the floating gate regions 60 are located on both sides of the polysilicon gate layer 50 and are separated from other films and structures.

[0088] Specifically, the isolation dielectric layer 70 is an insulator. Based on the tunneling effect, a voltage application terminal 630 is connected to the floating gate layer 610 outside the floating gate region 60. Applying a voltage to the voltage application terminal 630 can regulate the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50.

[0089] For example, such as Figure 4 , Figure 5 and Figure 8 As shown, if a positive voltage 80 is applied to the floating gate layer 610 outside the floating gate region 60, the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50 can be reduced. In contrast, as... Figure 6 and Figure 9 As shown, if a negative voltage 90 is applied to the floating gate layer 610 outside the floating gate region 60, the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50 can be increased.

[0090] Please see 2 and Figure 3 In one embodiment of the present invention, since the specific positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 is not defined in the above description, it is necessary to describe in detail the positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 for better understanding and explanation.

[0091] Specifically, such as Figure 2 and Figure 3 As shown, the arrangement direction of the lead-out region 20, the source region 30, and the drain region 40 is denoted as the first direction. In the first direction, a floating gate region 60 is provided on the side of the drain region 40 away from the source region 30, and a floating gate region 60 is provided on the side of the source region 30 away from the drain region 40. That is, floating gate regions 60 can be formed on both sides of the electron channel in the well region 110 at the bottom of the polysilicon gate layer 50. At this time, applying a voltage to the floating gate layer 610 outside the floating gate region 60 can adjust the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50.

[0092] Furthermore, since the drain region 40 is located on one side of the polysilicon gate layer 50, and the lead-out region 20 and the source region 30 are located on the other side of the polysilicon gate layer 50, the floating gate region 60 can be formed outside the drain region 40 because the drain region 40 is located on one side of the polysilicon gate layer 50. For the floating gate region 60 at the lead-out region 20 and the source region 30, the floating gate region 60 can be provided between the source region 30 and the lead-out region 20, and / or, the floating gate region 60 can be provided on the side of the lead-out region 20 away from the drain region 40.

[0093] Specifically, for the floating gate region 60 at the lead-out region 20 and the source region 30, the floating gate region 60 can be provided between the source region 30 and the lead-out region 20. Alternatively, the floating gate region 60 can be provided on the side of the lead-out region 20 away from the drain region 40. Or, the floating gate region 60 can be provided both between the source region 30 and the lead-out region 20, and also on the side of the lead-out region 20 away from the drain region 40. In all three cases, when a voltage is applied to the floating gate layer 610 outside the floating gate region 60, it can regulate the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50.

[0094] Please see Figure 2 and Figure 7 In one embodiment of the present invention, other directions intersecting with the first direction are referred to as the second direction. In the second direction, floating gate regions 60 are respectively provided on both sides of the polysilicon gate layer 50.

[0095] Specifically, such as Figure 2 and Figure 7 As shown, since the positions of the lead-out region 20, the source region 30, and the drain region 40 are already determined, the position of the floating gate region 60 in the first direction is relatively fixed. However, in the second direction, as long as corresponding floating gate regions 60 are respectively provided on both sides of the polysilicon gate layer 50, and the floating gate regions 60 on both sides of the polysilicon gate layer 50 can be separated from the lead-out region 20, the source region 30, and the drain region 40, the position of the floating gate region 60 in the second direction is not fixed.

[0096] Specifically, the position of the floating gate region 60 in the second direction is not fixed. Specifically, in the definition of the second direction, any direction intersecting the first direction is considered the second direction; that is, the second direction intersects the first direction, and both the first and second directions are perpendicular to the plane containing the upper surface of the substrate 10. Furthermore, if the angle between the first and second directions is small, for example, 5°~15°, then the floating gate region 60 in the first direction and the floating gate region 60 in the second direction have similar functions. To ensure that the floating gate region 60 in the first direction and the floating gate region 60 in the second direction each perform their corresponding functions, therefore... Figure 2 As shown, the angle between the first direction and the second direction can be set to 90°, that is, the first direction and the second direction are perpendicular to each other.

[0097] Please see Figure 2 , Figure 3 and Figure 7 In the above description, the specific positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 is not specified. It is only required that the floating gate regions 60 are located on both sides of the polysilicon gate layer 50 and are separated from other film layers. Subsequent analysis shows that the floating gate regions 60 can be formed only in the first direction within the well region 110, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50. Alternatively, the floating gate regions 60 can be formed only in the second direction within the well region 110, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50. Alternatively, the floating gate regions 60 can be formed both in the first direction within the well region 110, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50, and also in the second direction within the well region 110, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50.

[0098] Please see Figure 2 , Figure 3 , Figure 4 and Figure 7 In one embodiment of the present invention, the floating gate region 60 includes at least two floating gate layers 610, a floating gate medium layer 620 is disposed between two adjacent floating gate layers 610, and the inner sidewall of the isolation medium layer 70 is adjacent to the floating gate layer 610.

[0099] Of course, in other embodiments, the floating gate region 60 includes at least two floating gate layers 610, a floating gate dielectric layer 620 is disposed between two adjacent floating gate layers 610, and the inner sidewall of the isolation dielectric layer 70 is adjacent to the floating gate dielectric layer 620. The floating gate dielectric layer 620 and the isolation dielectric layer 70 can be regarded as an integral insulating layer.

[0100] Specifically, such as Figure 3 , Figure 7As shown, a floating gate region 60 is provided on the side of the drain region 40 away from the source region 30, and the floating gate region includes at least four floating gate layers 610. On the side of the source region 30 away from the drain region 40, a floating gate region 60 is provided between the source region 30 and the lead-out region 20, and the floating gate region 60 includes at least two floating gate layers 610. And / or, a floating gate region 60 is provided on the side of the lead-out region 20 away from the drain region 40, and the floating gate region 60 includes at least four floating gate layers 610.

[0101] Please see Figure 10 In one embodiment of the present invention, a method for fabricating a semiconductor device is proposed, which may include the following steps.

[0102] Step S10: Provide a substrate 10, and form a well region 110 in the substrate 10, and form at least two trenches 100 in the well region 110.

[0103] Step S20: Form an isolation medium layer 70 in at least two trenches 100 of the trap region 110.

[0104] Step S30: A floating gate region 60 is formed on the surface of the isolation dielectric layer 70. The floating gate region 60 includes a floating gate layer 610 and a floating gate dielectric layer 620 disposed adjacently. The floating gate layer 610 and the floating gate dielectric layer 620 are perpendicular to the plane on the upper surface of the substrate 10.

[0105] Step S40: Form an alternately spaced lead-out region 20, source region 30, and drain region 40 within the well region 110.

[0106] Step S50: A gate dielectric layer 510 is formed on the surface of the well region 110, and a polysilicon gate layer 50 is formed on the surface of the gate dielectric layer 510. The polysilicon gate layer 50 and the gate dielectric layer 510 are etched sequentially so that the gate dielectric layer 510 and the polysilicon gate layer 50 are located between the source region 30 and the drain region 40, and the lead-out region 20 and the source region 30 are located on the same side of the gate dielectric layer 510.

[0107] Step S60: A voltage application terminal 630 is connected to the floating gate layer 610 outside the floating gate region 60 to apply a voltage to the voltage application terminal 630 in order to adjust the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50.

[0108] The floating gate region 60 is located on both sides of the polysilicon gate layer 50, and the arrangement direction of the floating gate layer 610 and the floating gate dielectric layer 620 in the floating gate region 60 is the same as the arrangement direction between the two floating gate regions 60.

[0109] In the above steps, the specific positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 is not limited. It is only required that the floating gate regions 60 are located on both sides of the polysilicon gate layer 50 and are separated from other films and structures. Specifically, the isolation dielectric layer 70 is an insulator. Based on the tunneling effect, a voltage application terminal 630 is connected to the floating gate layer 610 outside the floating gate region 60. Applying a voltage to the voltage application terminal 630 can adjust the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50.

[0110] For example, such as Figure 5 and Figure 8 As shown, if a positive voltage 80 is applied to the floating gate layer 610 outside the floating gate region 60, the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50 can be reduced. In contrast, as... Figure 6 and Figure 9 As shown, if a negative voltage 90 is applied to the floating gate layer 610 outside the floating gate region 60, the electron concentration in the well region 110 at the bottom of the polysilicon gate layer 50 can be increased.

[0111] Please see Figures 11 to 22 In one embodiment of the present invention, since the specific positional relationship between at least two floating gate regions 60 and polysilicon gate layer 50 is not defined in the above description, it is necessary to describe the positional relationship between at least two floating gate regions 60 and polysilicon gate layer 50 in detail below for better understanding and explanation.

[0112] Please see Figure 11 In one embodiment of the present invention, a substrate 10 is provided, and a well region 110 may be formed on the substrate 10 by ion implantation. After the well region 110 is formed on the substrate 10, a patterned photoresist layer (not shown in the figure) is formed on the well region 110. Using the patterned photoresist layer as a mask, the exposed well region 110 is etched to form at least two trenches 100 on the well region 110.

[0113] Please see Figure 12 In one embodiment of the present invention, after forming at least two trenches 100 on the well region 110, an isolation dielectric layer 70 is formed in the at least two trenches 100 by a linear oxidation process. The isolation dielectric layer 70 is located on the bottom inner wall and the side inner wall of the trenches 100, and the isolation dielectric layer 70 is an insulator.

[0114] Please see Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18In one embodiment of the present invention, in step S30, a floating gate region 60 is formed on the surface of the isolation dielectric layer 70. The floating gate region 60 includes a floating gate layer 610 and a floating gate dielectric layer 620 disposed adjacently. The floating gate layer 610 and the floating gate dielectric layer 620 are perpendicular to the plane on the upper surface of the substrate 10. This step may include the following steps.

[0115] Step S310: On the surface of the isolation dielectric layer 70, a polysilicon deposition process is performed to form a floating gate layer 610, and the floating gate layer 610 is etched to retain the floating gate layer 610 on the inner wall of the side of the isolation dielectric layer 70.

[0116] Step S320: A dielectric layer is deposited between adjacent floating gate layers 610 to form a floating gate dielectric layer 620. The specific fabrication process is as follows... Figures 13 to 18 As shown.

[0117] Please see Figure 13 In one embodiment of the present invention, after the isolation medium layer 70 is formed in at least two trenches 100, a floating gate layer 610 may be formed by deposition inside the isolation medium layer 70 and on the surface of the trap region 110.

[0118] Please see Figure 14 In one embodiment of the present invention, after the floating gate layer 610 is formed inside the isolation dielectric layer 70 and on the surface of the well region 110, the floating gate layer 610 inside the isolation dielectric layer 70 and the floating gate layer 610 on the surface of the well region 110 can be etched by dry etching, so that the floating gate layer 610 is retained only on the inner side wall of the isolation dielectric layer 70.

[0119] Specifically, dry etching is a technique that uses gaseous plasma to remove materials. It does not use liquid chemical reagents; instead, it removes material by chemically reacting with or physically bombarding the material being etched using active particles (such as ions and free radicals) generated by gas discharge. For example, plasma etching uses active particles in plasma for both chemical reactions and physical bombardment.

[0120] Please see Figure 15 In one embodiment of the present invention, after the floating gate layer 610 is retained on the inner side wall of the isolation medium layer 70, the floating gate medium layer 620 can be formed by deposition between the two floating gate layers 610 of the isolation medium layer 70 and on the surface of the well region 110.

[0121] Please see Figure 16In one embodiment of the present invention, after forming a floating gate dielectric layer 620 between the two floating gate layers 610 of the isolation dielectric layer 70 and on the surface of the well region 110, the floating gate dielectric layer 620 between the two floating gate layers 610 of the isolation dielectric layer 70 and the floating gate dielectric layer 620 on the surface of the well region 110 can be etched by dry etching, so that the floating gate dielectric layer 620 is only retained on the inner side wall of the floating gate layer 610.

[0122] Specifically, such as Figure 16 As shown, if the trench 100 on the well region 110 is small in size, for example, the second trench 100 viewed from left to right is smaller, then the floating gate region 60 includes two floating gate layers 610 and one floating gate dielectric layer 620, with the floating gate dielectric layer 620 located between the two floating gate layers 610. If the trench 100 on the well region 110 is large in size, then it is possible to... Figure 16 Inside the isolation dielectric layer 70, a floating gate layer 610 and a floating gate dielectric layer 620 can be further formed, such as... Figure 17 and Figure 18 As shown, and in Figure 18 The production of floating gate area 60 was finally completed.

[0123] Specifically, such as Figure 17 As shown, after the floating gate dielectric layer 620 is retained on the inner side wall of the floating gate layer 610, the floating gate layer 610 can be formed by deposition between the two floating gate dielectric layers 620 of the isolation dielectric layer 70 and on the surface of the well region 110. Next, the floating gate layer 610 between the two floating gate dielectric layers 620 of the isolation dielectric layer 70 and the floating gate layer 610 on the surface of the well region 110 can be etched using dry etching, so that the floating gate layer 610 is retained only on the inner side wall of the floating gate dielectric layer 620.

[0124] Specifically, such as Figure 18 As shown, after the floating gate layer 610 is retained on the inner side wall of the floating gate dielectric layer 620, the floating gate dielectric layer 620 can be formed by deposition between the two floating gate layers 610 of the isolation dielectric layer 70 and on the surface of the well region 110. Next, the floating gate dielectric layer 620 on the surface of the well region 110 can be etched by dry etching so that the floating gate dielectric layer 620 is retained between the two floating gate layers 610, and the fabrication of the floating gate region 60 is finally completed.

[0125] Please see Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18In other embodiments (not shown in the figures), in Figure 13 After the floating gate layer 610 is formed within the intermediate isolation dielectric layer 70, it can also be used in... Figure 13 Three trenches 100 are formed within the floating gate layer 610 using trench etching. Next, a floating gate dielectric layer 620 is deposited within the three trenches 100 of the floating gate layer 610 and on the surface of the well region 110. The floating gate dielectric layer 620 on the surface of the well region 110 is then polished using chemical mechanical polishing (CMP), ultimately completing the process as described above. Figure 18 Fabrication of the mid-floating grid area 60.

[0126] Specifically, trench etching is a specific etching process, such as Figure 11 As shown, the purpose is to form deep and narrow trenches 100 in semiconductor materials. These trenches 100 can be used to isolate different devices, fabricate buried gate structures, or serve as dielectric layers for capacitors. For example, reactive ion etching (RIE) can ensure high precision and good contour control.

[0127] Please see Figure 19 In one embodiment of the present invention, after the floating gate region 60 is fabricated, the lead-out region 20, the source region 30 and the drain region 40 can be formed on the trap region 110 by ion implantation.

[0128] In one embodiment of the present invention, step S40, which involves forming a spaced-out region 20, a source region 30, and a drain region 40 within the well region 110, may include the following steps.

[0129] Step S410: Obtain the positions of three adjacent floating gate regions 60. Between the first and second floating gate regions 60, form a lead-out region 20 on the well region 110. Between the second and third floating gate regions 60, form a source region 30 and a drain region 40 on the well region 110. Figure 19 As shown.

[0130] Step S420, or, obtain the positions of two adjacent floating gate regions 60, and between the two floating gate regions 60, sequentially form an extraction region 20, a source region 30, and a drain region 40 on the well region 110. (Not shown in the figure.)

[0131] Step S430, or, obtain the positions of two adjacent floating gate regions 60, and form a source region 30 and a drain region 40 on the well region 110 between the two floating gate regions 60. On the outside of the floating gate region 60 corresponding to the source region 30, form a lead-out region 20 on the well region 110. Not shown in the figure.

[0132] Please see Figure 19 In this embodiment, the structure corresponding to step S410 is described. Specifically, between the first floating gate region 60 and the second floating gate region 60 of the well region 110, an extraction region 20 is formed by ion implantation. Between the second floating gate region 60 and the third floating gate region 60 of the well region 110, a source region 30, a lightly doped source region 310, a drain region 40, and a lightly doped drain region 410 are formed by ion implantation. The source region 30 is located within the lightly doped source region 310, and the drain region 40 is located within the lightly doped drain region 410.

[0133] Please see Figure 20 In one embodiment of the present invention, after forming the lead-out region 20, the source region 30 and the drain region 40 on the well region 110, a gate dielectric layer 510 of 120 Å can be grown on the surface of the well region 110, the lead-out region 20, the source region 30, the drain region 40 and the floating gate region 60 by means of a furnace tube.

[0134] Please see Figure 21 In one embodiment of the present invention, after forming a gate dielectric layer 510 on the surfaces of the well region 110, the lead-out region 20, the source region 30, the drain region 40, and the floating gate region 60, a polysilicon gate layer 50 is formed on the surface of the gate dielectric layer 510 by deposition. Next, a patterned photoresist layer (not shown) is formed on the polysilicon gate layer 50. Using the patterned photoresist layer as a mask, the exposed polysilicon gate layer 50 is etched, leaving a portion of the polysilicon gate layer 50 on the gate dielectric layer 510. The remaining polysilicon gate layer 50 is located between the source region 30 and the drain region 40.

[0135] Please see Figure 22 In one embodiment of the present invention, a portion of the polysilicon gate layer 50 is retained on the gate dielectric layer 510, and the remaining polysilicon gate layer 50 is located between the source region 30 and the drain region 40. Subsequently, a patterned photoresist layer (not shown) is formed on the gate dielectric layer 510. Using the patterned photoresist layer as a mask, the exposed gate dielectric layer 510 is etched, retaining the gate dielectric layer 510 at the bottom of the remaining polysilicon gate layer 50. The gate dielectric layer 510 serves to isolate the polysilicon gate layer 50.

[0136] Please see Figure 2 , Figure 7 , Figures 23 to 31 In another embodiment of the present invention, since the specific positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 is not defined in the above description, it is necessary to describe in detail the positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 for better understanding and explanation.

[0137] Specifically, the arrangement direction of the lead-out region 20, source region 30, and drain region 40 is denoted as the first direction. Other directions intersecting the first direction are denoted as the second direction. In the second direction, a floating gate region 60 can be formed within the well region 110, and the floating gate region 60 is located on both sides of the polysilicon gate layer 50. In the second direction, as long as corresponding floating gate regions 60 are respectively provided on both sides of the polysilicon gate layer 50, and the floating gate regions 60 on both sides of the polysilicon gate layer 50 can be separated from the lead-out region 20, source region 30, and drain region 40, the position of the floating gate region 60 in the second direction is not fixed. The position of the floating gate region 60 in the second direction is not fixed, specifically in the definition of the second direction: other directions intersecting the first direction are denoted as the second direction, that is, the second direction intersects with the first direction.

[0138] It is also worth mentioning that if the angle between the first direction and the second direction is small, for example, 5°~15°, then the floating gate region 60 in the first direction and the floating gate region 60 in the second direction have similar functions. In order to ensure that the floating gate region 60 in the first direction and the floating gate region 60 in the second direction each perform their corresponding functions, therefore... Figures 23 to 31 As shown, the angle between the first direction and the second direction can be set to 90°, that is, the first direction and the second direction are perpendicular to each other.

[0139] Please see Figures 23 to 31 In one embodiment of the present invention, after step S50, a gate dielectric layer 510 is formed on the surface of the well region 110, a polysilicon gate layer 50 is formed on the surface of the gate dielectric layer 510, and the polysilicon gate layer 50 and the gate dielectric layer 510 are etched sequentially so that the gate dielectric layer 510 and the polysilicon gate layer 50 are located between the source region 30 and the drain region 40, and the lead-out region 20 and the source region 30 are located on the same side of the gate dielectric layer 510, the following steps are performed.

[0140] Step S610: The arrangement direction of the lead-out region 20, the source region 30 and the drain region 40 is recorded as the first direction, and the other directions that intersect with the first direction are recorded as the second direction.

[0141] Step S620: On both sides of the polysilicon gate layer 50 in the second direction, at least two trenches 100 are formed in the well region 110, and an isolation dielectric layer 70 is formed in the at least two trenches 100 in the well region 110.

[0142] Step S630: On the surface of the isolation dielectric layer 70, a polysilicon deposition process is performed to form a floating gate layer 610, and the floating gate layer 610 is etched to retain the floating gate layer 610 on the inner wall of the side of the isolation dielectric layer 70.

[0143] Step S640: A dielectric layer is deposited between adjacent floating gate layers 610 to form a floating gate dielectric layer 620. The specific fabrication process is as follows... Figures 23 to 31 .

[0144] Please see Figure 2 , Figure 7 and Figure 23 In one embodiment of the present invention, in the second direction, a patterned photoresist layer (not shown in the figure) can be formed on both sides of the polysilicon gate layer 50 in the well region 110. Using the patterned photoresist layer as a mask, the exposed well region 110 is etched to form at least two trenches 100 on the well region 110.

[0145] Please see Figure 24 In one embodiment of the present invention, after forming at least two trenches 100 on the well region 110, an isolation dielectric layer 70 is formed in the at least two trenches 100 by a linear oxidation process. The isolation dielectric layer 70 is located on the bottom inner wall and the side inner wall of the trenches 100, and the isolation dielectric layer 70 is an insulator.

[0146] Please see Figure 25 In one embodiment of the present invention, after the isolation medium layer 70 is formed in at least two trenches 100, a floating gate layer 610 may be formed by deposition inside the isolation medium layer 70 and on the surface of the trap region 110.

[0147] Please see Figure 26 In one embodiment of the present invention, after the floating gate layer 610 is formed inside the isolation dielectric layer 70 and on the surface of the well region 110, the floating gate layer 610 inside the isolation dielectric layer 70 and the floating gate layer 610 on the surface of the well region 110 can be etched by dry etching, so that the floating gate layer 610 is retained only on the inner side wall of the isolation dielectric layer 70.

[0148] Please see Figure 27 In one embodiment of the present invention, after the floating gate layer 610 is retained on the inner side wall of the isolation medium layer 70, the floating gate medium layer 620 can be formed by deposition between the two floating gate layers 610 of the isolation medium layer 70 and on the surface of the well region 110.

[0149] Please see Figure 28In one embodiment of the present invention, after forming a floating gate dielectric layer 620 between the two floating gate layers 610 of the isolation dielectric layer 70 and on the surface of the well region 110, the floating gate dielectric layer 620 between the two floating gate layers 610 of the isolation dielectric layer 70 and the floating gate dielectric layer 620 on the surface of the well region 110 can be etched by dry etching, so that the floating gate dielectric layer 620 is only retained on the inner side wall of the floating gate layer 610.

[0150] Please see Figure 29 In one embodiment of the present invention, after a floating gate dielectric layer 620 is retained on the inner side wall of the floating gate layer 610, the floating gate layer 610 can be formed by deposition between the two floating gate dielectric layers 620 of the isolation dielectric layer 70 and on the surface of the well region 110.

[0151] Please see Figure 30 In one embodiment of the present invention, after a floating gate layer 610 is formed between the two floating gate dielectric layers 620 of the isolation dielectric layer 70 and on the surface of the well region 110, the floating gate layer 610 between the two floating gate dielectric layers 620 of the isolation dielectric layer 70 and the floating gate layer 610 on the surface of the well region 110 can be etched by dry etching, so that the floating gate layer 610 is only retained on the inner side wall of the floating gate dielectric layer 620.

[0152] Please see Figure 31 In one embodiment of the present invention, after the floating gate layer 610 is retained on the inner side wall of the floating gate dielectric layer 620, the floating gate dielectric layer 620 can be formed by deposition between the two floating gate layers 610 of the isolation dielectric layer 70 and on the surface of the well region 110. Next, the floating gate dielectric layer 620 on the surface of the well region 110 can be etched using a dry etching method to retain the floating gate dielectric layer 620 between the two floating gate layers 610, thus completing the fabrication of the floating gate region 60.

[0153] Please see Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 and Figure 31 In other embodiments (not shown in the figures), in Figure 25 After the floating gate layer 610 is formed within the intermediate isolation dielectric layer 70, it can also be used in... Figure 25Three trenches 100 are formed within the floating gate layer 610 using trench etching. Next, a floating gate dielectric layer 620 is deposited within the three trenches 100 of the floating gate layer 610 and on the surface of the well region 110. The floating gate dielectric layer 620 on the surface of the well region 110 is then polished using chemical mechanical polishing (CMP), ultimately completing the process as described above. Figure 31 Fabrication of the mid-floating grid area 60.

[0154] Please see Figure 2 , Figure 3 and Figure 7 In the above description, the specific positional relationship between at least two floating gate regions 60 and the polysilicon gate layer 50 is not specified. It is only required that the floating gate regions 60 are located on both sides of the polysilicon gate layer 50 and are separated from other film layers. Subsequent analysis shows that the floating gate regions 60 can be formed within the well region 110 in the first direction, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50. Alternatively, the floating gate regions 60 can be formed within the well region 110 in the second direction, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50. Alternatively, the floating gate regions 60 can be formed both in the first direction within the well region 110, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50, and also in the second direction within the well region 110, with the floating gate regions 60 located on both sides of the polysilicon gate layer 50.

[0155] Specifically, in the fabrication methods of semiconductor devices, it is possible to... Figures 11 to 22 As shown, a floating gate region 60 is formed only in the first direction within the well region 110, and the floating gate region 60 is located on both sides of the polysilicon gate layer 50. Alternatively, it can be as follows: Figures 23 to 31 As shown, a floating gate region 60 is formed only in the second direction within the well region 110, and the floating gate region 60 is located on both sides of the polysilicon gate layer 50. However, before step S23, it is still necessary to fabricate the lead-out region 20, the source region 30, and the drain region 40 within the well region 110, and to fabricate the gate dielectric layer 510 and the polysilicon gate layer 50 on the surface of the well region 110. Alternatively, it can be as follows: Figures 11 to 22 and such Figures 23 to 31 As shown, in the first direction, a floating gate region 60 is formed in the well region 110, and the floating gate region 60 is located on both sides of the polysilicon gate layer 50. In the second direction, a floating gate region 60 is formed in the well region 110, and the floating gate region 60 is located on both sides of the polysilicon gate layer 50.

[0156] In summary, this invention proposes a semiconductor device and its fabrication method. The unexpected technical effect is that by forming adjacent floating gate layers and floating gate dielectric layers in the well regions on both sides of the bottom of the gate, and applying a voltage to the outermost floating gate layer based on the tunneling effect, the electron concentration of the electron channel in the well region at the bottom of the gate can be adjusted, thereby adjusting the threshold voltage of the semiconductor device and making the threshold voltage of the semiconductor device controllable.

[0157] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention. As used herein and throughout the claims below, unless otherwise specified, "a" and "the" include the plural references. Similarly, as used herein and throughout the claims below, unless otherwise specified, "in" means "in" and "on".

Claims

1. A semiconductor device, characterized in that, include: A substrate, wherein the substrate includes a well region, and the well region includes a lead-out region, a source region and a drain region disposed at intervals; A gate dielectric layer is disposed on the surface of the well region, the gate dielectric layer is located between the source region and the drain region, and the lead-out region and the source region are located on the same side of the gate dielectric layer; A polycrystalline silicon gate layer is disposed on the surface of the gate dielectric layer; At least two floating gate regions are formed within the well region. Each floating gate region includes an adjacent floating gate layer and a floating gate dielectric layer, and the floating gate layer and the floating gate dielectric layer are perpendicular to the plane containing the upper surface of the substrate. as well as An isolation dielectric layer is formed between the floating gate region and the well region; A voltage application terminal is connected to the floating gate layer outside the floating gate region to apply a voltage to the voltage application terminal in order to adjust the electron concentration in the well region at the bottom of the polysilicon gate layer; The floating gate region is located on both sides of the polysilicon gate layer, and the arrangement direction of the floating gate layer and the floating gate dielectric layer in the floating gate region is the same as the arrangement direction of the floating gate regions on both sides.

2. The semiconductor device according to claim 1, characterized in that, The arrangement direction of the lead-out region, the source region, and the drain region is denoted as the first direction; In the first direction, the floating gate region is provided on the side of the drain region away from the source region, and the floating gate region is provided on the side of the source region away from the drain region.

3. The semiconductor device according to claim 2, characterized in that, On the side of the source region away from the drain region, a floating gate region is provided between the source region and the lead-out region, and / or, on the side of the lead-out region away from the drain region, a floating gate region is provided.

4. The semiconductor device according to claim 1, 2, or 3, characterized in that, Other directions that intersect with the first direction are designated as the second direction; In the second direction, floating gate regions are respectively provided on both sides of the polysilicon gate layer.

5. The semiconductor device according to claim 1, characterized in that, The floating grid region includes at least two floating grid layers, and a floating grid dielectric layer is disposed between two adjacent floating grid layers; The inner sidewall of the isolation medium layer is adjacent to the floating grid layer.

6. The semiconductor device according to claim 1, characterized in that, The floating gate region is provided on the side of the drain region away from the source region, and the floating gate region includes at least four floating gate layers; The source region is located on the side away from the drain region, and a floating gate region is provided between the source region and the lead-out region. The floating gate region includes at least two floating gate layers, and / or, the floating gate region is provided on the side of the lead-out region away from the drain region, and the floating gate region includes at least four floating gate layers.

7. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided in which a well region is formed, wherein at least two trenches are formed in the well region; An isolation medium layer is formed in at least two trenches in the well region; A floating gate region is formed on the surface of the isolation dielectric layer. The floating gate region includes an adjacent floating gate layer and a floating gate dielectric layer. The floating gate layer and the floating gate dielectric layer are perpendicular to the plane on the upper surface of the substrate. Within the well region, an outlet region, a source region, and a drain region are formed at intervals. A gate dielectric layer is formed on the surface of the well region, and a polysilicon gate layer is formed on the surface of the gate dielectric layer. The polysilicon gate layer and the gate dielectric layer are etched sequentially, such that the gate dielectric layer and the polysilicon gate layer are located between the source region and the drain region, and the lead-out region and the source region are located on the same side of the gate dielectric layer. A voltage application terminal is connected to the floating gate layer outside the floating gate region to apply a voltage to adjust the electron concentration in the well region at the bottom of the polysilicon gate layer. The floating gate region is located on both sides of the polysilicon gate layer, and the arrangement direction of the floating gate layer and the floating gate dielectric layer in the floating gate region is the same as the arrangement direction between the two floating gate regions.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The step of forming a floating gate region on the surface of the isolation dielectric layer, the floating gate region comprising adjacent floating gate layers and a floating gate dielectric layer, wherein the floating gate layers and the floating gate dielectric layer are perpendicular to the plane containing the upper surface of the substrate, includes: On the surface of the isolation dielectric layer, a polysilicon deposition process is performed to form a floating gate layer, and the floating gate layer is etched to retain the floating gate layer on the inner wall of the side portion of the isolation dielectric layer. Between adjacent floating gate layers, a dielectric layer deposition process is performed to form a floating gate dielectric layer.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of forming a spaced-out lead-out region, a source region, and a drain region within the well region includes: The positions of three adjacent floating gate regions are obtained. Between the first and second floating gate regions, a lead-out region is formed on the well region. Between the second and third floating gate regions, a source region and a drain region are formed on the well region. Alternatively, the positions of two adjacent floating gate regions are obtained, and between the two floating gate regions, an extraction region, a source region, and a drain region are sequentially formed on the well region; Alternatively, the positions of two adjacent floating gate regions are obtained, and a source region and a drain region are formed on the well region between the two floating gate regions. Outside the floating gate region corresponding to the source region, a lead-out region is formed on the well region.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, After the steps of forming a gate dielectric layer on the surface of the well region, forming a polysilicon gate layer on the surface of the gate dielectric layer, and sequentially etching the polysilicon gate layer and the gate dielectric layer such that the gate dielectric layer and the polysilicon gate layer are located between the source region and the drain region, and the lead-out region and the source region are located on the same side of the gate dielectric layer, the method further includes: The arrangement direction of the lead-out region, the source region, and the drain region is denoted as the first direction, and other directions that intersect with the first direction are denoted as the second direction; At least two trenches are formed in the well region on both sides of the polysilicon gate layer in the second direction, and an isolation dielectric layer is formed in the at least two trenches of the well region. On the surface of the isolation dielectric layer, a polysilicon deposition process is performed to form a floating gate layer, and the floating gate layer is etched to retain the floating gate layer on the inner wall of the side portion of the isolation dielectric layer. Between adjacent floating gate layers, a dielectric layer deposition process is performed to form a floating gate dielectric layer.

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