Solar cell and method of manufacturing the same, stacked cell, and photovoltaic module

Abstract

The application relates to a solar cell and a preparation method thereof, a laminated cell and a photovoltaic module. The preparation method of the solar cell comprises the following steps: performing double-side texturing on a silicon wafer; the silicon wafer comprises a first surface, and the first surface comprises a first region and a second region; performing etching on the first region, the etching comprising: after a first stage is performed at a first temperature, cooling to a second temperature to perform a second stage; preparing a passivation contact structure on the first surface; and preparing an electrode on the second region. After the double-side texturing is performed on the silicon wafer, the first stage etching is performed at the first temperature first, etching nucleus points are rapidly formed, then the second stage etching is performed by cooling to the second temperature, and the etching rate is reduced, so that directional growth of the texturing structure can be realized, the structure size difference is reduced, and the etching uniformity is improved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a solar cell and its preparation method, a tandem cell, and a photovoltaic module. Background Technology

[0002] In the field of photovoltaic cells, the etching process of silicon wafers affects product performance and yield. Traditional silicon wafer etching technology suffers from poor etching uniformity, resulting in inconsistent cell surface morphology and consequently fluctuations in photoelectric conversion efficiency, severely restricting the large-scale production and performance improvement of photovoltaic cells. Therefore, it is necessary to improve traditional technologies. Summary of the Invention

[0003] Based on this, this application provides a solar cell that can effectively improve etching uniformity, a method for fabricating the same, a tandem cell, and a photovoltaic module.

[0004] The technical solution to the above-mentioned technical problems in this application is as follows.

[0005] The first aspect of this application provides a method for preparing a solar cell, comprising the following steps:

[0006] A silicon wafer is texturized on both sides; the silicon wafer includes a first surface, and the first surface includes a first region and a second region.

[0007] Etching is performed on a first region, the etching comprising: performing a first stage at a first temperature, and then cooling to a second temperature to perform a second stage;

[0008] A passivated contact structure is prepared on the first surface;

[0009] Electrodes are prepared in the second region.

[0010] In some embodiments, the difference between the first temperature and the second temperature in the method for preparing the solar cell is 5°C to 30°C.

[0011] In some embodiments, in the method for preparing a solar cell, the first temperature is 40°C to 60°C, and the second temperature is 30°C to 40°C.

[0012] In some embodiments, the time for the first stage in the method for preparing a solar cell is 100s to 200s, and the time for the second stage is 400s to 500s.

[0013] In some embodiments, the cooling rate in the solar cell fabrication method is 3°C / min to 10°C / min.

[0014] In some embodiments, the etching process in the fabrication method of the solar cell is performed using an alkaline solution, wherein the solute in the alkaline solution includes inorganic bases and organic amines.

[0015] In some embodiments, in the method for preparing solar cells, the alkaline solution comprises the following components by mass: 30-50 parts of inorganic alkali, 5-40 parts of organic amine, and 10-65 parts of water.

[0016] In some embodiments, the method for fabricating a solar cell satisfies at least one of the following characteristics:

[0017] (1) The mass ratio of the organic amine to the inorganic base is (0.1~1):1;

[0018] (2) The organic amine includes at least one of tetramethylammonium hydroxide and choline;

[0019] (3) The inorganic base includes at least one of potassium hydroxide and sodium hydroxide.

[0020] In some embodiments, the method for fabricating a solar cell includes fabricating the passivated contact structure by sequentially fabricating a tunneling oxide layer and a doped polycrystalline silicon layer on a first surface.

[0021] In some embodiments, the method for fabricating a solar cell, after double-sided texturing and before etching the first region, includes: setting a mask layer in the second region.

[0022] In some embodiments, the method for fabricating a solar cell includes a silicon wafer with a second surface opposite to the first surface; after double-sided texturing and before setting a mask layer, the method includes: diffusing the second surface to form a PN junction.

[0023] The second aspect of this application provides a solar cell, which is prepared using the method for preparing a solar cell provided in the first aspect.

[0024] In some embodiments, the solar cell includes a silicon wafer, a passivated contact structure disposed on a first surface, and an electrode disposed in a second region. The first region of the silicon wafer includes a pyramid structure, and the pyramid structure of the first region satisfies at least one of the following characteristics:

[0025] (1) The height difference between any two of the pyramid structures is ≤1.2 μm;

[0026] (2) The width difference between any two of the pyramid structures is ≤1.8 μm;

[0027] (3) The bottom width of the pyramid structure is 2 μm to 5 μm.

[0028] A third aspect of this application provides a tandem battery, including a bottom battery and a top battery, wherein the bottom battery includes the solar cell provided in the second aspect.

[0029] The fourth aspect of this application provides a photovoltaic module, including the solar cell provided in the second aspect or the tandem cell provided in the third aspect.

[0030] The method for fabricating solar cells in this application involves texturing a silicon wafer on both sides, followed by etching a first region on the first surface of the silicon wafer. The etching process first involves a first-stage etching at a first temperature to rapidly form etch nuclei, and then cooling to a second temperature for a second-stage etching to reduce the etching rate. This process enables directional growth of the texturized structure, reduces structural size differences, and improves etching uniformity. This, in turn, facilitates the uniformity of subsequent passivation contact structure deposition, improves the passivation effect, and ultimately enhances the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application and to more completely understand this application and its beneficial effects, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A cross-sectional view of a silicon wafer provided in one embodiment;

[0033] Figure 2 A diagram showing the temperature changes at different stages of an etching process, as provided in one embodiment.

[0034] Figure 3 A schematic cross-sectional view of the etched silicon wafer and mask layer provided in one embodiment;

[0035] Figure 4 A cross-sectional structural schematic diagram of a solar cell provided in one embodiment;

[0036] Figure 5 A scanning electron microscope image of a silicon substrate in a solar cell provided according to one embodiment.

[0037] Figure label:

[0038] 11. Silicon wafer; 11a. First surface; 11b. Second surface; A. First region; B. Second region;

[0039] 12: Passivated contact structure; 121: Tunneling oxide layer; 122: Doped polysilicon layer; 13: Passivation layer; 14: Anti-reflection layer; 15: Back electrode; 16: Front electrode;

[0040] 20: Mask layer. Detailed Implementation

[0041] The present application will be further described in detail below with reference to the embodiments and examples. It should be understood that these embodiments and examples are only used to illustrate the present application and are not intended to limit the scope of the present application. The purpose of providing these embodiments and examples is to make the disclosure of the present application more thorough and comprehensive.

[0042] It should also be understood that this application can be implemented in many different forms and is not limited to the embodiments and examples described herein. Those skilled in the art can make various alterations or modifications without departing from the spirit of this application, and the resulting equivalent forms also fall within the protection scope of this application. For example, features described or illustrated as part of one embodiment can be combined in a suitable manner in another embodiment to produce new embodiments. Furthermore, numerous specific details are set forth in the following description to provide a fuller understanding of this application; it should be understood that this application can be implemented without one or more of these details.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for descriptive purposes only and is not intended to be limiting of the application.

[0044] Unless otherwise stated or in case of contradiction, the terms or phrases used herein shall have the following meanings:

[0045] In this application, the terms "multiple", "various", "multiple times", etc., unless otherwise specified, refer to a quantity greater than or equal to 2. For example, "one or more" means one or more than or equal to two.

[0046] The terms “combinations of,” “any combination of,” and “any combination of” used in this article include all suitable combinations of any two or more of the listed items.

[0047] In this document, the term "suitable" as used in "suitable combination", "suitable method", "any suitable method", etc., refers to the ability to implement the technical solution of this application, solve the technical problem of this application, and achieve the expected technical effect of this application.

[0048] In this application, terms such as "further," "even further," and "particularly" are used to describe purposes and indicate differences in content, but should not be construed as limiting the scope of protection of this application.

[0049] In this application, the terms "first aspect," "second aspect," "third aspect," "fourth aspect," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features. Moreover, "first," "second," "third," "fourth," etc., serve only as a non-exhaustive enumeration and should be understood not to constitute a closed limitation on quantity.

[0050] In this application, the technical features described in an open-ended manner include both closed technical solutions consisting of the listed features and open technical solutions that include the listed features.

[0051] In this application, when numerical intervals (i.e., numerical ranges) are mentioned, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed herein should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include numerical interval types such as percentage intervals, ratio intervals, and proportion intervals.

[0052] Unless otherwise specified, the temperature parameters in this application are permitted to be either constant-temperature treatment or variations within a certain temperature range. It should be understood that the constant-temperature treatment allows temperature fluctuations within the precision range of the instrument control, such as ±5℃, ±4℃, ±3℃, ±2℃, or ±1℃.

[0053] In this application, the terms "room temperature" or "normal temperature" generally refer to 4℃ to 35℃, for example, 20℃ ± 5℃. In some embodiments of this application, "room temperature" or "normal temperature" refers to 10℃ to 30℃. In some embodiments of this application, "room temperature" or "normal temperature" refers to 20℃ to 30℃.

[0054] In this application, if the unit of a data range is only followed by the right endpoint, it indicates that the units of the left and right endpoints are the same. For example, 3~5 h means that the units of the left endpoint "3" and the right endpoint "5" are both h (hours).

[0055] All references to documents mentioned in this application are incorporated herein by reference as if each document were individually incorporated by reference. Unless they conflict with the inventive purpose and / or technical solution of this application, all cited documents are incorporated herein by reference in their entirety and for all purposes. When citing documents in this application, the definitions of relevant technical features, terms, nouns, phrases, etc., are also incorporated herein by reference. When citing documents in this application, examples and preferred embodiments of the cited technical features may also be incorporated herein by reference, but only to the extent that they enable the implementation of this application. It should be understood that when the cited content conflicts with the description in this application, this application shall prevail or modifications shall be made adaptably to the description in this application.

[0056] The mass or weight of the relevant components mentioned in the embodiments of this application can refer not only to the specific content of each component, but also to the proportional relationship of mass or weight between the components. Therefore, any scaling up or down of the content of the relevant components according to the embodiments of this application is within the scope disclosed in the embodiments of this application. Specifically, the mass or weight mentioned in the embodiments of this application can be units known in the chemical industry, such as μg, mg, g, and kg.

[0057] One embodiment of this application provides a method for preparing a solar cell, comprising the following steps:

[0058] Step S100: Perform double-sided texturing on the silicon wafer; see [link / reference] Figure 1 The silicon wafer 11 includes a first surface 11a, which includes a first region A and a second region B.

[0059] It is understood that the first region A and the second region B do not intersect; further, it is understood that the first surface 11a includes a plurality of alternating first regions A and second regions B; further, in some examples, the first surface 11a is the back side of the solar cell. Further, the silicon wafer 11 includes a second surface 11b opposite to the first surface 11a, and the second surface 11b is the front side of the solar cell.

[0060] Step S200: Etch the first region A of the first surface 11a. The etching includes: performing a first stage at a first temperature, and then cooling to a second temperature to perform a second stage.

[0061] It is understandable that in step S200, the first temperature is higher than the second temperature. After texturing the silicon wafer 11 on both sides, the first stage of etching is performed at the higher first temperature to quickly form etch nuclei. Then, the temperature is lowered to the second temperature for the second stage of etching, reducing the etching rate. This allows for the directional growth of the textured structure, reduces structural size differences, improves etching uniformity, and forms a submicron-level textured surface. This is beneficial for the uniformity of subsequent passivation contact structure deposition, improves the passivation effect, and ultimately enhances the photoelectric conversion efficiency of the solar cell.

[0062] Compared to depositing a passivation layer on a flat surface, submicron textured surfaces can improve the uniformity of passivation layer deposition. For example, during laser doping, submicron textured surfaces can form a more uniform borosilicate glass layer. Furthermore, submicron textured surfaces can increase the lateral conduction path of charge carriers and reduce contact resistance. At the same time, compared to directly etching to a flat surface, which requires additional polishing steps, the etching method of this application is less expensive.

[0063] The textured surface of the first region A after etching provides an atomically flat substrate for the passivation contact structure, reducing interfacial recombination; the textured surface of the second region B after texturing is used for light reflection, and the electrode contact area needs to maintain a certain roughness to ensure adhesion; through this partitioned and differentiated treatment, the synergistic optimization of efficient passivation of the first region A and optical management of the second region B is achieved.

[0064] In some of these examples, in step S200, the difference between the first temperature and the second temperature is 5°C to 30°C.

[0065] It can be understood that in step S200, the first temperature is 5℃~30℃ higher than the second temperature; further, it can be understood that the difference between the first temperature and the second temperature includes, but is not limited to, 5℃, 6℃, 7℃, 8℃, 9℃, 10℃, 11℃, 12℃, 13℃, 14℃, 15℃, 16℃, 17℃, 18℃, 19℃, 20℃, 21℃, 22℃, 23℃, 24℃, 25℃, 26℃, 27℃, 28℃, 29℃, and 30℃; in some examples, it can be any two of these point values ​​as the end values, the same applies below. For example, the difference between the first temperature and the second temperature is 15℃~20℃.

[0066] By controlling the difference between the first and second temperatures, after the first stage of etching at a higher temperature, the difference in reactivity caused by the temperature difference can effectively improve the accuracy and controllability of the etching profile, thereby improving the etching uniformity.

[0067] In some of these examples, in step S200, the cooling rate is 3°C / min to 10°C / min.

[0068] It is understood that in step S200, the cooling rate includes, but is not limited to, 3℃ / min, 4℃ / min, 5℃ / min, 6℃ / min, 7℃ / min, 8℃ / min, 9℃ / min, and 10℃ / min. Optionally, the cooling rate is 3℃ / min to 5℃ / min.

[0069] By controlling the rate at which the temperature drops from the first temperature to the second temperature, the rhythm of thermal change is adjusted, thermal stress damage is reduced, the defect rate of silicon wafers is lowered, and a smooth transition from rapid removal to fine finishing is achieved, thereby improving etching uniformity and balancing production efficiency.

[0070] In some of these examples, in step S200, the first temperature is 40°C to 60°C.

[0071] It is understood that in step S200, the first temperature includes, but is not limited to, 40℃, 41℃, 42℃, 43℃, 44℃, 45℃, 46℃, 47℃, 48℃, 49℃, 50℃, 51℃, 52℃, 53℃, 54℃, 55℃, 56℃, 57℃, 58℃, 59℃, and 60℃. Optionally, the first temperature is 50℃~60℃.

[0072] By controlling the initial temperature, the high efficiency of the first stage of etching is ensured, a large amount of silicon material is quickly removed and the basic etching contour is established, thus shortening the overall etching time and improving process efficiency.

[0073] In some of these examples, in step S200, the temperature is increased to a first temperature at a rate of 3°C / min to 10°C / min.

[0074] It is understood that the heating rate includes, but is not limited to, 3℃ / min, 4℃ / min, 5℃ / min, 6℃ / min, 7℃ / min, 8℃ / min, 9℃ / min, and 10℃ / min. Optionally, the heating rate is 3℃ / min to 5℃ / min.

[0075] By controlling the heating rate, uneven distribution of etching reagent concentration is reduced, thus improving etching consistency.

[0076] It is understandable that the etching temperature is controlled by the etching solution used in the etching process; see [link to relevant documentation]. Figure 2 The etching process includes a heating stage (Q1), a first stage (Q2), a cooling stage (Q3), and a second stage (Q4). In the heating stage (Q1), the temperature is increased from the initial temperature T0 (20℃~30℃) to the first temperature T1 at a heating rate V1, and maintained at the first temperature T1 for a time t1 to perform the first stage (Q2). In the cooling stage (Q3), the temperature is decreased to the second temperature T2 at a cooling rate V2, and maintained at the second temperature T2 for a time t2 to perform the second stage (Q4).

[0077] In some examples, in step S200, the difference between the heating rate V1 and the cooling rate V2 is ≤2℃ / min. Optionally, the difference between the heating rate V1 and the cooling rate V2 is 0~2℃ / min.

[0078] It is understandable that the solution temperature can be controlled through a gradient heating / cooling program.

[0079] In some of these examples, in step S200, the second temperature is 30°C to 40°C.

[0080] It is understood that in step S200, the second temperature includes, but is not limited to, 30℃, 31℃, 32℃, 33℃, 34℃, 35℃, 36℃, 37℃, 38℃, 39℃, and 40℃. Optionally, the second temperature is 35℃~40℃.

[0081] By controlling the second temperature, etching details can be adjusted and etching uniformity improved.

[0082] In some examples, the first stage in step S200 lasts for 100s to 200s.

[0083] It is understood that in step S200, the time of the first stage includes, but is not limited to, 100s, 110s, 120s, 130s, 140s, 150s, 160s, 170s, 180s, 190s, and 200s.

[0084] In some of these examples, the second phase in step S200 lasts for 400 to 500 seconds.

[0085] It is understood that in step S200, the time of the second stage includes, but is not limited to, 400s, 410s, 420s, 430s, 440s, 450s, 460s, 470s, 480s, 490s, and 500s.

[0086] It is understandable that the etching temperatures and temperature differences, heating rates, cooling rates, and etching times in the first and second stages work together to achieve a balance between etching rate, structural accuracy, and silicon wafer stability, thereby effectively improving etching uniformity. This design, through kinetic-thermodynamic coupling control, enables different heating rate stages to complement each other, ultimately obtaining a highly uniform submicron structure (pyramid height 0.65±0.05μm, base 0.8±0.1μm).

[0087] In some examples, in step S200, an alkaline solution is used for etching, the solute of which includes inorganic bases and organic amines.

[0088] Compared to using a single alkaline solution, etching in an alkaline solution containing both inorganic alkali and organic amine involves a first-stage etching dominated by the inorganic alkali, performed at a higher temperature to rapidly form etch nuclei. Subsequent etching at a lower temperature allows the organic amine to adsorb onto the silicon wafer surface, via -NH3... + Hydrogen bonding with Si-OH inhibits lateral etching and reduces the size difference of the textured structure. The temperature and alkaline solution can be mutually adjusted to achieve directional growth of the textured structure, effectively improving etching uniformity. This is beneficial to the uniformity of subsequent deposition of passivation contact structure, improving the passivation effect, and thus improving the photoelectric conversion efficiency of solar cells.

[0089] Meanwhile, compared to using a single alkaline solution, using an inorganic alkali and an organic amine in combination can reduce the contamination of the silicon wafer by metal ions during the etching process (Na). + (Residual residue), enhancing the passivation effect.

[0090] In some of these examples, in step S200, the alkaline solution comprises, by mass parts, the following components: 30-50 parts of inorganic alkali, 5-40 parts of organic amine, and 10-65 parts of water.

[0091] It is understood that in an alkaline solution, the mass fractions of inorganic alkali include, but are not limited to, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, and 50 parts; the mass fractions of organic amine include, but are not limited to, 5, 8, 10, 12, 15, 18, 20, 22, 25, 28, 30, 32, 35, 38, and 40 parts; and the mass fractions of water include, but are not limited to, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, and 65 parts. Furthermore, it is understood that the solution concentration can be adjusted using an online conductivity sensor, and the concentration can be maintained stable by adding water and alkaline components.

[0092] In some of these examples, in step S200, the alkaline solution comprises, by mass parts, the following components: 35-45 parts of inorganic alkali, 20-40 parts of organic amine, and 15-45 parts of water.

[0093] In some of these examples, in step S200, the alkaline solution comprises, by mass parts, the following components: 35-40 parts of inorganic alkali, 20-30 parts of organic amine, and 30-45 parts of water.

[0094] It is understood that in some other examples, in step S200, the alkaline solution comprises the following components by mass percentage: 40% to 50% inorganic base, 20% to 40% organic amine and 10% to 40% water.

[0095] Furthermore, in some other examples, in step S200, the alkaline solution is composed of the following components by mass percentage: 40%~50% inorganic base, 20%~40% organic amine and 10%~40% water.

[0096] In some of these examples, in step S200, the mass ratio of organic amine to inorganic base is (0.1~1):1.

[0097] It is understood that the mass ratio of organic amine to inorganic base includes, but is not limited to, 0.1:1, 0.2:1, 0.3:1, 0.4:1, 0.5:1, 0.6:1, 0.7:1, 0.8:1, 0.9:1, and 1:1. Optionally, the mass ratio of organic amine to inorganic base is (0.3~1):1. Optionally, the mass ratio of organic amine to inorganic base is (0.5~1):1. Further, the mass ratio of organic amine to inorganic base is (0.5~0.8):1.

[0098] By controlling the mass ratio of organic amine to inorganic alkali, the pH value and reactivity of the etching solution can be adjusted, affecting the etching rate and selectivity. Combined with temperature control, this facilitates precise control of the etching rate, improves the etching uniformity of the silicon wafer surface, optimizes the anisotropy of the etching morphology, and reduces contamination of the silicon wafer by impurities during etching (Na). + Residual <1e12atoms / cm 2 ).

[0099] In some of these examples, in step S200, the organic amine includes at least one of tetramethylammonium hydroxide (TMAH) and choline.

[0100] In some of these examples, in step S200, the inorganic base includes at least one of potassium hydroxide and sodium hydroxide.

[0101] In some of these examples, in step S200, after etching is completed, ultrasonic-assisted cleaning is performed to remove residual particles from the surface.

[0102] In some examples, during step S200, when etching the first region A of the first surface 11a, the second surface 11b is protected by a gas, such as ozone protection, to prevent the second surface 11b from being etched.

[0103] See Figure 3 In some of these examples, after step S100 and before step S200, the process includes setting a mask layer 20 in the second region B.

[0104] It is understood that a mask layer 20 is set in the second region B, and the mask layer 20 in the second region B is etched in step S200 to prevent the silicon wafer 11 in the second region B from being etched in step S200, thereby reducing corrosion damage to the silicon wafer 11 in the second region B, facilitating subsequent deposition of metal electrodes, and making connection easier. It is further understood that the mask layer 20 in the second region B is removed in step S200.

[0105] In some of these examples, the mask layer is selected from any combination of the following:

[0106] (1) SiNx layer; optionally, thickness of 80 nm to 150 nm; optionally, refractive index of 2.0 to 2.3; optionally, deposition method of PECVD; optionally, deposition temperature of 380±20℃ and power density of 0.4 to 0.6 W / cm³. 2 ;

[0107] (2) Al2O3 / SiNx composite layer; optionally, the thickness of Al2O3 is 20 nm to 50 nm; optionally, the thickness of SiNx is 50 nm to 100 nm; optionally, the deposition method is ALD deposition;

[0108] (3) Photoresist / SiO2 composite layer, the photoresist is AZ4620 or SU-8; optionally, the thickness of the photoresist is 2μm~5μm and the thickness of the SiO2 is 100±10nm.

[0109] It is understood that this application does not restrict the way the mask layer is set in the second region B. The mask layer can be set directly in the second region B and the first region A can be left unset; or the mask layer can be set as a whole in the first region A and the second region B, and then the mask layer in the first region A can be removed.

[0110] It is understood that the silicon wafer 11 includes a second surface 11b opposite to the first surface 11a; in some examples, after step S100 and before step S200, step S300 is included: diffusion is performed on the second surface 11b to form a PN junction.

[0111] It is understandable that the formation of the PN junction occurs before the mask layer is set in the second region B in step S200.

[0112] When a PN junction is formed by diffusion on the second surface 11b of the silicon wafer 11, the mixture generated by decomposition will be deposited onto the first surface 11a to form a doped silicon glass layer. Double-sided texturing of the silicon wafer 11 is beneficial for removing the doped silicon glass layer on the first surface 11a.

[0113] It is understandable that silicon wafers include P-type silicon wafers and N-type silicon wafers.

[0114] In some examples, the silicon wafer is a P-type silicon wafer, and the base dopant is at least one element from Group III; optionally, the base dopant includes boron (B) with a resistivity of 1 Ω·cm to 3 Ω·cm; optionally, the emitter PN junction is formed by phosphorus diffusion with a surface concentration of 5 × 10⁻⁶. 19 ~ 2×10 20 cm -3 It is understandable that the mixture generated during the phosphorus diffusion process will be deposited onto the first surface to form a phosphorus-doped silicon glass layer, namely a phosphorus silicon glass layer (PSG).

[0115] In other examples, the silicon wafer is an N-type silicon wafer, and the base dopant is at least one element from Group V; optionally, the base dopant includes phosphorus (P) and / or antimony, with a resistivity of 0.5 Ω·cm to 2 Ω·cm; optionally, the emitter PN junction is formed by boron diffusion, with a surface concentration of 3 × 10⁻⁶. 19 ~ 1×10 20 cm -3 It is understandable that the mixture generated during the decomposition of boron during diffusion will be deposited onto the first surface to form a boron-doped silicon glass layer, namely a borosilicate glass layer (BSG).

[0116] Step S400: See Figure 4 A passivated contact structure 12 is prepared on the first surface 11a.

[0117] It is understood that in some of these examples, in step S400, passivated contact structures 12 are prepared in both the first region A and the second region B of the first surface 11a.

[0118] In some of these examples, step S400 includes step S410: sequentially preparing a tunneling oxide layer 121 and a doped polysilicon layer 122 on the first surface 11a.

[0119] It is understood that this application does not limit the method of preparing the tunneling oxide layer 121 and the doped polysilicon layer 122. The method of preparing the tunneling oxide layer 121 includes, but is not limited to, thermal oxidation method, plasma oxidation method, etc. The doped polysilicon layer 122 includes two steps: "polysilicon deposition" and "doping". The method of "polysilicon deposition" includes, but is not limited to, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc. "Doping" includes diffusion doping, in-situ doping, etc.

[0120] In some examples, after step S410 and before step S500, step S420 is included: preparing a passivation layer 13 on the first surface 11a. Optionally, the passivation layer 13 includes an aluminum oxide layer. It is understood that this application does not limit the manner in which the passivation layer 13 is prepared, including but not limited to atomic layer deposition (ALD).

[0121] In some examples, after step S420 and before step S500, step S430 is included: preparing an antireflection layer 14 on at least one of the first surface 11a and the second surface 11b of the battery. Optionally, the antireflection layer 14 comprises silicon nitride (SiN). x ), silicon dioxide (SiO2) and silicon oxynitride (SiO2) y N z At least one of the following. It is understood that this application does not limit the method of preparing the antireflection layer, including but not limited to plasma-enhanced chemical vapor deposition (PECVD).

[0122] It is understood that the method for preparing solar cells provided in this application is applicable to the preparation of TOPCon solar cells.

[0123] Step S500: An electrode is prepared in the second region B of the first surface 11a.

[0124] It can be understood that the electrode prepared in the second region B of the first surface 11a is the back electrode 15; in some examples, in step S500, a metal electrode is prepared in the second region B.

[0125] Further, step S500 includes fabricating an electrode on the second surface 11b of the silicon wafer 11. It can be understood that the electrode fabricated on the second surface 11b of the silicon wafer 11 is a front electrode 16.

[0126] The method for fabricating solar cells provided in this application can achieve directional growth of textured structures, reduce structural size differences, improve etching uniformity, thereby improving the uniformity of the passivation layer, enhancing the passivation effect, and ultimately improving the photoelectric conversion efficiency of the solar cell.

[0127] One embodiment of this application provides a solar cell, which is prepared using the solar cell preparation method provided in the first aspect.

[0128] In some of these examples, see Figure 4 The solar cell includes a silicon wafer 11, a passivation contact structure 12 disposed on a first surface 11a of the silicon wafer 11, and a back electrode 15 disposed on a second region B of the first surface 11a of the silicon wafer 11. The first region A of the silicon wafer 11 includes multiple pyramid structures, and the height difference between any two pyramid structures is ≤1.2 μm and the width difference is ≤1.8 μm.

[0129] It is understood that the first region of the silicon wafer includes at least two pyramid structures, which refer to pyramid structures arranged side by side on a plane.

[0130] In some examples, within the first region A of the solar cell, the height difference between any two pyramid structures is 0.25 μm to 1.2 μm, and the width difference between any two pyramid structures is 0.4 μm to 1.8 μm. In some examples, within the second region B of the solar cell, the height difference between any two pyramid structures is 0.5 μm to 2 μm, and the width difference between any two pyramid structures is 0.7 μm to 2.5 μm. It can be understood that, within the first region A, the height difference between any two pyramid structures includes, but is not limited to, 0.25 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, and 1.2 μm, and the width difference between any two pyramid structures includes, but is not limited to, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, and 1.8 μm. In the second region B, the height difference between any two pyramid structures includes, but is not limited to, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, and 2 μm, and the width difference between any two pyramid structures includes, but is not limited to, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 2 μm, and 2.5 μm.

[0131] In some examples, in the solar cell, the base width of the pyramid structure in the first region A is 2 μm to 5 μm. In some examples, in the solar cell, the base width of the pyramid structure in the second region B is 6 μm to 10 μm. It can be understood that the base width of the pyramid structure in the first region A includes, but is not limited to, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, and 5 μm. The base width of the pyramid structure in the second region B includes, but is not limited to, 6 μm, 7 μm, 8 μm, 9 μm, and 10 μm.

[0132] In some examples, in the solar cell, the uniformity σ of the pyramid structure in the first region A is <2%. Optionally, the uniformity σ of the pyramid structure in the first region A is 1.5% < σ < 2%. In some examples, in the solar cell, the uniformity of the pyramid structure in the second region B is 25% < σ < 30%. It can be understood that the uniformity σ of the pyramid structure in the first region A includes, but is not limited to, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, and 2%; and the uniformity of the pyramid structure in the second region B includes, but is not limited to, 25%, 26%, 27%, 28%, 29%, and 30%. Compared to the second region B, the optical scattering loss in the first region A is lower, with a 2%-3% reduction in reflectivity.

[0133] In some examples, in solar cells, under illumination of light at 300 nm to 1100 nm, the reflectivity of region A is 10.5% to 11.8%, and the reflectivity of region B is 12.5% ​​to 14.2%. Compared to region B, region A has improved light-harvesting capability.

[0134] In some examples, in the solar cells, the base width distribution of the pyramid structure in region A exhibits a Gaussian distribution (narrow peak); while in region B, the base width distribution of the pyramid structure exhibits a Poisson distribution (broad peak). Compared to region B, region A is more conducive to continuous coverage of the passivation contact structure, resulting in a 15% improvement in minority carrier lifetime.

[0135] In some examples, in the solar cell, the proportion of the (111) crystal facets of the pyramid structure in the first region A is ≥90%; optionally, the proportion of the (111) crystal facets of the pyramid structure in the first region A is 90%~95%. In some examples, in the solar cell, the proportion of the (111) crystal facets of the pyramid structure in the second region B is 60%~70%. It can be understood that the proportion of the (111) crystal facets of the pyramid structure in the first region A includes, but is not limited to, 90%, 91%, 92%, 93%, 94%, and 95%; and the proportion of the (111) crystal facets of the pyramid structure in the second region B includes, but is not limited to, 60%, 62%, 65%, 68%, and 70%. Compared with the second region B, the first region A can improve the growth quality of the passivation contact structure.

[0136] In some examples of solar cells, in region A, the lateral / vertical ratio of the pyramid structure is 1:1.8 (vertical dominance), while in region B, the lateral / vertical ratio is 1:1.2 (isotropic). Compared to region B, region A reduces the electrode contact area, resulting in improved flyback effect (FF).

[0137] The test parameters for height difference, width difference, bottom width, and uniformity are shown in Table 1.

[0138] Table 1

[0139]

[0140] In some of these examples, the passivation contact structure 12 in the solar cell includes a tunneling oxide layer 121 and a doped polycrystalline silicon layer 122, wherein the tunneling oxide layer 121 is disposed between the silicon wafer 11 and the doped polycrystalline silicon layer 122.

[0141] In some of these examples, the solar cell includes a front electrode 16 disposed on the second surface 11b of the silicon wafer 11.

[0142] In some of these examples, the solar cell includes a passivation layer 13 disposed between the silicon wafer 11 and the front electrode 16.

[0143] In some examples, the solar cell includes an antireflection layer 14 disposed between the passivation contact structure 12 and the silicon wafer 11, and / or, an antireflection layer 14 disposed between the passivation layer 13 and the silicon wafer 11.

[0144] The solar cell provided in this application improves the photoelectric conversion efficiency of the solar cell by controlling the uniformity of the textured surface structure of the silicon wafer in the first region without metal electrodes, thereby enhancing the uniformity of the passivation layer deposition.

[0145] One embodiment of this application provides a tandem solar cell, including a bottom cell and a top cell, wherein the bottom cell includes the aforementioned solar cell. Further, the top cell includes a perovskite solar cell.

[0146] It is understood that tandem solar cells include, but are not limited to, two-terminal tandem solar cells, three-terminal tandem solar cells, and four-terminal tandem solar cells. Furthermore, tandem solar cells include, but are not limited to, perovskite solar cells stacked with crystalline silicon solar cells.

[0147] One embodiment of this application provides a photovoltaic module, including the above-described solar cell or the above-described tandem cell.

[0148] In some of these examples, the photovoltaic modules include:

[0149] A battery string is formed by electrically connecting multiple solar cells or solar cells prepared by the above-described method, or by electrically connecting multiple tandem cells described above.

[0150] Encapsulating film, used to cover the surface of the battery string; and

[0151] A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

[0152] It can be understood that solar cells or tandem cells are electrically connected in the form of a single sheet or multiple segments to form multiple cell strings, and multiple cell strings are electrically connected in series and / or parallel. Furthermore, solar cells or tandem cells can be single-sheet cells or sliced ​​cells; sliced ​​cells refer to cells formed from a single, complete cell through a cutting process.

[0153] In some of these examples, multiple battery strings can be electrically connected via conductive strips.

[0154] In some examples, the encapsulating film includes a first encapsulating layer and a second encapsulating layer, the first encapsulating layer covering one of the front and back sides of the battery, and the second encapsulating layer covering the other of the front and back sides of the battery; further, the first encapsulating layer and the second encapsulating layer may each independently include at least one of organic encapsulating films such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, and polyethylene terephthalate (PET) film.

[0155] In some of these examples, the cover can be a glass cover, a plastic cover, or other light-transmitting cover.

[0156] The present application will be described in further detail below with reference to specific embodiments, but the embodiments of the present application are not limited thereto.

[0157] Example 1

[0158] (1) The silicon wafer is texturized on both sides; the silicon wafer includes a first surface (back side) and a second surface (front side) disposed opposite to each other, the first surface including a first region and a second region;

[0159] (2) Boron diffusion is performed on the second surface of the silicon wafer to form a PN junction, and the borosilicate glass layer around the first surface is removed;

[0160] (3) An etching mask is formed in the second region of the first surface of the silicon wafer;

[0161] (4) Immerse the silicon wafer in an alkaline solution to etch the first region of the first surface of the silicon wafer. During the etching process, control the solution temperature according to a gradient heating / cooling program. Heat up to 50°C at a heating rate of 3°C / min and maintain for 200s (first stage); cool down to 35°C at a cooling rate of 3°C / min and maintain for 400s (second stage). This step will remove the etching mask of the second region.

[0162] Etching was followed by ultrasonic-assisted cleaning to remove residual particles from the surface; scanning electron microscope image as follows. Figure 5 As shown;

[0163] The alkaline solution comprises, by mass, the following components: 40 parts inorganic alkali, 20 parts organic amine, and 40 parts water; the mass ratio of organic amine to inorganic alkali is 0.5:1; the organic amine is tetramethylammonium hydroxide.

[0164] (5) A tunneling oxide layer and a doped polysilicon layer are sequentially prepared on the first surface of the silicon wafer, and the tunneling oxide layer and the doped polysilicon layer on the second surface are removed.

[0165] (6) Prepare an aluminum oxide passivation layer on the front side of the silicon wafer;

[0166] (7) Prepare antireflection layers on the first and second surfaces of the battery;

[0167] (8) A positive electrode is prepared on the second surface of the battery, and a back metal electrode is prepared in the second region of the first surface of the battery.

[0168] Example 2

[0169] The solution is basically the same as in Example 1, except that, by mass, the alkaline solution comprises the following components: 50 parts of inorganic alkali, 5 parts of organic amine, and 45 parts of water; the mass ratio of organic amine to inorganic alkali is 0.1:1.

[0170] Example 3

[0171] The solution is basically the same as in Example 1, except that, by mass, the alkaline solution comprises the following components: 40 parts of inorganic alkali, 40 parts of organic amine, and 20 parts of water; the mass ratio of organic amine to inorganic alkali is 1:1.

[0172] Example 4

[0173] It is basically the same as Example 1, except that the organic amine is choline.

[0174] Example 5

[0175] It is basically the same as Example 1, except that the temperature of the first stage is 50°C and the temperature of the second stage is 30°C.

[0176] Example 6

[0177] The process is basically the same as in Example 1, except that the temperature in the first stage is 60°C and the time is 100s; the temperature in the second stage is 40°C and the time is 500s.

[0178] Example 7

[0179] It is basically the same as Example 1, except that the temperature in the first stage is 40°C and the temperature in the second stage is 30°C.

[0180] Example 8

[0181] The solution is essentially the same as in Example 1, except that, by mass, the alkaline solution comprises the following components: 60 parts potassium hydroxide and 40 parts water.

[0182] Example 9

[0183] The solution is essentially the same as in Example 1, except that, by mass, the alkaline solution comprises the following components: 60 parts tetramethylammonium hydroxide and 40 parts water.

[0184] Comparative Example 1

[0185] The process is basically the same as in Example 1, except that the alkaline solution is a 60% potassium hydroxide aqueous solution; the temperature of the first stage is 75°C, and the temperature of the second stage is 90°C.

[0186] Comparative Example 2

[0187] It is basically the same as Example 1, except that the temperature in the first stage is 35°C and the temperature in the second stage is 50°C.

[0188] Comparative Example 3

[0189] It is basically the same as Example 1, except that the temperature of the first stage and the second stage is 50°C.

[0190] The reflectivity and pyramid CV value of the back side of the silicon wafer after etching in each embodiment and comparative example (4) were tested.

[0191] The solar cells prepared in each embodiment and comparative example were tested under AM 1.5G illumination conditions with a solar irradiance of 1000 W / m². 2 The speed is 0.02V / s. -1 The JV curves were obtained by forward and reverse scanning to obtain the photovoltaic index (Voc), short-circuit current density (Jsc), fill factor (FF), and photoelectric conversion efficiency (η). The results are shown in Table 2.

[0192] Table 2

[0193]

[0194] As shown in Table 2, compared with Comparative Example 1, the silicon wafers etched in each embodiment have lower reflectivity and lower pyramid CV values. This indicates that by etching at a gradient temperature, this application can achieve directional growth of textured structures, improve the etching uniformity of silicon wafers, and thus improve the photoelectric conversion efficiency of solar cells.

[0195] The synergistic effect of surface temperature gradient and organic amine can simultaneously optimize light trapping and carrier transport performance.

[0196] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0197] The embodiments described above are merely illustrative of several implementation methods of this application, intended to facilitate a detailed understanding of the technical solutions of this application, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. It should be understood that technical solutions obtained by those skilled in the art based on the technical solutions provided in this application through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this patent application should be determined by the content of the appended claims, and the specification can be used to interpret the content of the claims.

Claims

1. A method for preparing a solar cell, characterized in that, Includes the following steps: A silicon wafer is texturized on both sides; the silicon wafer includes a first surface, and the first surface includes a first region and a second region. The first region is etched using an alkaline solution, wherein the solute in the alkaline solution includes an inorganic base and an organic amine. The etching process includes: performing a first stage at a first temperature, followed by cooling to a second temperature for a second stage; the first temperature is 40°C to 60°C, and the second temperature is 30°C to 40°C. A passivated contact structure is prepared on the first surface; Electrodes are prepared in the second region.

2. The method for preparing a solar cell as described in claim 1, characterized in that, The difference between the first temperature and the second temperature is 5℃~30℃.

3. The method for preparing a solar cell as described in claim 2, characterized in that, The first temperature is 50℃~60℃, and the second temperature is 35℃~40℃.

4. The method for preparing a solar cell as described in claim 3, characterized in that, The first stage lasts 100-200 seconds, and the second stage lasts 400-500 seconds.

5. The method for preparing a solar cell as described in claim 1, characterized in that, The cooling rate is 3℃ / min to 10℃ / min.

6. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that, The alkaline solution comprises the following components by mass: 30-50 parts inorganic alkali, 5-40 parts organic amine, and 10-65 parts water.

7. The method for preparing a solar cell as described in claim 6, characterized in that, The alkaline solution comprises, by mass, the following components: 35-45 parts inorganic alkali, 20-40 parts organic amine, and 15-45 parts water.

8. The method for preparing a solar cell as described in claim 6, characterized in that, The preparation method satisfies at least one of the following characteristics: (1) The mass ratio of the organic amine to the inorganic base is (0.1~1):1; (2) The organic amine includes at least one of tetramethylammonium hydroxide and choline; (3) The inorganic base includes at least one of potassium hydroxide and sodium hydroxide.

9. The method for preparing a solar cell according to any one of claims 1-5 and 7-8, characterized in that, The preparation of the passivated contact structure includes: sequentially preparing a tunneling oxide layer and a doped polycrystalline silicon layer on the first surface.

10. The method for preparing a solar cell according to any one of claims 1-5 and 7-8, characterized in that, After the double-sided texturing is completed, before etching the first region, a mask layer is set in the second region.

11. The method for preparing a solar cell as described in claim 10, characterized in that, The silicon wafer includes a second surface opposite to the first surface; after the double-sided texturing and before the mask layer is applied, the process includes: diffusion on the second surface to form a PN junction.

12. A solar cell, characterized in that, The solar cell is prepared by the method described in any one of claims 1 to 11.

13. The solar cell according to claim 12, characterized in that, The solar cell includes a silicon wafer, a passivated contact structure disposed on the first surface, and an electrode disposed in the second region. The first region of the silicon wafer includes a pyramid structure, and the pyramid structure of the first region satisfies at least one of the following characteristics: (1) The height difference between any two of the pyramid structures is ≤1.2 μm; (2) The width difference between any two of the pyramid structures is ≤1.8 μm; (3) The bottom width of the pyramid structure is 2 μm to 5 μm.

14. A stacked battery, characterized in that, It includes a bottom cell and a top cell, wherein the bottom cell includes a solar cell as described in any one of claims 12 to 13.

15. A photovoltaic module, characterized in that, This includes the solar cell as described in any one of claims 12-13 or the tandem cell as described in claim 14.

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