TopCon battery and TopCon battery preparation method

Abstract

The invention discloses a TopCon cell and a TopCon cell preparation method, and belongs to the field of solar cells. The structure of the passivation layer is optimized, the doped polycrystalline silicon layer is reserved in the metal contact area, the doped polycrystalline silicon layer and the substrate form a high-low junction to provide field passivation, and ohmic contact is formed between the doped polycrystalline silicon layer and the electrode; a doped polycrystalline silicon carbide layer is arranged in a non-metal contact area, and the doped polycrystalline silicon carbide layer and a substrate form a heterojunction to provide field passivation and serve as a carrier transverse transmission layer. The parasitic absorption of the passivation layer is reduced by removing the doped polycrystalline silicon layer in the non-metal contact region. The light absorption coefficient of the doped polycrystalline silicon carbide layer is low and the doped polycrystalline silicon carbide layer is thin, so that parasitic absorption can be reduced. Ohmic contact is formed between the doped polycrystalline silicon layer in the reserved metal contact area and the electrode, so that low recombination loss can be ensured when the doped polycrystalline silicon layer is in contact with the metal grid line. Field passivation is formed in the metal contact area and the non-metal area, and the passivation effect of the whole surface of the substrate is guaranteed.

Description

Technical Field

[0001] This application relates to the field of solar cells, and in particular to a TopCon cell and a method for preparing a TopCon cell. Background Technology

[0002] Traditional TopCon (Tunnel Oxide Passivated Contact) solar cells sequentially deposit a tunneling layer and a doped polysilicon layer as passivation layers across the entire substrate surface. However, due to the material structure and doping concentration of the doped polysilicon layer, the doped polysilicon layer in traditional TopCon cells has a relatively high light absorption coefficient, leading to severe parasitic absorption problems. This problem affects the cell's short-circuit current and bifaciality. Therefore, there is a need to provide a TopCon cell and a TopCon cell fabrication method to solve the parasitic absorption problem in the existing technology. Summary of the Invention

[0003] The purpose of this application is to provide a TopCon battery and a method for preparing a TopCon battery, thereby solving the problem of parasitic absorption.

[0004] To achieve the above objectives, this application provides a TopCon battery, comprising: a substrate; one side surface of the substrate having a metal contact region and a non-metal contact region;

[0005] The metal contact region is sequentially provided with a first tunneling layer, a doped polysilicon layer, and an electrode along a direction away from the substrate; the electrode is in ohmic contact with the doped polysilicon layer.

[0006] The non-metallic contact area is provided with a second tunneling layer and a doped polycrystalline silicon carbide layer in sequence along the direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than that of the doped polycrystalline silicon layer.

[0007] Optionally, the second tunneling layer covers the doped polycrystalline silicon layer and the non-metallic contact region; the doped polycrystalline silicon carbide layer covers the second tunneling layer;

[0008] The electrode penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer, and makes ohmic contact with the doped polycrystalline silicon layer.

[0009] Optionally, the TopCon cell further includes: a passivation antireflection layer; the passivation antireflection layer covers the surface of the doped polycrystalline silicon carbide layer opposite to the substrate;

[0010] The electrode penetrates the passivation antireflection layer, the doped polycrystalline silicon carbide layer, and the second tunneling layer, and makes ohmic contact with the doped polycrystalline silicon layer.

[0011] Optionally, the passivation antireflection layer includes any one or more of the following: silicon nitride layer, silicon oxynitride layer, silicon oxide layer, aluminum oxide layer, aluminum nitride layer, aluminum oxynitride layer, and magnesium fluoride layer.

[0012] Optionally, the thickness of the passivation antireflection layer is 70nm-150nm, including the values ​​at both ends.

[0013] Optionally, the activation impurity concentration of the doped polycrystalline silicon layer is 1×10⁻⁶. 20 cm -3 -1×10 21 cm -3 And includes the values ​​at both ends;

[0014] The thickness of the doped polycrystalline silicon layer is 20nm-100nm, including the values ​​at both ends.

[0015] Optionally, the activation impurity concentration of the doped polycrystalline silicon carbide layer is 1×10⁻⁶. 20 cm -3 -1×10 21 cm -3 And includes the values ​​at both ends;

[0016] The thickness of the doped polycrystalline silicon carbide layer is 20nm-50nm, including the values ​​at both ends.

[0017] Optionally, the width of the metal contact area is 80μm-200μm, including the values ​​at both ends; the width of the non-metal contact area is 1000μm-2000μm, including the values ​​at both ends.

[0018] To achieve the above objectives, this application also provides a method for fabricating a TopCon battery, comprising:

[0019] A first tunneling layer and a doped polysilicon layer are sequentially prepared in the metal contact area on one side of the substrate in a direction away from the substrate.

[0020] A second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially formed in the non-metallic contact region on one side of the substrate in a direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than that of the doped polycrystalline silicon layer.

[0021] After the doped polycrystalline silicon layer and the doped polycrystalline silicon carbide layer are prepared, an electrode is prepared in the metal contact region to make the electrode ohmic contact with the doped polycrystalline silicon layer.

[0022] Optionally, a second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially formed in the non-metallic contact region on one side of the substrate along a direction away from the substrate, including:

[0023] After the doped polycrystalline silicon layer is prepared, the second tunneling layer and the doped polycrystalline silicon carbide layer are sequentially prepared in the doped polycrystalline silicon layer and the non-metallic contact area along the direction away from the substrate.

[0024] Accordingly, fabricating an electrode in the metal contact region to make the electrode ohmic in contact with the doped polycrystalline silicon layer includes:

[0025] The electrode is fabricated such that it penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer, and makes ohmic contact with the doped polycrystalline silicon layer.

[0026] Obviously, the TopCon cell provided in this application optimizes the passivation layer structure. A doped polycrystalline silicon layer is retained in the metal contact region, forming a high-low junction with the substrate to provide field passivation and an ohmic contact with the electrode. A doped polycrystalline silicon carbide layer is disposed in the non-metal contact region, forming a heterojunction with the substrate to provide field passivation and serving as a carrier lateral transport layer. On the one hand, removing the doped polycrystalline silicon layer in the non-metal contact region reduces parasitic absorption of the passivation layer. Furthermore, since the doped polycrystalline silicon carbide layer has a low light absorption coefficient and is thin, parasitic absorption is also reduced. On the other hand, retaining the doped polycrystalline silicon layer in the metal contact region to form an ohmic contact with the electrode ensures low recombination loss when in contact with the metal grid line. In addition, field passivation is formed in both the metal contact region and the non-metal region, ensuring passivation effect across the entire substrate surface. This application also provides a method for fabricating a TopCon cell, and the TopCon cell fabricated by this method also possesses the aforementioned beneficial effects. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a TopCon battery provided in an embodiment of this application;

[0029] Figure 2 This is a flowchart illustrating a TopCon battery fabrication method provided in an embodiment of this application.

[0030] The following are the descriptions of the reference numerals:

[0031] 1-Substrate; 2-First tunneling layer; 3-Doped polycrystalline silicon layer; 4-Second tunneling layer; 5-Doped polycrystalline silicon carbide layer; 6-Passivation antireflection layer; 7-Electrode. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a TopCon battery provided in an embodiment of this application. The structure may include: a substrate 1; one side surface of the substrate 1 has a metal contact area and a non-metal contact area;

[0034] The metal contact area is sequentially provided with a first tunneling layer 2, a doped polysilicon layer 3 and an electrode 7 along the direction away from the substrate 1; the electrode 7 is in ohmic contact with the doped polysilicon layer 3.

[0035] The non-metallic contact area is provided with a second tunneling layer 4 and a doped polycrystalline silicon carbide layer 5 in sequence along the direction away from the substrate 1; the light absorption coefficient of the doped polycrystalline silicon carbide layer 5 is less than that of the doped polycrystalline silicon layer 3.

[0036] This embodiment does not limit the specific type of substrate 1. For example, substrate 1 can be doped single crystal silicon, including but not limited to phosphorus-doped N-type single crystal silicon, boron-doped or gallium-doped P-type single crystal silicon.

[0037] This embodiment does not limit the specific location of the passivation structure formed by the first tunneling layer 2, the doped polycrystalline silicon layer 3, the second tunneling layer 4 and the doped polycrystalline silicon carbide layer 5. For example, it can be located on the front side of the substrate 1; it can be located on the back side of the substrate 1; or it can be located on both the front and back sides of the substrate 1.

[0038] This embodiment does not limit the specific type of the first tunneling layer 2. For example, the first tunneling layer 2 can be a tunneling oxide layer, including but not limited to phosphorus- or boron-containing silicon oxide layers, silicon oxynitride layers, aluminum oxide layers, and aluminum oxynitride layers. This embodiment does not limit the specific thickness of the first tunneling layer 2. For example, the thickness of the first tunneling layer 2 can be 0.5 nm to 2 nm, including the values ​​at both ends.

[0039] This embodiment does not limit the specific type of the second tunneling layer 4. For example, the second tunneling layer 4 can be a tunneling oxide layer, including but not limited to phosphorus- or boron-containing silicon oxide layers, silicon oxynitride layers, aluminum oxide layers, and aluminum oxynitride layers. This embodiment does not limit the specific thickness of the second tunneling layer 4. For example, the thickness of the second tunneling layer 4 can be 0.5 nm to 2 nm, including the values ​​at both ends.

[0040] This embodiment does not limit the specific type of doped polysilicon layer 3. For example, the doped polysilicon layer 3 can be a phosphorus-doped or boron-doped polysilicon layer. This embodiment also does not limit the specific activation impurity concentration of the doped polysilicon layer 3. For example, the activation impurity concentration of the doped polysilicon layer 3 can be 1×10⁻⁶. 20 cm -3 -1×10 21 cm -3 The thickness of the doped polysilicon layer 3 is not limited in this embodiment. For example, the thickness of the doped polysilicon layer 3 can be 20nm-100nm, and the thickness of the doped polysilicon layer 3 can be 20nm-100nm, including the values ​​at both ends.

[0041] This embodiment does not limit the specific type of doped polycrystalline silicon carbide layer 5. For example, the doped polycrystalline silicon carbide layer 5 can be a phosphorus-doped or boron-doped polycrystalline silicon carbide layer. This embodiment also does not limit the specific activation impurity concentration of the doped polycrystalline silicon carbide layer 5. For example, the activation impurity concentration of the doped polycrystalline silicon carbide layer 5 can be 1×10⁻⁶. 20 cm -3 -1×10 21 cm -3 The thickness of the doped polycrystalline silicon carbide layer 5 is not limited in this embodiment. For example, the thickness of the doped polycrystalline silicon carbide layer 5 can be 20nm-50nm, including the values ​​at both ends. It should be noted that when the doped polycrystalline silicon carbide layer 5 covers both the non-metallic contact area and the metallic contact area, the thinner the thickness of the doped polycrystalline silicon carbide layer 5, the more beneficial it is for the electrode 7 paste to burn through the second tunneling layer 4 and contact the doped polycrystalline silicon layer 3.

[0042] This embodiment does not limit the specific width of the metal contact area and the non-metal contact area. For example, the width of the metal contact area can be 80μm-200μm, including the values ​​at both ends; the width of the non-metal contact area can be 1000μm-2000μm, including the values ​​at both ends. It should be noted that in this embodiment, the pattern of the metal contact area corresponds to the pattern of the metal electrode 7 and is distributed in a grid pattern.

[0043] This embodiment does not limit the specific type of material used for electrode 7. For example, the material of electrode 7 may include, but is not limited to, silver, aluminum, copper and their alloys.

[0044] Furthermore, in this embodiment, the second tunneling layer 4 can cover the doped polycrystalline silicon layer 3 and the non-metallic contact area; the doped polycrystalline silicon carbide layer 5 can cover the second tunneling layer 4; the electrode 7 penetrates the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4, making ohmic contact with the doped polycrystalline silicon layer 3. It should be noted that the different materials are spatially distributed by dividing the contact area into metal and non-metallic areas. In this embodiment, the metal contact area is a stack of the first tunneling layer 2, the doped polycrystalline silicon layer 3, the second tunneling layer 4, and the doped polycrystalline silicon carbide layer 5, and the non-metallic contact area is the second tunneling layer 4 and the doped polycrystalline silicon carbide layer 5. In this embodiment, the step of patterning the second tunneling layer 4 and the doped polycrystalline silicon carbide layer 5 can be omitted, simplifying the fabrication process.

[0045] Furthermore, in order to achieve the anti-reflection and passivation functions, this embodiment may also include: a passivation anti-reflection layer 6; the passivation anti-reflection layer 6 covers the surface of the doped polycrystalline silicon carbide layer 5 away from the substrate 1; the electrode 7 penetrates the passivation anti-reflection layer 6, the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4, and makes ohmic contact with the doped polycrystalline silicon layer 3.

[0046] This embodiment does not limit the specific type of the passivation antireflection layer 6. For example, the passivation antireflection layer 6 may include any one or more of the following: silicon nitride layer, silicon oxynitride layer, silicon oxide layer, aluminum oxide layer, aluminum nitride layer, aluminum oxynitride layer, and magnesium fluoride layer. This embodiment does not limit the specific thickness of the passivation antireflection layer 6. For example, the thickness of the passivation antireflection layer 6 may be 70nm-150nm, including the values ​​at both ends.

[0047] Based on the above embodiments, this application optimizes the passivation layer structure. A doped polysilicon layer is retained in the metal contact region, forming a high-low junction with the substrate to provide field passivation and an ohmic contact with the electrode. A doped polysilicon carbide layer is disposed in the non-metal contact region, forming a heterojunction with the substrate to provide field passivation and serving as a carrier lateral transport layer. On the one hand, removing the doped polysilicon layer in the non-metal contact region reduces parasitic absorption of the passivation layer. Furthermore, since the doped polysilicon carbide layer has a low light absorption coefficient and is thin, parasitic absorption is also reduced. On the other hand, retaining the doped polysilicon layer in the metal contact region to form an ohmic contact with the electrode ensures low recombination loss when in contact with the metal gate line. In addition, field passivation is formed in both the metal contact region and the non-metal region, ensuring passivation effect across the entire substrate surface.

[0048] Please refer to Figure 2 , Figure 2 A flowchart of a TopCon battery fabrication method provided in this application embodiment, the method may include:

[0049] S101: A first tunneling layer and a doped polysilicon layer are sequentially prepared in the metal contact area on one side of the substrate in a direction away from the substrate.

[0050] Furthermore, in order to remove dirt and mechanical damage from the surface of substrate 1 and form a polished or pyramidal textured surface, substrate 1 can be cleaned and dried before step S101. This embodiment does not limit the specific cleaning method, as long as it can ensure that dirt and mechanical damage on the surface of substrate 1 are removed and a polished or pyramidal textured surface is formed. For example, wet chemical cleaning and drying of substrate 1 can be used.

[0051] This embodiment does not limit the specific method of preparing the first tunneling layer 2 and the doped polysilicon layer 3, as long as the first tunneling layer 2 and the doped polysilicon layer 3 can be formed in the metal contact area. For example, the first tunneling layer 2 can be prepared on one side of the substrate 1; after the first tunneling layer 2 is formed, the doped polysilicon layer 3 is prepared on the surface of the first tunneling layer 2 away from the substrate 1; after the doped polysilicon layer 3 is formed, patterning processing is performed to remove the doped polysilicon layer 3 and the first tunneling layer 2 in the non-metal contact area.

[0052] This embodiment does not limit the specific method of preparing the first tunneling layer 2. The corresponding preparation method can be selected according to the specific type of the first tunneling layer 2. For example, when the first tunneling layer 2 is a tunneling oxide layer, oxygen high-temperature thermal oxidation or plasma-enhanced oxidation by introducing nitrous oxide in a PECVD (Plasma Enhanced Chemical Vapor Deposition) device can be used to oxidize one side surface of the substrate 1 and form the first tunneling layer 2 on one side surface of the substrate 1.

[0053] This embodiment does not limit the specific method of preparing the doped polycrystalline silicon layer 3. For example, it can be prepared by depositing a doped amorphous silicon layer on the surface of the first tunneling layer 2 away from the substrate 1 using a PECVD device. The reaction gas source can be, but is not limited to, silane, phosphine, diborane, or hydrogen. After the doped amorphous silicon layer is formed, it is crystallized in an annealing device to form the doped polycrystalline silicon layer 3. This preparation method is an in-situ doping method. In addition, the doped amorphous silicon layer can also be formed by impurity diffusion.

[0054] This embodiment does not limit the specific timing of crystallization. The doped amorphous silicon layer can be crystallized directly after its formation; alternatively, both the doped amorphous silicon layer and the doped amorphous silicon carbide layer can be crystallized simultaneously after their formation. This embodiment does not limit the specific value of the annealing temperature; for example, the annealing temperature can be 850℃-1100℃, including both extremes. This embodiment does not limit the specific type of annealing atmosphere; for example, the annealing atmosphere can be an inert gas such as nitrogen or argon, or a hydrogen-nitrogen mixture.

[0055] This embodiment does not limit the specific method of patterning. For example, an oxide mask can be prepared on the surface of the doped amorphous silicon layer away from the substrate 1. After forming the oxide mask, the oxide mask, the doped amorphous silicon layer and the first tunneling oxide layer in the non-metallic contact area are removed. After removing the first tunneling oxide layer, the oxide mask in the metal contact area is removed.

[0056] This embodiment does not limit the specific type of oxide mask. For example, the oxide mask may include a silicon oxide mask or a silicon oxynitride mask. This embodiment does not limit the specific method of preparing the oxide mask. The corresponding preparation method can be selected according to the specific type of oxide mask. For example, an oxide mask can be deposited on the surface of the doped amorphous silicon layer away from the substrate 1 using a PECVD device. The reaction gas source includes, but is not limited to, silane, nitrous oxide, or ammonia.

[0057] This embodiment does not limit the specific method for removing the oxide mask in the non-metallic contact area. For example, a laser can be used to create openings in the oxide mask in the non-metallic contact area; alternatively, a blocking paste can be printed on the surface of the oxide mask in the metallic contact area, and after printing the blocking paste, hydrofluoric acid etching can be used to remove the oxide mask in the non-metallic contact area. It should be noted that the oxide mask in the metallic contact area can be directly removed by hydrofluoric acid etching.

[0058] This embodiment does not limit the specific method for removing the doped amorphous silicon layer in the non-metallic contact region. For example, alkaline solution etching can be used to remove the doped amorphous silicon layer in the non-metallic contact region. It should be noted that the first tunneling layer 2 will also be removed during the removal of the doped amorphous silicon layer.

[0059] Furthermore, in this embodiment, after removing the oxide mask in the metal contact area, the surface of substrate 1 can also be cleaned; the cleaning method includes, but is not limited to, water washing or RCA cleaning. RCA cleaning is a wet chemical cleaning method.

[0060] S102: A second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially prepared in the non-metallic contact area on one side of the substrate in the direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than that of the doped polycrystalline silicon layer.

[0061] Furthermore, in order to simplify the process flow, in this embodiment, after the doped polycrystalline silicon layer 3 is prepared, a second tunneling layer 4 and a doped polycrystalline silicon carbide layer 5 are sequentially prepared in the non-metallic contact area of ​​the doped polycrystalline silicon layer 3 in the direction away from the substrate 1; accordingly, an electrode 7 is prepared so that the electrode 7 penetrates the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4 and makes ohmic contact with the doped polycrystalline silicon layer 3.

[0062] This embodiment does not limit the specific method of preparing the second tunneling layer 4. The corresponding preparation method can be selected according to the specific type of the second tunneling layer 4. For example, when the second tunneling layer 4 is a tunneling oxide layer, high-temperature thermal oxidation with oxygen or plasma-enhanced oxidation by introducing nitrous oxide in a PECVD device can be used to oxidize the surface of the doped polysilicon layer 3 away from the substrate 1 and the non-metallic contact area, thereby forming the second tunneling layer 4 on the surface of the doped polysilicon layer 3 away from the substrate 1 and the non-metallic contact area.

[0063] This embodiment does not limit the specific method of preparing the doped polycrystalline silicon carbide layer 5. For example, it can be prepared by depositing a doped amorphous silicon carbide layer on the surface of the second tunneling layer 4 away from the substrate 1 using a PECVD device. The reaction gas source can be, but is not limited to, silane, phosphine, diborane, or hydrogen. After forming the doped amorphous silicon carbide layer, the doped amorphous silicon carbide layer is crystallized in an annealing device to form the doped polycrystalline silicon carbide layer 5. This preparation method is an in-situ doping method. Alternatively, the doped amorphous silicon carbide layer can also be formed by impurity diffusion.

[0064] Furthermore, in order to achieve the anti-reflection and passivation functions, in this embodiment, after step S102, a passivation anti-reflection layer 6 can be prepared on the surface of the doped polycrystalline silicon carbide layer 5 away from the substrate 1; correspondingly, an electrode 7 is prepared so that the electrode 7 penetrates the passivation anti-reflection layer 6, the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4, and makes ohmic contact with the doped polycrystalline silicon layer 3.

[0065] This embodiment does not limit the specific type of the passivation antireflection layer 6. For example, the passivation antireflection layer 6 may include any one or more of the following: silicon nitride layer, silicon oxynitride layer, silicon oxide layer, aluminum oxide layer, aluminum nitride layer, aluminum oxynitride layer, and magnesium fluoride layer. This embodiment does not limit the specific method of preparing the passivation antireflection layer 6. The corresponding preparation method can be selected according to the specific type of the passivation antireflection layer 6. For example, the passivation antireflection layer 6 can be deposited on the surface of the doped polycrystalline silicon carbide layer 5 away from the substrate 1 using a PECVD device or an ALD (Atomic Layer Deposition) device. The reaction gas source includes, but is not limited to, silane, ammonia, trimethylaluminum, or nitrous oxide.

[0066] S103: After the doped polycrystalline silicon layer and the doped polycrystalline silicon carbide layer are prepared, an electrode is prepared in the metal contact region to make the electrode ohmic contact with the doped polycrystalline silicon layer.

[0067] This embodiment does not limit the specific method of preparing electrode 7. For example, electrode 7 can be prepared in the metal contact area by screen printing or electroplating. Screen printing requires high-temperature sintering and annealing to evaporate the organic solvent in the metal paste, burn through the surface passivation and antireflection layer 6 of the glass powder particles, and form a metal-semiconductor contact between the metal particles and the doped polycrystalline silicon layer 3. Electroplating requires laser pretreatment to remove the surface passivation and antireflection layer 6 and the doped polycrystalline silicon carbide layer 5 of the electroplated area, so that the electroplated metal and the doped polycrystalline silicon layer 3 form a metal-semiconductor contact.

[0068] The TopCon solar cell fabricated based on the above embodiments features an optimized passivation layer structure. A doped polycrystalline silicon layer is retained in the metal contact region, forming a high-low junction with the substrate to provide field passivation and an ohmic contact with the electrode. A doped polycrystalline silicon carbide layer is disposed in the non-metal contact region, forming a heterojunction with the substrate to provide field passivation and serving as a lateral carrier transport layer. On one hand, removing the doped polycrystalline silicon layer in the non-metal contact region reduces parasitic absorption in the passivation layer. Furthermore, the low light absorption coefficient and thinness of the doped polycrystalline silicon carbide layer also reduce parasitic absorption. On the other hand, retaining the doped polycrystalline silicon layer in the metal contact region to form an ohmic contact with the electrode ensures low recombination loss when in contact with the metal gate line. In addition, field passivation is formed in both the metal contact region and the non-metal region, ensuring passivation across the entire substrate surface.

[0069] The following example illustrates the TopCon battery fabrication process, which is as follows:

[0070] Step 1, Cleaning: The silicon wafer is cleaned and dried using a wet chemical method to remove dirt and mechanical damage from the surface of the silicon wafer and to form a polished or pyramidal textured surface. No restrictions are placed on the cleaning process here.

[0071] Step 2, Primary Oxidation: The cleaned silicon wafers are subjected to surface oxidation treatment, which is carried out by high-temperature oxygen thermal oxidation or by plasma-enhanced oxidation by introducing nitrous oxide in the PECVD equipment to form a tunneling oxide layer on the surface of the silicon wafer.

[0072] Step 3, Amorphous silicon deposition: A doped amorphous silicon thin film is deposited on the surface of the silicon wafer using a PECVD device. The reaction gas source is silane, phosphine, diborane, or hydrogen, etc.

[0073] Step 4, Oxide Mask Deposition: A silicon oxide or silicon oxynitride mask is deposited on the surface of a doped amorphous silicon thin film using a PECVD device. The reaction gas source is silane, nitrous oxide, or ammonia, etc.

[0074] Step 5, Patterning: Patterning etching is performed on the oxide mask and the doped amorphous silicon thin film. The specific process includes: fabrication of patterned oxide mask, fabrication of patterned doped amorphous silicon thin film, hydrofluoric acid etching and post-cleaning.

[0075] Among them, the preparation of patterned oxide masks may include laser film opening, or blocking paste printing and hydrofluoric acid etching, etc., to remove the oxide mask in the non-metal contact area and retain the oxide mask in the metal contact area.

[0076] Patterned doped amorphous silicon thin films can be prepared by etching with an alkaline solution to remove the doped amorphous silicon thin film in the non-metallic contact area; during the removal of the doped amorphous silicon thin film, the tunneling oxide layer formed in step 2 will also be removed.

[0077] Hydrofluoric acid etching is used to remove the remaining oxide mask in the metal contact area, and the silicon wafer surface is cleaned by water washing or RCA cleaning.

[0078] Step 6, Secondary oxidation: The cleaned silicon wafer is subjected to surface oxidation treatment, which is carried out by high-temperature oxygen thermal oxidation or by introducing nitrous oxide into the PECVD equipment for plasma-enhanced oxidation, forming a tunnel oxide layer on the surface of the silicon wafer and the patterned doped amorphous silicon thin film.

[0079] Step 7, Deposition of doped amorphous silicon carbide: A PECVD device is used to deposit a doped amorphous silicon carbide film on the surface of the silicon wafer. The reaction gas source is silane, methane, phosphine, diborane or hydrogen, etc.

[0080] Step 8, High-Temperature Annealing and Crystallization: The silicon wafer is placed in a high-temperature annealing apparatus at 850 to 1100°C, where the doped amorphous silicon film and the doped amorphous silicon carbide film prepared in Steps 3 and 7 crystallize to form a doped polycrystalline silicon film and a doped polycrystalline silicon carbide film. The annealing atmosphere is an inert gas such as nitrogen or argon, or a hydrogen-nitrogen mixture.

[0081] Step 9: Surface passivation and antireflection film deposition: PECVD, ALD and other equipment are used to deposit a surface passivation and antireflection film on the silicon wafer surface to form a surface passivation and antireflection film on the outside of the doped polycrystalline silicon film. The reaction gas source is silane, ammonia, trimethylaluminum or nitrous oxide, etc.

[0082] Step 10, Metallization: Using screen printing or electroplating, prepare metal electrodes with the same pattern in the metal contact area. Screen printing requires high-temperature sintering and annealing to evaporate the organic solvents in the metal paste, burn through the surface passivation and antireflection film with glass powder particles, and form a metal-semiconductor contact between the metal particles and the doped polycrystalline silicon film. Electroplating requires laser pretreatment to remove the passivation and antireflection film and the doped polycrystalline silicon carbide film from the electroplated area, forming a metal-semiconductor contact between the electroplated metal and the doped polycrystalline silicon film.

[0083] This document uses specific examples to illustrate the principles and implementation methods of this application. The various embodiments are progressive, with each embodiment focusing on its differences from others. Similar or identical parts between embodiments can be referred to interchangeably. The descriptions of the embodiments above are merely illustrative of the method and core ideas of this application. For those skilled in the art, various improvements and modifications can be made to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0084] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A TopCon battery, characterized in that, include: Substrate; one side surface of the substrate has a metal contact area and a non-metal contact area; The metal contact region is sequentially provided with a first tunneling layer, a doped polysilicon layer, and an electrode along a direction away from the substrate; the electrode is in ohmic contact with the doped polysilicon layer. The non-metallic contact area is provided with a second tunneling layer and a doped polycrystalline silicon carbide layer in sequence along the direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than that of the doped polycrystalline silicon layer.

2. The TopCon battery according to claim 1, characterized in that, The second tunneling layer covers the doped polycrystalline silicon layer and the non-metallic contact region; the doped polycrystalline silicon carbide layer covers the second tunneling layer; The electrode penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer, and makes ohmic contact with the doped polycrystalline silicon layer.

3. The TopCon battery according to claim 2, characterized in that, Also includes: A passivation antireflection layer; the passivation antireflection layer covers the surface of the doped polycrystalline silicon carbide layer opposite to the substrate; The electrode penetrates the passivation antireflection layer, the doped polycrystalline silicon carbide layer, and the second tunneling layer, and makes ohmic contact with the doped polycrystalline silicon layer.

4. The TopCon battery according to claim 3, characterized in that, The passivation antireflection layer includes any one or more of the following: silicon nitride layer, silicon oxynitride layer, silicon oxide layer, aluminum oxide layer, aluminum nitride layer, aluminum oxynitride layer, and magnesium fluoride layer.

5. The TopCon battery according to claim 3, characterized in that, The thickness of the passivation antireflection layer is 70nm-150nm, including the values ​​at both ends.

6. The TopCon battery according to claim 1, characterized in that, The activation impurity concentration of the doped polysilicon layer is 1×10⁻⁶. 20 cm -3 -1×10 21 cm -3 And includes the values ​​at both ends; The thickness of the doped polycrystalline silicon layer is 20nm-100nm, including the values ​​at both ends.

7. The TopCon battery according to claim 1, characterized in that, The activation impurity concentration of the doped polycrystalline silicon carbide layer is 1×10⁻⁶. 20 cm -3 -1×10 21 cm -3 And includes the values ​​at both ends; The thickness of the doped polycrystalline silicon carbide layer is 20nm-50nm, including the values ​​at both ends.

8. The TopCon battery according to claim 1, characterized in that, The width of the metal contact area is 80μm-200μm, including the values ​​at both ends; the width of the non-metal contact area is 1000μm-2000μm, including the values ​​at both ends.

9. A method for preparing a TopCon battery, characterized in that, include: A first tunneling layer and a doped polysilicon layer are sequentially prepared in the metal contact area on one side of the substrate in a direction away from the substrate. A second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially formed in the non-metallic contact region on one side of the substrate in a direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than that of the doped polycrystalline silicon layer. After the doped polycrystalline silicon layer and the doped polycrystalline silicon carbide layer are prepared, an electrode is prepared in the metal contact region to make the electrode ohmic contact with the doped polycrystalline silicon layer.

10. The method for preparing a TopCon battery according to claim 9, characterized in that, A second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially formed in the non-metallic contact region on one side of the substrate in a direction away from the substrate, including: After the doped polycrystalline silicon layer is prepared, the second tunneling layer and the doped polycrystalline silicon carbide layer are sequentially prepared in the doped polycrystalline silicon layer and the non-metallic contact area along the direction away from the substrate. Accordingly, fabricating an electrode in the metal contact region to make the electrode ohmic in contact with the doped polycrystalline silicon layer includes: The electrode is fabricated such that it penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer, and makes ohmic contact with the doped polycrystalline silicon layer.

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