Enhanced mode high electron mobility transistor device

Abstract

The embodiment of the utility model relates to an enhancement mode high electron mobility transistor device. An enhanced mode high electron mobility transistor device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas. A high electron mobility transistor device includes a gate structure extending over a top surface of a semiconductor body, biased to electrically control a two-dimensional electron gas, and including a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is made of a layer of conductive material, and the functional layer is made of a layer of two-dimensional semiconductor material and includes a first doped portion having P-type conductivity extending over a top surface of the semiconductor body and interposed along a first axis between the semiconductor body and the gate contact. According to the embodiment of the invention, the low power consumption of the transistor in use is ensured, and the integration of the transistor into an electronic circuit in a design step is simplified.

Description

Technical Field

[0001] This disclosure relates to an improved enhancement-mode high electron mobility transistor. Specifically, this disclosure relates to an enhancement-mode high electron mobility transistor comprising a gate structure extending on a semiconductor body and having gate contacts and a functional layer of a two-dimensional semiconductor (e.g., a transition metal dichloride) interposed between the semiconductor body and the gate contacts. Background Technology

[0002] As is well known, high electron mobility transistor devices comprise heterostructures that have an interface between two different semiconductor material layers, such as aluminum gallium nitride (AlGaN) and gallium nitride (GaN). High electron mobility transistor devices based on AlGaN / GaN heterostructures possess a two-dimensional electron gas (2D electron gas) at this interface.

[0003] A two-dimensional electron gas layer represents a high-charge-density electron cloud, in which charges possess high mobility. These properties make high-electron-mobility transistor devices attractive for radio frequency (RF) and power electronics applications. Specifically, high-electron-mobility transistors exhibit high breakdown field (equivalent to approximately 2 MV / cm–4 MV / cm), high charge carrier density, and two-dimensional electron gas mobility (e.g., greater than approximately 10⁻⁶). 13 cm －2 Approximately 1000cm 2 V －1 s －1 -2000cm 2 V －1 s －1 ).

[0004] Typically, GaN / AlGaN high electron mobility transistors are known to operate in depletion mode, i.e., normally-on mode. However, in various applications, GaN / AlGaN high electron mobility transistors in enhancement mode (i.e., normally-off mode) are used to improve the reliability of the corresponding electronic circuits and reduce their design complexity and power consumption.

[0005] Currently, different solutions are known for providing enhancement-mode high electron mobility transistors. Figure 1A -1D shows some known types of enhancement-mode high electron mobility transistors (with reference to a three-axis Cartesian system defined by mutually orthogonal X, Y, and Z axes).

[0006] Specifically, Figure 1AA high electron mobility transistor 1 of a known type is shown, comprising a substrate 3 of semiconductor material layers (e.g., silicon or silicon carbide) overlapping each other along the Z-axis, a first GaN structural layer 5, and a second GaN structural layer 7, the second structural layer 7 having a bottom surface 7a facing the first structural layer 5 and a top surface 7b opposite the bottom surface 7a relative to the Z-axis. The high electron mobility transistor 1 also includes source contacts 8 and drain contacts 9 of a metal material layer, which are physically separated from each other and extend on the top surface 7b of the second structural layer 7. Furthermore, the high electron mobility transistor 1 includes trench gate contacts 10 extending into the second structural layer 7, recessed to form trenches. Specifically, the trench gate contacts 10 extend partially inside and partially outside the trenches in the second structural layer 7. The presence of the trench gate contacts 10 reduces the thickness of the second structural layer 7 measured along the Z-axis at the trench gate contacts 10 (specifically, below the latter), and therefore, due to the resulting modification of the band diagram of the high electron mobility transistor 1, the thickness of the second structural layer 7 is reduced when no gate voltage V is applied. G In this case, it prevents the formation of a two-dimensional electron gas (referred to here by reference numeral 11) under the trench gate contact 10.

[0007] Figure 1B A high electron mobility transistor 1 of a known type is shown, whose structure is similar to Figure 1A However, here the gate contact 10 is not slotted and extends above the top surface 7b of the second structural layer 7. Furthermore, below the gate contact 10, a two-dimensional electron gas interruption region 13 of the second structural layer 7 extends (e.g., extending from the top surface 7b toward the bottom surface 7a, but not reaching the bottom surface 7a), in which negatively charged substances (e.g., fluoride ions, F) have been incorporated. － These negative charges in the two-dimensional electron gas interruption region 13 modify the energy band diagram of the high electron mobility transistor 1 and prevent electron flow even when no gate voltage V is applied. G In this case, a two-dimensional electron gas 11 is formed below the trench gate contact 10.

[0008] Figure 1C A high electron mobility transistor 1 of a known type is shown, whose structure is similar to Figure 1A However, here the gate contact 10 is not a trench contact and extends above the top surface 7b of the second structural layer 7 without direct physical contact with it. Furthermore, a GaN functional layer 15 with P-type conductivity extends between the gate contact 10 and the second structural layer 7. The functional layer 15 is doped with a dopant such as magnesium and has a thickness of approximately 50 nm measured along the Z-axis, and is designed in such a way that it modifies the band diagram of the high electron mobility transistor 1 to prevent [the transistor from operating without a gate voltage V]. GIn this case, a two-dimensional electron gas 11 is formed below the trench gate contact 10 (further details in this regard can be found in the paper "Physics and technology of gallium nitride materials for power electronics" F. Roccaforte, P. Fiorenza, R. Lo Nigro, F. Gianniazzo, G. Greco, La Rivista del NuovoCimento).

[0009] Figure 1D A high electron mobility transistor 1 of a known type (specifically, a MIS high electron mobility transistor) is shown, which has similar characteristics to... Figure 1A The structure is as follows. However, here, the trench gate contact 10 extending into the second structural layer 7 is surrounded by a dielectric region 17, which is physically interposed between the second structural layer 7 and the trench gate contact 10, and further extends on the top surface 7b of the second structural layer 7 between the source contact 8 and the drain contact 9. Figure 1D In this structure, the trench extends along the Z-axis through the entire second structural layer 7 and also partially extends into the first structural layer 5. The trench gate contact 10 and the dielectric region 17 allow for operation without an applied gate voltage V. G In the case of interrupting the two-dimensional electronic gas 11 at the latter.

[0010] However, known solutions have different problems, such as manufacturing difficulties and low reliability of high electron mobility transistors.

[0011] For example, for Figure 1CFor a high electron mobility transistor 1, achieving a sufficiently high hole concentration in the functional layer 15 to prevent the formation of a two-dimensional electron gas 11 may be difficult due to the high ionization energy of the magnesium acceptor. Furthermore, the functional layer 15 is typically defined by a p-GaN layer uniformly deposited on the top surface 7b by plasma etching; however, such plasma etching is difficult to control precisely and may damage the region that keeps the top surface 7b exposed, thereby introducing defects into the lattice of the second structural layer 7. Alternative fabrication processes that do not utilize plasma etching include, for example, selective growth of the functional layer 15 (however, using processes such as metal-organic chemical vapor deposition (MOCVD) in a controlled manner over a wide wafer area is complex; further details on this process can be found in Yuliang et al., “AlGaN / GaN high electron mobility transistors with selective area grown p-GaN gates,” Journal of Semiconductors, 37.114002 (2016)) or hydrogen plasma deactivation of the functional layer 15 outside the area used to become the gate region (however, reactivation of the functional layer 15 may occur if thermal treatment is performed on the high electron mobility transistor after hydrogen plasma treatment has been performed; further details on this process can be found in Hao et al., “Normally-off p-GaN / AlGaN / GaN high electron mobility transistors using hydrogen plasma treatment,” Appl. Phys. Lett., 109.152106 (2016)).

[0012] Therefore, none of the known solutions currently available can provide a reliable enhancement-mode high electron mobility transistor with optimal electrical performance. Utility Model Content

[0013] The purpose of this disclosure is to provide an enhancement-mode high electron mobility transistor to at least partially solve the aforementioned problems in the prior art.

[0014] One aspect of this disclosure provides an enhancement-mode high electron mobility transistor device, comprising: a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas; and a gate structure located on the top surface of the semiconductor body and including a functional layer and gate contacts in direct physical and electrical contact with the functional layer, wherein the gate structure can be biased to electrically control the two-dimensional electron gas, wherein the gate contacts are made of a conductive material layer, and the functional layer is made of a two-dimensional semiconductor material layer, and the functional layer includes a first doped portion having P-type conductivity on the top surface of the semiconductor body, and the functional layer is interposed between the semiconductor body and the gate contacts along a first axis.

[0015] According to one or more embodiments, the functional layer is formed of a two-dimensional semiconductor monolayer or a two-dimensional semiconductor multilayer, wherein the two-dimensional semiconductor multilayer includes a plurality of two-dimensional semiconductor monolayers overlapping each other along the first axis.

[0016] According to one or more embodiments, the two-dimensional semiconductor of the functional layer is one of the following: transition metal diols; phosphorous acid; antimony; arsenylene; tellurium; selenium; and 2D nitrides.

[0017] According to one or more embodiments, the semiconductor body is made of a semiconductor material layer and includes: a substrate; a channel layer; and a barrier layer having a bottom surface and a top surface opposite each other along the first axis, the bottom surface of the barrier layer facing the channel layer, and the top surface of the barrier layer forming the top surface of the semiconductor body, wherein a two-dimensional electron gas is configured to be generated at the interface between the channel layer and the barrier layer.

[0018] According to one or more embodiments, the high electron mobility transistor device further includes: a source contact and a drain contact, both made of a conductive material layer and spaced apart from each other on the top surface of the semiconductor body, and the source contact and the drain contact being spaced apart from the gate structure, wherein the functional layer is at least partially located between the source contact and the drain contact along a second axis orthogonal to the first axis, and wherein the gate contact is located on the functional layer between the source contact and the drain contact along the second axis.

[0019] According to one or more embodiments, the functional layer further includes a second doped portion having N-type conductivity on the top surface of the semiconductor body, the first doped portion extending between the second doped portions along the second axis.

[0020] The embodiments of this disclosure provide a normally-off high electron mobility transistor, which ensures low power consumption during use and simplifies its integration into electronic circuits during the design process. Attached Figure Description

[0021] To better understand this disclosure, preferred embodiments will now be described by way of non-limiting example only with reference to the accompanying drawings, in which:

[0022] Figure 1A - Figure 1D A lateral cross-sectional view of various high electron mobility transistors of known types is shown;

[0023] Figure 2 A cross-sectional view of a high electron mobility transistor according to one embodiment is shown;

[0024] Figure 3 A schematic perspective view of a high electron mobility transistor according to one embodiment is shown;

[0025] Figure 4 An illustration is shown according to an embodiment. Figure 2 A graph showing the electrical characteristics of a high electron mobility transistor;

[0026] Figure 5 An example is shown. Figure 2 Energy band diagram of a high electron mobility transistor;

[0027] Figure 6A - Figure 6I A cross-sectional view of the fabrication steps of a high electron mobility transistor according to one embodiment is shown; and

[0028] Figure 7A - Figure 7H An embodiment is shown. Figure 2 A cross-sectional view of the manufacturing steps of a high electron mobility transistor. Detailed Implementation

[0029] Specifically, the accompanying drawings are illustrated with reference to a three-axis Cartesian system defined by mutually orthogonal X-axis, Y-axis, and Z-axis.

[0030] In the following description, elements common to different embodiments are indicated by the same reference numerals.

[0031] Figure 2 A high electron mobility transistor (HMT) device 20 according to one embodiment is shown. Figure 2 It is a cross-sectional view of the high electron mobility transistor device 20 (i.e., on the XZ plane defined by the X and Z axes). Figure 2Elements for understanding this embodiment are shown. Although not shown, other elements or components may be present in the finished high electron mobility transistor device 20 without departing from the scope of this disclosure.

[0032] The high electron mobility transistor device 20 (hereinafter also simply referred to as high electron mobility transistor 20) includes a substrate 23 with a semiconductor material layer (e.g., silicon or silicon carbide, silicon carbide or sapphire) overlapping each other along the Z-axis; a first structural layer 25 (or the channel layer 25 of the high electron mobility transistor 20), particularly gallium nitride (GaN), for example by epitaxial growth on the substrate 23; and a second structural layer 27 (or the barrier layer 27 of the high electron mobility transistor 20), particularly aluminum gallium nitride (AlGaN), or more generally, a compound based on a ternary or quaternary alloy of gallium nitride, such as AlxGa1-xN, AlInGaN, InxGa1-xN, AlxIn1-xAl, for example by epitaxial growth on the channel layer 25.

[0033] In detail, the barrier layer 27 has a bottom surface 27a facing the channel layer 25 and a top surface 27b opposite to the bottom surface 27a relative to the Z-axis.

[0034] The channel layer 25 and the barrier layer 27 are formed in a manner known per se for generating a two-dimensional electron gas (two-dimensional electron gas, in Figure 2 The heterostructure is indicated by reference numeral 31 in the attached figure. Specifically, a two-dimensional electron gas 31 is formed at the interface between the channel layer 25 and the barrier layer 27, specifically at the bottom surface 27a of the barrier layer 27. In other words, charge carriers belonging to the two-dimensional electron gas can move freely in any direction in the XY plane (defined by the X and Y axes) at said interface, while they are confined along the Z-axis.

[0035] In a manner not shown in the figure, one or more additional buffer layers of known types may optionally be present between the substrate 23 and the channel layer 25, as needed.

[0036] For purely illustrative and non-limiting purposes, the channel layer 25 has a thickness along the Z-axis, for example, between about 1 μm and 5 μm, and includes approximately 10 μm of... 14 at / cm 3 and about 10 16 at / cm 3 The doping density between these values, the barrier layer 27 has a thickness (along the Z-axis) including, for example, between approximately 5 nm and 30 nm and less than approximately 10 nm. 17 at / cm 3 The doping density.

[0037] Optionally, the high electron mobility transistor 20 also includes a passivation layer extending on the top surface 27b of the barrier layer 27 and having the function of protecting the barrier layer 27 from oxidation. Figure 6I (shown as reference numeral 42 in the figure). The passivation layer 42 is made of a passivation material layer, such as Al2O3, and its thickness along the Z-axis includes, for example, between approximately 20 nm and 100 nm.

[0038] Substrate 23, channel layer 25, and barrier layer 27 form a semiconductor body 35 comprising the high electron mobility transistor 20 with the aforementioned heterostructure. The semiconductor body 35 has a top surface (therefore denoted by the same reference numerals hereinafter) formed by the top surface 27b of the barrier layer 27 and a bottom surface opposite the top surface 27b along axis Z, and... Figure 2 It is indicated by reference numeral 35a in the attached figure.

[0039] In detail, the high electron mobility transistor 20 optionally further includes source contacts 28 and drain contacts 29 of a conductive material layer (e.g., a metal, such as gold or platinum or a Ti / Al / Ni / Au metal multilayer, subjected to heat treatment at high temperatures (e.g., about 800°C)). The source contacts 28 and drain contacts 29 are physically decoupled from each other and extend on the top surface 27b of the barrier layer 27, making electrical contact with the barrier layer 27.

[0040] For example, source region 37 and drain region 38 (optionally) extend from top surface 27b toward bottom surface 27a into barrier layer 27. For example, source region 37 and drain region 38 extend along the Z-axis through barrier layer 27 (i.e., until reaching bottom surface 27a) and also partially extend into channel layer 25. Source region 37 and drain region 38 are spaced apart from each other through portions of barrier layer 27. Source contact 28 and drain contact 29 are perpendicularly overlapped (along the Z-axis) on source region 37 and drain region 38, respectively, and are electrically connected to the latter via, for example, ohmic contacts (not shown). In particular, source region 37 and drain region 38 have N-type conductivity and are formed, for example, by implanting dopant within barrier layer 27.

[0041] Furthermore, the high electron mobility transistor 20 includes a gate structure 32 that can be biased (e.g., by an external bias circuit) to electrically control a two-dimensional electron gas 31. The gate structure 32 extends on the top surface 27b of the barrier layer 27 and extends between (at a distance from) the source contact 28 and the drain contact 29. The gate structure 32 includes a functional layer (or 2D layer) 34 and gate contacts 33.

[0042] Specifically, the gate voltage V GThis can be applied to the gate structure 32 (specifically, to the gate contact 33) such that when it is below the gate threshold voltage (e.g., greater than about 1V and, for example, included between about 1V and about 2V), the two-dimensional electron gas 31 is not present in the region perpendicularly aligned (along the Z-axis) to the gate structure 32 at the interface between the channel layer 25 and the barrier layer 27, and when it is greater than or equal to the gate threshold voltage, the two-dimensional electron gas 31 is not present in the region perpendicularly aligned (along the Z-axis) to the gate structure 32 at the interface between the channel layer 25 and the barrier layer 27. The gate threshold voltage of the two-dimensional electron gas 31 exists in the region of the interface perpendicularly aligned to the gate structure 32 (also referred to as the two-dimensional electron gas activation region, and...). Figure 2 (Referring to 36 in the figure). The absence of a two-dimensional electron gas 31 in the two-dimensional electron gas activation region 36 arranged below the gate structure 32 is caused by the functional layer 34, which alters the energy of the electrons present therein, locally preventing the formation of a potential well and thus preventing the accumulation of electrons, as better described below.

[0043] The functional layer 34 extends on a portion of the top surface 27b of the barrier layer 27, particularly between the source contact 28 and the drain contact 29, so as not to make physical or electrical contact with the latter, and the gate contact 33 is made of a layer of conductive material (e.g., a metal such as gold or platinum) and makes physical and electrical contact with the functional layer 34.

[0044] Functional layer 34 is a two-dimensional semiconductor material layer, particularly a transition metal dichalcogenide, such as MoS2, MoSe2, MoTe2, WS2, or WSe2. Although transition metal dichalcogenides, particularly molybdenum disulfide MoS2 (the latter being used for illustrative purposes only), are considered below, other two-dimensional semiconductor material layers, such as Xenes (phosphine, antimonyne, arsenic, tellurene, selenene, etc.) and 2D nitrides (2D-GaN, 2D-InN, 2D-AlN), can be used similarly.

[0045] exist Figure 2 In the embodiments, the functional layer 34 has P-type conductivity, for example, a doping density of 10. 19 at / cm 3 Peace Treaty 10 20 at / cm 3 Between. For example, the functional layer 34 can be provided by doping with materials such as niobium (Nb) or zinc (Zn) or by plasma functionalization (e.g., oxygen plasma), as better described below.

[0046] Specifically, the functional layer 34 is formed of a single layer or a layered (or multi-layered) structure of transition metal dichalcogenides. In the case of a layered structure, the functional layer 34 comprises multiple layers (single layers) of transition metal dichalcogenides that overlap each other (i.e., each layer extends parallel to the XY plane and these layers overlap each other along the Z-axis); more specifically, the number of overlapping transition metal dichalcogenide single layers is less than or equal to the threshold number of layers (depending on the transition metal dichalcogenide used, and for example, five layers for MoS2) in order to ensure the enhancement mode behavior of the high electron mobility transistor 20.

[0047] According to an exemplary embodiment, the functional layer 34 of the high electron mobility transistor 20 is composed of a P-type conductivity and a doping density of N. A Equal to approximately 1.10 19 cm －3 The high electron mobility transistor 20 is formed by a single layer of MoS2, and the barrier layer 27 has a thickness between about 8 nm and about 12 nm (measured along the Z-axis, between the top surface 27b and the bottom surface 27a), and has an aluminum concentration between about 12% and about 18%. For example, considering an aluminum concentration of about 14% in the barrier layer 27: for a barrier layer thickness of about 8 nm, the functional layer 34 consists of one or two layers having N A >10 19 cm －3 The MoS2 is formed; for a barrier layer thickness of approximately 12 nm, the functional layer 34 consists of a single layer of N2. A >10 19 cm －3 MoS2 is formed, or it consists of two layers of N. A >10 20 cm －3 MoS2 is formed.

[0048] exist Figure 2 In this embodiment, the gate contact 33 extends on the functional layer 34, and both the functional layer 34 and the gate contact 33 extend along the X-axis between the source contact 28 and the drain contact 29 (at a distance from the latter). Specifically, the functional layer 34 is interposed along the Z-axis between the gate contact 33 and the barrier layer 27, particularly to physically separate the gate contact 33 and the barrier layer 27 from each other. In other words, the functional layer 34 has a first surface 34a and a second surface 34b opposite to each other along the Z-axis; the barrier layer 27 contacts the first surface 34a of the functional layer 34, and the gate contact 33 contacts the second surface 34b of the functional layer 34.

[0049] Figure 3 Different embodiments of the high electron mobility transistor 20 are shown in perspective view, which is similar to... Figure 2The high electron mobility transistor shown is an example where the gate contact 33 extends over a region of functional layer 34 (hereinafter referred to as the first region and indicated by reference numeral 34′ in the figure) that does not extend along the X-axis between the source contact 28 and the drain contact 29. In other words, functional layer 34 includes two first regions 34′ and a second region 34″ interposed along the Y-axis between the first regions 34′; the second region 34″ extends along the X-axis between the source contact 28 and the drain contact 29 (without direct physical and electrical contact with the latter), and the first region 34′ is not included along the X-axis between the source contact 28 and the drain contact 29.

[0050] In addition, such as Figure 6I As shown and better described below, the functional layer 34 may not have P-type conductivity throughout its entire extension. In this case, the functional layer 34 includes a first doped portion 40′ and two second doped portions 40″ extending along the X-axis on opposite sides of the first doped portion 40′; in other words, the first doped portion 40′ is included between and interposed between the second doped portions 40″ along the X-axis. In particular, the gate contact 33 extends only on the first doped portion 40′ (and therefore does not overlap perpendicularly along the Z-axis on the second doped portions 40″).

[0051] The first doped portion 40′ has P-type conductivity, for example, a doping density of approximately 10. 19 at / cm 3 With about 10 20 at / cm 3 Between, and the second doped portion 40″ has N-type conductivity, for example, a doping density of about 10. 15 at / cm 3 With about 10 17 at / cm 3 between.

[0052] In other words, the portion of the functional layer 34 aligned perpendicularly to the gate contact 33 along the Z-axis has P-type conductivity, while the portion of the functional layer 34 not aligned perpendicularly to the gate contact 33 along the Z-axis has N-type conductivity.

[0053] In other words, in Figure 2 and Figure 3 In one embodiment, the functional layer 34 of the high electron mobility transistor 20 is formed solely of the first doped portion 40' of the P-type, while... Figure 6I In one embodiment, it includes a first p-type doped portion 40′ and a second n-type doped portion 40″. Figure 6I In this case, the two-dimensional electron gas activation region 36 is aligned with the first doped portion 40′ along the Z-axis, that is, its extension in the XY plane is defined by the first doped portion 40′.

[0054] Figure 4 The transconductance I of the high electron mobility transistor 20 is shown for illustrative and non-limiting purposes only. DS -V GS An example, where I DS It is the drain current (measured between drain contact 29 and source contact 28), V GS It is the gate voltage (applied between gate contact 33 and source contact 28), and the gate current I of the high electron mobility transistor 20. GS The trend (measured between gate contact 33 and source contact 28) is that the gate voltage V GS The function. As can be seen, the high electron mobility transistor 20 for V GS ≤0V is in the off state, and for V GS >0V is in the ON state (in detail, it refers to V GS ≤0V has approximately 1.10 －11 I on the order of A DS And for V GS >0V has approximately 1.10 －4 I on the order of A DS , where I DS With varying drain voltage V applied between drain contact 29 and source contact 28 DS The value increases to V GS Values ​​greater than 0V, and for example in Figure 4 (V varies between approximately 0.1V and 3.1V). Furthermore, for example, V values ​​ranging from approximately -1V to 9V... GS Gate current I GS With approximately 1.10 －10 The order of magnitude of A.

[0055] Figure 5 It is shown in V GS At 0V, the energy band diagram (or structure) of the high electron mobility transistor 20 according to the latter exemplary embodiment. Specifically, the energy band diagram shows the energy of electrons present in the high electron mobility transistor 20 as a function of the thickness of the same high electron mobility transistor 20, which is measured along the Z-axis from the second surface 34b of the functional layer 34 toward the substrate 23 through the two-dimensional electron gas activation region 36. Specifically, Figure 5 The example shown refers to a high electron mobility transistor 20, which has a monolayer of MoS2 (with a band gap of approximately 1.9 eV, a thickness along the Z-axis of approximately 0.65 nm, and a band gap of approximately 1.10). 19 cm －3 dopant concentration N AThe aluminum concentration in the barrier layer 27 is approximately 14%, and the thickness along the Z-axis of the barrier layer 27 is approximately 12 nm. As described above, this high electron mobility transistor 20 is an enhancement-mode high electron mobility transistor because it operates at zero V. GS When the transistor is in the off state, and specifically at the interface between the barrier layer 27 and the channel layer 25, the energy of the electrons is greater than the Fermi level E of the high electron mobility transistor 20. F (that is, in V) GS At 0V, the two-dimensional electron gas 31 is not generated below the functional layer 34.

[0056] Figure 6A -6I illustrates the steps of an embodiment of the fabrication process for the high electron mobility transistor 20 in a cross-sectional view. Specifically, for illustrative and non-limiting purposes, refer to Figure 6I The high electron mobility transistor 20 shown in the illustration is used to describe the manufacturing process, wherein the functional layer 34 includes a first doped portion 40′ of P-type and a second doped portion 40″ of N-type.

[0057] refer to Figure 6A A substrate 23, such as silicon or silicon carbide (SiC), or sapphire (Al2O3) or others, is disposed with semiconductor material layers. Above the substrate 23, a channel layer 25, particularly gallium nitride (GaN), is formed continuously along the Z-axis in a manner known per se, for example by epitaxial growth on the substrate 23; and a barrier layer 27, particularly aluminum gallium nitride (AlGaN), or more generally, compounds based on ternary or quaternary alloys of gallium nitride, such as AlxGa1-xN, AlInGaN, InxGa1-xN, AlxIn1-xAl, for example by epitaxial growth on the channel layer 25. The channel layer 25 and the barrier layer 27 form a heterostructure in a manner known per se, wherein a two-dimensional electron gas 31 is formed. In a manner not shown in the figures, one or more buffer layers may be formed between the substrate 23 and the channel layer 25 in a manner known per se (e.g., epitaxial growth on the substrate 23 before forming the channel layer 25 on one or more buffer layers). As an example, the channel layer 23 has a thickness along the Z-axis, for example, between about 1 μm and 5 μm, and the barrier layer 27 has a thickness along the Z-axis, for example, between about 5 nm and 30 nm.

[0058] refer to Figure 6BA two-dimensional semiconductor layer 50, particularly a two-dimensional semiconductor layer 50 of transition metal dichalcogenides such as MoS2, MoSe2, MoTe2, WS2, or WSe2, is formed on the barrier layer 27 (i.e., on the top surface 27b, particularly to completely and uniformly cover the entire top surface 27b). Although transition metal dichalcogenides, particularly MoS2 (the latter being used for illustrative purposes only), are considered below, other two-dimensional semiconductor material layers, such as Xenes (phosphine, antimonyne, arsenene, tellurene, selenene) and 2D nitrides (2D-GaN, 2D-InN, 2D-AlN), can be similarly used. The two-dimensional semiconductor layer 50 is used to form the functional layer 34. An exemplary two-dimensional semiconductor layer 50 of MoS2 is formed on the barrier layer 27 by deposition and is inherently N-type conductive. In other words, the N-type conductivity of the two-dimensional semiconductor layer 50 is not intentionally obtained, but rather obtained as is known from the MoS2 deposition technique used. In detail, the formation of the two-dimensional semiconductor layer 50 on the barrier layer 27 is performed by deposition techniques such as chemical vapor deposition (CVD); more details of this can be found in the prior art paper "Vertical 2D / 3D Semiconductor Heterostructures Based on Epitaxial Molybdenum Disulfide and Gallium Nitride," ACS Nano 10, 3580-3588 (2016)) by Ruzmetov et al., molecular beam epitaxy (MBE) or pulsed laser deposition (PLD); further details of this can be found in the prior art paper "Influence of GaN / AlGaN / GaN(0001) and Si(100)substrates on structural properties of extremely thin MoS2 films grown by pulsed laser deposition," Appl. Surf. Sci. 395, 232–236 (2017)) by Chromik et al. More specifically, this deposition is performed without the addition of dopants, and therefore in an inherent manner. In an exemplary embodiment, the formation of the two-dimensional semiconductor layer 50 includes depositing a MoS2 layer (monolayer) on the barrier layer 27; however, other embodiments may include depositing multiple layers of MoS2 on the barrier layer 27, which overlap each other along the Z-axis.

[0059] refer to Figure 6CA two-dimensional semiconductor layer 50 is defined by a first etching (indicated by arrows and reference numeral 54 in the figure) to form a functional layer 34. Specifically, the first etching 54 is a plasma etching, particularly a chlorine-based plasma (further details in this regard are available in the prior art document “Controlled Plasma Thinning of Bulk MoS2 Flakes for Photodetector Fabrication,” ACS Omega 4, 19693–19704 (2019)). For example, the first etching 54 is of a layer-by-layer controlled type.

[0060] More specifically, the formation of the functional layer 34 from the two-dimensional semiconductor layer 50 is performed via a known photolithography step, followed by a first etching 54. Specifically, a first photoresist layer 52 is deposited on the two-dimensional semiconductor layer 50 using a known photolithography technique (given that the first etching 54 has a suitable thickness, for example, between 1 and 3 μm). The first photoresist layer 52 serves as a first mask and covers a first region 50′ of the two-dimensional semiconductor layer 50, leaving an exposed second region 50″ of the two-dimensional semiconductor layer 50, which is transverse to the first region 50′. The first region 50′ of the two-dimensional semiconductor layer 50 forms the functional layer 34, while the second region 50″ defines the area in which the source contact 28, the drain contact 29, and an optional partial passivation layer 42 will be fabricated. Therefore, the method continues with a first etching 54 to selectively remove the second region 50″ of the two-dimensional semiconductor layer 50, leaving the first region 50′ of the two-dimensional semiconductor layer 50, thereby forming the functional layer 34. The first photoresist layer 52 is then removed in a manner known per se, exposing the second surface 34b of the functional layer 34.

[0061] refer to Figure 6D Source region 37 and drain region 38 are formed in barrier layer 27 (optionally, in a manner known per se, not shown), and subsequently source contact 28 and drain contact 29 (optionally) are formed on source region 37 and drain region 38, respectively. Source region 37 and drain region 38 are formed, for example, by a photolithography step, which passes through a second photoresist layer 58 serving as a second mask, leaving an exposed area of ​​the top surface 27b of barrier layer 27 not covered by functional layer 34 (in... Figure 6D(Referring to 56 in the accompanying drawings), and then by implanting dopant (not shown) into the exposed region 56 on the top surface 27b of the barrier layer 27, followed by heat treatment (e.g., annealing) to promote the diffusion of the dopant. The second photoresist layer 56 is again used as a second mask to provide the source contact 28 and drain contact 29, so as to be perpendicularly aligned (along the Z-axis) to the source region 37 and drain region 38 respectively, and not in direct physical contact with the functional layer 34. For example, source contacts 28 and drain contacts 29 are formed by depositing a first metal layer (or source and drain metal layers) 60 (e.g., gold or platinum) using techniques such as sputtering, CVD, or MBE; the first metal layer 60 may also include a stack of metal layers (e.g., a first titanium layer to improve adhesion, and one or more gold or platinum layers overlapped thereon) on the exposed area 56 of the top surface 27b and on the second photoresist layer 56, and then by peeling off the second photoresist layer 56 to leave the portion of the first metal layer 60 forming the source contacts 28 and drain contacts 29. Otherwise, in the absence of source region 37 and drain region 38, different methods may include using a second photoresist layer 56 as a second mask to deposit a first metal layer 60 on the exposed area 56 of the top surface 27b and on the second photoresist layer 56, followed by a thermal process (in an inert gas, for example at a temperature of about 800°C), which results in the formation of source and drain contacts 28, 29 and the stripping of the second photoresist layer 56.

[0062] refer to Figure 6E A passivation layer 42 (optionally) is formed on the functional layer 34 and on a portion of the top surface 27b not covered by the functional layer 34, the source contact 28, or the drain contact 29. The passivation layer 42 protects the barrier layer 27 from oxidation and improves the electrical decoupling of the gate structure 32 from the source and gate contacts 28, 29. This occurs, for example, by depositing a passivation material layer (e.g., Al2O3). Specifically, a third photoresist layer (not shown) is formed on the source and drain contacts 28 and 29 to expose a portion of the top surface 27b of the functional layer 34 and the barrier layer 27 (in other words, the third photoresist layer has a shape complementary to the second photoresist layer 56), a passivation material layer is deposited on the third photoresist layer (e.g., by atomic layer deposition (ALD)), on the functional layer 34, and on the exposed portion of the top surface 27b of the barrier layer 27, and the passivation layer 42 is defined by stripping away the third photoresist layer.

[0063] Reference Figure 6F The first portion of the passivation layer 42 is removed and vertically overlapped (along the Z-axis) onto the region of the functional layer 34 to form the first portion 40′ of the functional layer 34 (hereinafter also referred to as the first region of the functional layer 34, and in...). Figure 6G(Seen with reference numeral 68′ in the figure). Specifically, this occurs by forming a gate photoresist layer 64 on the source and gate contacts 28, 29 and on the second region 42″ of the passivation layer 42, leaving the first region 42′ of the passivation layer 42 exposed, which vertically overlaps (along the Z-axis) on the first region 68′ of the functional layer 34. The second region 42″ of the passivation layer 42 has a shape complementary to the first region 42′ of the passivation layer 42, and thus extends on both the portion of the functional layer 34 for forming the second doped portion 40″ of the functional layer 34 and the portion of the functional layer 34 in direct contact with the barrier layer 27. After the gate photoresist layer 64 is formed, a second etching is performed on the first region 42′ of the passivation layer 42 exposed by the gate photoresist layer 64 (in detail, for example, by wet etching with NaOH or BOE, in...). Figure 6F (Indicated by arrows and reference numeral 66). The second etch 66 selectively removes a first portion of the passivation layer 42, thereby exposing the first region 68′ of the functional layer 34.

[0064] refer to Figure 6G The functional layer 34 is provided with a first p-type doped portion 40'. In other words, the functional layer 34 is doped at its first region 68' to have p-type conductivity where it is exposed to the gate photoresist layer 64. This is provided by exposing the first region 68' of the functional layer 34 (shown by an arrow in the figure and indicated by reference numeral 67) to plasma (doped plasma), specifically oxygen plasma, which allows for selective functionalization of the gate photoresist layer 64. In practice, the oxygen plasma chemically reacts with the MoS2 of the functional layer 34 in its first region 68' and alters its conductivity to p-type (e.g., doping density N). A Equal to approximately 1.10 19 cm －3 (This is a function of the time the functional layer 34 is exposed to oxygen plasma); specifically, the exposure to oxygen plasma occurs at low argon power and percentage, without etching the functional layer 34 but only allowing it to be doped. On the other hand, the gate photoresist layer 64 and the passivation layer 42 prevent the oxygen plasma from reacting with the second doped portion 40" of the functional layer 34, which therefore continues to have N-type conductivity. For example, at a power between about 50 W and about 200 W and at about 1.10 －3Plasma is generated at a pressure of mbar using a gas composition containing approximately 70-80% oxygen and 30-20% argon. Further details regarding the functionalization via oxygen plasma can be found in the following papers: F. Gianniazzo, G. Fisichella, G. Greco, S. Di Franco, I. Deretzis, A. La Magna, C. Bongiorno, G. Nicotra, C. Spinella, M. Scopelliti, B. Pignatro, S. Agnello, F. Roccaforte, “Ambipolar MoS2 Transistors by Nanoscale Tailoring of Schottky Barrier Using Oxygen Plasma Functionalization,” ACS Appl. Mater. Interfaces 9, 23164-23174 (2017) or in the paper J. Jadwiszczak, et al, “Plasma Treatment of Ultrathin Layered Semiconductors for Electronic Device Applications,” ACS Appl. Electron. Mater. 2021. DOI:10.1021 / acsaelm.0c00901.

[0065] Reference Figure 6HA gate contact 33, which together with the functional layer 34 defines the gate structure 32, is formed on a first doped portion 40' of the functional layer 34. Specifically, a second metal layer (or gate conductive layer) 70 is deposited using a gate photoresist layer 64 as a mask. The second metal layer 70 is a conductive material layer, such as a metal, like gold or platinum, and is formed using deposition techniques such as sputtering, CVD, or MBE. For example, the second metal layer 70 may comprise a stack of metal layers (e.g., a first titanium layer for improving adhesion and one or more gold or platinum layers overlapped thereon). More specifically, a first portion of the second metal layer 70 is formed on the gate photoresist layer 64, and a second portion of the second metal layer 70 is formed on the first doped portion 40' of the functional layer 34 (i.e., at the first region 68'). Subsequently, a stripping of the gate photoresist layer 64 is performed to remove the gate photoresist layer 64 and the first portion of the second metal layer 70 overlapped thereon, leaving the second portion of the gate photoresist layer 64 forming the gate contact 33. Because the gate photoresist layer 64 is used for both the P-type doping of the first doped portion 40′ of the functional layer 34 and the deposition for the gate contact 33, the gate contact 33 is automatically vertically aligned (along the Z-axis) with the first doped portion 40′ of the functional layer 34.

[0066] At the end of the stripping process of the gate photoresist layer 64, the obtained Figure 6I The high electron mobility transistor 20 is shown.

[0067] Other manufacturing steps of known types may be followed (e.g., forming other dielectrics, passivation layers, or metallization layers), and are not of interest for the purposes of this disclosure, and therefore are not described in detail herein.

[0068] Furthermore, although an embodiment in which the functional layer 34 includes a first doped portion 40′ of P-type and a second doped portion 40″ of N-type has been described, Figure 6A - Figure 6I The manufacturing process shown is applicable, but it can obviously also be applied in a similar manner to embodiments of high electron mobility transistors 20 in which the second doped portion 40″ of the N-type is absent. In this case, the first photoresist layer 52 covers only the portion of the two-dimensional semiconductor layer 50 used to form the P-type functional layer 34, and a reference is performed throughout the entire functional layer 34 (which is completely exposed by the passivation layer 42 and the gate photoresist layer 64). Figure 6G The doping steps are described.

[0069] Figure 7A - Figure 7H The steps of different embodiments of the fabrication process of the high electron mobility transistor 20 are illustrated in a cross-sectional view. Specifically, for illustrative and non-limiting purposes, reference is made to... Figure 2The high electron mobility transistor 20 shown in the illustration is used to describe the manufacturing process, wherein the functional layer 34 is fully P-type conductive.

[0070] refer to Figure 7A As previously referenced Figure 6A As described, a substrate 23 is arranged, and a channel layer 25 and a barrier layer 27 are continuously formed on the substrate 23 along the Z-axis, respectively.

[0071] refer to Figure 7B A two-dimensional semiconductor layer 50, particularly a two-dimensional semiconductor of a transition metal dichalcogenide such as MoS2, MoSe2, MoTe2, WS2, or WSe2, is formed on the barrier layer 27 (i.e., on the top surface 27b, particularly to completely and uniformly cover the entire top surface 27b). Although transition metal dichalcogenides, particularly MoS2 (the latter being used for illustrative purposes only), are considered below, other two-dimensional semiconductor material layers, such as Xenes (phosphine, antimonyne, arsenene, tellurene, selenene) and 2D nitrides (2D-GaN, 2D-InN, 2D-AlN), can be similarly used. The two-dimensional semiconductor layer 50 is used to form the functional layer 34. An exemplary embodiment of the two-dimensional semiconductor layer 50 of MoS2 is formed on the barrier layer 27 by deposition in the presence of an acceptor-type dopant (e.g., niobium or magnesium), thereby exhibiting P-type conductivity. In other words, the p-type conductivity of the two-dimensional semiconductor layer 50 is not inherently obtained, but is generated by the addition of acceptor dopant during the deposition of MoS2. Specifically, the formation of the two-dimensional semiconductor layer 50 on the barrier layer 27 is carried out by a deposition technique such as chemical vapor transport (CVT) in the presence of one or more acceptor dopant. For example, the chemical transport reaction is carried out in a tube furnace using vapor, which is released from sulfur (S) powder in a crucible heated to approximately 200°C and from a mixture of MoO3, Nb2O5 powder (Nb source), and NaCl (reaction promoter) in a crucible heated to approximately 800°C; the vapor is transported by a carrier gas (Ar) at a flow rate of approximately 100 sccm to a sample set at approximately 800°C for a duration of approximately 30 minutes to obtain the two-dimensional semiconductor layer 50 of MoS2: the Nb doping density N... A Equal to approximately 1.10 19 cm －3(Further details on this can be found in the paper by Li et al., “P-type Doping in Large-Area Monolayer MoS2 by Chemical Vapor Deposition,” ACS Appl. Mater. Interfaces 12, 6276-6282 (2020)). In an exemplary embodiment, the formation of the two-dimensional semiconductor layer 50 includes depositing a P-type MoS2 layer (monolayer) on the barrier layer 27; however, other embodiments may include depositing multiple P-type MoS2 layers on the barrier layer 27, which overlap each other along the Z-axis.

[0072] refer to Figure 7C A two-dimensional semiconductor layer 50 having P-type conductivity is defined by a first etching 54 (specifically, chlorine-based plasma etching) to form a functional layer 34, as referenced. Figure 6C Specifically, a first photoresist layer 52 is deposited on the two-dimensional semiconductor layer 50, and a first etching 54 is performed to selectively remove the second region 50″ of the two-dimensional semiconductor layer 50, leaving the first region 50′ of the two-dimensional semiconductor layer 50, thereby forming the functional layer 34. The first photoresist layer 52 is then removed.

[0073] refer to Figure 7D Source region 37 and drain region 38 are formed in barrier layer 27 (in a manner known per se and not shown), and subsequently source contact 28 and drain contact 29 are formed on source region 37 and drain region 38, respectively, as previously referenced. Figure 6D As stated above.

[0074] Reference Figure 7E A passivation layer 42 (optional) is formed on the functional layer 34 and on a portion of the top surface 27b not covered by the functional layer 34, the source contact 28, or the drain contact 29, as previously described. Figure 6E As stated above.

[0075] refer to Figure 7F As previously referenced Figure 6F The first portion of the passivation layer 42 is removed to expose a first region 68' of the functional layer 34. In this embodiment of the high electron mobility transistor 20, the first portion of the passivation layer 42 is vertically overlapped (along the Z-axis) on a portion of the P-type functional layer 34, over which the gate contact 33 extends; alternatively, and in a manner not shown, the first portion of the passivation layer 42 may be vertically overlapped (along the Z-axis) throughout the P-type functional layer 34 such that, when removed, the entire functional layer 34 is exposed and the gate contact 33 extends throughout the functional layer 34.

[0076] refer to Figure 7G And as previously referenced Figure 6H As described, the gate contact 33, which together with the functional layer 34 defines the gate structure 32, is formed on and exposed in a first region 68' of the functional layer 34. Thus, the gate contact 33 is formed on a portion of the P-type functional layer 34 (optionally and in a manner not shown, throughout the functional layer 34).

[0077] At the end of the stripping process of the gate photoresist layer 64, the obtained Figure 7H The high electron mobility transistor 20 is shown.

[0078] Other manufacturing steps of known types may be followed (e.g., forming other dielectrics, passivation layers, or metallization layers) and are not of interest for the purposes of this invention, therefore such other manufacturing steps are not described in detail herein.

[0079] An examination of the features of this disclosure made in accordance with this disclosure reveals its advantages.

[0080] Due to the p-type doped two-dimensional semiconductor (specifically, having a high doping concentration, e.g., greater than 10⁻⁶), 19 cm －3 The functional layer 34, where the high electron mobility transistor 20 operates in an enhanced manner, alters the electron energy band at the interface between the channel layer 25 and the barrier layer 27, resulting in an increase in the minimum value of the AlGaN conduction band relative to the Fermi level and preventing the formation of potential wells (such as...) at the AlGaN / GaN interface. Figure 5 (As shown). The end result is that even without a gate voltage V G In this case, the two-dimensional electron gas 31 below the functional layer 34 is turned off. Therefore, the high electron mobility transistor 20 is normally off, which ensures low power consumption during use and simplifies its integration into the electronic circuit during the design process.

[0081] Two-dimensional semiconductors such as MoS2 have a lattice height that corresponds to that of aluminum in barrier layer 27, and this allows for the growth of a functional layer 34 with high quality and electrical and mechanical properties on barrier layer 27.

[0082] In addition, refer to Figure 6I An embodiment of the high electron mobility transistor 20 has been shown to demonstrate that the presence of the second doped portion 40″ of the N-type of the functional layer 34 reduces the overdrive current of the high electron mobility transistor 20 and thus improves its reliability and electrical performance.

[0083] The fabrication process of the described high electron mobility transistor 20 is easy to perform and allows for the generation of a self-aligned gate structure 32.

[0084] Finally, it is clear that modifications and variations may be made to this disclosure as described and illustrated herein without departing from the scope of this disclosure as defined by the appended claims. For example, the different embodiments described may be combined with each other to provide further solutions.

[0085] The passivation layer 42 may be absent, therefore the manufacturing process may not include the reference layer. Figure 6E The steps described in 6F, 7E, and 7F. In this case, the gate photoresist layer 64 extends in direct contact with the top surface 27b of the barrier layer 27 and the functional layer 34.

[0086] Furthermore, in the absence of source region 37 and drain region 38, the barrier layer 27 may optionally be partially recessed at the source and drain contacts 28 and 29. In effect, the partial recess of the barrier layer 27 prior to the deposition of source and drain contacts 28 and 29 (and subsequent annealing) reduces the specific contact resistance.

[0087] In one embodiment, an enhancement-mode high electron mobility transistor device (20) includes a semiconductor body (35) having a top surface (27b) and including heterostructures (25, 27) configured to generate a two-dimensional electron gas (31). The high electron mobility transistor device includes a gate structure (32) extending on the top surface (27b) of the semiconductor body (35), which can be biased to electrically control the two-dimensional electron gas (31), and includes a functional layer (34) and gate contacts (33) in direct physical and electrical contact with each other. The gate contacts (33) are made of a conductive material layer, and the functional layer (34) is made of a two-dimensional semiconductor material layer and includes a first doped portion (40′) having P-type conductivity extending on the top surface (27b) of the semiconductor body (35) and positioned between the semiconductor body (35) and the gate contacts (33) along a first axis (Z).

[0088] The functional layer (34) can be formed by a two-dimensional semiconductor monolayer or by a two-dimensional semiconductor multilayer including multiple two-dimensional semiconductor monolayers overlapping each other along the first axis (Z).

[0089] The two-dimensional semiconductor of the functional layer (34) can be one of the following: transition metal dichalcogenide; phosphorene; antimonene; arsenite; tellurene; selenite; and 2D nitride.

[0090] The semiconductor body (35) may be a semiconductor material layer and may include a substrate (23), a channel layer (25), and a barrier layer (27) that overlap each other along a first axis (Z). The barrier layer has a bottom surface (27a) and a corresponding top surface (27b) that are opposite each other along the first axis (Z). The bottom surface (27a) of the barrier layer (27) faces the channel layer (25), and the top surface (27b) of the barrier layer (27) forms the top surface (27b) of the semiconductor body (35). A two-dimensional electron gas (31) may be configured to be generated at the interface between the channel layer (25) and the barrier layer (27).

[0091] The high electron mobility transistor device (20) may further include source contacts (28) and drain contacts (29), which are conductive material layers extending on the upper surface (27b) of the semiconductor body (35), spaced apart from each other and from the gate structure (32). A functional layer (34) extends at least partially between the source contacts (28) and drain contacts (29) along a second axis (X) orthogonal to the first axis (Z). A gate contact (33) extends on the functional layer (34) such that it is included between the source contacts (28) and drain contacts (29) along the second axis (X), or extends on a portion of the functional layer (34) such that it is not included between the source contacts (28) and drain contacts (29) along the second axis (X).

[0092] The functional layer (34) may also include a second doped portion (40″) having N-type conductivity and extending on the top surface (27b) of the semiconductor body (35), and a first doped portion (40′) extending between the second doped portions (40″) along a second axis (X).

[0093] In one embodiment, the fabrication process of the high electron mobility transistor device (20) in enhancement mode includes forming a semiconductor body (35) having a top surface (27b) and including a heterostructure (25, 27) configured to generate a two-dimensional electron gas (31). The process includes forming a gate structure (32) on the top surface (27b) of the semiconductor body (35), the gate structure (32) being biasable to electrically control the two-dimensional electron gas (31) and including a functional layer (34) and a gate contact (33) in direct physical and electrical contact with each other. The gate contact (33) is made of a conductive material layer, and the functional layer (34) is made of a two-dimensional semiconductor material layer and includes a first doped portion (40′) having P-type conductivity extending on the top surface (27b) of the semiconductor body (35) and positioned along a first axis (Z) between the semiconductor body (35) and the gate contact (33).

[0094] The step of forming the gate structure (32) may include forming a functional layer (34) on the top surface (27b) of the semiconductor body (35), the functional layer (34) having a first surface (34a) and a second surface (34b) opposite to each other along a first axis (Z), the first surface (34a) facing the semiconductor body (35). Forming the gate structure may include forming a gate photoresist layer (64) on the functional layer (34) that exposes a first region (68′) of the second surface (34b) of the functional layer (34). The first region (68′) of the second surface (34b) of the functional layer (34) is adapted to define a first doped portion (40′). Forming the gate structure may include forming a gate conductive layer (70) on the gate photoresist layer (64) and on the first region (68′) of the second surface (34b) of the functional layer (34). A first portion of the gate conductive layer (70) extends on the gate photoresist layer (64), and a second portion of the gate conductive layer (70) extends on the functional layer (34) at a first region (68′) of the second surface (34b). The process includes removing the gate photoresist layer (64) and the first portion of the gate conductive layer (70) by stripping. The second portion of the gate conductive layer (70) forms the gate contact (33).

[0095] The step of forming the functional layer (34) may include forming a two-dimensional semiconductor layer (50) having N-type conductivity by deposition on the top surface (27b) of a semiconductor body (35). The process includes forming a first photoresist layer (52) on the two-dimensional semiconductor layer (50) covering a first region (50′) of the two-dimensional semiconductor layer (50) and exposing a second region (50″) of the two-dimensional semiconductor layer (50) laterally to the first region (50′) of the two-dimensional semiconductor layer (50). The process includes selectively removing the second region (50″) of the two-dimensional semiconductor layer (50) by a plasma-based first etching (54). The first region (50′) of the two-dimensional semiconductor layer (50) is adapted to form the functional layer (34). The process includes removing the first photoresist layer (52) from the two-dimensional semiconductor layer (50). After forming the gate photoresist layer (64), the manufacturing process may further include the following steps: exposing a first region (68′) of the second surface (34b) of the functional layer (34) to a doping plasma through the gate photoresist layer (64), the doping plasma being configured to dope the two-dimensional semiconductor, thereby forming a first doped portion (40′) having P-type conductivity at the first region (68′) of the second surface (34b) of the functional layer (34).

[0096] The step of forming the functional layer (34) may include forming a two-dimensional semiconductor layer (50) of a doped two-dimensional semiconductor having P-type conductivity by deposition on the top surface (27b) of a semiconductor body (35) in the presence of one or more acceptor dopants. Forming the functional layer may include forming a first photoresist layer (52) on the two-dimensional semiconductor layer (50) covering a first region (50′) of the two-dimensional semiconductor layer (50) and exposing a second region (50″) of the two-dimensional semiconductor layer (50) laterally to the first region (50′) of the two-dimensional semiconductor layer (50). Forming the functional layer may include selectively removing the second region (50″) of the two-dimensional semiconductor layer (50) by a plasma-based first etching (54), the first region (50′) of the two-dimensional semiconductor layer (50) forming a first doped portion (40′) of the functional layer (34). Forming the functional layer may include removing the first photoresist layer (52) from the first region (50′) of the two-dimensional semiconductor layer (50).

[0097] The manufacturing process may also include the following steps: forming source contacts (28) and drain contacts (29) of a conductive material layer at a certain distance on the top surface (27b) of the semiconductor body (35), wherein the functional layer (34) extends between the source contacts (28) and the drain contacts (29) along a second axis (X) orthogonal to the first axis (Z).

[0098] The manufacturing process may further include forming a passivation layer (42) on the second surface (34b) of the functional layer (34) and on a region of the top surface (27b) of the semiconductor body (35) extending between the functional layer (34) and the source contact (28) and between the functional layer (34) and the drain contact (29). The process may include selectively removing the first region (42') of the passivation layer (42) by a second etching (66) after forming a gate photoresist layer (64) extending on the passivation layer (42) to expose a first region (42') of the passivation layer (42), thereby exposing a first region (68') of the second surface (34b) of the functional layer (34), wherein the first region (42') of the passivation layer (42) is on the first region (68') of the second surface (34b) of the functional layer (34).

[0099] One embodiment of this disclosure provides an enhancement-mode high electron mobility transistor and a manufacturing process thereof that overcomes the shortcomings of the prior art.

[0100] In one embodiment, an enhancement-mode high electron mobility transistor (HEMT) device includes a semiconductor body having a top surface and comprising a heterostructure configured to generate a two-dimensional electron gas (2D electron gas). The HEMT device includes a gate structure on the top surface of the semiconductor body. The gate structure includes a functional layer and gate contacts that are in direct physical and electrical contact with the functional layer. The gate structure is biasable to electrically control the 2D electron gas. The gate contacts are made of a conductive material layer, and the functional layer is made of a 2D semiconductor material layer and includes a first doped portion having P-type conductivity on the top surface of the semiconductor body, and the functional layer is interposed between the semiconductor body and the gate contacts along a first axis.

[0101] One aspect of this disclosure provides a method comprising: forming a heterostructure of an enhancement-mode high electron mobility transistor device, the heterostructure including a channel layer and a barrier layer on the channel layer; forming a functional layer of a gate structure of the high electron mobility transistor device on the barrier layer by depositing a two-dimensional semiconductor material layer on the barrier layer; forming a gate contact of the gate structure on the functional layer, wherein the functional layer has a first portion directly below the gate contact and a second portion not directly below the gate contact; and forming a source contact and a drain contact of the high electron mobility transistor device on the barrier layer, wherein the source contact and the drain contact are spaced apart from the functional layer.

[0102] According to one or more embodiments, the method includes: doping a first region of the functional layer with a first conductivity type; and doping a second region of the functional layer with a second conductivity type opposite to the first conductivity type.

[0103] According to one or more embodiments, forming the source and drain contacts includes: depositing a first photoresist layer on the functional layer and the barrier layer; exposing a portion of the barrier layer by patterning the photoresist; depositing a first conductive material layer on the exposed portion of the barrier layer and the photoresist; and defining the source and drain contacts from the first conductive material layer by performing a first stripping process on the first photoresist layer.

[0104] According to one or more embodiments, forming the gate contact includes: depositing a second photoresist layer on the functional layer and on the source and drain contacts; exposing a first region of the functional layer by patterning the second photoresist layer; depositing a second conductive material layer on the first region of the functional layer and on the source and drain contacts; and defining the gate contact from the second conductive material layer by performing a stripping process of the second photoresist layer.

[0105] According to one or more embodiments, the method includes depositing a passivation layer on a second region of the functional layer and on a barrier layer between the second region of the functional layer and the source contact.

[0106] According to one or more embodiments, forming the functional layer comprises depositing a single monolayer of transition metal diol.

[0107] According to one or more embodiments, the transition metal diol includes molybdenum.

[0108] According to one or more embodiments, forming the functional layer includes depositing multiple monolayers of transition metal diols.

[0109] Another aspect of this disclosure provides a manufacturing process for an enhancement-mode high electron mobility transistor device, the process comprising: forming a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas; and forming a gate structure on the top surface of the semiconductor body capable of being biased to electrically control the two-dimensional electron gas, the gate structure including a functional layer and gate contacts in direct physical and electrical contact with each other, wherein the gate contacts are made of a conductive material layer, and the functional layer is made of a two-dimensional semiconductor material layer, and the functional layer includes a first doped portion having P-type conductivity on the top surface of the semiconductor body, and the functional layer is interposed between the semiconductor body and the gate contacts along a first axis.

[0110] According to one or more embodiments, forming the gate structure includes: forming the functional layer on the top surface of the semiconductor body, the functional layer having a first surface and a second surface opposite to each other along a first axis, the first surface facing the semiconductor body; forming a gate photoresist layer on the functional layer, the gate photoresist layer exposing a first region of the second surface of the functional layer adapted to define the first doped portion; forming a gate conductive layer of a conductive material layer on the gate photoresist layer and on the first region of the second surface of the functional layer, wherein a first portion of the gate conductive layer is located on the gate photoresist layer, and a second portion of the gate conductive layer is located on the functional layer at the first region of the second surface; and removing the gate photoresist layer and the first portion of the gate conductive layer by stripping, the second portion of the gate conductive layer forming the gate contact.

[0111] According to one or more embodiments, forming the functional layer includes: forming a two-dimensional semiconductor layer having N-type conductivity by deposition on the top surface of the semiconductor body; forming a first photoresist layer covering a first region of the two-dimensional semiconductor layer on the two-dimensional semiconductor layer and exposing a second region of the two-dimensional semiconductor layer transverse to the first region of the two-dimensional semiconductor layer; selectively removing the second region of the two-dimensional semiconductor layer by etching based on a first plasma, wherein the first region of the two-dimensional semiconductor layer is adapted to form the functional layer; removing the first photoresist layer from the two-dimensional semiconductor layer; and forming a first doped portion having P-type conductivity at the first region of the second surface of the functional layer by exposing the first region of the second surface of the functional layer to a doping plasma through the gate photoresist layer, wherein the doping plasma is configured to dope the two-dimensional semiconductor.

[0112] According to one or more embodiments, forming the functional layer includes: forming a two-dimensional semiconductor layer of a doped two-dimensional semiconductor having P-type conductivity by depositing on the top surface of the semiconductor body in the presence of one or more acceptor-type dopants; forming a first photoresist layer on the two-dimensional semiconductor layer covering a first region of the two-dimensional semiconductor layer and exposing a second region of the two-dimensional semiconductor layer laterally to the first region of the two-dimensional semiconductor layer; selectively removing the second region of the two-dimensional semiconductor layer by etching based on a first plasma, wherein the first region of the two-dimensional semiconductor layer forms the first doped portion of the functional layer; and removing the first photoresist layer from the first region of the two-dimensional semiconductor layer.

[0113] According to one or more embodiments, the manufacturing process further includes forming source and drain contacts on the top surface of the semiconductor body at a distance from the functional layer, wherein the functional layer extends between the source and drain contacts along a second axis orthogonal to the first axis.

[0114] According to one or more embodiments, the manufacturing process further includes: forming a passivation layer of a passivation material layer on a region of the second surface of the functional layer and on a region of the top surface of the semiconductor body, the region of the top surface extending between the functional layer and the source contact and between the functional layer and the drain contact; and after the formation of the gate photoresist layer on the passivation layer to expose the first region of the passivation layer overlapping the first region of the second surface of the functional layer along the first axis, selectively removing the first region of the passivation layer by a second etching to expose the first region of the second surface of the functional layer.

[0115] The various embodiments described above can be combined to provide other embodiments. If desired, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide other embodiments.

[0116] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An enhancement-mode high electron mobility transistor device, characterized in that, include: A semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas; as well as A gate structure is located on the top surface of the semiconductor body and includes a functional layer and gate contacts that are in direct physical and electrical contact with the functional layer. The gate structure can be biased to electrically control the two-dimensional electron gas. The gate contacts are made of a conductive material layer, and the functional layer is made of a two-dimensional semiconductor material layer. The functional layer includes a first doped portion with P-type conductivity on the top surface of the semiconductor body, and the functional layer is interposed between the semiconductor body and the gate contacts along a first axis.

2. The high electron mobility transistor device according to claim 1, characterized in that, The functional layer is formed by a two-dimensional semiconductor monolayer or a two-dimensional semiconductor multilayer, wherein the two-dimensional semiconductor multilayer includes a plurality of two-dimensional semiconductor monolayers that overlap each other along the first axis.

3. The enhancement-mode high electron mobility transistor device according to claim 1, wherein the two-dimensional semiconductor of the functional layer is one of the following: transition metal diols; phosphorous acid; antimony; arsenylene; tellurium; selenium; and 2D nitrides.

4. The high electron mobility transistor device according to claim 1, characterized in that, The semiconductor body is made of layers of semiconductor material and includes layers that overlap each other along the first axis: Substrate; Channel layer; as well as A barrier layer having a bottom surface and a top surface opposite each other along the first axis, the bottom surface of the barrier layer facing the channel layer, and the top surface of the barrier layer forming the top surface of the semiconductor body, wherein a two-dimensional electron gas is configured to be generated at the interface between the channel layer and the barrier layer.

5. The high electron mobility transistor device according to claim 1, characterized in that, Also includes: The source and drain contacts are both made of a conductive material layer and are spaced apart from each other on the top surface of the semiconductor body, and are spaced apart from the gate structure. The functional layer is located at least partially between the source and drain contacts along a second axis orthogonal to the first axis, and the gate contact is located on the functional layer between the source and drain contacts along the second axis.

6. The high electron mobility transistor device according to claim 5, characterized in that, The functional layer further includes a second doped portion having N-type conductivity on the top surface of the semiconductor body, the first doped portion extending between the second doped portions along the second axis.

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