Heterojunction laminated cell with fission suede and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, in particular to a heterojunction laminated cell with a fission suede and a preparation method thereof, and the preparation method comprises the following steps: removing a spire after texturing, then attaching nano mask particles, carrying out texturing again to obtain a silicon wafer after suede fission, and carrying out cell preparation on the silicon wafer.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a heterojunction tandem solar cell with a fission textured surface and its preparation method. Background Art

[0002] Heterojunction (HJT) solar cells, or amorphous silicon thin-film heterojunction solar cells, are composed of two different semiconductor materials forming a heterojunction. They involve depositing an amorphous silicon thin film on crystalline silicon, combining the advantages of crystalline silicon and thin-film solar cells, offering high conversion efficiency, low processing temperature, high stability, low degradation rate, and bifacial power generation. Due to the presence of the amorphous silicon thin film, the requirements for the crystal interface state are extremely high, especially the textured surface of the silicon wafer. Currently, the textured surface prepared from monocrystalline silicon wafers is generally a pyramid structure. The characteristic of pyramid textured surfaces is the uniformity of the large pyramids. While reducing the size of the pyramid texture allows for greater light absorption, achieving both small and uniform pyramids is extremely difficult. Furthermore, sharp pyramid structures can generate microcracks or stress concentrations in subsequent processes, leading to structural damage. Additionally, since the heterojunction interface is directly located on the silicon wafer surface, the roughness of the textured surface affects the uniform deposition of the amorphous / microcrystalline silicon thin film, thus requiring optimization. In particular, when fabricating 2T tandem solar cells using heterojunction-stacked perovskite, the thickness of the perovskite layer is generally between 500-1000 nm. If the crystalline silicon textured surface at the heterojunction interface is sharp or the tower tip is too high, it will pierce the perovskite film, leading to a decrease in the performance of the tandem solar cell.

[0003] Therefore, in existing technologies, the use of traditional textured tops and uneven textured surfaces in batteries is not conducive to thin film deposition and coverage, and the preparation of multilayer interfaces is difficult. Summary of the Invention

[0004] The purpose of this invention is to provide a heterojunction tandem solar cell with fission texture and its preparation method, which solves the technical problems in the prior art where the traditional textured tower tip and uneven textured surface are not conducive to thin film deposition and coverage, and the preparation of the tandem interface is difficult.

[0005] This invention discloses a heterojunction tandem solar cell with a fission textured surface. The textured surface of the silicon wafer is provided with towers, the towers are without tower tips, the top surface of the towers consists of two planes, a first tower groove is provided between the two planes, and a second tower groove is provided between adjacent towers. Both sides of the silicon wafer of the solar cell are provided with an amorphous / microcrystalline thin film and a first transparent conductive layer. The front side of the silicon wafer is also provided with a nickel oxide hole transport layer, a perovskite layer, a C60 electron transport layer, a tin oxide buffer layer, and a second transparent conductive layer. After texturing, the tower tips are removed, and then nanomask particles are attached, and texturing is performed again to obtain a textured fission silicon wafer. The solar cell is fabricated on the silicon wafer.

[0006] Furthermore, the second transparent conductive layer is a TCO transparent conductive layer.

[0007] Furthermore, the first transparent conductive layer has a thickness of 10-20 nm on the N-side and a thickness of 80-100 nm on the P-side.

[0008] Furthermore, the thickness of the perovskite layer is 200nm-500nm.

[0009] Furthermore, the size of the tower surface is 200-700nm, the height of the tower surface is 200-700nm, the width of the plane is 10-100nm, the distance between the planes on the same tower is 10-50nm, and the depth of the first tower trench is 10-100nm.

[0010] A method for fabricating a heterojunction tandem solar cell with a fission-textured surface includes: texturing a silicon wafer, removing the peaks, attaching nanomask particles, and texturing again to obtain a silicon wafer with a fission-textured surface; and fabricating the solar cell on the silicon wafer. The method further includes step A, which involves removing the nanomask particles, repeatedly removing the peaks, attaching nanomask particles, and texturing again. Step A is repeated at least twice.

[0011] Furthermore, it also includes step A, which involves removing the nanomask particles and then repeatedly removing the top of the tower, attaching the nanomask particles, and then performing texturing again.

[0012] Furthermore, step A is repeated at least twice.

[0013] Furthermore, the concentration of the etching solution used in the texturing step decreases with the number of repetitions.

[0014] Furthermore, the etching solution is an etching solution obtained by combining a 3%-5% high-concentration alkaline etching solution and a texturing additive;

[0015] And / or etching solutions containing 3%-5% HF and 7%-9% HNO3;

[0016] and / or etching solutions containing 2%-4% KOH;

[0017] And / or a mixture containing 1%-3% HF and 5%-6% HNO3;

[0018] And / or etching solutions containing 1%-2% low-concentration alkaline etching solution and texturing additives.

[0019] Furthermore, the perovskite layer is applied using slot coating.

[0020] Furthermore, the nanomask particles are nano-polyimide adhesive particles.

[0021] Furthermore, the nanomask particles are removed by washing with a 10%-20% concentration ethanol solution in a sealed ultrasonic container at a temperature of 50-80°C for 60-120 seconds.

[0022] Furthermore, the nanomask particles are attached via laser transfer.

[0023] Furthermore, during the laser transfer process, the laser power is 10-15W, the transfer film thickness is 50-80µm, and the polyimide particles are 10-100nm. This ingeniously achieves a non-contact textured oriented mask, allowing for flexible adjustment of the mask area, mask size, and mask dimensions on the transfer film, which facilitates process upgrades and adjustments.

[0024] Furthermore, the nanomask particles are attached to areas that cannot be etched.

[0025] Furthermore, the attachment locations are velvet towers and velvet grooves.

[0026] Furthermore, the specific steps include:

[0027] S1. The silicon wafer is etched with a high concentration of alkaline to obtain the first textured surface;

[0028] S2. Remove the tip of the first velvet layer to obtain the second velvet layer;

[0029] S3. Attach nano-mask particles to the second textured surface;

[0030] S4. The second textured surface is etched with a medium concentration of alkali to obtain the third textured surface;

[0031] S5. Clean the nanomask particles on the second textured surface.

[0032] S6. Remove the third napped peak to obtain the fourth napped surface;

[0033] S7. Laser transfer nanomask particles are applied to the fourth textured surface to form a mask;

[0034] S8. The fourth textured tower platform is modified with a low-concentration alkaline mixture to form corrosion pits, thus obtaining the fifth textured surface;

[0035] S9. Clean the nanomask particles on the fifth textured surface, and then acid-wash, water-wash, and dry the modified silicon wafer to obtain the textured silicon wafer.

[0036] Furthermore, the first velvet surface is etched with a 3%-5% high-concentration alkaline etching solution and velvet additives for 400-800 seconds at a temperature of 60-80°C, resulting in a velvet height of 1-2 μm and a velvet width of 1-5 μm.

[0037] Traditional processes directly create small textured surfaces, which result in extremely unevenness. This invention first prepares large textured surfaces. The advantage of large textured surfaces is that there is no interference from small or micro textured surfaces. At this point, the large textured surfaces are evenly distributed on the silicon wafer. However, large textured surfaces have lower light absorption and sharper peaks. This step is to first form a uniform large textured surface to facilitate subsequent splitting from the large textured surface into small textured surfaces, thereby increasing light absorption.

[0038] Furthermore, the spire is modified with a low-concentration oxygen-rich mixed etching solution, and the height of the spire removal is 0.1um-0.3um.

[0039] Furthermore, the low-concentration oxygen-rich mixed etching solution is an etching solution containing 3%-5% HF and 7%-9% HNO3.

[0040] Furthermore, the etching time for removing the tower tip is 120-300s, the temperature is 25-35℃, and the height of the tower tip is removed by 0.1um-0.3um, forming a tower platform. At this point, a certain height difference of the textured surface is retained while the tower tip is removed, which is beneficial for light absorption and subsequent directional masking on the tower platform. The unmasked areas are etched with a medium-concentration alkaline etching solution.

[0041] Furthermore, the second textured surface is etched using a medium-concentration alkaline etching solution, which is an etching solution containing 2%-4% KOH, with an etching time of 200-400s and an etching temperature of 60-80℃.

[0042] Since the first textured surface, namely the large textured surface, and the second textured surface, namely the tower textured surface, have been formed, they are collectively referred to as the tower large textured surface. After the tower large textured surface is masked in step 3, it is etched into a small textured surface by setting a medium alkaline concentration of 2%-4% KOH for 200-400s and a temperature of 60-80℃, thereby realizing the process of transforming a uniform large textured surface into a uniform small textured surface.

[0043] Furthermore, the third textured tower tip is modified with a low-concentration oxygen-enriched mixture, which is a mixture containing 1%-3% HF and 5%-6% HNO3, and the tower tip height is reduced by 0.1µm-0.3µm.

[0044] Since the large textured surface of the tower is split into small textured surfaces, and the small textured surfaces have tower tips, the sharp pyramid structure will generate microcracks or stress concentrations in subsequent processes, resulting in damage to the battery structure and affecting film deposition. Therefore, the small textured surfaces after splitting are modified with tower tips again.

[0045] Furthermore, the fourth textured tower platform is etched using a 1%-2% medium-concentration alkaline etching solution and textured additives.

[0046] Compared with the prior art, the beneficial effects of the present invention are:

[0047] 1. This invention cleverly achieves non-contact textured surface orientation masking by using laser transfer nanomask particles. The mask area, mask size, and mask dimensions can be flexibly adjusted on the transfer film, which is beneficial for upgrading and debugging the textured surface process.

[0048] 2. A small and uniform textured surface on the heterojunction interface substrate was achieved, which improved the texture yield, increased light absorption, and facilitated further improvement in the conversion efficiency of heterojunction cells;

[0049] 3. It reduces the difficulty of preparing the interface of heterojunction stacked cells, solves the problem that textured tower tips are not conducive to thin film deposition and coverage, reduces coverage defects during thin film deposition, improves the quality of passivation layers, and improves product yield. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the suede fission process of the present invention.

[0052] Figure 2 This is a schematic diagram of the laser transfer nanomask particles of the present invention.

[0053] Figure 3 This is a schematic diagram showing the setting of adhesive dots for the transfer film of the present invention.

[0054] Figure 4 This is a schematic diagram of the heterojunction stacked battery with fission textured surface of the present invention.

[0055] In the above figures, the meanings of each mark are as follows: 1-first textured surface, 2-second textured surface, 3-nanomask particle, 4-third textured surface, 5-fourth textured surface, 6-fifth textured surface, 7-first tower trench, 8-second tower trench, 9-silicon wafer, 10-laser, 11-transfer film, 12-amorphous layer, 13-microcrystalline layer, 14-first transparent conductive layer, 15-nickel oxide hole transport layer, 16-perovskite layer, 17-C60 electron transport layer, 18-tin oxide buffer layer, 19-TCO transparent conductive layer, 20-electrode, 21-tower. DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them.

[0057] Example 1

[0058] This embodiment discloses a heterojunction tandem solar cell with a fission textured surface and its preparation method, including the following steps:

[0059] Step 1: Pre-clean the silicon wafer 9 to remove the surface damage layer and impurities, and then perform gettering;

[0060] Step 2: Remove PSG from the silicon wafer 9 after gettering to remove the surface phosphosilicate glass layer;

[0061] Step 3: Perform high-concentration alkaline etching on silicon wafer 9 to obtain the first textured surface 1;

[0062] Since traditional processes directly create small textured surfaces, they will be extremely uneven. This step uses a 5% high-concentration alkaline etching solution and texturing additives to etch large textured surfaces for 400 seconds at a temperature of 80°C. The height of the large textured surface is 1.5µm and the width is 3µm. At this point, the large textured surface is free from interference from small and micro textured surfaces. The large textured surface will be evenly distributed on the silicon wafer 9, which is beneficial for subsequent splitting from the large textured surface into small textured surfaces.

[0063] Step 4: Modify the tip of the first textured surface 1 using a low-concentration oxygen-enriched mixed etching solution, removing 0.3 μm of the tip to obtain the second textured surface 2;

[0064] Because the pyramid tip is not conducive to the uniform deposition of amorphous silicon / microcrystalline silicon thin films and perovskite thin films, and the tip size is small, excessive etching will reduce the overall pyramid height or even turn it into a flat surface, which is not conducive to light absorption. This step uses a specific low-concentration oxygen-rich mixed etching solution to etch a large area of ​​the pyramid tip: HF concentration 3%, HNO3 concentration 7%, time 150s, temperature 25℃, removing 0.3um of the pyramid tip height, forming the pyramid 21. At this point, a certain textured surface height difference is preserved while the pyramid tip is removed, which is beneficial for light absorption and subsequent directional masking on the pyramid 21. The unmasked areas are etched using a high-concentration alkaline etching solution.

[0065] Step 5: Use laser 10 to transfer nano-polyimide adhesive particles with a particle size of 20nm, and oriented them to adhere to the second velvet surface 2.

[0066] As HJT cell silicon wafers become increasingly thinner, traditional high-temperature oxygen-introducing masks or printing masks are used. The high-temperature process and printing pressure increase the wafer breakage rate. Furthermore, traditional masks lack directional properties, being full-surface masks. This step utilizes laser transfer of nano-polyimide particles, such as… Figure 2 and Figure 3As shown, the laser 10 has a power of 10W, the transfer film 11 has a thickness of 50µm, and the polyimide particles are 10nm. This ingeniously achieves a non-contact textured surface orientation mask. The mask area, mask size, and mask dimensions can be flexibly adjusted on the transfer film 11, which is beneficial for upgrading and debugging the textured surface process.

[0067] Step 6: Perform medium-concentration alkaline etching on the second textured surface 2 to obtain the third textured surface 4, with a textured surface height of 1µm and a textured surface width of 1µm;

[0068] Since the first textured surface 1, i.e. the large textured surface, and the second textured surface 2, i.e. the tower 21 textured surface, have been formed, they are collectively referred to as the tower 21 large textured surface. After the tower 21 large textured surface is masked in step 5, it is etched into a small textured surface by setting a medium alkali concentration of 4% KOH for 300 seconds and a temperature of 80℃, thereby realizing the process of transforming a uniform large textured surface into a uniform small textured surface.

[0069] Step 7: Clean the nano-polyimide particles on the second velvet surface 2 with an ethanol solution placed in an ultrasonic container;

[0070] The nano-polyimide adhesive particles used as a mask on the textured surface after fission are cleaned. Incomplete or inadequate cleaning will leave residue on the silicon wafer 9, resulting in poor appearance and the formation of new composite centers. This step involves cleaning the mask using a 20% ethanol solution in a sealed ultrasonic container at 50°C for 120 seconds.

[0071] Step 8: Modify the tip of the third textured surface 4 with a low-concentration oxygen-enriched mixture, remove 0.3 μm from the tip, and obtain the fourth textured surface 5;

[0072] Since the large textured surface of Tower 21 splits into smaller textured surfaces, and these smaller textured surfaces then have apexes, the sharp pyramidal structure can cause microcracks or stress concentrations in subsequent processes, leading to damage to the battery structure and affecting film deposition. Therefore, the smaller textured surfaces after splitting are modified again to remove the apexes. Because the apexes of the smaller textured surfaces are smaller than those of the larger textured surfaces, a low-concentration oxygen-enriched mixture of 3% HF and 5% HNO3 is used for modification, reducing the apex height by 0.3 μm.

[0073] Step 9: Laser transfer of nano-polyimide particles with a size of 10nm is performed on the fourth textured surface 5 to form a mask;

[0074] To further improve the light absorption of the small textured surface, since the top of the small textured surface is currently a tower 21, which is beneficial for thin film deposition but affects light absorption, the tower 21 small textured surface is micro-modified by masking with smaller nano-polyimide particles.

[0075] Step 10: Modify the fourth textured surface 5 tower 21 with a low-concentration alkaline mixture to form a 50nm first tower groove 7, and obtain the fifth textured surface 6;

[0076] This textured surface further develops into smaller textured surfaces on tower 21, thus preserving tower 21 for film deposition and coverage, while also allowing nanotextile textures to grow on it, increasing light absorption. When modifying the fourth textured surface 5, a 1% low-concentration alkaline etching solution and texturing additives are used for etching. Figure 1 The fifth velvet surface is shown in Figure 6.

[0077] Step 11: Clean the nano-polyimide particles on the fifth velvet surface 6 with an ethanol solution placed in an ultrasonic container;

[0078] Step 12: The modified silicon wafer 9 is acid-washed, water-washed, and dried to obtain the textured silicon wafer 9.

[0079] Step 13: PECVD deposition of amorphous / microcrystalline thin films on both sides of the prepared silicon wafer 9;

[0080] Step 14: The first transparent conductive layer 14 is deposited on both sides of the silicon wafer 9 using PVD or RPD, with 10nm deposited on the N-side and 100nm deposited on the P-side.

[0081] Step 15: Deposit nickel oxide on the front side of silicon wafer 9;

[0082] Step 16: A perovskite layer 16 with a thickness of 500nm is applied to the front side of silicon wafer 9 using a slit coating. In conventional processes, the thickness of the perovskite layer 16 deposited in this step is 1200nm. Due to the poor uniformity of the textured surface of the bottom cell prepared by traditional processes, the standard deviation of the textured surface height can reach more than 400nm. A thicker perovskite film is required for coverage to prevent leakage caused by incomplete pyramid coverage. However, excessive thickness will lead to light absorption saturation and increase the resistance loss caused by the useless layer. It will also cause photogenerated carriers to recombine before reaching electrode 20, reducing current output. Defects at the interface between perovskite and crystalline silicon will cause carrier recombination. Excessive thickness will introduce more bulk defects, exacerbating a series of problems such as recombination.

[0083] The bottom cell prepared by the method of the present invention has good uniformity of texture height, and the size and height difference of the texture can be controlled below 25nm. The thickness of the perovskite can be flexibly optimized and adjusted, which greatly improves the yield of perovskite / tandem cell film.

[0084] Step 17: After the perovskite layer 16 is completed, the C60 electron transport layer 17, the tin oxide buffer layer 18, the TCO transparent conductive layer 19, and the electrode 20 are grown sequentially on the front side of the silicon wafer 9, thereby completing the fabrication of the tandem solar cell.

[0085] Example 2

[0086] This example, as a preferred embodiment of the present invention, discloses a heterojunction tandem battery with fission texture and its preparation method. The only change from Example 1 is that the tip of the third texture 4 is modified with a low-concentration oxygen-rich mixture, and 0.2 μm is removed from the tip to obtain the fourth texture 5.

[0087] Example 3

[0088] This example, as a preferred embodiment of the present invention, discloses a heterojunction tandem battery with fission texture and its preparation method. The only change from Example 1 is that the fourth texture 5 tower 21 is modified with a 1.5% low-concentration alkaline mixture to form a 60nm first tower groove 7, thus obtaining the fifth texture 6.

[0089] Example 4

[0090] This example, as a preferred embodiment of the present invention, discloses a heterojunction tandem solar cell with fission texture and its preparation method. The only change from Example 1 is that a perovskite layer 16 with a thickness of 500 nm is applied to the front side of the silicon wafer 9.

[0091] Example 5

[0092] This example, as a preferred embodiment of the present invention, discloses a heterojunction tandem solar cell with fission texture and its preparation method. The only change from Example 1 is that a perovskite layer 16 with a thickness of 400 nm is applied to the front side of the silicon wafer 9.

[0093] Comparative Example 1

[0094] This example, as a comparative example of the present invention, discloses a heterojunction tandem solar cell with a fission-textured surface and its preparation method. The only change from Example 1 is that a conventional process is used to prepare the interface texture for the heterojunction tandem solar cell. The conventional process involves first performing initial polishing and cleaning on the silicon wafer, followed by texturing. The texturing time is 600 s, the texturing temperature is 75°C, and the alkali concentration is 1.5%, thus obtaining the textured surface. The conventional process achieves small or large textures by adjusting the texturing time or the concentration of the chemical solution, resulting in a relatively simple method and a small window for adjusting the texture uniformity. After the bottom cell is completed, a perovskite layer with a thickness of 600 nm is applied to the front side of the silicon wafer using a slot coating technique.

[0095] Comparative Example 2

[0096] This example, as a comparative example of the present invention, discloses a heterojunction tandem solar cell with a fission-textured surface and its preparation method. The only change from Example 1 is that a conventional process is used to prepare the interface texture for the heterojunction tandem solar cell. The conventional process involves first performing initial polishing and cleaning on the silicon wafer, followed by texturing. The texturing time is 500 s, the texturing temperature is 80°C, and the alkali concentration is 1.5%, thus obtaining the textured surface. The conventional process achieves small or large textures by adjusting the texturing time or the concentration of the chemical solution, resulting in a relatively simple method and a small window for adjusting the texture uniformity. After the bottom cell is completed, a perovskite layer with a thickness of 800 nm is applied to the front side of the silicon wafer using a slot coating technique.

[0097] Comparative Example 3

[0098] This example, as a comparative example of the present invention, discloses a heterojunction tandem solar cell with a fission textured surface and its fabrication method. The only change from Example 1 is that a conventional process is used without masking, or a silicon dioxide mask layer is formed on the silicon wafer at 800°C using oxygen. Because it is a high-temperature gas mask, the gas is dispersed and lacks directional masking, resulting in uneven textured surface fabrication after masking. After the bottom cell is completed, a perovskite layer with a thickness of 1200 nm is applied to the front side of the silicon wafer using a slot coating method.

[0099] Comparison of nap size, standard deviation, and nap yield between the embodiments and comparative examples using the method of the present invention:

[0100]

[0101] The data shows that the small velvet surface prepared by the method of the present invention has excellent uniformity, with a standard deviation of velvet surface size of 11.93-20.03 nm, while the standard deviation of velvet surface size of conventional methods reaches 254.98-321.73 nm. The height difference of the velvet surface prepared by the present invention can be controlled to below 20 nm, and the uniformity is better than that of conventional methods.

[0102] The standard deviation of the textured surface height of this invention is 13.52-24.66 nm, while the standard deviation of the textured surface height of conventional methods reaches 229.63-428.40 nm. The standard deviation of the textured surface height of this invention can be controlled below 25 nm, which is superior to conventional methods and is beneficial to the uniformity of subsequent processes for depositing amorphous / microcrystalline films, TCO and other films.

[0103] The nap yield of this invention is 617792.9-732004.6 mm², while the nap yield of conventional methods is 165450.7-194236.4 mm². 2 The yield was 507,996.29 mm higher on average than that of conventional methods. 2 The higher the fiber shearing rate, the better the light absorption, thereby improving the conversion efficiency of the solar cells.

[0104] Comparison of the coverage yield of perovskite thin films for heterojunction tandem solar cells prepared using the method of the present invention in the embodiments and comparative examples:

[0105] category The spire was exposed and pierced. Poor shape retention Overall yield Example 1 0％ 0％ 100％ Example 2 0％ 0％ 100％ Example 3 0％ 0％ 100％ Comparative Example 1 40％ 30％ 30％ Comparative Example 2 35％ 25％ 40％ Comparative Example 2 20％ 20％ 60％

[0106] Thanks to the textured fission process, a uniform, multi-tiered, nano-textured surface without sharp peaks is obtained, which reduces the difficulty of fabricating the interface of heterojunction tandem solar cells. This solves the problem that textured peaks are detrimental to thin film deposition and coverage, reduces coverage defects during thin film deposition, improves passivation layer quality, and increases product yield. Traditional processes, as shown in the comparative example, require significantly increasing the thickness of the perovskite layer to reduce the proportion of exposed peaks and poorly coated perovskite films. However, excessive thickness can lead to light absorption saturation and increased resistance loss due to useless layers; it can also cause recombination of photogenerated carriers before they reach the electrodes, reducing current output; and defects at the perovskite-silicon interface can lead to carrier recombination, with excessive thickness introducing more bulk defects and exacerbating recombination, among other problems.

[0107] Comparison of photoelectric conversion efficiency between heterojunction tandem solar cells prepared using the method of this invention and comparative examples:

[0108]

[0109]

[0110] The data shows that the heterojunction silicon bottom cell prepared using Examples 4 to 5 of this invention, followed by the deposition of a perovskite thin film, ultimately yielded a heterocrystalline silicon / perovskite tandem solar cell. This cell exhibited an efficiency 1.62% higher than that of the conventional process comparative examples 1-3, with both short-circuit current and fill factor exceeding those of the conventional process comparative examples. This indicates that the textured surface of the bottom cell prepared by the process of this invention reduces the difficulty of interface preparation for heterojunction tandem solar cells, solves the problem of textured surface tips hindering thin film deposition and coverage, reduces coverage defects during thin film deposition, improves the passivation layer quality, and thus enhances the conversion efficiency of the tandem solar cell.

[0111] The above are the embodiments listed in this example. However, this example is not limited to the optional embodiments described above. Those skilled in the art can arbitrarily combine the above methods to obtain other various embodiments. Anyone can derive other various forms of embodiments based on the inspiration of this example. The above specific embodiments should not be construed as limiting the scope of protection of this example. The scope of protection of this example should be determined by the claims, and the specification can be used to interpret the claims.

Claims

1. A heterojunction tandem battery with a fission textured surface, characterized in that: The silicon wafer (9) has a textured surface with a tower (21). The tower (21) has no top. The top surface of the tower (21) is two planes. A first tower groove (7) is provided between the two planes. A second tower groove (8) is provided between adjacent towers (21). The silicon wafer (9) of the battery has an amorphous / microcrystalline thin film and a first transparent conductive layer (14) on both the front and back. The front side of the silicon wafer (9) also has a nickel oxide hole transport layer (15), a perovskite layer (16), a C60 electron transport layer (17), a tin oxide buffer layer (18), and a second transparent conductive layer.

2. A heterojunction tandem battery with a fission textured surface according to claim 1, characterized in that: The second transparent conductive layer is a TCO transparent conductive layer (19).

3. A heterojunction tandem battery with a fission textured surface according to claim 1, characterized in that: The first transparent conductive layer has a thickness of 10-20 nm on the N-side and 80-100 nm on the P-side.

4. A heterojunction tandem battery with a fission textured surface according to claim 1, characterized in that: The thickness of the perovskite layer (16) is 200nm-500nm.

5. A method for preparing a heterojunction tandem solar cell with a fission textured surface according to any one of claims 1-4, characterized in that: After texturing the silicon wafer, the top of the wafer is removed, then nanomask particles are attached, and texturing is performed again to obtain a silicon wafer with textured surface fission. The silicon wafer is then used to fabricate a battery. The process also includes step A, which involves removing the nanomask particles, repeatedly removing the top of the wafer, attaching nanomask particles, and texturing again. Step A is repeated at least twice.

6. The method for preparing a heterojunction tandem solar cell with a fission textured surface according to claim 5, characterized in that: The nanomask particles are nano-polyimide adhesive particles.

7. The method for preparing a heterojunction tandem solar cell with a fission textured surface according to claim 5, characterized in that: The perovskite layer is applied using slot coating.

8. The method for preparing a heterojunction tandem solar cell with a fission textured surface according to claim 5, characterized in that: The nanomask particles are attached via laser transfer.

9. The method for preparing a heterojunction tandem solar cell with a fission textured surface according to claim 8, characterized in that: During the laser transfer process, the laser power is 10-15W, the transfer film thickness is 50-80um, and the polyimide particles are 10-100nm.

10. The method for preparing a heterojunction tandem solar cell with a fission textured surface according to claim 5, characterized in that: The nanomask particles are removed by washing with a 10%-20% concentration ethanol solution in a sealed ultrasonic container at a temperature of 50-80℃ for 60-120 seconds.

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