Multilayer ceramic capacitor

Abstract

Provided is a laminated ceramic capacitor capable of suppressing the occurrence of cracks occurring inside a laminated body due to electrostriction when a high voltage is applied. The laminated ceramic capacitor according to the present invention comprises: a laminated body including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the dielectric layer includes a first main surface and a second main surface facing each other in a height direction, which is a stacking direction of the plurality of dielectric layers, a first side surface and a second side surface facing each other in a width direction orthogonal to the height direction, and a first end surface and a second end surface facing each other in a length direction orthogonal to the height direction and the width direction. The inner layer part is formed by alternately stacking dielectric layers and internal electrode layers, and the outer layer part is configured to sandwich the inner layer part from the first main surface side and the second main surface side; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface. The inner layer portion is configured from an inner dielectric layer among the plurality of dielectric layers disposed in the inner layer portion, and the inner dielectric layer includes a void. The inner dielectric layer includes a longitudinal direction center portion-side dielectric layer disposed in a region of a center portion in the longitudinal direction of the inner layer portion, and a longitudinal direction end portion-side dielectric layer disposed in a region of an end portion in the longitudinal direction of the inner layer portion. The amount of voids contained in the longitudinal-direction end-side dielectric layer is less than the amount of voids contained in the longitudinal-direction center-side dielectric layer.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] Conventional multilayer ceramic capacitors consist of a capacitor body made of a sintered ceramic body containing a dielectric such as barium titanate. Inside this capacitor body, internal electrodes containing noble metal materials such as Ag or Ag-Pd alloys or base metal materials such as Ni are arranged to alternately extend to one end face and the other end face, separated by ceramic layers (dielectric layers). Furthermore, internal electrodes at one potential are electrically connected to external electrodes, and internal electrodes at another potential are electrically connected to external electrodes (see Patent Document 1).

[0003] Regarding the multilayer ceramic capacitor described in Patent Document 1, in a multilayer ceramic capacitor in which a metal material is used as the internal electrode and the external electrode comprises multiple metal components and a glass component containing a metal that is the same as or can be alloyed with the metal material, the feature is that the external electrode is bonded to the wiring substrate via a conductive resin adhesive, and the area occupancy (porosity) of the metal component relative to the cross-sectional area of ​​the external electrode is 60-95%. Therefore, this multilayer ceramic capacitor can be mounted on the wiring substrate inexpensively and with high reliability without the use of solder.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2001-237137 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] However, in a multilayer ceramic capacitor with a typical structure like that in Patent Document 1, electrostriction occurs when a voltage is applied. The stress caused by this electrostriction concentrates at the effective ends in the length and width directions, and at half the height of the multilayer ceramic capacitor. When a high voltage is applied, cracks originate from these stress concentration points. While cracks caused by electrostriction are difficult to sort through screening, they pose a risk of becoming a problem in the market because they lead to a deterioration in high-temperature load reliability and moisture resistance.

[0009] Therefore, some methods exist to reduce cracks caused by electrostriction. Setting the applied voltage during screening to prevent electrostriction from occurring is a representative countermeasure. However, when the voltage that induces electrostriction is low, there is a problem that the voltage required for screening cannot be applied, resulting in a decrease in screening effectiveness.

[0010] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor capable of suppressing the generation of cracks inside the multilayer caused by electrostriction when a high voltage is applied.

[0011] Technical solutions for solving the problem

[0012] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including multiple stacked dielectric layers and multiple stacked internal electrode layers, and including a first main surface and a second main surface opposite each other in the height direction which is the stacking direction of the multiple dielectric layers, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height direction and the width direction, and including an inner layer portion formed by alternating stacking of dielectric layers and internal electrode layers, and an inner layer portion disposed between the first main surface side and the second main surface side. The inner layer comprises an outer layer, a first external electrode disposed on a first end face, and a second external electrode disposed on a second end face, wherein the inner layer is composed of an inner dielectric layer among a plurality of dielectric layers disposed in the inner layer, the inner dielectric layer containing voids, the inner dielectric layer having a length-direction central-side dielectric layer disposed in a region of the central portion in the length direction of the inner layer, and a length-direction end-side dielectric layer disposed in a region of the end portion in the length direction of the inner layer, the amount of voids contained in the length-direction end-side dielectric layer being less than the amount of voids in the length-direction central-side dielectric layer.

[0013] If voids exist in the dielectric layer, the mechanical strength is lower compared to areas where the dielectric layer is filled with ceramic. Therefore, if voids exist at locations where electrostrictive stress is concentrated, electrostrictive cracks can originate in the dielectric layer starting from these voids. Electrostriction tends to occur at the longitudinal ends of the dielectric layer located within the inner layer of the laminate. According to the laminated ceramic capacitor of the present invention, by reducing the amount of voids near the longitudinal ends of the dielectric layer located within the inner layer of the laminate, which is a location of electrostrictive stress concentration, compared to the central portion along the longitudinal direction, the generation of electrostrictive cracks can be reduced. Furthermore, by reducing the amount of voids in the dielectric layer at the longitudinal ends, the sinterability of the ceramic is improved, the shrinkage rate at the longitudinal ends is increased, thereby increasing the exposure of the inner electrode layer and improving contact with the outer electrodes.

[0014] Invention Effects

[0015] According to the present invention, a multilayer ceramic capacitor capable of suppressing the generation of cracks occurring inside the multilayer body due to electrostriction caused by the application of high voltage can be provided.

[0016] The above-mentioned objects, other objects, features, and advantages of the present invention will become clearer from the following detailed description of specific embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention.

[0018] Figure 2 yes Figure 1 A sectional view at line II-II.

[0019] Figure 3 yes Figure 1 A cross-sectional view at line III-III.

[0020] Figure 4 (a) is in Figure 1 A schematic cross-sectional view of the internal dielectric layer is shown at line II-II, and (b) is at... Figure 1 A schematic cross-sectional view of the internal dielectric layer is shown at line III-III.

[0021] Figure 5 (a) illustrates a configuration in which the opposing electrode portion of the internal electrode layer of a multilayer ceramic capacitor according to an embodiment of the present invention is divided into two parts. Figure 1 (b) is a cross-sectional view at line III-III, showing the structure in which the internal electrode layer of the multilayer ceramic capacitor of the present invention is divided into three opposing electrodes. Figure 1 The cross-sectional view at line III-III, (c) shows the structure of the internal electrode layer of the multilayer ceramic capacitor of the present invention, which is divided into four opposing electrodes. Figure 1 A cross-sectional view at line III-III. Detailed Implementation

[0022] 1. Multilayer ceramic capacitor

[0023] The multilayer ceramic capacitor according to embodiments of the present invention will be described.

[0024] Figure 1 This is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 yes Figure 1 A sectional view at line II-II. Figure 3 yes Figure 1 A cross-sectional view at line III-III. Figure 4 (a) is in Figure 1 A schematic cross-sectional view of the internal dielectric layer is shown at line II-II. Figure 4 (b) is in Figure 1 A schematic cross-sectional view of the internal dielectric layer is shown at line III-III.

[0025] like Figures 1 to 3As shown, the multilayer ceramic capacitor 10 includes a cuboid multilayer 12 and external electrodes 30 disposed at both ends of the multilayer 12.

[0026] The laminate 12 has multiple dielectric layers 14 stacked on top of each other, and multiple internal electrode layers 20 stacked on the dielectric layers 14. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b facing each other in the height direction x, a first side surface 12c and a second side surface 12d facing each other in the width direction y, which is orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f facing each other in the length direction z, which is orthogonal to both the height direction x and the width direction y. In this laminate 12, the corners and edges are rounded.

[0027] Furthermore, the term "corner" refers to the portion where three adjacent faces of the laminate 12 intersect, and the term "edge" refers to the portion where two adjacent faces of the laminate 12 intersect. Additionally, the term "cubic-pole shape" refers to the entire component having a first main face 12a and a second main face 12b, a first side face 12c and a second side face 12d, and a first end face 12e and a second end face 12f. Furthermore, some or all of the first main face 12a and the second main face 12b, the first side face 12c and the second side face 12d, and the first end face 12e and the second end face 12f may have irregularities or protrusions. The dielectric layer 14 and the internal electrode layer 20 are laminated in the height direction x.

[0028] like Figure 2 as well as Figure 3 As shown, the laminate 12 has an inner layer 16 formed by alternating layers of dielectric layers 14 and internal electrode layers 20 along the height direction x connecting the first main surface 12a and the second main surface 12b, a first outer layer 18a formed by a plurality of dielectric layers 14 disposed between the internal electrode layer 20 located on the side closest to the first main surface 12a and the first main surface 12a, and a second outer layer 18b formed by a plurality of dielectric layers 14 disposed between the internal electrode layer 20 located on the side closest to the second main surface 12b and the second main surface 12b.

[0029] The inner layer 16 is composed of multiple inner dielectric layers 14a among multiple dielectric layers 14. That is, the inner layer 16 is configured such that multiple inner electrode layers 20 are opposed to each other across the inner dielectric layers 14a. There are voids inside the inner dielectric layers 14a.

[0030] In addition, if Figure 4As shown in (a), the inner dielectric layer 14a further includes a longitudinal central-side dielectric layer 14a1 disposed in a region at the center of the inner layer portion 16 in the longitudinal direction z, and a longitudinal end-side dielectric layer 14a2 disposed in a region at the end of the inner layer portion 16 in the longitudinal direction z. The amount of voids contained in the longitudinal end-side dielectric layer 14a2 is preferably less than the amount of voids contained in the longitudinal central-side dielectric layer 14a1. Furthermore, in Figure 4 In (a), the illustration of the internal electrode layer 20 is omitted.

[0031] The difference between the area occupancy rate PCL of the voids in the LT cross-section of the dielectric layer 14a1 on the central side of the length direction and the area occupancy rate PEL of the voids in the LT cross-section of the dielectric layer 14a2 on the end side of the length direction is preferably 2.0% or more and 8.0% or less.

[0032] The region LA, in which the amount of voids in the end-side dielectric layer 14a2 is less than the amount of voids in the center-side dielectric layer 14a1, is a region disposed inside the inner layer 16 in the length direction z, starting from both ends of the inner layer 16. The dimension l1 of the length direction z of the region LA, in which the amount of voids in the end-side dielectric layer 14a2 is less than the amount of voids in the center-side dielectric layer 14a1, is preferably 10% or less relative to the dimension l0 of the inner layer 16 in the length direction z.

[0033] In addition, if Figure 4 As shown in (b), the inner dielectric layer 14a has a width-direction central-side dielectric layer 14a3 disposed in the central portion of the inner layer portion 16 in the width direction y, and a width-direction end-side dielectric layer 14a4 disposed in the end portions of the inner layer portion 16 in the width direction y. The amount of voids contained in the width-direction end-side dielectric layer 14a4 is less than the amount of voids contained in the width-direction central-side dielectric layer 14a3. Furthermore, in Figure 4 In (b), the illustration of the internal electrode layer 20 is omitted.

[0034] The difference between the area occupancy (PCW) of the voids in the WT cross-section of the central dielectric layer 14a3 in the width direction and the area occupancy (PEW) of the voids in the WT cross-section of the end dielectric layer 14a4 in the width direction is preferably 0.5% or more and 8.0% or less.

[0035] The region WA, in which the amount of voids in the end-side dielectric layer 14a4 in the width direction is less than the amount of voids in the center-side dielectric layer 14a3 in the width direction, is disposed inside the inner layer 16 in the width direction y, starting from both ends of the inner layer 16. The dimension w1 of the width direction y of the region WA, in which the amount of voids in the end-side dielectric layer 14a4 in the width direction is less than the amount of voids in the center-side dielectric layer 14a3 in the width direction, relative to the dimension w0 of the inner layer 16 in the width direction y, is preferably 15% or less.

[0036] In addition, the voids are measured using the following method.

[0037] A cross-sectional image of the laminate 12 was obtained using a scanning electron microscope (SEM), and the ceramic filling and void portions were binarized. Furthermore, the ratio of the area occupied by the void portions to the area of ​​the entire binarized image was set as the porosity.

[0038] The first outer layer 18a is located on the first main surface 12a side of the laminate 12, and is an assembly of multiple dielectric layers 14, i.e. multiple outer dielectric layers 14b, located between the first main surface 12a and the inner electrode layer 20 closest to the first main surface 12a.

[0039] The second outer layer 18b is located on the second main surface 12b side of the laminate 12, and is an assembly of multiple dielectric layers 14, i.e. multiple outer dielectric layers 14b, located between the second main surface 12b and the inner electrode layer 20 closest to the second main surface 12b.

[0040] The area sandwiched between the first outer layer 18a and the second outer layer 18b is the inner layer 16.

[0041] The dimensions of the laminate 12 are not particularly limited, but the dimension in the length direction z is preferably 0.95 mm or more and 3.1 mm or less, the dimension in the width direction y is preferably 0.49 mm or more and 2.47 mm or less, and the dimension in the height direction x is preferably 0.49 mm or more and 2.47 mm or less.

[0042] The dielectric layer 14 can be formed of a dielectric material, for example. As the dielectric material, a dielectric ceramic containing a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. When the above-mentioned dielectric material is used as the main component, depending on the desired characteristics of the laminate 12, for example, a material containing a minor component such as a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound, in a smaller amount than the main component, can also be used.

[0043] The thickness of the dielectric layer 14 after firing is preferably 0.5 μm or more and 10 μm or less.

[0044] The number of stacked dielectric layers 14 is preferably 50 or more and 1000 or less.

[0045] The first internal electrode layer 20a is disposed on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode layer 20a has a first opposing electrode portion 22a opposite to the second internal electrode layer 20b, and a first lead-out electrode portion 24a located at one end of the first internal electrode layer 20a and extending from the first opposing electrode portion 22a to the first end face 12e of the laminate 12. The end of the first lead-out electrode portion 24a extends to the surface of the first end face 12e and is exposed from the laminate 12. That is, the end of the first lead-out electrode portion 24a is not exposed on the first main surface 12a, the second main surface 12b, the second end face 12f, the first side face 12c, and the second side face 12d. In detail, the end of the first internal electrode layer 20a is slightly recessed from the second end face 12f.

[0046] The shape of the first opposing electrode portion 22a of the first internal electrode layer 20a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion in plan view may be rounded, or the corner portion may be formed obliquely in plan view (conical). Alternatively, it may be obliquely conical in plan view depending on the orientation.

[0047] The shape of the first lead-out electrode portion 24a of the first internal electrode layer 20a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion in plan view may be rounded, or the corner portion may be formed obliquely in plan view (conical). Alternatively, it may be obliquely conical in plan view depending on the orientation.

[0048] The width of the first opposing electrode portion 22a of the first internal electrode layer 20a and the width of the first lead-out electrode portion 24a of the first internal electrode layer 20a can be formed with the same width, or one of them can be formed with a narrower width.

[0049] The second internal electrode layer 20b is disposed on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode layer 20b has a second opposing electrode portion 22b opposite to the first internal electrode layer 20a, and a second lead-out electrode portion 24b located at one end of the second internal electrode layer 20b and extending from the second opposing electrode portion 22b to the second end face 12f of the laminate 12. The end of the second lead-out electrode portion 24b extends to the surface of the second end face 12f and is exposed from the laminate 12. That is, the end of the first lead-out electrode portion 24a is not exposed on the first main face 12a and the second main face 12b, the first end face 12e and the first side face 12c and the second side face 12d. In detail, the end of the second internal electrode layer 20b is slightly recessed from the first end face 12e.

[0050] The shape of the second opposing electrode portion 22b of the second inner electrode layer 20b is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion in plan view can be rounded, or the corner portion can be formed obliquely in plan view (conical). Alternatively, it can be obliquely conical in plan view depending on the orientation.

[0051] The shape of the second lead-out electrode portion 24b of the second inner electrode layer 20b is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion in plan view can be rounded, or the corner portion can be formed obliquely in plan view (conical). Alternatively, it can be obliquely conical in plan view depending on the orientation.

[0052] The width of the second opposing electrode portion 22b of the second internal electrode layer 20b and the width of the second lead-out electrode portion 24b of the second internal electrode layer 20b can be formed with the same width, or one of them can be formed with a narrower width.

[0053] The laminate 12 includes a side portion (hereinafter referred to as "W gap") 26a formed between one end of the first counter electrode portion 22a and the second counter electrode portion 22b in the width direction y and the first side surface 12c, and between the other end of the first counter electrode portion 22a and the second counter electrode portion 22b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes an end portion (hereinafter referred to as "L gap") 26b formed between the end of the first inner electrode layer 20a opposite to the first lead-out electrode portion 24a and the second end surface 12f, and between the end of the second inner electrode layer 20b opposite to the second lead-out electrode portion 24b and the first end surface 12e.

[0054] The internal electrode layer 20 can be made of a suitable conductive material, such as a metal like Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. The internal electrode layer 20 may also contain dielectric particles with the same composition as the ceramic contained in the dielectric layer 14.

[0055] The thickness of the internal electrode layer 20 is preferably 0.2 μm or more and 2.0 μm or less.

[0056] Furthermore, the total number of the first internal electrode layer 20a and the second internal electrode layer 20b is preferably 50 or more and 1,000 or less.

[0057] In addition, if Figure 5 As shown, Figure 1The stacked body 12 shown can also be configured such that, in addition to the first internal electrode layer 20a and the second internal electrode layer 20b, a floating internal electrode layer 20c is provided that is not led out to either the first end face 12e or the second end face 12f, thereby dividing the opposing electrode portion 22 into multiple parts by the floating internal electrode layer 20c. For example, Figure 5 The bisection structure shown in (a) Figure 5 The triplet structure shown in (b) Figure 5 The four-cell structure shown in (c) can, of course, be a structure with more than four cells. By dividing the opposing electrode section 22 into multiple components, multiple capacitor components are formed between the opposing first inner electrode layer 20a, second inner electrode layer 20b, and floating inner electrode layer 20c, forming a structure in which these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is lower, enabling a higher withstand voltage for the multilayer ceramic capacitor 10.

[0058] Furthermore, the floating internal electrode layer 20c, like the first internal electrode layer 20a and the second internal electrode layer 20b, can be made of a suitable conductive material, such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0059] like Figures 1 to 3 As shown, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0060] The external electrode 30 includes a base electrode layer 32 and a plating layer 34 disposed on the surface of the base electrode layer 32, the base electrode layer 32 comprising a metallic component and glass.

[0061] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0062] The first external electrode 30a is connected to the first internal electrode layer 20a and is disposed at least on the surface of the first end face 12e. Furthermore, the first external electrode 30a extends from the first end face 12e of the laminate 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode layer 20a.

[0063] The second external electrode 30b is connected to the second internal electrode layer 20b and is disposed at least on the surface of the second end face 12f. Furthermore, the second external electrode 30b extends from the second end face 12f of the laminate 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode layer 20b.

[0064] Within the laminate 12, an electrostatic capacitor is formed by the first opposing electrode portion 22a of the first inner electrode layer 20a and the second opposing electrode portion 22b of the second inner electrode layer 20b being opposed to each other across the dielectric layer 14. Therefore, an electrostatic capacitor can be obtained between the first outer electrode 30a connected to the first inner electrode layer 20a and the second outer electrode 30b connected to the second inner electrode layer 20b, exhibiting the characteristics of a capacitor.

[0065] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0066] The first base electrode layer 32a is connected to the first inner electrode layer 20a and disposed on the surface of the first end face 12e. Furthermore, the first base electrode layer 32a extends from the first end face 12e and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 24a of the first inner electrode layer 20a.

[0067] The second base electrode layer 32b is connected to the second inner electrode layer 20b and disposed on the surface of the second end face 12f. Furthermore, the second base electrode layer 32b extends from the second end face 12f and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 24b of the second inner electrode layer 20b.

[0068] The substrate electrode layer 32 comprises at least one selected from the sintered layer, the conductive resin layer, and the thin film layer.

[0069] The following describes the structures in which the base electrode layer 32 is provided as the above-described sintered layer, conductive resin layer, and thin film layer.

[0070] (The situation of burning the attached layer)

[0071] The sintered layer comprises a metallic component and glass. The metallic component of the sintered layer may include at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc. The sintered layer is obtained by applying a conductive paste comprising glass and metal to a laminate and then sintering it. The sintered layer is formed by simultaneously sintering a chip having an internal electrode layer 20 and a dielectric layer 14 and applying a conductive paste to the chip; however, it can also be sintered after the chip having the internal electrode layer 20 and the dielectric layer 14 has been sintered. The sintered layer may also be multilayered.

[0072] The thickness of the first end face 12e and the second end face 12f in the length direction z at the center of the first base electrode layer 32a in the height direction x of the first end face 12e is preferably 10 μm or more and 150 μm or less.

[0073] The thickness of the first end face 12e and the second end face 12f in the length direction z at the center of the second base electrode layer 32b in the height direction x of the second end face 12f is preferably, for example, 10 μm or more and 150 μm or less.

[0074] The thickness of the first base electrode layer 32a located at the center of the length direction z of the first end face 12e and the second end face 12f, which is part of the first main surface 12a and the second main surface 12b, in the height direction x of the first main surface 12a and the second main surface 12b, is preferably 10 μm or more and 100 μm or less.

[0075] Furthermore, the thickness of the second base electrode layer 32b, located at the center of the length direction z connecting the first end face 12e and the second end face 12f, which is part of the first main surface 12a and the second main surface 12b, in the height direction x connecting the first main surface 12a and the second main surface 12b, is preferably, for example, 10 μm or more and 100 μm or less.

[0076] The thickness of the first base electrode layer 32a located at the center of the length direction z of the first end face 12e and the second end face 12f, which is part of the first side face 12c and the second side face 12d, in the width direction y of the first side face 12c and the second side face 12d is preferably 10 μm or more and 100 μm or less.

[0077] Furthermore, the thickness of the second base electrode layer 32b located at the center of the length direction z connecting the first end face 12e and the second end face 12f, and the thickness of the thickness of the thickness of the second base electrode layer 32b located on a portion of the first side face 12c and the second side face 12d in the width direction y is preferably 10 μm or more and 100 μm or less.

[0078] (In the case of conductive resin layer)

[0079] The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0080] The first conductive resin layer, serving as the first base electrode layer 32a, is preferably also covered with other layers such as a sintered layer, and the second conductive resin layer, serving as the second base electrode layer 32b, is preferably also covered with other layers such as a sintered layer.

[0081] Specifically, the first conductive resin layer and the second conductive resin layer are preferably disposed on top of other layers such as the sintered layer on the first end face 12e and the second end face 12f, and are configured to extend to other layers such as the sintered layer on the first main face 12a and the second main face 12b, and the first side face 12c and the second side face 12d. However, the first conductive resin layer and the second conductive resin layer may also be disposed only on other layers such as the sintered layer on the first end face 12e and the second end face 12f.

[0082] The thicknesses of the first conductive resin layer and the second conductive resin layer are preferably, for example, 10 μm or more and 200 μm or less.

[0083] The first conductive resin layer and the second conductive resin layer contain thermosetting resin and metal components.

[0084] The first and second conductive resin layers, because they contain thermosetting resins, are more flexible than, for example, the base electrode layer 32, which contains a sintered product containing a coating film or conductive paste. Therefore, even when the multilayer ceramic capacitor 10 is subjected to physical impacts or impacts caused by thermal cycling, the conductive resin layers can function as buffer layers to prevent cracks from forming in the multilayer ceramic capacitor 10.

[0085] Specific examples of thermosetting resins include various known thermosetting resins such as epoxy resins, phenolic resins, polyurethane resins, silicone resins, and polyimide resins. Among these, epoxy resins, with their excellent heat resistance, moisture resistance, and adhesion, are one of the most suitable resins.

[0086] In both the first and second conductive resin layers, a curing agent is preferably included together with the thermosetting resin. When using epoxy resin as the base resin, various known compounds such as phenolic, amine, anhydride, and imidazole compounds can be used as the curing agent for the epoxy resin.

[0087] Ag, Cu, or alloys thereof can be used as the metals contained in the first and second conductive resin layers. Furthermore, materials in which Ag has been applied to the surface of metal powder can be used. When using materials in which Ag has been applied to the surface of metal powder, Cu or Ni are preferred as the metal powder.

[0088] Furthermore, materials for which Cu has undergone anti-oxidation treatment can also be used. The reason for using metals coated with Ag is that it is possible to use an inexpensive base metal while maintaining the aforementioned properties of Ag.

[0089] The metal contained in the first conductive resin layer and the second conductive resin layer preferably comprises 35 vol% or more and 75 vol% or less relative to the total volume of the conductive resin.

[0090] The shape of the metal contained in the first and second conductive resin layers is not particularly limited. The conductive filler can also be spherical, flat, etc.

[0091] The average particle size of the metals contained in the first and second conductive resin layers is not particularly limited. The average particle size of the conductive filler may, for example, be between 0.3 μm and 10 μm.

[0092] The metal contained in the first and second conductive resin layers primarily bears the responsibility for the electrical conductivity of the conductive resin layers. Specifically, conductive fillers are in contact with each other, thereby forming electrical pathways within the conductive resin layers.

[0093] The metal contained in the first conductive resin layer and the second conductive resin layer can be made of spherical, flat, or other materials, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0094] Alternatively, the conductive resin layer can be formed directly on the laminate without forming a sintered layer.

[0095] Next, regarding the plating layers 34 disposed on the substrate electrode layer 32, namely the first plating layer 34a and the second plating layer 34b, refer to... Figure 2 as well as Figure 3 Please provide an explanation.

[0096] The first plating layer 34a and the second plating layer 34b may include at least one material selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0097] The first plating layer 34a is configured to completely cover the first substrate electrode layer 32a.

[0098] The second plating layer 34b is configured to completely cover the second substrate electrode layer 32b.

[0099] The first plating layer 34a and the second plating layer 34b can also be formed by multiple layers. In this case, the plating layer 34 is preferably a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the substrate electrode layer 32 based on Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer based on Sn plating.

[0100] That is, in this case, the first plating layer 34a has a first lower plating layer 36a and a first upper plating layer 38a located on the surface of the first lower plating layer 36a.

[0101] In addition, the second plating layer 34b has a second lower plating layer 36b and a second upper plating layer 38b located on the surface of the second lower plating layer 36b.

[0102] The lower plating layer 36 based on Ni plating is used to prevent the base electrode layer 32 from being eroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer 38 based on Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, so that it can be easily mounted.

[0103] The thickness of each of the lower plating layer 36 and the upper plating layer 38 is preferably 1.0 μm or more and 15.0 μm or less.

[0104] The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, in the length direction z is set as dimension L. The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, in the height direction x is set as dimension T. The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, in the width direction y is set as dimension W.

[0105] Regarding the dimensions of the multilayer ceramic capacitor 10, the length dimension L in the z-direction is 1.0 mm or more and 3.2 mm or less, the width dimension W in the y-direction is 0.5 mm or more and 2.5 mm or less, and the height dimension T in the x-direction is 0.5 mm or more and 2.5 mm or less. Furthermore, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0106] If voids exist in the dielectric layer 14, the mechanical strength is lower compared to areas where ceramic is filled in the dielectric layer 14. Therefore, if voids exist at locations where electrostrictive stress is concentrated, electrostrictive cracks will originate in the dielectric layer 14 starting from these voids. Electrostriction is prone to occur at the ends of the dielectric layer 14 in the width direction y within the inner layer portion 16 of the laminate 12.

[0107] exist Figure 1 In the multilayer ceramic capacitor 10 shown, the amount of voids near the ends of the dielectric layer 14 in the inner layer portion 16 of the laminate 12, which is a concentration point of electrostrictive stress, is less than that in the central portion in the length direction z. Specifically, the amount of voids contained in the dielectric layer 14a2 at the ends in the length direction is less than that contained in the dielectric layer 14a1 at the central portion in the length direction. As a result, the generation of electrostrictive cracks can be reduced.

[0108] In addition, Figure 1 In the multilayer ceramic capacitor 10 shown, by configuring the end-side dielectric layer 14a2 along the length direction to contain less voids than the central-side dielectric layer 14a1 along the length direction, the sinterability of the ceramic is improved, the shrinkage rate of the end-side dielectric layer 14a2 along the length direction is increased, thereby increasing the exposure of the inner electrode layer 20 and improving the contact with the outer electrode 30. This significantly reduces the generation of electrostrictive cracks.

[0109] In addition, Figure 1 In the multilayer ceramic capacitor 10 shown, if the difference between the area occupancy rate PCL of the voids in the LT cross section of the dielectric layer 14a1 on the central side of the length direction and the area occupancy rate PEL of the voids in the LT cross section of the dielectric layer 14a2 on the end side of the length direction is 2.0% or more and 8.0% or less, the generation of electrostrictive cracks can be further reduced.

[0110] Furthermore, in Figure 1 In the stacked ceramic capacitor 10 shown, if the amount of voids contained in the end dielectric layer 14a4 in the width direction is less than the amount of voids contained in the central dielectric layer 14a3 in the width direction, the generation of electrostrictive cracks can be significantly reduced.

[0111] Furthermore, in addition, Figure 1 In the multilayer ceramic capacitor 10 shown, if the difference between the area occupancy rate PCW of the voids in the WT cross section of the dielectric layer 14a3 on the central side of the width direction and the area occupancy rate PEW of the voids in the WT cross section of the dielectric layer 14a4 on the end side of the width direction is 0.5% or more and 8.0% or less, the effect of reducing the generation of electrostrictive cracks can be obtained more significantly.

[0112] 2. Manufacturing method of multilayer ceramic capacitors

[0113] Next, the manufacturing method of multilayer ceramic capacitors will be explained.

[0114] First, prepare a ceramic green sheet for the dielectric layer and a conductive paste for the internal electrode layer. The ceramic green sheet and the conductive paste for the internal electrode layer comprise an adhesive and a solvent. The adhesive and solvent can be any known adhesive and solvent.

[0115] Then, for example, conductive paste for the inner electrode layer is printed on a ceramic green sheet for the dielectric layer with a given pattern using screen printing, gravure printing, or the like. Thus, a ceramic green sheet with a pattern of a first inner electrode layer and a ceramic green sheet with a pattern of a second inner electrode layer are prepared.

[0116] (The process of obtaining the laminated wafer)

[0117] Next, a given number of outer ceramic green sheets without the pattern of the internal electrode layer are stacked to form a second outer layer portion on the second main surface side. Then, a ceramic green sheet with the pattern of the first internal electrode layer and a ceramic green sheet with the pattern of the second internal electrode layer are sequentially stacked on the second outer layer portion to form the structure of the present invention, thereby forming an inner layer portion. A given number of outer ceramic green sheets without the pattern of the internal electrode layer are stacked on the inner layer portion to form a first outer layer portion on the first main surface side. Thus, a laminated sheet is produced.

[0118] (The process of obtaining the stacked blocks)

[0119] Next, the laminated sheets are pressed in the lamination direction by means of isostatic pressing, thereby producing a laminated block.

[0120] (The process of obtaining stacked small pieces)

[0121] Then, by cutting the laminated blocks to a given size, small laminated pieces are cut out. At this point, the corners and edges of the small laminated pieces can also be rounded using methods such as tumbling.

[0122] (The process of obtaining the laminated body)

[0123] Next, the stacked small pieces are fired to form a laminate. At this time, by adjusting the heat distribution in the firing furnace during heat treatment, the heat involved in the central portion of the stacked small pieces along the length direction z is less than the heat involved in the ends of the stacked small pieces along the length direction z. As a result, the ceramic filling rate is higher at the ends of the stacked body along the length direction z compared to the central portion, and the amount of voids in the ends of the stacked body along the length direction z is less than the amount of voids in the central portion. The firing temperature is also based on the temperature of the dielectric layer and the internal electrode layer, but is preferably 900°C or higher and 1400°C or lower.

[0124] Next, prepare a conductive paste for the base electrode layer, which contains both metallic and glass components.

[0125] (The process of forming the external electrode)

[0126] A conductive paste, which serves as the base electrode layer, is applied to both ends of the laminate to form the base electrode layer. The conductive paste can be applied to both ends of the laminate using methods such as dipping or screen printing. The firing temperature is preferably 700°C or higher and 900°C or lower.

[0127] Next, as needed, a plating layer is formed on the surface of the substrate electrode layer. In this embodiment, two plating layers are formed on the surface of the substrate electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the substrate electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a roll plating method.

[0128] As described above, the multilayer ceramic capacitor 10 of this embodiment is manufactured.

[0129] According to the manufacturing method of the multilayer ceramic capacitor of the present invention, the ceramic filling rate is higher at the ends of the multilayer in the length direction z compared to the central portion of the multilayer in the length direction z, which reduces the amount of voids at the ends of the multilayer in the length direction z compared to the amount of voids in the central portion of the multilayer in the length direction z. Therefore, a multilayer ceramic capacitor capable of reducing the crack initiation rate of electrostrictive cracks can be obtained.

[0130] 3. Experimental Example

[0131] Next, in order to confirm the effect of the multilayer ceramic capacitor of the present invention, as an experimental sample, a multilayer ceramic capacitor as a sample was manufactured according to the above-described manufacturing method, and an experiment was conducted to confirm whether there were cracks caused by electrostriction.

[0132] (1) Specifications of the test specimens in the experimental example

[0133] First, according to the above-described method for manufacturing multilayer ceramic capacitors, samples of multilayer ceramic capacitors of the following specifications, namely Examples 1 to 10 and the comparative examples, were prepared.

[0134] (Specifications for multilayer ceramic capacitors)

[0135] • Dimensions of the multilayer ceramic capacitor (design value): L×W×T=1.6mm×0.8mm×0.8mm

[0136] • The main component of the dielectric layer is the ceramic material: BaTiO3

[0137] • Capacitance: 22μF

[0138] Rated voltage: 16V

[0139] • Material of the internal electrode layer: Ni

[0140] • Construction of external electrodes: conductive metal (Cu) and glass composition

[0141] • Film thickness at the center of the height direction of the first and second end faces of the external electrode: approximately 90 μm

[0142] · Coating

[0143] Two layers are formed: a Ni coating and a Sn coating.

[0144] Ni plating thickness: approximately 3μm

[0145] Sn plating thickness: approximately 5μm

[0146] (2) Evaluation methods for crack formation

[0147] Electrostriction tests on the multilayer ceramic capacitors involved in each sample were conducted using a breakdown voltage measuring device. As detailed for the breakdown voltage measuring device, the voltage was boosted to DC 150V at a boost rate of 100V / sec. The presence or absence of cracks was observed using an ultrasonic flaw detector. Specifically, firstly, the multilayer ceramic capacitors serving as samples were arranged with their main faces facing upwards. Next, the upper surface of the arranged multilayer ceramic capacitors was scanned using an ultrasonic probe. The reflected ultrasonic waves were observed, and the presence or absence of cracks was confirmed by detecting the reflected waves that returned earlier than the bottom surface waves.

[0148] Here, samples with confirmed cracks were counted as electrostriction defects, and the crack initiation rate was calculated. For each embodiment and comparative example, 100 samples were prepared, and the crack initiation rate was measured. Furthermore, the percentage of the total number of samples measured (100) to the number of cracks initiating was defined as the crack initiation rate. Additionally, the criteria for determining the crack initiation rate were as follows: 0% or more and 10% or less was marked with "◎", 11% or more and 30% or less was marked with "〇", 31% or more and 50% or less was marked with "△", and 51% or more and 100% or less was marked with "×".

[0149] (3) Results

[0150] Table 1 shows the crack initiation rate of the dielectric layer of the laminate based on Examples 1 to 10 and the comparative examples.

[0151] [Table 1]

[0152]

[0153] According to Table 1, the samples of Examples 1 to 10 all achieved a good result with a crack initiation rate of less than 50% because the amount of voids contained in the dielectric layer at the end of the length direction was less than the amount of voids contained in the dielectric layer at the center of the length direction.

[0154] Furthermore, for each sample in Examples 2 to 5, since the difference between the area occupancy rate PCL of the voids in the LT cross section of the dielectric layer on the central side of the length direction and the area occupancy rate PEL of the voids in the LT cross section of the dielectric layer on the end side of the length direction is 2.0% or more and 8.0% or less, a better result of crack initiation rate of 11% or more and 30% or less was obtained.

[0155] Furthermore, in each of the samples of Examples 7 to 10, since the difference between the area occupancy rate PCW of the voids in the WT cross section of the dielectric layer at the center in the width direction and the area occupancy rate PEW of the voids in the WT cross section of the dielectric layer at the end in the width direction is 0.5% or more and 8.0% or less, a further good result of a crack initiation rate of 10% or less was obtained.

[0156] On the other hand, in the comparative example, the crack initiation rate was 72% because the amount of voids contained in the dielectric layer at the end of the length direction was greater than that contained in the dielectric layer at the center of the length direction.

[0157] Based on the above results, in this invention, the inner layer of the laminate is composed of an inner dielectric layer containing voids. By setting the structure such that the amount of voids in the dielectric layer at the longitudinal end of the region where the inner dielectric layer is disposed in the longitudinal central portion of the inner layer is less than the amount of voids in the dielectric layer at the longitudinal central portion, the amount of voids near the longitudinal end of the dielectric layer in the inner layer of the laminate, which is a location of electrostrictive stress concentration, is less than the amount of voids near the longitudinal central portion, thus reducing the generation of electrostrictive cracks.

[0158] Furthermore, as described above, the embodiments of the present invention have been disclosed through the above description, but the present invention is not limited thereto.

[0159] That is, without departing from the technical concept and purpose of the present invention, various changes can be made to the above-described embodiments regarding the mechanism, shape, material, quantity, position or configuration, etc., and these are included in the present invention.

[0160] Explanation of reference numerals in the attached figures

[0161] 10: Multilayer ceramic capacitors;

[0162] 12: Layered body;

[0163] 12a: 1st main side;

[0164] 12b: 2nd main side;

[0165] 12c: First side view;

[0166] 12d: Second side view;

[0167] 12e: First end face;

[0168] 12f: Second end face;

[0169] 14: Dielectric layer;

[0170] 14a: Internal dielectric layer;

[0171] 14a1: Dielectric layer at the center of the length direction;

[0172] 14a2: End-side dielectric layer in the length direction;

[0173] 14a3: Dielectric layer in the central part of the width direction;

[0174] 14a4: End-side dielectric layer in the width direction;

[0175] 14b: External dielectric layer;

[0176] 16: Inner layer;

[0177] 18a: First outer layer;

[0178] 18b: Second outer layer;

[0179] 20: Internal electrode layer;

[0180] 20a: First internal electrode layer;

[0181] 20b: Second internal electrode layer;

[0182] 20c: Floating internal electrode layer;

[0183] 22: Opposite electrode section;

[0184] 22a: First opposing electrode section;

[0185] 22b: Second opposing electrode section;

[0186] 24a: First lead-out electrode section;

[0187] 24b: Second lead-out electrode section;

[0188] 26a: Side (W gap);

[0189] 26b: End (L gap);

[0190] 30: External electrode;

[0191] 30a: First external electrode;

[0192] 30b: Second external electrode;

[0193] 32: Substrate electrode layer;

[0194] 32a: First base electrode layer;

[0195] 32b: Second base electrode layer;

[0196] 34: Coating layer;

[0197] 34a: First plating layer;

[0198] 34b: Second plating layer;

[0199] 36: Lower plating layer;

[0200] 36a: First lower plating layer;

[0201] 36b: Second lower plating layer;

[0202] 38: Upper plating layer;

[0203] 38a: First upper plating layer;

[0204] 38b: Second upper plating layer;

[0205] WA: The region containing a void within the end-side dielectric layer in the width direction;

[0206] LA: The region containing a gap in the dielectric layer at the end along the length direction;

[0207] x: Height direction (stack direction);

[0208] y: width direction;

[0209] z: Length direction.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate includes a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and includes a first main surface and a second main surface opposite each other in the height direction which is the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height direction and the width direction, and includes an inner layer portion formed by alternating stacking of the dielectric layers and the internal electrode layers, and an outer layer portion configured to sandwich the inner layer portion from the first main surface side and the second main surface side; A first external electrode is disposed on the first end face; and The second external electrode is disposed on the second end face. in, The inner layer is composed of an inner dielectric layer among a plurality of dielectric layers disposed in the inner layer. The internal dielectric layer contains voids. The inner dielectric layer has a length-direction central portion side dielectric layer disposed in a region of the central portion in the length direction of the inner layer portion, and a length-direction end side dielectric layer disposed in a region of the end portion in the length direction of the inner layer portion. The amount of voids in the end-side dielectric layer along the length direction is less than the amount of voids in the central-side dielectric layer along the length direction.

2. The multilayer ceramic capacitor according to claim 1, wherein, The difference between the area occupancy (PCL) of the voids in the LT cross-section of the dielectric layer at the center of the length direction and the area occupancy (PEL) of the voids in the LT cross-section of the dielectric layer at the end of the length direction is more than 2.0% and less than 8.0%.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The inner dielectric layer further includes a width-direction central portion side dielectric layer disposed in the region of the central portion in the width direction of the inner layer portion, and a width-direction end side dielectric layer disposed in the region of the end portion in the width direction of the inner layer portion. The amount of voids in the end-side dielectric layer in the width direction is less than the amount of voids in the central-side dielectric layer in the width direction.

4. The multilayer ceramic capacitor according to claim 3, wherein, The difference between the area occupancy (PCW) of the voids in the WT cross-section of the central dielectric layer in the width direction and the area occupancy (PEW) of the voids in the WT cross-section of the end dielectric layer in the width direction is 0.5% or more and 8.0% or less.

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