Double-pulse test method

Abstract

The invention discloses a double-pulse test method, which relates to the technical field of power module test, and comprises the following steps: S1, building a double-pulse test platform; s2, setting parameters; s3, executing a double-pulse test; s4, exporting test parameters; and S5, parameter verification. According to the double-pulse test method, by optimizing the design of a test platform, electromagnetic interference is effectively reduced, the accuracy of waveform and parameter measurement is ensured, the width of the first pulse and the test inductance are quantitatively calculated through a formula, it is guaranteed that the test current accurately reaches a target value, and a foundation is laid for switch parameter extraction; moreover, a test voltage increasing criterion, waveform monitoring key points and a verification process after driving parameter adjustment are defined, consistency and reliability of test results are ensured, finally parameters such as switching loss, voltage spike and delay time are comprehensively extracted, actual characteristics of the power module are directly reflected, and the test accuracy is improved. And a key reference is provided for converter design such as drive circuit optimization and heat dissipation design.

Description

Technical Field

[0001] This invention relates to the field of power module testing technology, specifically a dual-pulse testing method. Background Technology

[0002] As the core component of a power electronic converter, the switching characteristics of the power module, such as switching losses, voltage spikes, and oscillations, directly affect the converter's efficiency, reliability, and safety. During the converter design and commissioning phases, precise testing of the power module's actual operating performance is necessary to verify the rationality of the drive circuit parameters and evaluate the module's performance under real-world conditions.

[0003] Existing testing methods have many shortcomings: some methods have large parasitic parameters on the test platform, resulting in severe waveform interference and failing to accurately reflect the true characteristics of the module; some methods have unreasonable parameter settings, making it difficult to accurately establish the target current during testing, affecting the accuracy of switch parameter extraction, and resulting in insufficient reliability of test results. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a dual-pulse testing method that solves the problems mentioned in the background section.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a double-pulse testing method, the double-pulse testing method comprising the following steps: S1. Set up a dual-pulse test platform: Build a physical or simulated physical test platform, use a high-voltage probe to measure the DS voltage of the power module, and a low-voltage probe to measure the GS voltage, where GS is the gate-source voltage. S2, Parameter Settings: Based on the target test voltage and current level, calculate the first pulse width and test inductance using the formula to ensure that the current reaches the target test value at the end of the first pulse; the calculation formula is as follows: ; S3. Perform a double-pulse test: The tests should be conducted according to the principle of increasing the test voltage from low to high. S4. Export test parameters: Export test parameters using bipulse calculation software, including but not limited to: Fall time: The time it takes for the current to drop from 90% to 10% during the power transistor's turn-off process; Turn-off delay time: the time from the falling edge of the drive signal to the start of current decline; Maximum voltage: The maximum voltage spike that occurs at the DS terminal during the switching process; Rise time: The time it takes for the current to rise from 10% to 90% during the turn-on process of the power transistor; Turn-on delay time: the time from the rising edge of the drive signal to the start of current rise; Maximum current: The maximum current value reached during the test; Turn-off loss: Energy loss generated during the turn-off process of a power transistor; Turn-on loss: Energy loss during the turn-on process of a power transistor; S5. Parameter Verification: If the GS waveform, DS voltage spike, and switching loss indicators do not meet the requirements based on the test results, adjust the driver board parameters; after adjusting the parameters, repeat steps S3-S4 and retest and verify until the test results meet the preset indicator requirements.

[0006] Furthermore, in step S1, the platform must meet the following requirements: the busbar connection length is controlled within 10cm; High and low voltage probes and cables are arranged separately to prevent electromagnetic interference between probes and cables; The test probe has a line length of ≤30cm and is arranged in a twisted pair manner with a twist pitch of 1.5cm / twist, twisted clockwise, and has a grounded shielding layer to avoid introducing external interference; The GS port test uses an optically isolated probe to ensure the accuracy of the gate-source voltage waveform measurement.

[0007] Furthermore, in step S2, The first pulse width, in seconds, is the duration of the first continuous pulse sent by the controller. Target test current, unit: A, is the current value that needs to be reached at the end of the first pulse; Test inductance, unit: H, is the inductance value connected in series in the test circuit; Test voltage, unit: V, i.e., the bus voltage of the test platform; Power transistor on-state voltage drop, unit: V, is the voltage drop across the transistor when the power module is turned on.

[0008] Furthermore, in step S3, the following are monitored in real time during the test: whether the GS waveform exhibits abnormal oscillation; if the GS waveform exceeds a preset threshold, it is determined to be an abnormal oscillation, deviating from the reference drive voltage by ±20% or the oscillation frequency by >1MHz, in order to evaluate the stability of the gate drive signal. Whether the DS voltage exhibits abnormal oscillations, deviating from the steady-state voltage by ±15% or oscillating more than 3 times per switching cycle, or whether the DS voltage exceeds a preset threshold, is determined to be an abnormal oscillation. Also, whether the voltage spike exceeds a preset safety threshold, i.e., ≤80% of the module's rated withstand voltage. During the test, check whether the active clamping circuit operates normally. If the feedback data from the active clamping circuit exceeds the preset threshold, it is considered abnormal. If the operating voltage deviates from the design value by ±10% or the response delay is >50ns, it is considered abnormal. During the test, the driver board should trigger overcurrent protection (i.e., overcurrent > target current 120%) and overvoltage protection (i.e., overvoltage > test voltage 110%).

[0009] Furthermore, in step S5, the driving board parameters include, but are not limited to, gate resistance and driving voltage.

[0010] This invention provides a dual-pulse testing method, which has the following beneficial effects: 1. This dual-pulse testing method effectively reduces electromagnetic interference and ensures the accuracy of waveform and parameter measurements by optimizing the test platform design, such as short busbars, low parasitic inductance, and optically isolated probes. Furthermore, it quantitatively calculates the first pulse width and test inductance using formulas to ensure the test current accurately reaches the target value, laying the foundation for switching parameter extraction. It also clarifies the test voltage increment criteria, waveform monitoring points, and verification procedures after drive parameter adjustments, ensuring the consistency and reliability of test results. Finally, it comprehensively extracts parameters such as switching losses, voltage spikes, and delay time, directly reflecting the actual characteristics of the power module and providing crucial references for converter design, such as drive circuit optimization and heat dissipation design. 2. This dual-pulse testing method facilitates the twisting of two lines, eliminating the time-consuming manual twisting process of braiding the lines. Simply hold the handheld box and slide it uniformly downwards along the surface of the lines, causing the rollers to rotate along the outer wall of the lines. The force is then transmitted to the power gear via a transmission belt, transmission wheel, first bevel gear, second bevel gear, and transmission gear. This causes the power gear to roll along the side of the inner gear ring, driving the movable box to rotate. As a result, the two lines naturally twist together under the rotation of the movable box, thus facilitating the twisting of the lines to prevent external interference. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the steps of a dual-pulse testing method according to the present invention; Figure 2 This is a schematic diagram of the natural droop of the circuit and the external structure of the handheld box in the dual-pulse testing method of the present invention. Figure 3 This is a schematic diagram of the internal structure of the handheld box and the active box of the dual-pulse testing method of the present invention; Figure 4 This invention provides a double-pulse testing method. Figure 3 Enlarged structural diagram at point A in the middle; Figure 5 This is a schematic diagram of the handheld box and the active box after separation in the dual-pulse testing method of the present invention; Figure 6 This is a schematic diagram of the through-hole structure of a dual-pulse testing method according to the present invention.

[0012] In the diagram: 1. Test probe; 2. Circuit; 3. Stranding assembly; 301. Handheld box; 302. Mounting slot; 303. Annular slide; 304. Miniature pulley; 305. Movable box; 306. Wire hole; 307. Roller; 308. Transmission groove; 309. Transmission belt; 310. Transmission wheel; 311. First bevel gear; 312. Second bevel gear; 313. Transmission gear; 314. Power gear; 315. Internal gear ring. Detailed Implementation

[0013] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0014] like Figure 1 As shown, the present invention provides a technical solution: a double-pulse testing method, which includes the following steps: S1. Set up a dual-pulse test platform: Build a physical or simulated physical test platform, use a high-voltage probe to measure the DS voltage of the power module, and a low-voltage probe to measure the GS voltage, where GS is the gate-source voltage. The platform must meet the following requirements: the busbar connection length must be controlled within 10cm; High and low voltage probes and cables are arranged separately to prevent electromagnetic interference between probes and cables; The test probe 1 has a line 2 length ≤ 30cm and is arranged in a twisted pair manner with a twist pitch of 1.5cm / twist, twisted clockwise, and with a grounded shielding layer to avoid introducing external interference; The GS port test uses an optically isolated probe to ensure the accuracy of the gate-source voltage waveform measurement; S2, Parameter Settings: Based on the target test voltage and current level, calculate the first pulse width and test inductance using the formula to ensure that the current reaches the target test value at the end of the first pulse; the calculation formula is as follows: ;

[0015] in, The first pulse width, in seconds, is the duration of the first continuous pulse sent by the controller. Target test current, unit: A, is the current value that needs to be reached at the end of the first pulse; Test inductance, unit: H, is the inductance value connected in series in the test circuit; Test voltage, unit: V, i.e., the bus voltage of the test platform; Power transistor on-state voltage drop, unit: V, is the voltage drop across the transistor when the power module is turned on; S3. Perform a double-pulse test: The tests should be conducted according to the principle of increasing the test voltage from low to high. During the test, the following are monitored in real time: whether the GS waveform exhibits abnormal oscillation. If the GS waveform exceeds the preset threshold, it is determined to be an abnormal oscillation, deviating from the reference drive voltage by ±20% or the oscillation frequency by >1MHz, in order to evaluate the stability of the gate drive signal. Whether the DS voltage exhibits abnormal oscillations, deviating from the steady-state voltage by ±15% or oscillating more than 3 times per switching cycle, or whether the DS voltage exceeds a preset threshold, is determined to be an abnormal oscillation. Also, whether the voltage spike exceeds a preset safety threshold, i.e., ≤80% of the module's rated withstand voltage. During the test, check whether the active clamping circuit operates normally. If the feedback data from the active clamping circuit exceeds the preset threshold, it is considered abnormal. If the operating voltage deviates from the design value by ±10% or the response delay is >50ns, it is considered abnormal. During the test, the driver board should trigger overcurrent protection mechanisms (i.e., protection against overcurrent exceeding 120% of the target current) and overvoltage protection mechanisms (i.e., protection against overvoltage exceeding 110% of the test voltage). S4. Export test parameters: Export test parameters using bipulse calculation software, including but not limited to: Fall time: The time it takes for the current to drop from 90% to 10% during the power transistor's turn-off process; Turn-off delay time: the time from the falling edge of the drive signal to the start of current decline; Maximum voltage: The maximum voltage spike that occurs at the DS terminal during the switching process; Rise time: The time it takes for the current to rise from 10% to 90% during the turn-on process of the power transistor; Turn-on delay time: the time from the rising edge of the drive signal to the start of current rise; Maximum current: The maximum current value reached during the test; Turn-off loss: Energy loss generated during the turn-off process of a power transistor; Turn-on loss: Energy loss during the turn-on process of a power transistor; S5. Parameter Verification: If the GS waveform, DS voltage spike, and switching loss indicators do not meet the requirements based on the test results, adjust the driver board parameters, which include but are not limited to the gate resistance and drive voltage. After adjusting the parameters, repeat steps S3-S4 and retest until the test results meet the preset requirements.

[0016] Example

[0017] First, clarify the purpose of the test: to evaluate the switching characteristics of the IGBT power module, verify the rationality of the gate resistance parameters of the driver board, observe the oscillation and voltage spikes during the switching process, and provide a reference for the design of photovoltaic inverters; The busbars are connected by copper busbars, with a length controlled within 10cm and a parasitic inductance measurement value ≤50nH; a 100μF / 1200V decoupling capacitor is connected in parallel to the busbars. The high-voltage probe measures the DS voltage, and the low-voltage probe measures the GS voltage. The two probes are respectively arranged on both sides of the platform, with a cable spacing of ≥30cm. The test probe 1 has a line 2 length ≤ 20cm and uses twisted pair shielding; the GS port uses an optically isolated probe with a bandwidth ≥ 100MHz. Target test voltage Target test current IGBT on-state voltage drop Test inductance According to the formula The first pulse width is calculated as follows:

[0018] The test voltage started at 400V and increased in increments of 200V to 800V; during the 800V test, the following was observed: The GS waveform shows no obvious oscillations, and the rising or falling edges are steep. DS voltage spike The voltage did not exceed the module's withstand voltage of 1200V; The active clamp did not activate, and the driver board was not triggered by protection. The parameters were exported using the calculation software as follows:

[0019] The initial gate resistance was 10Ω, and testing revealed slightly high turn-on losses. (Upper MOSFET) Approaching the preset target After adjusting the gate resistance to 8Ω and retesting, the turn-on loss decreased to [amount missing]. The waveform is normal and meets the design requirements.

[0020] Based on the above description, this invention effectively reduces electromagnetic interference and ensures the accuracy of waveform and parameter measurements by optimizing the test platform design, such as short busbars, low parasitic inductance, and optically isolated probes. Furthermore, it quantitatively calculates the first pulse width and test inductance using formulas to ensure the test current accurately reaches the target value, laying the foundation for switch parameter extraction. It also clarifies the test voltage increment criteria, waveform monitoring points, and verification procedures after drive parameter adjustments, ensuring the consistency and reliability of test results. Finally, it comprehensively extracts parameters such as switching losses, voltage spikes, and delay times, directly reflecting the actual characteristics of the power module and providing crucial references for converter design, such as drive circuit optimization and heat dissipation design.

[0021] like Figures 2-6 As shown in the attached diagram, the tooth grooves on the inner side of the internal gear ring 315 and the outer side of the drive gear 314 are too dense and appear dark. For specific structural details, please refer to [reference needed]. Figure 4 The enlarged view clearly shows the structure of the internal gear ring 315 and the drive gear 314. There are two test probes 1, with a wire 2 connected to the top of each probe. The top of the wire 2 is connected to an oscilloscope. There are two wires on the wire 2 corresponding to the test probes 1, marked with black and red respectively. The surface of the wire 2 has anti-slip textures to enhance friction. The twisting assembly 3 includes a handheld box 301 fitted over the wire 2. The handheld box 301 has an installation groove 302 inside. The top and bottom of the inner wall of the installation groove 302 have annular grooves 303. A miniature pulley 304 is slidably connected inside the annular groove 303. The shaft end of the miniature pulley 304 is connected to a movable box 305. The surface of the movable box 305 has symmetrical wire holes 306. The wire 2 passes through the wire holes 306, and the outer walls of the wire 2 are fitted together. There is a roller 307, which is rotatably connected to both sides inside the wire hole 306. A transmission groove 308 is opened in the middle of the roller 307, and a transmission belt 309 is engaged inside the transmission groove 308. The end of the transmission belt 309 away from the transmission groove 308 passes through the interior of the movable box 305 and engages with a transmission wheel 310. The transmission wheel 310 is rotatably connected to the movable box 305. A first bevel gear 311 is fixed on the side of the transmission wheel 310, and a second bevel gear 312 is engaged at the bottom of the first bevel gear 311. The second bevel gear 312 is rotatably connected to the movable box 305. A transmission gear 313 is fixed on the top of the second bevel gear 312, and a power gear 314 is engaged at the side of the transmission gear 313. The side of the power gear 314 extends to the outside of the movable box 305 and is engaged with an internal gear ring 315. The internal gear ring 315 is fixed inside the mounting groove 302. The specific operation is as follows: As can be seen from the above, the test probe 1 has a line length ≤30cm and is arranged in a twisted pair manner to avoid introducing external interference. When twisting is required, the handheld box 301 is manually held, avoiding hijacking the movable box 305. The handheld box 301 is held so that it slides down the surface of the line 2. At this time, the roller 307 rolls and rotates inside the wire hole 306 along the outer wall of the line 2. This drives the transmission wheel 310 through the transmission belt 309, causing the first bevel gear 311 to rotate. The first bevel gear 311 then drives the second bevel gear 312, causing the transmission gear 313 to mesh with the power gear 314 and rotate. This causes the power gear 314 to rotate along the inner side of the internal gear ring 315. The surface rolls in a ring, thereby driving the movable box 305 to slide along the annular groove 303 inside the handheld box 301 via the miniature pulley 304 and rotate. When the movable box 305 rotates, the two wire holes 306 carry the corresponding wires 2 inside them and make a circular motion around the central axis of the movable box 305. Thus, when the handheld box 301 slides down along the surface of the wires 2, the wires 2 inside the two wire holes 306 are twisted together by the rotation of the movable box 305. The miniature pulley 304 is a damping pulley whose starting threshold is greater than the natural restoring force after the double wires are twisted, thereby preventing the twisted wires 2 from driving the miniature pulley 304 to slide back due to rotation, which would cause the twisting to fail. Based on the above description, in order to facilitate the twisting of the two lines 2, the present invention eliminates the need for manual twisting of the two lines 2 by braiding them, which would otherwise be time-consuming. Instead, the handheld box 301 is simply held and forcefully slid downwards at a uniform speed along the surface of the line 2, causing the roller 307 to roll and rotate along the outer wall of the line 2. The force is then transmitted to the power gear 314 via the transmission belt 309, transmission wheel 310, first bevel gear 311, second bevel gear 312, and transmission gear 313. This causes the power gear 314 to roll along the side of the inner gear ring 315, thereby driving the movable box 305 to rotate. As a result, the two lines 2 naturally twist together under the rotation of the movable box 305, thus facilitating the twisting of the lines 2 to prevent external interference.

[0022] In summary, when using this dual-pulse testing method, firstly, while twisting the circuit 2 of the test probe 1, the manual person holds the handheld box 301, avoiding hijacking the movable box 305. Holding the handheld box 301, it slides down the surface of the circuit 2 from top to bottom. At this time, the roller 307 rolls and rotates inside the wire hole 306 along the outer wall of the circuit 2. This drives the transmission wheel 310 through the transmission belt 309, causing the first bevel gear 311 to rotate. The first bevel gear 311 then drives the second bevel gear 312, causing the transmission gear 313 to mesh with the power gear 314 and rotate. This causes the power gear 314 to roll in a ring along the inner side of the internal gear ring 315, thereby driving the movable box 305 to slide and rotate through the micro pulley 304 along the annular groove 303 inside the handheld box 301. When the movable box 305 rotates, the two wire holes 306 carry the corresponding wires 2 inside them and make a circular motion around the central axis of the movable box 305. As a result, when the handheld box 301 slides down along the surface of the wires 2, the wires 2 inside the two wire holes 306 are twisted and intertwined by the rotation of the movable box 305.

[0023] The embodiments of the present invention are given for illustrative and descriptive purposes only, and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention and to design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A double-pulse testing method, characterized in that: The dual-pulse testing method includes the following steps: S1. Set up a dual-pulse test platform: Build a physical or simulated physical test platform, use a high-voltage probe to measure the DS voltage of the power module, and a low-voltage probe to measure the GS voltage, where GS is the gate-source voltage. S2, Parameter Settings: Based on the target test voltage and current level, calculate the first pulse width and test inductance using the formula to ensure that the current reaches the target test value at the end of the first pulse. The calculation formula is as follows: ； S3. Perform a double-pulse test: The tests should be conducted according to the principle of increasing the test voltage from low to high. S4. Export test parameters: Export test parameters using dual-pulse calculation software; S5. Parameter Verification: Based on the test results, if the GS waveform, DS voltage spike, and switching loss indicators do not meet the requirements, adjust the driver board parameters; after adjusting the parameters, repeat steps S3-S4 and retest and verify until the test results meet the preset indicator requirements. In step S2, the first pulse width, in seconds, is the duration of the first continuous pulse sent by the controller. Target test current, unit: A, is the current value that needs to be reached at the end of the first pulse; Test inductance, unit: H, is the inductance value connected in series in the test circuit; Test voltage, unit: V, i.e., the bus voltage of the test platform; Power transistor on-state voltage drop, unit: V, is the voltage drop across the transistor when the power module is turned on.

2. The double-pulse testing method according to claim 1, characterized in that: In step S1, the platform must meet the following requirements: the busbar connection length is controlled within 10cm; High and low voltage probes and cables are arranged separately to prevent electromagnetic interference between probes and cables; The test probe has a line length of ≤30cm and is arranged in a twisted pair manner with a twist pitch of 1.5cm / twist, twisted clockwise, and has a grounded shielding layer to avoid introducing external interference; The GS port test uses an optically isolated probe to ensure the accuracy of the gate-source voltage waveform measurement.

3. The double-pulse testing method according to claim 1, characterized in that: In step S3, the following are monitored in real time during the test: whether the GS waveform exhibits abnormal oscillation; if the GS waveform exceeds a preset threshold, it is determined to be an abnormal oscillation, deviating from the reference drive voltage by ±20% or the oscillation frequency by >1MHz, in order to evaluate the stability of the gate drive signal. Whether the DS voltage exhibits abnormal oscillations, deviating from the steady-state voltage by ±15% or oscillating more than 3 times per switching cycle, or whether the DS voltage exceeds a preset threshold, is determined to be an abnormal oscillation. Also, whether the voltage spike exceeds a preset safety threshold, i.e., ≤80% of the module's rated withstand voltage. During the test, check whether the active clamping circuit operates normally. If the feedback data from the active clamping circuit exceeds the preset threshold, it is considered abnormal. If the operating voltage deviates from the design value by ±10% or the response delay is >50ns, it is considered abnormal. During the test, the driver board should trigger overcurrent protection (i.e., overcurrent > target current 120%) and overvoltage protection (i.e., overvoltage > test voltage 110%).

4. The double-pulse testing method according to claim 1, characterized in that: In step S5, the parameters of the driving board include, but are not limited to, gate resistance and driving voltage.

5. The double-pulse testing method according to claim 1, characterized in that: In step S4, the test parameters include, but are not limited to: Fall time: The time it takes for the current to drop from 90% to 10% during the power transistor's turn-off process; Turn-off delay time: the time from the falling edge of the drive signal to the start of current decline; Maximum voltage: The maximum voltage spike that occurs at the DS terminal during the switching process; Rise time: The time it takes for the current to rise from 10% to 90% during the turn-on process of the power transistor; Turn-on delay time: the time from the rising edge of the drive signal to the start of current rise; Maximum current: The maximum current value reached during the test; Turn-off loss: Energy loss generated during the turn-off process of a power transistor; Turn-on loss: Energy loss generated during the turn-on process of a power transistor.

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