Chip function detection method based on interconnected IP, electronic device and medium
By setting up a chip function detection module and configuration file during the chip IP verification stage, and using interconnect IP verification components for simulation detection, the problem of low chip development efficiency in existing technologies is solved, enabling rapid and accurate detection in the IP stage and reducing integration iterations in the SoC stage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 沐曦集成电路(南京)有限公司
- Filing Date
- 2025-09-25
- Publication Date
- 2026-06-05
AI Technical Summary
Existing technologies cannot perform chip function testing at the IP stage, resulting in low chip development efficiency and requiring repeated iterative adjustments when problems are discovered at the SoC system level.
During the chip IP verification phase, by setting up the chip function detection module and configuration file, the interconnect IP verification component is used to perform simulation detection and generate abnormal prompts to solve the problem.
It enables rapid and accurate chip function testing at the IP stage, reduces integration iterations at the SoC stage, and improves chip development efficiency.
Smart Images
Figure CN120870834B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a chip function testing method, electronic device, and medium based on interconnect IP. Background Technology
[0002] Chip architecture comprises multiple intellectual property (IP) and fabric IP. Intellectual property (IP) refers to functional modules within the chip, such as processor cores, memory units, and various IP cores. Fabric IP refers to the communication architecture intellectual property modules within a Network on Chip (NoC). Fabric IP enables efficient communication and data transmission between multiple chip IPs within the chip, building complex System on Chip (SoC) systems. The functional characteristics of fabric IP differ between upstream and downstream chip IPs. Currently, only protocol-related information can be checked at the IP level; chip functionality testing can only be performed at the complex SoC system level. When chip functionality malfunctions, it can directly cause errors or crashes in the entire chip system. Furthermore, when a chip functionality problem is discovered at the complex SoC system level, it's necessary to return to the IP level for adjustments, followed by repeated SoC-level integration, potentially requiring multiple iterations. All of these factors impact chip development efficiency. Implementing chip functionality testing at the IP stage would significantly reduce the probability of functional problems occurring at the SoC system level. Therefore, how to implement chip function testing at the IP stage and improve chip development efficiency has become an urgent technical problem to be solved. Summary of the Invention
[0003] The purpose of this invention is to provide a chip function testing method, electronic device, and medium based on interconnect IP, which can realize chip function testing at the IP stage and improve chip development efficiency.
[0004] According to a first aspect of the present invention, a chip function testing method based on interconnect IP is provided, comprising:
[0005] Step S1: In the chip IP verification stage, obtain the nth combination A to be verified in the chip design. n And A n Corresponding chip function detection configuration file E n , where A n ={B n C n}, B n For the nth object to be verified, C n For the nth verification component, C n It includes a preset chip function detection module D. n If Bn If it is a chip IP, then C n For simulation and B n Interactive IP verification component, if B n For interconnected IPs, then C n For simulation and B n Interactive chip IP verification component, E n Used to store A n The corresponding chip function testing configuration information, where n ranges from 1 to N, and N is the total number of combinations to be verified in the chip design;
[0006] Steps S2 and C n To B n Send stimuli to perform simulation;
[0007] Steps S3 and D n Based on C n To B n Send incentives and E n Perform chip function testing; if an anomaly is detected, generate an anomaly message.
[0008] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.
[0009] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.
[0010] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the chip function testing method, electronic device, and medium based on interconnect IP provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects:
[0011] This invention improves chip development efficiency by setting a chip function detection module in the verification component and combining it with a chip function detection configuration file to accurately and quickly detect chip functions during the chip IP verification stage. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a flowchart of a chip function testing method based on interconnect IP provided in an embodiment of the present invention. Detailed Implementation
[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0015] This invention provides a chip function testing method based on interconnect IP, such as... Figure 1 As shown, it includes:
[0016] Step S1: In the chip IP verification stage, obtain the nth combination A to be verified in the chip design. n And A n The corresponding chip function detection configuration file E n , where A n ={B n C n}, B n For the nth object to be verified, C n For the nth verification component, C n It includes a preset chip function detection module D. n If B n If it is a chip IP, then C n For simulation and B n Interactive IP verification component, if B n For interconnected IPs, then C n For simulation and B n Interactive chip IP verification component, E n Used to store A n The corresponding chip function detection configuration information, where n ranges from 1 to N, and N is the total number of combinations to be verified in the chip design.
[0017] It should be noted that in chip design, there may be an i-th combination A to be verified. i And the j-th group of unverified combinations A in integrated circuit design j B in i and B j For different instances of the same IP module, C i and C j For instances of the same bus verification component, if A i A corresponding chip function detection configuration file E has been established. i Then Aj E can be reused directly i As A j The corresponding detection configuration file E j This further improves the efficiency of chip function testing, where the values of i and j are both from 1 to N, and i ≠ j.
[0018] All C in the embodiments of the present invention n All are generated based on a pre-defined general verification component architecture, which includes components such as a driver, monitor, sequencer, and reference model, as well as a pre-defined chip function testing module D. n B n This corresponds to the Register Transfer Level (RTL) code of the object to be verified, in C. n It is used for simulation and B n A validation component for interactive objects, C n Able to simulate and B n The object of interaction to B n Send stimuli for simulation verification, D n Based on E n Perform chip function testing.
[0019] Steps S2 and C n To B n Send stimuli to perform simulation.
[0020] Steps S3 and D n Based on C n To B n Send incentives and E n Perform chip function testing; if an anomaly is detected, generate an anomaly message.
[0021] In step S3, if no abnormality is detected, then A n If the corresponding chip function test passes, an error message is generated if an anomaly is detected. The chip IP or interconnect IP can be modified during the chip IP verification stage based on the error message. In other words, the chip function test problem is solved in advance during the chip IP verification stage, reducing the chip integration iteration process in the SoC stage.
[0022] As one embodiment, the chip function detection configuration information includes a first chip function feature, and step S1 includes:
[0023] Step S11: Obtain the list of chip functions corresponding to the interaction between each chip IP and the interconnection IP.
[0024] It should be noted that the chip characteristics corresponding to the interaction between each chip IP and the interconnect IP are known information, so the list of chip functions corresponding to the interaction between each chip IP and the interconnect IP can be obtained directly.
[0025] Step S12: Obtain the nth group of combinations to be verified in the integrated circuit design A. n .
[0026] Step S13, B n and C n The feature in the chip function list corresponding to the interaction is set to E. n The first chip functional characteristics.
[0027] For example, B n and C n The chip function list corresponding to the interaction includes chip function feature 1, chip function feature 2, and chip function feature 3. Then, the corresponding E... n The first chip functional features are set as chip functional feature 1, chip functional feature 2 and chip functional feature 3.
[0028] As one embodiment, step S3 includes:
[0029] Steps S31 and D n Get C n To B n Send the stimulus for parsing to obtain the corresponding stimulus feature information.
[0030] Specifically, the incentive feature information may include address bit width, data bit width, and read / write attributes.
[0031] Steps S32 and D n Determine whether the corresponding incentive feature information conforms to E n The first chip functional characteristic in the diagram, if it meets the criteria, is E. n The first chip functional feature that matches the description is labeled with the first tag.
[0032] It should be noted that each chip functional feature has corresponding excitation feature information, and this information is known. Therefore, D n By obtaining C n To B n By sending the incentive feature information corresponding to the incentive, it can be determined whether the corresponding incentive feature information conforms to E. n The first chip functional characteristics. The first label is used to indicate that the corresponding first chip function has passed the test.
[0033] Steps S33 and C n To B n After sending the stimulus to complete the simulation, if E nAll first chip functional features have been labeled with the first tag, then A n If the corresponding chip functional feature detection passes, otherwise, based on E n An error message is generated for the first chip functional feature that does not have a first tag added.
[0034] It should be noted that, based on E n The abnormal prompt information generated by the first chip functional feature without the first tag can provide a reference for users to modify the chip IP or interconnect IP, making it easier for users to quickly and accurately modify the chip IP or interconnect IP.
[0035] To further improve the accuracy of chip function testing, as one embodiment, the chip function testing configuration information includes a first chip function feature and a second chip function feature, and step S1 includes:
[0036] Step C11: Obtain the chip function list corresponding to the interaction between each chip IP and the interconnection IP, and the chip function list corresponding to the interaction between each interconnection IP and all interconnected chip IPs.
[0037] Step C12: Obtain the nth group of combinations to be verified in the integrated circuit design. n .
[0038] Step C13, B n and C n The feature in the chip function list corresponding to the interaction is set to E. n The first chip functional feature in the A n The corresponding interconnect IP interacts with all interconnected chip IPs. The chip function list excluding B is used. n and C n Chip features other than those in the chip function list corresponding to the interaction are set to E. n The second chip functional characteristics.
[0039] It should be noted that the first chip's functional characteristic is A n The corresponding chip functional characteristics to be implemented, the second chip functional characteristic is A. n Correspondingly, chip function features that should not appear can be detected by simultaneously setting the first chip function feature and the second chip function feature. This can detect whether the chip function features that should be implemented appear, as well as whether the chip function features that should not appear but may appear erroneously, thus improving the accuracy of chip function detection.
[0040] For example, an interconnect IP connects to three chip IPs: chip IP 1, chip IP 2, and chip IP 3. The chip functions implemented through the interaction between chip IP 1 and the interconnect IP are chip function features 1, 2, and 3; the chip functions implemented through the interaction between chip IP 2 and the interconnect IP are chip function features 4 and 5; and the chip functions implemented through the interaction between chip IP 3 and the interconnect IP are chip function features 1 and 6. Therefore, the list of chip functions corresponding to the interaction between this interconnect IP and all interconnected chip IPs is chip function features 1, 2, 3, 4, 5, and 6. When A... n B in n For the first chip IP, C n For the verification component that interacts with the first chip IP, then E n The first chip functional characteristics are set as chip functional characteristic 1, chip functional characteristic 2, and chip functional characteristic 3, E n The second chip functional features are set as chip functional feature 4, chip functional feature 5 and chip functional feature 6.
[0041] As one embodiment, step S3 includes:
[0042] Steps C31 and D n Get C n To B n Send the stimulus for parsing to obtain the corresponding stimulus feature information.
[0043] Specifically, the incentive feature information may include address bit width, data bit width, and read / write attributes.
[0044] Steps C32 and D n Determine whether the corresponding incentive feature information conforms to E n The first chip functional characteristic in the diagram, if it meets the criteria, is E. n If the first chip functional feature matches the description, add a first tag and proceed to step C34. If it does not match, proceed to step C33.
[0045] It should be noted that each chip functional feature has corresponding excitation feature information, and this information is known. Therefore, D n By obtaining C n To B n By sending the incentive feature information corresponding to the incentive, it can be determined whether the corresponding incentive feature information conforms to E. n The first chip functional characteristics. The first label is used to indicate that the corresponding first chip function has passed the test.
[0046] Steps C33 and D nDetermine whether the corresponding incentive feature information conforms to E n If the second chip's functional characteristics are met, then it is E. n Add a second tag to the second chip functional characteristics that match the description, and execute step C34.
[0047] It should be noted that since the interaction IP involves multiple chip IPs, there is a possibility that incorrect stimuli may be issued based on the functional characteristics of other chip IPs. Therefore, step C33 can be used to further check whether it conforms to E. n The second chip functional characteristics are identified, and a second label is added to those that meet the second chip functional characteristics, thereby further improving the accuracy of chip function detection.
[0048] Step C34, if C n To B n Sending stimuli to complete the simulation and C n To B n If all the sent stimuli have been parsed, proceed to step C35; otherwise, return to step C31.
[0049] Step C35, if E n If all first-chip functional features have been labeled with the first tag and all second-chip features have not been labeled with the second tag, then A n If the corresponding chip functional feature detection passes, otherwise, based on E n The first chip functional characteristics without the first label and E n The second chip feature with the second tag is used to generate anomaly alert information.
[0050] It should be noted that, based on E n The first chip functional characteristics without the first label and E n Adding a second tag to the second chip feature generates anomaly prompts, which can provide users with a reference for modifying chip IP or interconnect IP, making it easier for users to quickly and accurately modify chip IP or interconnect IP.
[0051] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0052] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.
[0053] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.
[0054] This invention improves chip development efficiency by setting a chip function detection module in the verification component and combining it with a chip function detection configuration file to accurately and quickly detect chip functions during the chip IP verification stage.
[0055] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A chip function testing method based on Internet IP, characterized in that, include: Step S1: In the chip IP verification stage, obtain the nth combination A to be verified in the chip design. n And A n The corresponding chip function detection configuration file E n , where A n ={B n C n }, B n For the nth object to be verified, C n For the nth verification component, C n Generates based on a pre-defined general verification component architecture, which includes an exciter, monitor, sequencer, and reference model. n It also includes a preset chip function detection module D n If B n If it is a chip IP, then C n For simulation and B n Interactive IP verification component, if B n For interconnected IPs, then C n For simulation and B n Interactive chip IP verification component, E n Used to store A n The corresponding chip function testing configuration information, where n ranges from 1 to N, and N is the total number of combinations to be verified in the chip design, B n This corresponds to the register-transfer level code of the object to be verified, C. n It is used for simulation and B n A validation component for interactive objects, C n Able to simulate and B n The object of interaction to B n Send stimuli for simulation verification, D n Based on E n Perform chip function testing; Steps S2 and C n To B n Send stimuli to perform simulation; Steps S3 and D n Based on C n To B n Sending incentives and based on E n Perform chip function testing. If no abnormality is detected, then A n If the corresponding chip function test passes, an error message is generated if an error is detected. Based on the error message, the chip IP or interconnect IP is modified during the chip IP verification stage.
2. The method according to claim 1, characterized in that, The chip function detection configuration information includes a first chip function feature, and step S1 includes: Step S11: Obtain the chip function list corresponding to the interaction between each chip IP and the interconnection IP; Step S12: Obtain the nth group of combinations to be verified in the integrated circuit design A. n ; Step S13, B n and C n The feature in the chip function list corresponding to the interaction is set to E. n The first chip functional characteristics.
3. The method according to claim 2, characterized in that, Step S3 includes: Steps S31 and D n Get C n To B n Send the stimulus for parsing to obtain the corresponding stimulus feature information; Steps S32 and D n Determine whether the corresponding incentive feature information conforms to E n The first chip functional characteristic in the diagram, if it meets the criteria, is E. n Add a first tag to the first chip functional characteristics that match the description; Steps S33 and C n To B n After sending the stimulus to complete the simulation, if E n All first chip functional features have been labeled with the first tag, then A n If the corresponding chip functional feature detection passes, otherwise, based on E n An error message is generated for the first chip functional feature that does not have a first tag added.
4. The method according to claim 1, characterized in that, The chip function detection configuration information includes a first chip function feature and a second chip function feature. Step S1 includes: Step C11: Obtain the chip function list corresponding to the interaction between each chip IP and the interconnection IP, and the chip function list corresponding to the interaction between each interconnection IP and all interconnected chip IPs. Step C12: Obtain the nth group of combinations to be verified in the integrated circuit design. n ; Step C13, B n and C n The feature in the chip function list corresponding to the interaction is set to E. n The first chip functional feature in the A n The corresponding interconnect IP interacts with all interconnected chip IPs. The chip function list excluding B is used. n and C n Chip features other than those in the chip function list corresponding to the interaction are set to E. n The second chip functional characteristics.
5. The method according to claim 4, characterized in that, Step S3 includes: Steps C31 and D n Get C n To B n Send the stimulus for parsing to obtain the corresponding stimulus feature information; Steps C32 and D n Determine whether the corresponding incentive feature information conforms to E n The first chip functional characteristic in the diagram, if it meets the criteria, is E. n If the first chip functional feature matches, add a first tag and proceed to step C34; if it does not match, proceed to step C33. Steps C33 and D n Determine whether the corresponding incentive feature information conforms to E n If the second chip's functional characteristics are met, then it is E. n Add a second tag to the second chip functional characteristics that match the above, and execute step C34; Step C34, if C n To B n Sending stimuli to complete the simulation and C n To B n If all the sent stimuli have been parsed, proceed to step C35; otherwise, return to step C31. Step C35, if E n If all first-chip functional features have been labeled with the first tag and all second-chip features have not been labeled with the second tag, then A n If the corresponding chip functional feature detection passes, otherwise, based on E n The first chip functional characteristics without the first label and E n The second chip feature with the second tag is used to generate anomaly alert information.
6. The method according to claim 3 or 5, characterized in that, The stimulus characteristics include address bit width, data bit width, and read / write attributes.
7. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-6.
8. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-6.