Processing circuit, receiving circuit, laser radar and carrier

Abstract

The embodiment of the invention provides a processing circuit, a receiving circuit, a laser radar and a carrier. The processing circuit is used for the laser radar and is configured to obtain echo data of the laser radar and process the echo data. The processing circuit comprises a plurality of hosts, slaves and a transmission circuit, a plurality of hosts configured to obtain the echo data and store the echo data; the slave is configured to acquire the echo data stored by the plurality of hosts and process the echo data; a transmission circuit configured to transmit the echo data from the plurality of hosts to the slaves; the transmission circuit comprises a plurality of selection circuits which are connected in series, and the selection circuits are configured to conduct a plurality of transmission paths from a plurality of hosts to a plurality of slaves in a time-sharing mode. The processing circuit provided by the invention can reduce the occurrence of abnormal data processing problems, and improves the reliability of the laser radar.

Description

Technical Field

[0001] This disclosure relates to the field of optical detection technology, and more particularly to a processing circuit, a receiving circuit, a lidar, and a carrier. Background Technology

[0002] Optical detection technology uses light as a medium to detect objects. Compared to ordinary light sources, lasers have characteristics such as monochromaticity and good directionality, making them widely used for object detection. For example, LiDAR (Light Detection and Ranging) uses lasers to detect objects and has been applied in fields such as autonomous driving, drones, robot recognition, geographic mapping, and environmental monitoring.

[0003] LiDAR emits laser light during detection; when the laser encounters an object, it is reflected by the object's surface, forming an echo, which is received by the LiDAR. The LiDAR converts the received echo into echo data and processes this data to obtain information about the object. Ensuring that the LiDAR can correctly process the echo data and prevent malfunctions is a crucial means of improving its reliability. Summary of the Invention

[0004] This disclosure provides a processing circuit, a receiving circuit, a lidar, and a carrier to reduce the probability of echo data processing anomalies and improve the reliability of the lidar.

[0005] In a first aspect, a processing circuit is provided for a lidar system. The processing circuit is configured to acquire echo data from the lidar system and process the echo data. The processing circuit includes multiple master units, slave units, and a transmission circuit. The multiple master units are configured to acquire and store the echo data. The slave units are configured to acquire the echo data stored by the multiple master units and process the echo data. The transmission circuit is configured to transmit the echo data from the multiple master units to the slave units. The transmission circuit includes multiple selection circuits connected in series, and the multiple selection circuits are configured to time-division multiplely enable multiple transmission paths from the multiple master units to the slave units.

[0006] The above processing circuit uses multiple series-connected selection circuits to time-division multiple transmission paths from the master to the slave. Data stored by multiple master units can be transmitted to the slave unit in a time-division manner, and the slave unit can serially process the data stored by multiple master units to complete the processing of the LiDAR echo data. By distributing the timing pressure of the processing circuit through multiple series-connected selection circuits, the problem of slave units failing to accurately obtain echo data due to timing abnormalities, resulting in data processing anomalies, is reduced, thus improving the reliability of the LiDAR.

[0007] In one implementation, the plurality of selection circuits includes a first selection circuit, and the plurality of master devices includes the first master device. The first selection circuit and the first master device are coupled together. The first master device is configured to acquire and store first echo data. When the first selection circuit selects the first echo data stored by the first master device for output, the first echo data is output to the slave device through a first transmission path. The first transmission path includes the first selection circuit; the echo data includes the first echo data, and the plurality of transmission paths include the first transmission path.

[0008] Optionally, the first transmission path further includes a subsequent selection circuit of the first selection circuit. The first echo data is output to the slave device through the first selection circuit and the subsequent selection circuit of the first selection circuit. The subsequent selection circuit includes a selection circuit connected in series between the first selection circuit and the slave device.

[0009] In one implementation, the number of host circuits equals the number of select circuits. Setting the same number of select circuits as the number of host circuits facilitates the layout of both the select circuits and the host circuits, reducing chip design complexity. Furthermore, it simplifies wiring layout and further improves the top-level routing of the chip.

[0010] Optionally, the number of multiple hosts may be greater than the number of multiple selection circuits.

[0011] In one implementation, the selection circuit among the above plurality of selection circuits includes a multiplexer and a first flip-flop. The multiplexer includes at least one first input, a second input, a selection terminal, and an output terminal; the at least one first input is configured to be coupled to at least one of a plurality of hosts; the second input is configured to be coupled to the output terminal of a previous-level selection circuit or to a preset signal; the selection terminal is configured to select data from at least one first input and the second input terminal for output at the output terminal. The first flip-flop, coupled to the output terminal of the multiplexer and coupled to a clock signal, is configured to output data from the multiplexer output terminal according to the clock signal.

[0012] This selection circuit reduces the trace distance between the host and the multiplexer, as well as between two multiplexers in adjacent selection circuits. This helps to distribute the timing pressure on the processing circuit and reduce the problem of data not being transmitted correctly.

[0013] Optionally, the first flip-flops of multiple selection circuits can be coupled to a synchronous clock signal, which can enable each part of the transmission circuit to operate based on the synchronous clock signal, simplifying the timing design logic.

[0014] In one implementation, the slave device sends enable commands to multiple masters in a time-sharing manner. The multiple masters control multiple selection circuits to conduct multiple transmission paths from multiple masters to slave devices in a time-sharing manner according to the enable commands. The conducted transmission paths are the transmission paths from masters to slave devices enabled by the enable commands.

[0015] In one implementation, the transmission circuit further includes a delay circuit connected in series between two adjacent selection circuits. This delay circuit can further distribute timing pressure in the transmission path and reduce the impact of timing issues on the processing circuit.

[0016] Optionally, the delay circuit includes at least one second flip-flop connected in series.

[0017] In one implementation, multiple master units are distributed around the slave units. This helps reduce wiring complexity.

[0018] Optionally, multiple selection circuits may be distributed around the slave device.

[0019] Secondly, a receiving circuit is provided for lidar, the receiving circuit comprising:

[0020] A laser receiver is used to receive the echo of the laser emitted by the lidar and convert the echo into an electrical signal, which is used to generate echo data.

[0021] The processing circuit of the first aspect or any one of the first aspects is coupled to the laser receiver.

[0022] Thirdly, a lidar is provided, comprising: a laser transmitter for emitting a laser; a laser receiver for receiving the echo of the laser and converting the echo into an electrical signal, the electrical signal being used to generate echo data; and a processing circuit of the first aspect or any one thereof, coupled to the laser receiver, wherein a plurality of master units of the processing circuit are configured to distribute and store the echo data, and slave units of the processing circuit are configured to process the echo data.

[0023] Fourthly, a carrier is provided, comprising: a main body; and the lidar provided in the third aspect above, mounted on the main body.

[0024] Fifthly, an integrated circuit is provided, comprising: a first processing circuit according to the first aspect or any one of the first aspects; and a second processing circuit coupled to the first processing circuit and configured to receive echo information from the first processing circuit and process the echo information, wherein the echo information is obtained by the first processing circuit processing the echo data. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be provided as examples below. The accompanying drawings described below are merely embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. The accompanying drawings are used to provide a further understanding of the embodiments of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain this disclosure and do not constitute a limitation of this disclosure.

[0026] Figure 1 An example diagram of a lidar provided in some embodiments of this disclosure is shown.

[0027] Figure 2 An example diagram of a processing circuit provided in some embodiments of this disclosure is shown.

[0028] Figure 3 An example diagram of another processing circuit provided in some embodiments of this disclosure is shown.

[0029] Figure 4 An example diagram of yet another processing circuit provided in some embodiments of this disclosure is shown.

[0030] Figure 5 An example diagram of yet another processing circuit provided in some embodiments of this disclosure is shown.

[0031] Figure 6 An example diagram of yet another processing circuit provided in some embodiments of this disclosure is shown.

[0032] Figure 7 An example diagram of yet another processing circuit provided in some embodiments of this disclosure is shown.

[0033] Figure 8 An example of an echo signal during a single detection process of a lidar provided in some embodiments of this disclosure is shown.

[0034] Figure 9 An example diagram of a selection circuit provided in some embodiments of this disclosure is shown.

[0035] Figure 10 An example diagram of a transmission circuit provided in some embodiments of this disclosure is shown. Detailed Implementation

[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the specific implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0037] To keep the drawings simple, each figure only schematically shows the parts related to the corresponding embodiment, and they do not represent the actual structure of the product. In addition, for the sake of simplicity and ease of understanding, the figures schematically illustrate some structures or components, and there may be more or fewer similar structures or components in reality.

[0038] LiDAR (Light Detection and Ranging) uses laser light as a medium to detect objects and has found applications in a growing number of fields. For example, it is used in intelligent driving (also known as autonomous driving or assisted driving, including any level of autonomous driving, such as L1-L5), drones, robot recognition, geographic mapping, and environmental monitoring. During detection, LiDAR emits a laser beam; when the laser encounters an object, it is reflected by the object's surface, forming an echo, which is received by the LiDAR. The LiDAR converts the received echo into echo data and processes this data to obtain information about the object, such as its distance, position, or velocity, or even its three-dimensional structure.

[0039] LiDAR can be installed on the main body of vehicles such as vehicles, ships, aircraft (e.g., flying vehicles or drones), robots (e.g., industrial robots or household robots), and surveying equipment. For example, in intelligent driving scenarios, vehicles are equipped with LiDAR. As the vehicle moves, the LiDAR can detect the surrounding environment, obtain perception data (e.g., point cloud data), and provide it to the vehicle so that the vehicle can make decisions or control based on the perception data.

[0040] This disclosure does not limit the type of lidar. For example, the lidar may include mechanical lidar, semi-solid-state lidar, or solid-state lidar. Semi-solid-state lidar may include, for example, microelectromechanical system (MEMS) lidar, rotating mirror lidar, or prism lidar. Solid-state lidar may include, for example, optical phase array (OPA) lidar or flash lidar.

[0041] Please refer to Figure 1The diagram illustrates an example of a lidar provided in some embodiments of this disclosure. Figure 1 As shown, the lidar 100 includes a laser emitter 110, a laser receiver 120, an optical assembly 130, and at least one processing circuit. During the detection process of the lidar 100, the laser emitter 110 emits a laser. The laser is emitted through the optical assembly 130 and, upon encountering an object 10, is reflected by the surface of the object 10. Part of the reflected light (which can be called the echo) is received by the laser receiver 120 through the optical assembly 130 and converted into an electrical signal. After the electrical signal is processed by at least one processing circuit, information about the object, such as point cloud data, is obtained.

[0042] Laser emitter 110 may include at least one laser. LiDAR 100 may also include a driving circuit (also known as an excitation source) 140 and a control circuit 150; the driving circuit 140 drives the laser to emit laser light under the control of the control circuit 150, achieving pulsed laser emission. The laser may include, for example, a semiconductor laser, a fiber laser, or other types of lasers. Semiconductor lasers may include, for example, laser emitting circuits, vertical cavity surface emitting lasers (VCSELs), edge emitting lasers (EELs), distributed feedback lasers (DFBs), or similar devices. The above are merely examples, and the embodiments disclosed herein do not limit the type of laser.

[0043] The laser receiver 120 may include at least one detector; the detector may convert the received optical signal into an electrical signal using the photoelectric effect. The detector may include, for example, a photodetector circuit, a pin photodiode (PINPD), an avalanche photodiode (APD), a single-photon avalanche diode (SPAD), a silicon photomultiplier (SiPM), or similar devices. The above are merely examples, and the embodiments disclosed herein do not limit the type of detector.

[0044] Optical component 130 is used in the laser emission path to shape the laser emitted by laser emitter 110 and adjust the laser's exit path; in the laser receiving path, it is used to collect the echo reflected back by object 10 and converge the echo onto the photosensitive surface of laser receiver 120. Optical component 130 includes optical elements (which may be referred to as emitting optical elements) in the emission path and optical elements (which may be referred to as receiving optical elements) in the receiving path, and the optical elements in the emission path and the optical elements in the receiving path can be independent, partially multiplexed, or fully multiplexed. For example, optical component 130 may include independent emitting optical elements; for example, emitting optical elements include one or more optical elements such as emitting lenses, homogenizers, and beam splitters. As another example, optical component 130 may include independent receiving optical elements; for example, receiving optical elements include one or more optical elements such as receiving lenses and filters. Yet another example, optical component 130 may include optical elements that multiplex the receiving and emission paths; for example, multiplexed optical elements include one or more optical elements such as lens groups or scanning mirrors.

[0045] The processing of the electrical signal converted by the laser receiver 120 may include one or more of the following operations: preprocessing the electrical signal to obtain echo data (or response data), analyzing the echo data to extract echo information, acquiring point cloud data based on the echo information, and assembling the point cloud data, etc. At least one processing circuit may include, for example, a preprocessing circuit 160 and a data processing circuit 170. The preprocessing circuit 160 is used, for example, to preprocess the electrical signal to obtain echo data. The data processing circuit 170 is used, for example, to analyze the echo data to extract echo information, acquire point cloud data based on the echo information, and assemble the point cloud data, etc.

[0046] Preprocessing may include, for example, analog front-end processing, such as amplification, filtering, digitization, or one or more of these processes. The preprocessing circuit 160 may also be called an analog front-end circuit; for example, it may include one or more of amplification circuits, filtering circuits, and digitization circuits. The amplification circuit may include, for example, an amplifier used to amplify the electrical signal converted from the laser receiver 120. This can improve the signal-to-noise ratio. The filtering circuit may include, for example, a filter used to filter out noise or interference. The digitization circuit may include, for example, an analog-to-digital converter (ADC) or a time-to-digital converter (TDC). For example, the ADC converts the analog electrical signal into a digital signal representing the echo waveform by periodically sampling the output data of the laser receiver 120, obtaining echo data; this echo data may include data representing the echo time and / or echo intensity. For example, the laser echo is converted into an electrical signal by the laser receiver 120. This electrical signal can be converted (e.g., converted and amplified into a voltage, and compared with a reference voltage to generate an over-threshold signal to determine whether there is light incident) and provided to the TDC. The TDC performs timing based on the received electrical signal to measure the arrival time of the echo and obtain echo data. This echo data may include data reflecting the echo time and / or echo intensity.

[0047] Preprocessing may include, for example, histogram processing, which superimposes the electrical signals converted by the laser receiver 120 to obtain histogram data. This histogram data can be stored as echo data.

[0048] The processing of echo data can be achieved through a single data processing circuit or through multiple data processing circuits in a hierarchical (or phased) manner. For example, the lidar 100 includes a data processing circuit 170 for processing the echo data to obtain point cloud data and assembling the point cloud data into packets. As another example, the lidar 100 includes data processing circuits 171 and 172; wherein, data processing circuit 171 performs a first processing on the echo data and provides the processing result to data processing circuit 172; data processing circuit 172 performs a second processing on the processing result to obtain point cloud data packets. This disclosure does not limit the specific content of the first and second processing, that is, this disclosure does not limit the division of the echo data processing process on data processing circuits 171 and 172. For example, in some embodiments of this disclosure, the first processing circuit 171 analyzes the echo data to extract echo information and provides the echo information to the second processing circuit 172; the second processing circuit 172 obtains point cloud data based on the echo information and assembles the point cloud data into packets. For example, in some other embodiments of this disclosure, the first processing circuit 171 is used to analyze the echo data, extract echo information, and obtain point cloud data based on the echo information; the second processing circuit 172 is used to integrate the point cloud data obtained by the first processing circuit 171 and package the point cloud data. The first processing circuit 171 can also be called a front-end processing circuit, and the second processing circuit 172 can also be called a back-end processing circuit. By performing hierarchical processing of the echo data, the complexity of each processing circuit can be reduced, and the processing efficiency of the echo data can be improved.

[0049] Echo data may include one or more of the following: time or intensity. Data processing circuits 170 or 171 can analyze the echo data to obtain echo information. For example, data processing circuits 170 or 171 perform waveform analysis on the echo data to obtain one or more of the following information: peak value of the echo pulse, number of echo pulses, intensity of the echo pulse, arrival time of the echo pulse, pulse width of the echo pulse, slope of the echo pulse, area of ​​the echo pulse, etc. Data processing circuits 170 or 172 determine the generation of point cloud data based on the echo information. For another example, data processing circuits 170 or 171 determine the flight time based on time data, use the flight time to determine the distance information of the object, and the echo information may include the distance information; or data processing circuits 170 or 171 determine the flight time based on time data, use the flight time to determine the distance information of the object, and determine the position information of the object based on the distance information, and the echo information may include the position information. This disclosure does not limit the specific content of the echo information; the content of the echo information may differ depending on the processing operation performed by data processing circuit 171.

[0050] In some embodiments of this disclosure, the echo data may include histogram data. Optionally, data processing circuitry 170 or 171 may perform convolution calculations on the histogram data and analyze the convolution results to extract echo information.

[0051] Optionally, the processing circuit 170 or 171 can also perform one or more operations to improve the quality of the echo data, such as calibration or noise reduction. For example, it can perform one or more of the following operations: echo calibration, distance calibration, intensity calibration, ambient light calibration, high crosstalk filtering, ghost image filtering, etc. Optionally, the processing circuit 170 or 171 can also perform one or more operations such as receiving position offset feedback or adjusting light intensity feedback.

[0052] Data processing circuits 170, 171, or 172 may, for example, include one or more processors. Processors may include, for example, application-specific integrated circuits (ASICs), or programmable logic device (PLD) circuits, such as field-programmable gate arrays (FPGAs), or microcontroller units (MCUs), or digital signal processors (DSPs), or central processing units (CPUs), etc. For example, data processing circuit 171 may include a DSP, data processing circuit 172 may include one or more of FPGAs and MCUs; or, data processing circuit 170 may include both an FPGA and an MCU. This disclosure does not limit the number or type of processors included in the data processing circuits. Different data processing circuits may include processors of the same type or different types.

[0053] At the laser receiver, the laser receiving circuit 120, preprocessing circuit 160, and data processing circuit 170 can be fully or partially integrated together, or set up independently. Alternatively, the laser receiving circuit 120, preprocessing circuit 160, data processing circuit 171, and data processing circuit 172 can be fully or partially integrated together, or set up independently. For example, the laser receiving circuit 120 and preprocessing circuit 160 are integrated together; or the laser receiving circuit 120, preprocessing circuit 160, and data processing circuit 170 are integrated together; or the laser receiving circuit 120, preprocessing circuit 160, and data processing circuit 171 are integrated together; or the laser receiving circuit 120, preprocessing circuit 160, data processing circuit 171, and data processing circuit 172 are integrated together. In some embodiments, when multiple data processing circuits are integrated, they can be implemented in the form of a system on chip (SOC). The control circuit 150 at the laser emitter can be set up independently or integrated with the data processing circuit at the laser receiver. For example, in some embodiments of this disclosure, the control circuit 150 may be integrated with the data processing circuits 170 or 172.

[0054] The data processing circuit may also include a memory. During lidar detection, the electrical signal converted by the laser receiver is converted into echo data and stored in the memory. The processor retrieves the echo data from the memory and processes it. The memory can be configured as multiple storage circuits, distributed in a layout that facilitates the reading of echo data from the laser receiver and reduces the wiring complexity of the readout circuit. Multiple storage circuits provide echo data to the processor, which processes data from one storage circuit at a time. During processing, if there is a timing problem in the transmission of data from a certain storage circuit and the data fails to reach the processor in time, the processor will experience data processing anomalies, thus affecting the reliability of the lidar. This disclosure provides a processing circuit applicable to any of the above data processing circuits. By designing the transmission circuit of the processing circuit, the timing problem in the echo data transmission process is solved, improving the reliability of the lidar.

[0055] The processing circuit is described below with reference to the accompanying drawings.

[0056] Please refer to Figure 2 This illustrates an example diagram of a processing circuit provided in some embodiments of the present disclosure. For example... Figure 2As shown, the processing circuit 200 includes multiple masters, such as masters 1-N (where N is a positive integer greater than 1), and a slave 210. Masters 1-N are configured to acquire and store echo data. Slave 210 is used to acquire the echo data stored by masters 1-N and process the echo data. Masters 1-N may include, for example, static random-access memory (SRAM) or dynamic random-access memory (DRAM). DRAM may include, for example, synchronous dynamic RAM (SDRAM) or double-data-rate SDRAM (DDR). DDR may include, for example, DDR1, DDR2, DDR3, ..., DDR5, and with technological advancements, may also include DDR6. Slave 210 may include, for example, a processor, the type of which is as described above and is not limited in this disclosure.

[0057] Slave device 210 can acquire and process data from hosts 1-N serially, for example, processing data from one host i (i∈[1,N]) at a time. See the example below. Figure 3 This illustrates an example diagram of another processing circuit provided in some embodiments of this disclosure. For example... Figure 3 As shown, the processing circuit includes host 1-N, slave 310, and multiplexer MUX. The multiplexer has N input terminals, which are respectively used to connect to host 1-N; under the control of selection signal C, the signal of one input terminal is selected and output to slave 310.

[0058] In chip design, master units 1-N can be distributed around slave units 310. Master units 1-N are used to store echo data generated by the laser receivers, and readout lines can be set between master units 1-N and the laser receivers. Depending on the distribution of the laser receivers, for example, multiple laser receivers are distributed in a two-dimensional manner, and master units 1-N can be distributed in a dispersed manner, which can help reduce the complexity of the readout lines. Distributing multiple master units 1-N around slave units 310 can also reduce the routing complexity between master and slave units. Optionally, master units 1-N can be distributed closer to the edge of the chip. The edge of the chip has power supply terminals, and placing master units 1-N closer to the power supply terminals can reduce the impact of unwanted voltage drops on master units 1-N. With the development of technology and the increasing demand for detection, the chip area is increasing step by step. When the chip area is large, the routing distance between master units 1-N and slave units 310 is long, which poses challenges to the top-level routing and timing of the chip.

[0059] Figure 3The processing circuit shown selects data from master i at the slave 310 input via a multiplexer MUX, enabling slave 310 to serially process data from masters 1-N. The data output from the multiplexer MUX can be stored in a register. When slave 310 reads data from master i, it retrieves the data from the register. This circuit structure may encounter timing issues. For example, this circuit structure may not ensure that data from each master arrives at the register according to the predetermined timing. For instance, a master far from the slave may not arrive at the register before its setup time, causing the slave to fail to correctly read the echo data. For example, if some master i (e.g., one of masters 2-4) is far from the multiplexer MUX, and slave 310 will read data from master i at time t1, if the trace between master i and the multiplexer MUX is long, and the data transmitted by master i cannot arrive at the register before time t1, then slave 310 will fail to correctly read the data transmitted by master i at time t1, resulting in a timing problem. The aforementioned timing issues may cause echo data loss or receive echo data that does not match expectations, thereby affecting the normal operation of the processing circuit and reducing the reliability of the lidar. Furthermore, the dense wiring at the entry point of slave unit 310 still presents some top-level wiring problems.

[0060] Based on this, embodiments of this disclosure provide another processing circuit. By designing the transmission circuit of the processing circuit, the timing issues of the data transmission circuit are improved, thereby enhancing the reliability of the LiDAR. Furthermore, the processing circuit of embodiments of this disclosure can optimize circuit routing, further improving the top-level winding problem of the chip and enhancing the performance of the LiDAR chip. The following description is in conjunction with the accompanying drawings.

[0061] Please refer to Figure 4 This diagram illustrates an example of another processing circuit provided in some embodiments of the present disclosure. The processing circuit 400 can be used with a lidar and is configured to acquire and process the lidar echo data. The processing circuit 400 can, for example, be the data processing circuits 170 or 171 described above. The processing circuit 400 can be coupled to the lidar's laser receiver; the laser receiver receives the echo and converts it into an electrical signal, which is used to generate echo data. Figure 4As shown, the processing circuit 400 includes multiple master units 410, slave units 420, and a transmission circuit 430. The multiple master units, such as master units 1-N, are configured to acquire and store echo data. Slave units 420 are configured to acquire the echo data stored by master units 1-N and process the echo data. The transmission circuit 420 is configured to transmit echo data from master units 1-N to slave units 420. The transmission circuit 430 includes multiple selection circuits connected in series, such as selection circuit 1-M (where M is a positive integer greater than 1 and M is less than or equal to N), and selection circuit 1-M is configured to time-division multiple transmission paths from master units 1-N to slave units 420.

[0062] In the above processing circuit, multiple series-connected selection circuits are used to time-division multiple transmission paths from the master unit 410 to the slave unit 420, allowing data stored by the multiple master units 410 to be transmitted to the slave unit 420 in a time-division manner. The slave unit 420 can serially process the data stored by the multiple master units 410 to complete the processing of the LiDAR echo data. The series-connected selection circuits distribute the timing pressure on the processing circuit, reducing the problem of the slave unit 420 failing to accurately obtain echo data due to timing abnormalities, thus improving the reliability of the LiDAR.

[0063] For example, the host i (i∈[1,N]) is far from the slave 420, and the host i and slave 420 are connected by at least one selection circuit. Compared to the routing distance between host i and slave 420, the routing distance between host i and the selection circuit j (i∈[1,M]) coupled to host i is shorter. Data from host i can be transmitted to selection circuit j while meeting timing requirements, allowing selection circuit j to select the data from host i to be transmitted to slave 420. Since at least one selection circuit jM distributes the timing pressure from host i to slave 420, transmissions that do not meet timing requirements are greatly reduced, thereby improving the timing issues of the processing circuit, alleviating data processing anomalies caused by timing abnormalities in slave 420, and improving the reliability of the lidar. For example, taking host 1 as an example, host 1 is connected to slave 420 through selection circuit 1-M. Selection circuit 1-M sequentially selects and conducts data from host 1, realizing the transmission of data from host 1 to slave 420. Multiple selection circuits are configured to time-division multiple transmission paths from master to slave. Data stored in master 1-N can be time-division transmitted to slave 420, enabling slave 420 to perform serial processing of echo data.

[0064] Multiple selection circuits connected in series mean that the output of one selection circuit is used as the input of the next selection circuit. For example, the output of selection circuit 1 is used as an input of selection circuit 2; the output of selection circuit 2 is used as an input of selection circuit 3; and so on, with the output of selection circuit M-1 used as an input of selection circuit M. At least one first input terminal of selection circuit 1 is coupled to at least one host, and its second input terminal is coupled to a preset signal S. This preset signal S is, for example, a low-level signal by default. At least one first input terminal of selection circuit j (starting from j=2) is coupled to at least one host, and its second input terminal is coupled to the output terminal of the previous selection circuit. The number of hosts coupled to different selection circuits can be the same or different.

[0065] The echo data of the lidar can be distributed and stored in multiple hosts 1-N. The host i currently being read by the slave is called the first host, and the data stored in host i is called the first echo data; therefore, the lidar echo data includes the first echo data. The selection circuit j coupled to host i is called the first selection circuit. The first host is configured to acquire and store the first echo data. When the first selection circuit selects the first echo data stored by the first host for output, the first echo data is output to slave 420 through a first transmission path. This first transmission path includes the first selection circuit. Alternatively, the first transmission path includes the first selection circuit and a subsequent selection circuit of the first selection circuit, and the first echo data is output to slave 420 through the first selection circuit and the subsequent selection circuit of the first selection circuit. The subsequent selection circuit includes a selection circuit connected in series between the first selection circuit and slave 420.

[0066] For example, the first host is host 1, the first selection circuit is selection circuit 1, and the subsequent selection circuit includes selection circuit 2-M; the first transmission path includes selection circuit 1-M. The first echo data stored by host 1 is output to slave 420 through the first transmission path (including selection circuit 1-M). For example, the first host is host 2, the first selection circuit is selection circuit 2, and the subsequent selection circuit includes selection circuit 3-M; the first transmission path includes selection circuit 2-M. The first echo data stored by host 2 is output to slave 420 through the first transmission path (including selection circuit 2-M). For example, the first host is host N, the first selection circuit is selection circuit M; the first transmission path includes selection circuit M. The first echo data stored by host N is output to slave 420 through the first transmission path (including selection circuit M). The above multiple transmission paths include multiple first transmission paths from host 1-N to slave 420.

[0067] The processing circuits provided in the above embodiments can also be used in other devices, which include multiple distributed hosts. Data from the hosts is transmitted to slave devices via similar transmission circuits for processing. A host is, for example, the initiator of communication, and a slave is, for example, the responder of communication. This disclosure does not limit the type of host; for example, it may include a processing circuit (or processor), a storage circuit (or memory), or a control circuit (or controller). Similarly, this disclosure does not limit the type of slave device; for example, it may include a processing circuit (or processor), a storage circuit (or memory), or a control circuit (or controller).

[0068] This disclosure does not limit the number of main units; in practical use, the number can be set as needed. For example, in a lidar system, the number of main units can be set based on one or more of the following factors: the number of detectors, the detector arrangement, the complexity of the wiring, the processing power of the slave units, and the power consumption of the slave units. This disclosure also does not limit the storage space size (or storage capacity) of the main units, and the storage space sizes of different main units can be the same or different.

[0069] The slave and master devices can communicate via a bus, and the communication can be unidirectional or bidirectional. This disclosure does not limit the protocol followed by the bus transmission; it can be a general protocol, such as the Advanced Microcontroller Bus Architecture (AMBA) bus, CoreConnect bus, Wishbone bus, Avalon bus, or TileLink bus, or it can be a custom protocol.

[0070] Buses may include one or more of the following: data bus, address bus, and control bus. A data bus can be used to transmit data. An address bus can be used to transmit address information. A control bus can be used to transmit control signals. The read time of different masters can be controlled via the control bus. For example, in AXI bus transmission on an AMBA bus, master i and slave 420 can establish communication through a handshake mechanism. For instance, master i prepares for data communication (including sending or receiving) before slave 420; the master's handshake signal (VALID) reaches a valid value (e.g., high level) before the slave 420's handshake signal (READY). When the slave 420's handshake signal (READY) reaches a valid value (e.g., high level), the handshake between master i and slave 420 is completed, and data transmission begins. For example, slave device 420 prepares for data communication before master device i; slave device 420's handshake signal (READY) reaches a valid value (e.g., high level) before master device 420's handshake signal (VALID). When master device 420's handshake signal (VALID) reaches a valid value (e.g., high level), master device i and slave device 420 complete the handshake and begin data transmission. Alternatively, master device i and slave device 420 may prepare for data communication simultaneously; master device 420's handshake signal (VALID) and slave device 420's handshake signal (READY) both reach valid values ​​(e.g., high level), and data transmission begins.

[0071] In some embodiments of this disclosure, the handshake signal (READY) of the slave device 420 can be enabled by default, and data transmission can be achieved by controlling the handshake signal (VALID) of the master device i. This simplifies the control logic for data transmission. Embodiments of this disclosure do not limit the bus type between the master and slave devices. Data transmission implementation differs for different bus types, and this disclosure does not impose limitations on this.

[0072] In some embodiments of this disclosure, the slave device 420 can transmit an enable command to the master device i. This enable command can be used to control the master device i to enter an enabled state. For example, when the enable command is a high-level signal, the master device i enters the enabled state after receiving the enable command and transmits data to the slave device 420. For example, taking an AXI bus as an example, the enable command can be used to control the handshake signal (VALID) of the master device i. When the enable command controls the master device i to enter the enabled state, the handshake signal (VALID) of the master device i is a valid value.

[0073] Slave device 420 can send enable commands to hosts 1-N according to a set timing sequence. When slave device 420 asynchronously processes data from multiple hosts, it will not send enable commands to multiple hosts simultaneously. When slave device 420 can process data from at least two hosts simultaneously, it can send enable commands to at least two hosts simultaneously.

[0074] In some embodiments of this disclosure, the number of selection circuits M and the number of hosts N are the same, such as... Figure 4 As shown, the selection circuit includes two input terminals. The first input terminal of selection circuit 1 is coupled to host 1, and the second input terminal is coupled to a preset signal S. The first input terminal of selection circuit j (starting from j=2) is coupled to host i (i=j), and the second input terminal is coupled to the output terminal of the previous stage selection circuit j-1. Setting the same number of selection circuits in the processing circuit as the host can facilitate the layout of the selection circuits and the host, reducing the complexity of the chip design; it can also simplify the wiring layout and further improve the top-level routing of the chip. For example, please refer to... Figure 5 This illustrates an example diagram of yet another processing circuit provided in some embodiments of this disclosure. For example... Figure 5 As shown, the processing circuit 500 includes the same number of selection circuits as the host. The first input of selection circuit 531 is coupled to host 511, and the second input is coupled to a preset signal S (e.g., a low-level signal). The output of selection circuit 531 is coupled to the second input of selection circuit 532. The first input of selection circuit 532 is coupled to host 512. Similarly, the first input of selection circuit 538 is coupled to host 518, and the second input is coupled to the output of selection circuit 537. The output of selection circuit 538 is coupled to slave 520. Thus, during the transmission time of host 511, selection circuit 531 selects the signal output from the first input, while other selection circuits 532-538 select the signal output from the second input. Data from host 511 can be transmitted to slave 520 through selection circuits 531-538. Similarly, during the transmission time of host 512, selection circuit 532 selects the signal output of the first input terminal, and subsequent selection circuits 533-538 select the signal output of the second input terminal. Data from host 512 can be transmitted to slave 520 through selection circuits 532-538. Likewise, during the transmission time of host 518, selection circuit 538 selects the signal output of the first input terminal, and data from host 518 can be transmitted to slave 520 through selection circuit 538. This disclosure does not limit the output of the preceding selection circuit; for example, during the transmission time of host 512, selection circuit 531 can select to enable or disable the data from the first or second input terminal for output.

[0075] The above-described series selection circuit design results in shorter trace distances between the host and the selection circuit, as well as between the two selection circuits, and shorter data transmission times. This allows data to be delivered to the next stage while meeting timing requirements, thereby distributing the timing pressure of the processing circuit to multiple selection circuits and greatly reducing the probability of data transmission failures caused by timing issues.

[0076] Figure 5Although the example uses eight main units and selection circuits, it is merely an example and not intended to limit this disclosure. In practice, it may include more or fewer selection circuits or main units.

[0077] In some other embodiments of this disclosure, the number M of selection circuits may be less than the number N of hosts. For example, some or all of the selection circuits may be connected to two or more hosts and select the data output of different hosts at different times. For example, please refer to... Figure 6 This diagram illustrates an example of another processing circuit provided in some embodiments of the present disclosure. The processing circuit 600 includes host 1-N, slave 620, and transmission circuitry 630. Figure 4 The difference in the illustrated embodiment is that the selection circuit 1 of the transmission circuit 630 can be coupled to two hosts, such as host 1 and 2. Selection circuit 1 can select the data output of host 1 and host 2 at different times. For example, please refer to... Figure 7 This diagram illustrates an example of another processing circuit provided in some embodiments of the present disclosure. The processing circuit 700 includes host 1-N, slave 720, and transmission circuitry 730. Figure 4 The difference in the illustrated embodiment is that the selection circuit may include more input terminals for coupling to more hosts. For example, selection circuit j includes three input terminals, where selection circuit 1 is coupled to three hosts, such as hosts 1-3; selection circuit 2-M is coupled to two hosts, such as selection circuit 2 coupled to hosts 4 and 5; and selection circuit M is coupled to hosts N-1 and N. The figure only uses three input terminals as an example; in practice, there may be more or fewer input terminals, and the number of input terminals for different selection circuits may be the same or different, that is, the number of hosts coupled may be the same or different.

[0078] In a lidar system, the host device can be understood as a memory that stores echo data. The lidar's laser receiver may include multiple detectors, and the host device can be coupled to one or more detectors to store their echo data. In some embodiments of this disclosure, the host device can be coupled to the detectors via preprocessing circuitry. The electrical signals generated by the detectors are preprocessed to obtain echo data, which is then stored in the host device. In some embodiments of this disclosure, the echo data may include histogram data of the electrical signals generated by the detectors, and the host device can perform histogram data storage.

[0079] When storing data, the host can store data from one detector or data from multiple detectors. The stored data can carry the identifier of the corresponding detector, allowing for data stitching based on this identifier during subsequent data processing. For example, echo information or point cloud data can be stitched together based on the detector identifier. This disclosure does not limit the implementation of the detector identifier, as long as it can uniquely identify the detector in the laser receiver. For example, the laser receiver of a lidar includes a detector array; when the detector array is a two-dimensional array, the identifier can include the row and column number of the detector within the array; when the detector array is a one-dimensional array, the identifier can include either the row or column number of the detector within the array.

[0080] In some embodiments of this disclosure, multiple detectors can perform detection in parallel. The echo data generated by the multiple detectors performing parallel detection can be stored separately in host 1-N. Multiple detectors performing parallel detection can correspond to the same sub-field of view or different sub-fields of view. For example, the field of view of a lidar can be divided into multiple sub-fields of view. The lidar can perform independent detection on each sub-field of view. For example, the detection of multiple sub-fields of view can be performed in a time-division manner. For instance, sub-field of view A is scanned in the first detection period, and sub-field of view B is scanned in the second detection period. Alternatively, some sub-fields of view can be detected in parallel. For instance, sub-fields of view A and B are scanned in the first detection period, and sub-fields of view C and D are scanned in the second detection period, and sub-fields of view C and D can be detected in parallel. Furthermore, multiple sub-fields of view can be grouped, with parallel detection performed on sub-fields of view within the same group, and time-division detection performed on sub-fields of view in different groups.

[0081] When a lidar system detects a sub-field of view, it can perform multiple scans. During a single scan, the emitting area can emit one or more laser pulses, which, upon reflection from an object, generate echoes. Multiple laser pulses reflected from an object produce multiple echoes, which are then converted into multiple electrical signals by corresponding detectors. These multiple electrical signals can be accumulated, resulting in an increased amplitude of the echo signal while averaging out ambient light and other noise. This improves the quality of the echo signal and reduces noise interference. For an example, please refer to [reference needed]. Figure 8 This illustrates an example of the echo signal during a single detection process of a lidar provided in some embodiments of this disclosure. For example... Figure 8 As shown, the lidar performed K scans in a single detection. Figure 8 As shown on the left, a laser pulse is emitted during one scan. Figure 8As shown on the right, the electrical signals obtained by the detector are accumulated for these K scans to obtain the echo signal. The echo signal can be stored in the host in the form of histogram data. This disclosure does not limit the number of scans K; for example, it can be 400-500 times, or even thousands of times, or more or fewer.

[0082] This disclosure does not limit the storage method of histogram data of multiple detectors in the host. For example, the histogram data of the detection area (which may include one or more detectors) corresponding to a sub-field of view can be stored in one host or distributed across multiple hosts. The histogram data of the detection areas corresponding to different sub-fields of view can be stored in different hosts or in the same host. As another example, in the detection areas (which may include multiple detectors) corresponding to a sub-field of view being scanned in parallel, the histogram data of some detection areas can be stored in some hosts of multiple hosts, while the histogram data of other detection areas can be stored in other hosts of multiple hosts. For example, a first detection area and a second detection area are scanned in parallel. The histogram data of the detectors in the first detection area can be stored in multiple hosts 411-41x, and the histogram data of the detectors in the second detection area can be stored in hosts 41y-41N. Where y = x + 1, and both x and y are less than N. For example, When N is odd, x can be... Round up or down.

[0083] The slave device, for example, includes a processor and is configured to acquire echo data stored in multiple host machines, process the echo data, and obtain a processing result. The processing result may include echo information or point cloud data, the echo information being described as in the above embodiments. In some embodiments, the processing circuit can provide the processing result from the slave device to a subsequent processing circuit. For example, the processing circuit is a data processing circuit 171, and the subsequent processing circuit is a data processing circuit 172. Optionally, the slave device can provide the echo information to the subsequent processing circuit, which can then calculate point cloud data based on the echo information. Alternatively, the slave device can determine the echo information based on the echo data, calculate point cloud data based on the echo information, and provide the point cloud data to the subsequent processing circuit, which can then generate complete point cloud data and perform packetization and transmission of the point cloud data. For example, a slave device can perform point cloud computing based on the histogram data of a detector to obtain the echo information of a point (e.g., including one or more of waveform, pulse width, slope, leading edge time, amplitude, distance, or intensity information); it then transmits this echo information to a subsequent processing circuit (e.g., data processing circuit 172); the subsequent processing circuit obtains point cloud data based on the echo information, for example, calculates position information based on distance information, and stitches together the point cloud data from multiple master devices. Alternatively, after calculating the point cloud data for its corresponding detector, the slave device transmits the point cloud data to the subsequent processing circuit; the subsequent processing circuit then stitches and packages the point cloud data for transmission. For example, after calculating the point cloud data for its corresponding detector, the slave device stitches the point cloud data and transmits it to the subsequent processing circuit; the subsequent processing circuit then packages and transmits the point cloud data.

[0084] The selection circuit can time-division multiple master-to-slave transmission paths. Time-division means activating different master-to-slave transmission paths at different times. For example, the first master-to-slave transmission path can be activated at a first time, and the second master-to-slave transmission path at a second time. This disclosure does not limit the activation order of the transmission paths, that is, it does not limit the order in which the slave reads data stored by the master. For example, see [reference needed]. Figures 4-7 Data can be read from the host machine in sequential order of its serial numbers, or it can read data from the host machine out of order. For example, after reading data from host 1, the slave machine can read data from host n (where n is any value from 3 to N). In short, different reading orders can be set as needed, and this disclosure does not impose any restrictions.

[0085] In some embodiments of this disclosure, multiple selection circuits can time-divisionally activate the above multiple transmission paths under the control of the slave device. For example, when the slave device sends an enable command to the master device i, it can also send a first control signal to the selection circuit corresponding to the master device i (referred to as the first selection circuit for distinction), and a second control signal to the subsequent selection circuit of the first selection circuit (referred to as the second selection circuit for distinction). Under the control of the first control signal, the first selection circuit selects the data stored in the master device i for output; under the control of the second control signal, the second selection circuit selects the output data of the previous selection circuit for output, thereby activating the transmission path from the master device i to the slave device, so as to realize the output of the data stored in the master device i to the slave device. For example, the slave device enables the master device 1 through an enable command, controls the selection circuit 1 to select the data stored in the master device 1 for output through the first control signal, and controls the subsequent selection circuit 2-M to select the output data of the previous selection circuit for output through the second control signal, thereby activating the transmission path between the master device 1 and the slave device, and the data stored in the master device 1 is transmitted to the slave device sequentially through the selection circuits 1-M. At this time, all hosts 2-N are in an disabled state, and the transmission paths between hosts 2-N and slaves are not open.

[0086] In some embodiments of this disclosure, multiple selection circuits can time-divisionally activate multiple transmission paths under the control of the host. The slave device sends enable commands to multiple hosts 1-N in a time-division manner. The multiple hosts 1-N control multiple selection circuits 1-M to time-divisionally activate multiple transmission paths from hosts 1-N to slave devices according to the enable commands. The activated transmission paths are those from the host to the slave device enabled by the enable command. For example, when a slave device sends an enable command to host i, host i is in an enabled state. Host i can use the signal reflecting this enabled state as a first control signal and send it to the selection circuit (first selection circuit) coupled to it, causing the first selection circuit to select the data output of host i according to the received first control signal. Other hosts are in a disabled state and can use the signal reflecting this disabled state as a second control signal and send it to the corresponding selection circuit (second selection circuit), causing the second selection circuit to select the output data of the previous-level selection circuit for output according to the received second control signal. For example, taking the AXI bus and master 1 as an enabled state, when master 1 is enabled, its handshake signal (VALID) is valid (e.g., high level), while other masters 2-N are disabled, and their handshake signals (VALID) are invalid (e.g., low level). Master 1 can provide its handshake signal (VALID) as a first control signal to the selection terminal of selection circuit 1, and masters 2-N can provide their handshake signals (VALID) as a second control signal to the selection terminal of their corresponding selection circuit 2-M. Selection circuit 1 selects the data output of master 1 according to the first control signal of its selection terminal, and selection circuit 2-M selects the output data of the previous stage selection circuit according to the second control signal of its selection terminal. The data of master 1 can be sequentially selected and output to slaves. The data output of other masters is similar. It can be seen that when the number of masters and the number of selection circuits are the same, the handshake signal can be reused to control the output of the selection circuit, simplifying the implementation of the processing circuit. When the number of hosts and the number of selection circuits are different, the control signal of the selection circuit can be generated according to the enabled or disabled state of the hosts and the number of data input terminals of the selection circuit.

[0087] The selection circuit is described below with reference to the accompanying drawings.

[0088] Please refer to Figure 9 This illustrates an example diagram of a selection circuit provided in some embodiments of the present disclosure. For example... Figure 9As shown, in some embodiments of this disclosure, the selection circuit 900 may include a multiplexer (MUX) 910 and a first flip-flop (FF) 920. The multiplexer 910 includes at least one first input D1, a second input D2, a selection terminal SEL, and an output terminal OUT. At least one first input D1 is configured to be coupled to at least one of a plurality of hosts. The second input D2 is configured to be coupled to the output of the previous stage selection circuit, coupled to a preset signal, or coupled to a host. The second input D2 may be configured to be coupled to a preset signal. For example... Figure 4 In the selection circuit 1, the second input terminal D2 can be coupled to a preset signal S; for example... Figure 5 The second input terminal D2 of the selector circuit 531 can be coupled to a preset signal S. Alternatively, the second input terminal D2 can be configured to be coupled to a host computer. For example... Figure 6 In this case, circuit 1 can be coupled to host 2 through its second input terminal D2; for example, Figure 7 In this circuit, selection circuit 1 can be coupled to host 2 or host 3 via the second input terminal D2. The second input terminal D2 can be configured to be coupled to the output terminal of the previous stage selection circuit. For example... Figure 4 , Figure 6 ,and Figure 7 In this circuit, the selection circuit 2-M can be coupled to the output terminal OUT of the preceding selection circuit through its second input terminal D2; for example... Figure 5 The selection circuits 532-538 can be coupled to the output OUT of the preceding selection circuit via their second input D2. The selection terminal SEL is configured to select data from at least one of the first input terminals D1 and the second input terminal D2 and output it at the output terminal OUT. The first flip-flop 920 is coupled to the output terminal OUT of the multiplexer 910 and is coupled to a clock signal, and is configured to output the data at the output terminal of the multiplexer according to the clock signal.

[0089] Multiplexer 910 may include multiple input terminals. These input terminals are used to receive multiple data streams. The selection terminal SEL is used to receive a control signal. Under the control of the control signal, multiplexer 910 selects one input terminal to receive data and outputs it at output terminal OUT. First flip-flop 920 includes a data input terminal D, a clock signal terminal CLK, and an output terminal Q. The output terminal OUT of multiplexer 910 is coupled to the data input terminal D of the first flip-flop. Multiplexer 910 captures the data at its output terminal OUT under the influence of the clock signal and outputs the data at its output terminal Q. One or more of the rising or falling edges of the clock signal can serve as the trigger edge of the first flip-flop 920. The first flip-flop 920 may include, for example, a D flip-flop (data flip-flop), an RS flip-flop (reset-set flip-flop), or a JK flip-flop, etc. This disclosure does not limit the type of flip-flop.

[0090] The above selection circuit allows for shorter trace distances between the host and multiplexer 910, as well as between two multiplexers 910 in adjacent selection circuits, enabling data to be delivered to the first flip-flop 920 before its setup time. This distributes the timing load on the processing circuit, mitigating or even preventing problems with incorrect data transmission.

[0091] For the last selection circuit M in the transmission circuit, the output Q of the first flip-flop 920 is used to couple to the slave device (e.g., slave device 420 / 520 / 620 / 720). For the other selection circuits 1-(M-1) in the transmission circuit, the output Q of the first flip-flop 920 is used to couple to the second input D2 of the next-stage selection circuit.

[0092] The control signal for the selector SEL of the multiplexer 910 can be set to be the same as or similar to the control signal in the above embodiments. For example, using... Figure 5 Taking the transmission circuit shown as an example, the multiplexer 910 includes two input terminals. Figure 5 The selection circuit 531-538 in the middle can be adopted Figure 9 The structure of the selection circuit 900 is shown. The first input terminal D1 of the multiplexer 910 in the first selection circuit 531 is coupled to the host 511, and the second input terminal D2 is coupled to the preset signal S. The first input terminal D1 of the multiplexers 910 in the other selection circuits 532-538 is coupled to the host 512-518 respectively, and the second input terminal D2 is coupled to the output terminal Q of the first flip-flop 920 of the previous stage selection circuit. The output terminal Q of the first flip-flop 920 of the last stage selection circuit 538 is coupled to the slave device 520.

[0093] The master can provide control signals to the select terminal SEL of its coupled multiplexer 910. The control signal is exemplified by the handshake signal (VALID), which indicates the master's enable state. When the master is enabled, the handshake signal (VALID) is valid (e.g., high); when the master is disabled, the handshake signal (VALID) is invalid (e.g., low). When a slave enables one of the masters, multiple masters transmit their respective handshake signals (VALID) to the select terminal SEL of the coupled multiplexer 910. Because the handshake signal (VALID) of the multiplexer 910 coupled to the enabled master is valid, the data stored in the enabled master is output to the slave.

[0094] Taking the transmission of data from host 511 to slave 520 as an example: The handshake signal (VALID 1) of host 511 is valid. This handshake signal (VALID 1) is provided as a control signal to the selection terminal SEL of the multiplexer (referred to as MUX1 for distinction) in selection circuit 531, causing MUX1 to select the data at its first input terminal D1 (i.e., the data from host 511) for output. When the trigger edge of the clock signal arrives, the first flip-flop (referred to as FF1 for distinction) of selection circuit 531 updates the data at its output terminal Q to the data from host 511. The output terminal Q of FF1 is coupled to the second input terminal D2 of the multiplexer (referred to as MUX2 for distinction) in selection circuit 532. The first input terminal D1 of MUX2 is coupled to host 512. The handshake signal (VALID 2) of host 512 is invalid. This handshake signal (VALID 2) is provided as a control signal to the selection terminal SEL of MUX2, causing MUX2 to select the data at its second input terminal D2 (i.e., the data from host 511) for output. When the trigger edge of the clock signal arrives, the first flip-flop of the selection circuit 532 (referred to as FF2 for distinction) updates the data at the output terminal Q to the data output at the output terminal OUT of MUX2, i.e., the data of the master 511. Similarly, the data of the master 511 can be transmitted to the slave 520 via the selection circuits 531-538.

[0095] In some other embodiments of this disclosure, the processing circuit may include multiple slave devices. One slave device may be connected to multiple master devices using the transmission circuit provided in any of the above embodiments, thereby enabling one slave device to serially process data stored by multiple master devices; multiple slave devices may process data stored by different master devices in parallel. In still other embodiments of this disclosure, the slave devices may, for example, process data stored by different master devices in parallel. For example, the slave device includes multiple processing cores, wherein when a first processing core processes data stored by a certain master device, a second processing core may process data stored by other master devices in parallel. This can improve data processing efficiency. One or more transmission circuits of any kind can be designed for the slave device. In this way, different transmission circuits can transmit data to the slave device in parallel, further improving data transmission efficiency.

[0096] In the above transmission circuit, the wiring distances between the host and the corresponding multiplexer of the selection circuit, as well as between the multiplexers of the preceding and following selection circuits, are short, reducing data transmission time and ensuring that data arrives at the data input of the first flip-flop before its setup time. Through the data transmission via the first flip-flop of the multi-stage selection circuit, any host can transmit data to the slave device while meeting timing requirements. The slave device can then obtain the correct echo data, reducing the probability of data anomalies caused by timing issues.

[0097] In some embodiments of this disclosure, the first flip-flops 920 of multiple selection circuits can be coupled to a synchronous clock signal. This allows different parts of the transmission circuit to operate based on a synchronous clock signal, simplifying the timing design logic. For example, the first flip-flops 920 of multiple selection circuits can be coupled to the same clock signal. The clock signal can be obtained from the same clock signal source, reducing chip complexity.

[0098] In some embodiments of this disclosure, the transmission circuit may further include a delay circuit connected in series between two adjacent selection circuits in a plurality of selection circuits. The delay circuit utilizes timing elements for timing control, such as at least one second flip-flop connected in series. When the trace distance between selection circuits is long and timing pressures are still present, the delay circuit can further distribute the timing pressure in the transmission path, reducing the impact of timing problems on the processing circuit. For example, please refer to... Figure 10 This illustrates an example diagram of a transmission circuit provided in some embodiments of the present disclosure. For example... Figure 10 As shown, the transmission circuit 1000 includes multiple selection circuits and a delay circuit 1300 connected in series between two adjacent selection circuits. Figure 10 The illustration uses adjacent first selection circuit 1100 and second selection circuit 1200 as examples; delay circuits can also be connected in series between other adjacent selection circuits. Selection circuits may include, for example, the following... Figure 9The structures shown, for example, include a first selection circuit 1100 comprising a multiplexer 1110 and a first flip-flop 1120, and a second selection circuit 1200 comprising a multiplexer 1210 and a first flip-flop 1220. The delay circuit 1300 may include at least one second flip-flop 1310 connected in series. This disclosure does not limit the number of second flip-flops 1310, which can be determined based on the trace distance between adjacent selection circuits. The second flip-flop 1310 is implemented similarly to the first flip-flop, and may include, for example, a D flip-flop, an RS flip-flop, or a JK flip-flop, etc. Data to be transmitted can arrive at the second flip-flop before its setup time. For example, as... Figure 10 As shown, the delay circuit 1300 includes multiple second flip-flops 1310, further dispersing the timing pressure between adjacent selection circuits (e.g., the first selection circuit 1100 and the second selection circuit 1200). The data to be transmitted arrives at the second flip-flops 1310 before their setup time. Through the transmission of the data by the multiple second flip-flops 1310, the data to be transmitted can arrive at the first flip-flop 1220 before its setup time. The clock signal of the second flip-flops can be synchronized with the clock signal of the first flip-flops. For example, the second and first flip-flops can be coupled to the same clock signal.

[0099] In some embodiments of this disclosure, multiple master devices (e.g., master devices 511-518) can be distributed around the slave devices. This helps reduce routing complexity. Furthermore, the multiple master devices can be positioned closer to the edge of the chip. Power supply terminals are located at the edge of the chip; placing the master devices closer to these terminals reduces the impact of unwanted voltage drops on the master devices. Optionally, multiple selection circuits (e.g., selection circuits 531-538) can be distributed around the slave devices. This helps reduce routing complexity. Furthermore, the selection circuits can be positioned near their corresponding master devices. Reducing the trace length between the master device and the corresponding selection circuit further improves timing issues. Multiple master devices distributed around the slave devices may include multiple master devices arranged around the slave device. For example, radiating outwards in different directions from the slave device, with connections between different master devices and the slave device located in different radiating directions from the slave device. The distribution of multiple master devices around the slave device is only designed in terms of layout direction; the distance is not limited. For example, this disclosure does not limit the distance between master and slave devices; the distances between different master devices and slave devices can be the same or different. Optionally, multiple hosts can be arranged within a preset range with a preset distance as the radius, centered on the slave device. The distances between different hosts and slave devices can be the same or different, but not exceeding the preset distance. This disclosure does not limit the size of the preset distance and can be designed according to the performance requirements of the integrated circuit. The distance between the host and slave device includes, for example, the straight-line distance between the host and slave device, which can be determined based on the distance between the reference points of the host and the slave device. The reference point of the host can be, for example, the center point of the host or any point, and the reference point of the slave device can be, for example, the center point of the slave device or any point. Multiple hosts can be uniformly or non-uniformly distributed around the slave device. For example, the distances between different hosts and slave devices can be the same, or different. The distances between some hosts and slave devices can be the same, all different, or all the same; this disclosure does not impose any limitations. In some other embodiments of this disclosure, the connection lines between some hosts and slave devices can be located in the same radial direction as the slave device.

[0100] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish and describe related objects and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the number of related objects. For example, "first host" may include one host or multiple hosts.

[0101] "Multiple" includes two or more, and other classifiers are similar.

[0102] The terms "or" and "and / or" in this disclosure are used to describe relationships between related objects, indicating a non-exclusive inclusion. For example, "A and / or B" and "A or B" can both include: "A alone," "B alone," or "A and B," where "A" and "B" can include a single object or multiple objects. Similarly, "A, B and / or C," "A, B or C," and "A, B and C" can both include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B and C," where "A," "B," and "C" can include a single object or multiple objects. Additionally, the " / " in this disclosure is used to indicate an "or" relationship between related objects. The meanings of "at least one of A or B" and "one or more of A and B" in this disclosure are the same as the meaning of "A or B" above. The meanings of "one or more of A, B, and C" and "at least one of A, B, or C" are the same as the meaning of "A, B, or C" above. The meaning of "one or more of A, B, and C" is the same as the meaning of "A, B, or C" above.

[0103] In this disclosure, "coupling" includes signal connection between objects, which can be achieved directly through a medium (e.g., wires, traces, etc.) or through other components. Similarly, "connection" includes direct or indirect connection, or electrical or signal connection. The connected objects can be directly connected through a medium (e.g., wires, traces, etc.), indirectly connected through other components, or have internal connectivity.

[0104] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A processing circuit, characterized in that, For use with lidar, the processing circuit is configured to acquire echo data from the lidar and process the echo data; the processing circuit includes multiple master units, slave units, and transmission circuits. The plurality of hosts are configured to acquire the echo data and store the echo data; The slave device is configured to acquire the echo data stored in the plurality of host devices and process the echo data. The transmission circuit is configured to transmit the echo data from the plurality of hosts to the slave device; The transmission circuit includes multiple selection circuits connected in series, which are configured to time-division multiple transmission paths from the multiple hosts to the multiple slaves.

2. The processing circuit according to claim 1, characterized in that, The plurality of selection circuits includes a first selection circuit, and the plurality of hosts includes a first host, wherein the first selection circuit and the first host are coupled together. The first host is configured to acquire first echo data and store the first echo data; When the first selection circuit selects the first echo data stored in the first host for output, the first echo data is output to the slave device through the first transmission path, and the first transmission path includes the first selection circuit. The echo data includes the first echo data, and the plurality of transmission paths includes the first transmission path.

3. The processing circuit according to claim 2, characterized in that, The first transmission path further includes a subsequent selection circuit of the first selection circuit. The first echo data is output to the slave device through the first selection circuit and the subsequent selection circuit of the first selection circuit. The subsequent selection circuit includes a selection circuit connected in series between the first selection circuit and the slave device.

4. The processing circuit according to any one of claims 1-3, characterized in that, The number of the plurality of hosts is equal to the number of the plurality of selection circuits.

5. The processing circuit according to any one of claims 1-3, characterized in that, The number of the plurality of hosts is greater than the number of the plurality of selection circuits.

6. The processing circuit according to any one of claims 1-5, characterized in that, The selection circuit in the plurality of selection circuits includes a multiplexer and a first flip-flop. The multiplexer includes at least one first input, a second input, a selection terminal, and an output terminal; the at least one first input is configured to be coupled to at least one of the plurality of hosts. The second input terminal is configured to be coupled to the output terminal of the previous stage selection circuit or coupled to a preset signal; The selection terminal is configured to select data from one of the at least one first input terminal and the second input terminal and output it at the output terminal. The first trigger is coupled to the output of the multiplexer and to a clock signal, and is configured to output the data at the output of the multiplexer according to the clock signal.

7. The processing circuit according to claim 6, characterized in that, The first flip-flop of the plurality of selection circuits is coupled to a synchronous clock signal.

8. The processing circuit according to any one of claims 1-7, characterized in that, The slave device sends enable commands to the plurality of master devices in a time-division manner. The plurality of master devices control the plurality of selection circuits to conduct multiple transmission paths from the plurality of master devices to the slave device in a time-division manner according to the enable commands. The conducted transmission paths are the transmission paths from the master devices to the slave devices enabled by the enable commands.

9. The processing circuit according to any one of claims 1-8, characterized in that, The transmission circuit also includes a delay circuit, which is connected in series between two adjacent selection circuits in the plurality of selection circuits.

10. The processing circuit according to claim 9, characterized in that, The delay circuit includes at least one second flip-flop connected in series.

11. The processing circuit according to any one of claims 1-10, characterized in that, The multiple host machines are distributed around the slave machines.

12. The processing circuit according to any one of claims 1-11, characterized in that, The multiple selection circuits are distributed around the slave device.

13. A receiving circuit, characterized in that, For use with lidar, the receiving circuit includes: A laser receiver is used to receive the echo of the laser emitted by the lidar and convert the echo into an electrical signal, which is used to generate echo data. The processing circuit as described in any one of claims 1-12 is coupled to the laser receiver.

14. A lidar, characterized in that, include: A laser emitter, used to emit laser light; A laser receiver is used to receive the echo of the laser and convert the echo into an electrical signal, which is used to generate echo data; The processing circuit as described in any one of claims 1-12, coupled to the laser receiver, wherein a plurality of master units of the processing circuit are configured to distribute and store the echo data, and a slave unit of the processing circuit is configured to process the echo data.

15. A vehicle, characterized in that, include: main body; The lidar as described in claim 14 is mounted on the main body.

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