Flow control resistor module based on LDO (Low Dropout Regulator) zero pole tracking compensation and application of flow control resistor module

Abstract

The invention discloses a fluidic resistor module based on LDO zero pole tracking compensation. The fluidic resistor module comprises an operational transconductance amplifier, a PMOS transistor PM1 and a PMOS transistor PM2. The in-phase end of the operational transconductance amplifier is connected with the drain electrode of the PMOS transistor PM1, and the anti-phase end of the operational transconductance amplifier is connected with a first ideal voltage source; the output end G12 of the operational transconductance amplifier is connected with the grid electrode of the PMOS tube PM1 and the grid electrode of the PMOS tube PM2 at the same time; the drain electrode of the PMOS transistor PM1 is connected with an ideal current source Isense; the source electrode of the PMOS transistor PM1 and the drain electrode of the PMOS transistor PM2 are connected with an ideal voltage source VCC at the same time; a source electrode S2 of the PMOS transistor PM2 is connected with a capacitor C1, and the other end of the capacitor C1 is connected with a second ideal voltage source. The fluidic resistor module can generate an equivalent resistor inversely proportional to a sampling current, so that the equivalent fluidic resistor Rds can be linearly correlated with 1 / Isense, and the problems that a traditional fluidic resistor module cannot linearly change along with the 1 / Isense and the control is inaccurate are solved; meanwhile, the influence of process errors and temperature on the fluidic resistor is small, and generated errors are small.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a current-controlled resistor module based on LDO zero-point tracking compensation and its application. Background Technology

[0002] As integrated circuit process dimensions become smaller and integration density increases, power management chips are developing very rapidly. For power supply of high-computing-power chips, multiphase control circuits combined with DrMOS have become the mainstream development direction. DrMOS, which is designed for high current output, places high demands on the stability of LDO (Low Dropout Regulator) output under heavy load.

[0003] The classic LDO structure includes a first-stage error amplifier, a second-stage buffer, a third-stage output power transistor, a resistor-divider feedback network, an external load capacitor, and compensation structures. Classic compensation structures include traditional Miller compensation, Ahuja compensation based on Miller compensation, unity-gain bandwidth compensation, and pseudo-ESR power stage compensation. These compensation structures provide stable transient response characteristics for the LDO under different loads. However, when using Ahuja compensation based on Miller compensation, a pair of conjugate poles will be generated when the LDO load current is large. These conjugate poles can cause the LDO's transient response to oscillate at certain frequencies, leading to abnormal output voltage. Using zero-pole tracking, the current-controlled resistor needs to precisely follow the load current to maintain the Q value of the conjugate poles between 0.5 and 0.7 under heavy loads, minimizing its impact on stability. When using a pseudo-ESR power stage compensation structure, the pole position will change with the load current when the LDO load current changes. In some cases, it may even enter the in-band, causing a decrease in phase margin and affecting the stability of the LDO transient response. Using zero-pole tracking, the current-controlled resistor needs to accurately follow the load current in order to control the position of the zero point to accurately follow the change of the pole position. Summary of the Invention

[0004] The purpose of this invention is to propose a current-controlled resistor module based on LDO zero-point tracking compensation that can accurately control the equivalent resistance of a PMOS transistor and its application.

[0005] This invention provides a current-controlled resistor module based on LDO zero-pole tracking compensation, including an operational transconductance amplifier, a PMOS transistor PM1, and a PMOS transistor PM2; The non-inverting input of the operational transconductance amplifier is connected to the drain of PMOS transistor PM1, and the inverting input is connected to the first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected to both the gate of PMOS transistor PM1 and the gate of PMOS transistor PM2. The drain of the PMOS transistor PM1 is connected to an ideal current source I.sense The source of PMOS transistor PM1 and the drain of PMOS transistor PM2 are simultaneously connected to an ideal voltage source VCC; the source S2 of PMOS transistor PM2 is connected to capacitor C1, and the other end of capacitor C1 is connected to a second ideal voltage source.

[0006] The ideal current source I sense To simulate the LDO sampling load current, the PMOS transistor PM1 can convert the load current into a gate drive voltage. The ideal current source I... sense The signal is converted into a voltage signal V by PMOS transistor PM1. GS1 The drain of the PMOS transistor PM1 is clamped to 3.2V by an operational transconductance amplifier, thereby controlling the drain-source voltage of the PMOS transistor PM1 to be constant.

[0007] The capacitor C1 is a simulated Miller compensation capacitor. The source of the PMOS transistor PM2 is connected to capacitor C1 to simulate the current path of LDO Miller compensation, controlling the source voltage and drain voltage to be approximately equal.

[0008] Furthermore, in the current-controlled resistor module of the present invention, the positive power supply pin of the operational transconductance amplifier is connected to the power supply VDD, and the negative power supply pin is grounded. The power supply VDD supplies power to the operational transconductance amplifier.

[0009] Furthermore, the operational transconductance amplifier of the current-controlled resistor module described in this invention is a differential amplifier with differential input and single-ended output.

[0010] Furthermore, the first ideal voltage source of the current-controlled resistor module of the present invention is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

[0011] Furthermore, the source-drain voltages of PMOS transistors PM1 and PM2 in the current-controlled resistor module of the present invention are controlled to be less than 100mV, and both PMOS transistors PM1 and PM2 are in the deep linear region.

[0012] Since PMOS transistors PM1 and PM2 are located in the deep linear region, the equivalent drain-source resistance of PMOS transistors PM1 and PM2 is inversely proportional to the absolute value of the gate-source voltage.

[0013] Furthermore, the equivalent resistance of the PMOS transistor PM1 in the current-controlled resistor module of the present invention is R. ds1 And it satisfies Formula I, and when the PMOS transistor PM1 is in the deep linear region, it satisfies Formula II: , , The equivalent resistance of the PMOS transistor PM2 is R. ds2 And satisfy Formula III, , , , Where μ P C represents hole mobility. ox For the gate oxide capacitance, (W / L) PM1 The width-to-length ratio (W / L) of PMOS transistor PM1 PM2 V represents the aspect ratio of PMOS transistor PM2. GS V is the gate-source voltage of PMOS transistor PM1. th Threshold voltage; The R ds1 and R ds2 Both are with 1 / I sense Linear correlation.

[0014] Since the drain-source voltage of PMOS transistor PM1 is clamped, the current flowing through PMOS transistor PM1 is inversely proportional to its source-drain equivalent resistance.

[0015] Furthermore, the equivalent resistance R of the PMOS transistor PM2 in the current-controlled resistor module of the present invention... ds2 The error rate is ±10% within the temperature range of -40℃ to 125℃. And the equivalent resistance R of the PMOS transistor PM2 ds2 At any process angle of TT, FF, SS, SnFP, or FNSP, the error rate is ±10%.

[0016] One application of the flow-controlled resistor module based on any of the above descriptions, wherein the flow-controlled resistor module is used in a low-dropout linear regulator.

[0017] Furthermore, regarding the application of the current-controlled resistor module described in this invention, the compensation structure of the low-dropout linear regulator is Ahuja compensation, which controls the equivalent resistance R of the PMOS transistor PM2. ds2 Under heavy load, the Q value of the conjugate pole drops to 0.5~0.7, no frequency spikes appear, the phase margin is above 45°, and the response time is less than or equal to 5µs when the load changes from 0 to 250mA step.

[0018] Furthermore, regarding the application of the current-controlled resistor module described in this invention, the compensation structure of the low-dropout linear regulator is pseudo-ESR compensation, which is achieved by controlling the equivalent resistance R of the PMOS transistor PM2. ds2This allows the zero point position to follow the pole position change, achieving stable transient response of the LDO under full load, with a phase margin of over 45°, and a response time of less than or equal to 7µs when the load changes from 0 to 250mA step.

[0019] The present invention discloses a current-controlled resistor module based on LDO zero-pole tracking compensation and its application, the advantages of which are as follows: First, the current-controlled resistor module based on LDO zero-pole tracking compensation described in this invention, through its unique circuit structure (operational transconductance amplifier + dual PMOS transistors) and deep linear region operating design, achieves for the first time the equivalent resistance R. ds The reciprocal of the sampling current 1 / Isense Strict linear correlation. Significantly improved equivalent resistance R compared to existing technologies. ds The precision of control is improved. In particular, it solves the core challenges of Q-value control with conjugate poles in Ahuja compensation and dynamic zero-point tracking poles in pseudo-ESR compensation.

[0020] Since the drain-source voltage of PMOS transistor PM1 is clamped, and the current comes from the load current sampling current, the equivalent resistance of PMOS transistor PM1 is inversely proportional to the load current sampling current. Furthermore, because both PMOS transistors PM1 and PM2 are in the linear region, their gate-source voltages are approximately equal. Therefore, the equivalent resistances of PMOS transistors PM1 and PM2 are only inversely proportional to their gate-source voltages. Following this logic, the equivalent resistance of PMOS transistor PM2 is inversely proportional to the load current sampling current. This solves the problem of previous controlled resistances being inversely proportional to the square root of the load current sampling current, leading to inaccurate resistance control under heavy loads. This makes it more suitable for Ahuja compensation and pseudo-ESR compensation.

[0021] Since the ratio of the equivalent resistances of PMOS transistors PM1 and PM2 is only related to the ratio of their width to length, and their source voltages are approximately equal, the equivalent resistance of PM2 is minimally affected by threshold voltage and process variations, minimally affected by mobility variations under different processes, and minimally affected by temperature variations.

[0022] In summary, the current-controlled resistor module of this invention can generate an equivalent resistance that is inversely proportional to the sampling current. This module can not only make the equivalent current-controlled resistance R ds With 1 / Isense It exhibits linear correlation, solving the problem that traditional current-controlled resistor modules cannot follow 1 / I. sense The linear change results in imprecise control; at the same time, the flow control resistor is less affected by process errors and temperature, resulting in a smaller error. Attached Figure Description

[0023] Figure 1This is a circuit diagram of the current-controlled resistor module based on LDO zero-pole tracking compensation as described in Embodiment 1 of the present invention; Figure 2 This is a graph showing the relationship between the current control resistance of the current control resistor module described in this invention and the load current sampling current. Figure 3 This is a simulation diagram showing the change in the flow control resistance of the flow control resistance module described in this invention due to the influence of the manufacturing process. Figure 4 This is a simulation diagram showing the effect of temperature on the flow control resistance of the flow control resistance module described in this invention. Figure 5 This is a circuit topology diagram of the current-controlled resistor applied to Ahuja compensation according to Embodiment 2 of the present invention; Figure 6 This is a circuit topology diagram of the current-controlled resistor applied to pseudo-ESR compensation according to Embodiment 3 of the present invention. Detailed Implementation

[0024] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments are now described in detail with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the detailed embodiments, conventional conditions or conditions provided by the manufacturer shall apply.

[0025] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. Specific implementation method one:

[0026] A current-controlled resistor module based on LDO zero-pole tracking compensation includes an operational transconductance amplifier, a PMOS transistor PM1, and a PMOS transistor PM2; The non-inverting input of the operational transconductance amplifier is connected to the drain of PMOS transistor PM1, and the inverting input is connected to the first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected to both the gate of PMOS transistor PM1 and the gate of PMOS transistor PM2. The drain of the PMOS transistor PM1 is connected to an ideal current source I. sense The source of PMOS transistor PM1 and the drain of PMOS transistor PM2 are simultaneously connected to an ideal voltage source VCC; the source S2 of PMOS transistor PM2 is connected to capacitor C1, and the other end of capacitor C1 is connected to a second ideal voltage source.

[0027] In other embodiments, the positive power supply pin of the operational transconductance amplifier is connected to power supply VDD, and the negative power supply pin is grounded.

[0028] In other embodiments, the operational transconductance amplifier is a differential amplifier with differential input and single-ended output.

[0029] In other embodiments, the first ideal voltage source is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

[0030] In other embodiments, the source-drain voltages of the PMOS transistors PM1 and PM2 are controlled to be less than 100mV, and both PMOS transistors PM1 and PM2 are in the deep linear region.

[0031] In other embodiments, the equivalent resistance of the PMOS transistor PM1 is R. ds1 And it satisfies Formula I, and when the PMOS transistor PM1 is in the deep linear region, it satisfies Formula II: , , The equivalent resistance of the PMOS transistor PM2 is R. ds2 And satisfy Formula III, , , , Where μ P C represents hole mobility. ox For the gate oxide capacitance, (W / L) PM1 The width-to-length ratio (W / L) of PMOS transistor PM1 PM2 V represents the aspect ratio of PMOS transistor PM2. GS V is the gate-source voltage of PMOS transistor PM1. th Threshold voltage; The R ds1 and R ds2 Both are with 1 / I sense Linear correlation.

[0032] In other embodiments, the equivalent resistance R of the PMOS transistor PM2 ds2 The error rate is ±10% within the temperature range of -40℃ to 125℃. And the equivalent resistance R of the PMOS transistor PM2 ds2 At any process angle of TT, FF, SS, SnFP, or FNSP, the error rate is ±10%. Specific Implementation Method Two:

[0033] One application of the flow-controlled resistor module based on any of the above embodiments, wherein the flow-controlled resistor module is used in a low-dropout linear regulator.

[0034] In other embodiments, the compensation structure of the low-dropout linear regulator is Ahuja compensation, which is achieved by controlling the equivalent resistance R of the PMOS transistor PM2. ds2 Under heavy load, the Q value of the conjugate pole drops to 0.5~0.7, no frequency spikes appear, the phase margin is above 45°, and the response time is less than or equal to 5µs when the load changes from 0 to 250mA step.

[0035] In other embodiments, the compensation structure of the low-dropout linear regulator is a pseudo-ESR compensation, achieved by controlling the equivalent resistance R of the PMOS transistor PM2. ds2 This allows the zero point position to follow the pole position change, achieving stable transient response of the LDO under full load, with a phase margin of over 45°, and a response time of less than or equal to 7µs when the load changes from 0 to 250mA step. Example 1:

[0036] A current-controlled resistor module based on LDO zero-pole tracking compensation, such as Figure 1 As shown, it includes an operational transconductance amplifier, PMOS transistor PM1, and PMOS transistor PM2; The non-inverting input of the operational transconductance amplifier is connected to the drain of PMOS transistor PM1, and the inverting input is connected to the first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected to the gate of PMOS transistor PM1 and the gate of PMOS transistor PM2; the positive power supply pin of the operational transconductance amplifier is connected to the power supply VDD, and the negative power supply pin is grounded.

[0037] The drain of the PMOS transistor PM1 is connected to an ideal current source I. sense The source of PMOS transistor PM1 and the drain of PMOS transistor PM2 are simultaneously connected to an ideal voltage source VCC; the source S2 of PMOS transistor PM2 is connected to capacitor C1, and the other end of capacitor C1 is connected to a second ideal voltage source.

[0038] In this embodiment 1, the operational transconductance amplifier is a differential amplifier with differential input and single-ended output. The first ideal voltage source is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

[0039] The source-drain voltages of PMOS transistors PM1 and PM2 are controlled to be less than 100mV, and both PMOS transistors PM1 and PM2 are in the deep linear region.

[0040] In this embodiment 1, the design requirements for the PMOS transistor PM1 are as follows: the drain voltage of the PMOS transistor PM1 is clamped to 3.2V by the operational amplifier (which can be output through a voltage divider resistor in an LDO), and the source voltage of the PMOS transistor PM1 is 3.3V (3.3V output by the LDO), so that the PMOS transistor PM1 operates in the linear region, while the drain-source voltage is clamped to 100mV; simultaneously, the current flowing through the PMOS transistor PM1 is the load sampling current I. sense Thus, the equivalent resistance of the PMOS transistor PM1 is R. ds1 And it satisfies Formula I, and when the PMOS transistor PM1 is in the deep linear region, it satisfies Formula II: , , The design requirements for PMOS transistor PM2 are as follows: the drain voltage input of PMOS transistor PM2 is 3.3V (LDO output 3.3V), and the source voltage is connected to one end of capacitor C1. This results in a very small current flowing through PMOS transistor PM2, almost equivalent to no path to ground. Therefore, the source voltage of PMOS transistor PM2 is slightly lower than 3.3V, placing PMOS transistor PM2 in the deep linear region. The equivalent resistance of PMOS transistor PM2 is R. ds2 And satisfy Formula III, , The design requirements for the operational transconductance amplifier are as follows: the operational transconductance amplifier is a two-stage differential amplifier with differential input and single-ended output (OTA); the non-inverting input of the operational transconductance amplifier is connected to the drain of PMOS transistor PM1; the inverting input of the operational transconductance amplifier is connected to the first ideal voltage source with a voltage of 3.2V (from the output of the LDO voltage divider resistor); the output terminal G1_2 of the operational transconductance amplifier is connected to the gates of PMOS transistors PM1 and PM2 to achieve closed-loop control: when the load current is sampled, the current I... sense When the voltage increases, the voltage at the non-inverting input of the operational transconductance amplifier decreases, and the output voltage decreases accordingly, causing the |V| of PMOS transistors PM1 and PM2 to change. GS As the voltage rises, the equivalent resistance of PMOS transistor PM1 decreases, pulling up the drain voltage of PMOS transistor PM1 and maintaining the stability of the input voltage at the non-inverting input.

[0041] , (V) GS -V th The two can cancel each other out because the source voltages of PMOS transistors PM1 and PM2 are approximately equal. Although in reality, there are some differences in the source voltages of PMOS transistors PM1 and PM2, resulting in different threshold voltages, the error is small and has little impact on the equivalent resistance. , Where μ P C represents hole mobility. ox For the gate oxide capacitance, (W / L) PM1 The width-to-length ratio (W / L) of PMOS transistor PM1 PM2 V represents the aspect ratio of PMOS transistor PM2. GS V is the gate-source voltage of PMOS transistor PM1. th Threshold voltage; like Figure 2 As shown, the R ds1 and R ds2 Both are with 1 / I sense Linear correlation. The equivalent resistance of PMOS transistor PM2 is a current-controlled resistance, only affected by the width-to-length ratio of PMOS transistors PM1 and PM2, and the load current sampling current. Furthermore, compared to previous technologies, the equivalent resistance of PMOS transistor PM2 can follow 1... / Isense Precise changes and easier control of the zero point position: Moreover, the equivalent resistance of PMOS transistor PM2 is almost independent of the mobility, oxide capacitance and threshold voltage of PMOS transistor, so the equivalent current control resistance of PMOS transistor PM2 is greatly affected by errors caused by process changes and temperature.

[0042] like Figure 3 As shown, the equivalent resistance R of the PMOS transistor PM2 is... ds2 At any process angle of TT, FF, SS, SnFP, or FNSP, the variation is small, with an error rate of ±10%.

[0043] like Figure 4 As shown, the equivalent resistance R of the PMOS transistor PM2 is... ds2 The error rate is ±10% within the temperature range of -40℃ to 125℃; the variation is small. Example 2:

[0044] The current-controlled resistor module is used in a low-dropout linear regulator, and the compensation structure of the low-dropout linear regulator is Ahuja compensation, such as... Figure 5 As shown. The low-dropout linear regulator with the Ahuja compensation structure comprises a three-stage circuit; the first stage is an error amplifier EA, whose input is connected to the reference voltage and the feedback voltage V. FBThe output is connected to the second-stage buffer circuit; the output of the second-stage buffer circuit is connected to the gate of the power transistor PM; the drain of the power transistor PM is connected to ground via a series voltage divider resistor R1, R2, and R3. The gate of the power transistor PM is connected to the gate of the mirror transistor PMs, which provides the sampling current to the PMOS transistor PM1 of the current-controlled resistor module through a current mirror; the drain voltage of the power transistor PM serves as the source and output voltage of the PMOS transistor PM1, and the voltage divider resistors R1, R2, and R3 divide the output voltage to 3.2V, which is then input to the inverting input of the operational transconductance amplifier of the current-controlled resistor module. The drain of the power transistor PM is connected to the drain of the PMOS transistor PM2, and the source of the PMOS transistor PM2 is connected to capacitor C1. The other end of capacitor C1 is connected to the NMOS transistor in the error amplifier EA, forming an Ahuja compensation structure. In this embodiment 2, capacitor C1 is a Miller capacitor.

[0045] The feedback signal VFB is input to the error amplifier EA, clamped by the Vref voltage, and drives the power transistor PM through the second-stage buffer circuit. The on-resistance of the power transistor PM is controlled to change with the load current, stabilizing the output voltage at 3.3V. The PMOS transistor PM2 and capacitor C1 in the current-controlled resistor module form a compensation structure, introducing a zero point and splitting the positions of the dominant pole and the secondary pole, thereby improving the phase margin.

[0046] Under light load, the current-controlled resistor increases as the load decreases, allowing the feedforward zero generated by the Ahuja compensation structure to track the secondary point position at the output of the second-stage buffer circuit. Under heavy load, the current-controlled resistor value can be precisely controlled with the load current. By precisely controlling the Q value of the conjugate pole between 0.5 and 0.7, the frequency spike generated by the conjugate pole is controlled, preventing it from affecting the stability of the transient output. Ultimately, with an output current of 0-250mA, the phase margin is above 45°, the maximum bandwidth is 650kHz, and the response time is less than or equal to 5µs. Example 3:

[0047] The current-controlled resistor module is used in a low-dropout linear regulator, where the compensation structure is a pseudo-ESR compensation, such as... Figure 6As shown. The low-dropout linear regulator with pseudo-ESR compensation structure comprises a three-stage circuit. The first stage is an error amplifier EA1, with its input connected to the reference voltage and feedback voltage VFB1, and its output connected to the second-stage buffer 1 circuit. The output of the second-stage buffer 1 circuit is connected to the power transistor PMr. The power transistor PMr is connected to the series-connected voltage divider resistors R4, R5, and R6. The power transistor PMr is connected to the gates of the mirror transistors PMs1 and PMs2. The mirror transistor PMs2 provides the sampling current to the PMOS transistor PM1 of the current-controlled resistor module through a current mirror. The drain voltage of the power transistor PMr serves as the source and output voltage of the PMOS transistor PM1. The voltage divider resistors R4, R5, and R6 divide the output voltage to 3.2V, which is then input to the inverting input of the operational transconductance amplifier of the current-controlled resistor module. The drain of the power transistor PMr is connected to the drain of the PMOS transistor PM2, and the source of the drain of the PMOS transistor PM2 is connected to capacitor C2. The other end of capacitor C2 is connected to the drain of the mirror transistor PMs1, forming a pseudo-ESR compensation structure. In this embodiment 3, capacitor C2 is a clamping capacitor.

[0048] The feedback signal VFB1 is input to the error amplifier EA1 and clamped with the Vref voltage. This clamping signal drives the power transistor PMr through the second-stage buffer 1 circuit. The on-resistance of the power transistor PMr is controlled to change with the load current, stabilizing the output voltage at 3.3V. The PMOS transistor PM2, the mirror transistor PMs1, and the capacitor C2 in the current-controlled resistor module form a compensation structure, introducing two zeros and one pole. One zero acts as a dynamic zero, while the other zero and pole are close in position and can cancel each other out.

[0049] Under both light and heavy loads, the current-controlled resistor value can be precisely controlled, allowing the zero point to change with the pole position, thus achieving stable transient response of the LDO under full load. Ultimately, with an output current of 0-250mA, the phase margin is above 45°, the maximum bandwidth is 1.7MHz, and the response time is less than or equal to 7µs.

Claims

1. A current-controlled resistor module based on LDO zero-pole tracking compensation, characterized in that, This includes an operational transconductance amplifier, PMOS transistor PM1, and PMOS transistor PM2; The non-inverting input of the operational transconductance amplifier is connected to the drain of PMOS transistor PM1, and the inverting input is connected to the first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected to both the gate of PMOS transistor PM1 and the gate of PMOS transistor PM2. The drain of the PMOS transistor PM1 is connected to an ideal current source I. sense The source of PMOS transistor PM1 and the drain of PMOS transistor PM2 are simultaneously connected to an ideal voltage source VCC; the source S2 of PMOS transistor PM2 is connected to capacitor C1, and the other end of capacitor C1 is connected to a second ideal voltage source.

2. The current-controlled resistor module according to claim 1, characterized in that: The positive power supply pin of the operational transconductance amplifier is connected to the power supply VDD, and the negative power supply pin is grounded.

3. The current-controlled resistor module according to claim 1, characterized in that: The operational transconductance amplifier is a differential amplifier with differential input and single-ended output.

4. The current-controlled resistor module according to claim 1, characterized in that, The first ideal voltage source is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

5. The current-controlled resistor module according to claim 1, characterized in that: The source-drain voltages of PMOS transistors PM1 and PM2 are controlled to be less than 100mV, and both PMOS transistors PM1 and PM2 are in the deep linear region.

6. The current-controlled resistor module according to claim 5, characterized in that: The equivalent resistance of the PMOS transistor PM1 is R. ds1 And it satisfies Formula I, and when the PMOS transistor PM1 is in the deep linear region, it satisfies Formula II: ， ， The equivalent resistance of the PMOS transistor PM2 is R. ds2 And satisfy Formula III, ， ， ， Where μ P C represents hole mobility. ox For the gate oxide capacitance, (W / L) PM1 The width-to-length ratio (W / L) of PMOS transistor PM1 PM2 V represents the aspect ratio of PMOS transistor PM2. GS V is the gate-source voltage of PMOS transistor PM1. th Threshold voltage; The R ds1 and R ds2 Both are with 1 / I sense Linear correlation.

7. The current-controlled resistor module according to claim 6, characterized in that: The equivalent resistance R of the PMOS transistor PM2 ds2 The error rate is ±10% within the temperature range of -40℃ to 125℃. And the equivalent resistance R of the PMOS transistor PM2 ds2 At any process angle of TT, FF, SS, SnFP, or FNSP, the error rate is ±10%.

8. An application of the current-controlled resistor module according to any one of claims 1 to 7, characterized in that: The current-controlled resistor module is used in a low-dropout linear regulator.

9. The application of the current-controlled resistor module according to claim 8, characterized in that: The compensation structure of the low-dropout linear regulator is Ahuja compensation, which is achieved by controlling the equivalent resistance R of the PMOS transistor PM2. ds2 Under heavy load, the Q value of the conjugate pole drops to 0.5~0.7, no frequency spikes appear, the phase margin is above 45°, and the response time is less than or equal to 5µs when the load changes from 0 to 250mA step.

10. The use of the current-controlled resistor module according to claim 8, characterized in that: The compensation structure of the low-dropout linear regulator is pseudo-ESR compensation, which is achieved by controlling the equivalent resistance R of the PMOS transistor PM2. ds2 This allows the zero point position to follow the pole position change, achieving stable transient response of the LDO under full load, with a phase margin of over 45°, and a response time of less than or equal to 7µs when the load changes from 0 to 250mA step.

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