Clock control system

Abstract

The invention discloses a clock control system, and relates to the technical field of quantum computers, the system comprises an FPGA mother board for quantum measurement and control, a synchronous sampling source and a system clock chip, the FPGA mother board comprises a time interval measurement module and a PID control module; the system clock chip is used for providing a local clock signal for the time interval measurement module; the synchronous sampling source is used for providing a measurement clock signal for the time interval measurement module; the time interval measurement module is used for obtaining frequency and / or phase information of an external clock signal and the local clock signal according to the measurement clock signal; the PID control module is used for outputting a clock adjusting signal according to the frequency and / or phase information of the external clock signal and the local clock signal; and the system clock chip is also used for adjusting the frequency and / or phase of the local clock signal according to the clock adjusting signal so as to realize coherence of the local clock signal and an external clock signal.

Description

Technical Field

[0001] This invention relates to the field of quantum computer technology, and in particular to a clock control system. Background Technology

[0002] In ion trap quantum computers, each ion needs to independently control its quantum state. A localized electric field is constructed through a dedicated electrode combination to achieve high fidelity for single-qubit gates. When realizing ion movement and separation operations, adjacent electrode groups need to apply a gradually changing voltage gradient in concert to ensure that the ion migration process maintains sub-micron level positioning accuracy.

[0003] Furthermore, to overcome the limitations of traditional linear ion chains, a honeycomb electrode array is constructed in the XY plane to support two-dimensional ion confinement. Each ion requires six adjacent electrodes to form a three-dimensional constraint field. To suppress micro-motions caused by the radio frequency electric field, a compensation electrode group is deployed at the bottom of the chip, and phase synchronization technology is used to control ion displacement within λ / 20 (λ is the laser wavelength).

[0004] Furthermore, generating a microwave standing wave field using a distributed electrode array enables consistent coupling strength between different ions, supporting high-fidelity two-qubit gate operation. Configuring redundant electrodes to compensate for ambient magnetic field drift in real time helps reduce the frequency drift of ion hyperfine level transitions.

[0005] Based on the above reasons, it can be seen that the dense electrode architecture enables the ion trap system to simultaneously meet multiple requirements such as high-precision quantum manipulation, large-scale qubit expansion, and dynamic reconstruction, supporting its breakthrough in quantum computing under large-scale ion matrices; for example, the current advanced 512-qubit ion chip requires the integration of more than 1,500 electrodes.

[0006] The multi-channel DC source is used to control the electrodes of the ion trap quantum computing chip. The output of each channel of the DC source controls the execution of the computing timing, input timing, refresh timing, etc., which depend on a precise and stable clock signal.

[0007] Since the timing of ion trap monitoring or signal detection operations is directly related to the output timing of the DC source, and the output parameters and timing of the DC source also need to be dynamically adjusted according to the ion trap feedback results, the local clock needs to be synchronized with the external clock of the ion trap feedback results. Summary of the Invention

[0008] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, one object of this invention is to provide a clock control system that enables local clock signals to be correlated with external clock signals.

[0009] According to a first aspect of the present invention, a clock control system is provided, the system including an FPGA motherboard for quantum measurement and control, a synchronous sampling source and a system clock chip, the FPGA motherboard including a time interval measurement module and a PID control module;

[0010] The system clock chip is used to provide a local clock signal to the time interval measurement module;

[0011] The synchronous sampling source is used to provide a measurement clock signal to the time interval measurement module;

[0012] The time interval measurement module is used to obtain frequency and / or phase information of the external clock signal and the local clock signal based on the measurement clock signal;

[0013] The PID control module is used to output a clock adjustment signal based on the frequency and / or phase information of the external clock signal and the local clock signal;

[0014] The system clock chip is also used to adjust the frequency and / or phase of the local clock signal according to the clock adjustment signal.

[0015] Optionally, the system further includes a frequency synthesizer for outputting the external clock signal to the time interval measurement module, the frequency synthesizer being used to receive and adjust the external clock signal to match the local clock signal.

[0016] Optionally, the system further includes: a second DAC and a voltage-controlled crystal oscillator;

[0017] The voltage-controlled crystal oscillator is used to provide a reference clock signal to the system clock chip, so as to control the system clock chip to adjust the frequency and / or phase of the local clock signal;

[0018] The second DAC is used to convert the clock adjustment signal into an analog signal to control the voltage-controlled crystal oscillator to output the reference clock signal.

[0019] Optionally, the system further includes a first crystal oscillator;

[0020] The first crystal oscillator is used to provide a system configuration clock signal to the FPGA motherboard, so that the FPGA motherboard starts running and establishes an SPI connection with the system clock chip to obtain the local clock signal.

[0021] Optionally, the system may also include a communication module;

[0022] The first crystal oscillator is also used to provide the system configuration clock signal to the communication module.

[0023] Optionally, the communication module includes an Ethernet port and a serial transceiver connected to the Ethernet port based on a communication protocol, and the system configuration clock signal is provided to the serial transceiver.

[0024] Optionally, the system further includes a DDR for storing the quantum measurement and control commands received by the communication module;

[0025] The system clock chip is also used to provide the local clock signal to the DDR, so that the DDR performs data processing operations based on the local clock signal.

[0026] Optionally, the local clock signal provided by the system clock chip includes a parallel coherent measurement signal, a system global signal, and a DDR control signal;

[0027] The coherent measurement signal is provided to the time interval measurement module;

[0028] The system's global signal is used to control quantum measurement and control operations;

[0029] The DDR control signal is used to provide to the DDR.

[0030] Optionally, the system further includes:

[0031] The FLASH memory is used to store the system firmware. After the system is powered on, the system firmware is loaded from the FLASH memory to the FPGA motherboard.

[0032] The system also includes an EEPROM for storing the version number and serial number of the software and hardware.

[0033] Optionally, the quantum measurement and control includes multi-channel DC source control based on ion trap quantum computing, and the FPGA motherboard is used to output the output parameters of each channel of the DC source;

[0034] The system also includes a DAC subboard for executing the output parameters;

[0035] The local clock signal is used to control the timing of the output parameters of each channel of the DC source.

[0036] Optionally, the output parameters include the output voltage, and the DAC daughterboard refreshes the output voltage of each channel of the DC source at a certain period.

[0037] The period is generated based on the local clock signal output by the clock control system.

[0038] Optionally, the period is set to be less than the shortest variation interval of the output parameter in each channel of the DC source.

[0039] According to a second aspect of the present invention, an ion trap quantum computing DC electrode system is provided, comprising the clock control system described in any of the preceding embodiments.

[0040] According to a third aspect of the present invention, an ion trap quantum computing system is provided, including the clock control system described in any of the preceding claims.

[0041] In the solution provided by the embodiments of the present invention, the phase difference between the local clock signal and the external clock signal can be calculated by using the phase information of the external clock signal and the phase information of the local clock signal. The clock adjustment signal is a PID control signal output based on the phase difference. After constructing the PID formula between the phase difference and the output and performing parameter tuning to control the relationship between the output and the phase difference, the PID control signal is obtained and then converted into a reference clock signal.

[0042] Alternatively, if it is necessary to adjust the local clock signal to be in phase and frequency with the external clock signal, the phase information of the external clock signal and the local clock signal, as well as the frequency of the external clock signal and the local clock signal, are used as inputs to the PID control, thereby outputting a PID control signal.

[0043] In this way, the two clock signals can be at the same frequency and have a constant phase difference, or the two clock signals can be at different frequencies, but the change in phase difference conforms to a trigonometric function relationship or other functional relationship, thereby realizing the coherence between the local clock signal and the external clock signal.

[0044] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of the voltage control system of the first multi-channel DC source provided in the embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of the structure of the voltage control system for the second type of multi-channel DC source provided in the embodiments of the present invention;

[0047] Figure 3 This is a schematic diagram of the structure of the voltage control system of the third multi-channel DC source provided in the embodiments of the present invention;

[0048] Figure 4 This is a schematic diagram of the structure of an FPGA development board provided in an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of a clock control system provided in an embodiment of the present invention. Detailed Implementation

[0050] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0051] In one embodiment of the present invention, see Figure 1 A voltage control system for a multi-channel DC source is provided, including an FPGA (Field Programmable Gate Array) motherboard for outputting output parameters of each channel of the DC source, and at least two DAC (Digital-to-Analog Converter) daughterboards for executing the output parameters; each DAC daughterboard is equipped with a voltage reference chip and multiple DAC output channels, and each DAC output channel executes the output parameters based on the reference voltage signal provided by the voltage reference chip;

[0052] The FPGA motherboard is equipped with a voltage compensation module, which compensates the output parameters executed by the DAC daughterboard based on the reference voltage signal of each DAC.

[0053] In the above system, the FPGA motherboard refers to the circuit board developed based on FPGA, and the DAC daughterboard refers to the circuit board connected to the motherboard and including the DAC module. Figure 1 This example only shows the connection method between one DAC daughterboard and the motherboard. When there are two or more DAC daughterboards, each DAC daughterboard should be connected according to... Figure 1 The connection to the FPGA motherboard and multi-channel DC power supply is shown in the diagram. See [link / reference]. Figure 2 The multi-channel DAC refers to the DAC daughterboard. The FPGA motherboard and the DAC daughterboard can be connected via a motherboard connector. The motherboard connector integrates various communication interfaces, such as digital power supply, analog power supply, SPI (Serial Peripheral Interface), and a reference voltage signal V. REFn Interfaces for measured voltage values, etc.

[0054] Figure 2 In this circuit, the voltage reference chip can provide reference voltage signals to the multi-channel DAC and, via the motherboard connector, to the FPGA motherboard. The measured voltage value of the reference voltage signal is V. REFn The output format is an analog signal.

[0055] like Figure 2As shown, the multi-channel DAC module outputs an analog signal, and different initial voltage codes can represent different voltages. For example, a 20-bit voltage code can represent 2... 20 Different voltage values ​​correspond to the output current of a specified DAC output channel that controls a multi-channel DC source, each with an initial voltage encoding.

[0056] For example Figure 2 via D-Sub connector, V out 0~V out 39 indicates 40 DAC output channels, corresponding to the control of 40 output voltages of the multi-channel DC source.

[0057] The comparison results can be specifically as shown in the following examples.

[0058] The above output parameters include the output voltage. The FPGA motherboard or DAC daughterboard obtains the initial voltage code based on the output voltage and the nominal voltage value of the voltage reference chip.

[0059] The FPGA motherboard or DAC daughterboard obtains the initial voltage code based on the output voltage and the nominal voltage value of the voltage reference chip;

[0060] The voltage compensation module compensates the initial voltage code to obtain the compensated voltage code.

[0061] For example, if the output voltage is 5V and the nominal voltage is 1V, then the FPGA motherboard or DAC daughterboard will obtain 5 times the nominal voltage as the initial voltage code.

[0062] Specifically, the voltage compensation module compensates the initial voltage code to obtain the compensated voltage code based on the nominal voltage value of the voltage reference chip and the measured voltage value of the reference voltage signal.

[0063] In one embodiment, the compensation voltage code is determined as follows:

[0064]

[0065] Where Code′ represents the compensation voltage code; Code represents the initial voltage code; V REF0 Indicates the nominal voltage value; V REFn This represents the measured voltage value.

[0066] The nominal voltage value refers to the voltage value expected to be output by the voltage reference signal, while the measured voltage value is the measurement data obtained by actually measuring the voltage value of the reference voltage signal after controlling the output current of the specified output channel of the multi-channel DC source according to the received reference voltage signal.

[0067] In one embodiment, the system includes an ADC (Analog-to-Digital Converter) module for measuring the measured voltage value of a reference voltage signal, wherein the ADC module has more than 20 bits.

[0068] The initial voltage code for each channel is determined based on the output current voltage value, nominal voltage value, and DAC resolution of each channel. DAC resolution refers to the number of bits in the voltage code.

[0069] In cases where there are multiple DAC daughterboards, the nominal voltage value of the voltage reference chip on each DAC daughterboard is set to a uniform value.

[0070] If the preset nominal voltage values ​​corresponding to each daughterboard are similar, they can be processed as follows. "Similar nominal voltage values" can mean that each nominal voltage value is within a specified value range, or that the difference between the maximum and minimum values ​​does not exceed a preset nominal value threshold.

[0071] If similar conditions are met, the processing method could be to... REF0 The voltage is randomly set to the nominal voltage value of any sub-board, or to the average of all nominal voltage values. Then, when calculating the voltage code for each channel, the nominal value of the reference voltage signal is always V. REF0 Thus, since the compensation voltage encoding is based on the comparison result... The ratio is used for adjustment, which means that even if the output current voltage value of each channel deviates from the nominal value set by its own sub-board, the comparison result calculated by the above ratio still exists. The resulting compensation voltage code is adjusted according to a specific ratio, which allows the output voltage value between each channel of each sub-board to maintain a preset proportional relationship, so that the voltage gradient between electrodes can still remain linear, thereby improving the consistency of the output voltage.

[0072] After the voltage reference chip on any daughterboard provides a reference voltage signal to the voltage compensation module, the comparison result obtained by the voltage compensation module using this reference voltage signal is the comparison result corresponding to the voltage reference chip on that daughterboard.

[0073] In one scenario, a calculation module is set up on the motherboard to calculate the compensation voltage code according to the above formula, and then sends it to the DAC module of the daughterboard, so that the DAC module of the daughterboard can obtain the compensation voltage code. In this case, the output parameters output by the FPGA motherboard include the output voltage represented by the compensation voltage code. In another scenario, a calculation module can also be set up on the daughterboard to obtain the comparison result sent by the motherboard and then calculate the compensation voltage code according to the above formula. In this case, the output parameters include the comparison result.

[0074] The DAC daughterboard executes output parameters, including converting the compensation voltage code into an analog signal through the DAC module, and controlling the specified output channel to output a current with a voltage value represented by the compensation voltage code based on the obtained analog signal, thereby achieving compensation.

[0075] As can be seen from the above, according to the solution provided by the embodiments of the present invention, a reference voltage signal is provided by a voltage reference chip deployed on the daughter board. The reference voltage signal executes output parameters to control the voltage value of the output current of the multi-channel DC source. When current is actually output, the output parameters executed by the DAC daughter board are compensated based on the reference voltage signal of each DAC, thereby ensuring that the voltage value of the output current of each channel remains consistent with the reference voltage signal, that is, the voltage values ​​are exactly the same, or the adjusted voltage values ​​maintain a preset proportional relationship, thereby improving the consistency of the output voltage of the multi-channel DC source.

[0076] like Figure 3 As shown, the ADC module is located on the FPGA motherboard, and each voltage reference chip is connected in parallel with the ADC module; the ADC module receives the reference voltage signal provided by the voltage reference chip in the ON state based on the control of the switching element.

[0077] The ADC module is used to convert the reference voltage signal sent by each DAC module into a digital signal so that the voltage compensation module can receive the digital signal.

[0078] In this way, the voltage compensation module can perform calculations based on digital signals to obtain comparison results.

[0079] In one embodiment, see Figure 3 The ADC module is Figure 3 The high-precision ADC in the circuit, with its voltage reference chip in a non-ON state, is grounded via a resistor R with a similar resistance value to the ADC module, i.e., the GND line in the diagram. Switching elements thus control the connection between each DAC daughterboard and the motherboard. When the system needs to obtain the comparison result from the reference voltage signal of any DAC daughterboard, it controls the high-precision DAC to connect the voltage reference chip of that DAC daughterboard, from V... REF1 V REF2 ...V REFn The reference voltage signal sent by the voltage reference chip belonging to the DAC daughterboard is obtained.

[0080] Similar resistance values ​​refer to those that are the same as the resistance value of the ADC module, or whose difference from the resistance value of the ADC module is less than a preset resistance threshold.

[0081] exist Figure 3In this circuit, the switching element can be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). When the reference voltage signals of each daughter board connected in parallel to the high-precision ADC are not connected to the high-precision ADC, they are connected to GND through a bypass resistor R. By selecting resistors R with the same or similar resistance values, the degree of load change of the voltage reference chip of each DAC daughter board when connecting and disconnecting from the high-precision ADC can be reduced to a certain extent, thereby reducing the jitter of the reference voltage signal caused by load changes, which improves the stability of the reference voltage signal of each daughter board.

[0082] In one embodiment of the present invention, for each DAC daughterboard, a voltage reference chip deployed on the DAC daughterboard generates multiple reference voltage signals, wherein each reference voltage signal controls a predetermined number of designated output channels in a multi-channel DC source.

[0083] For example, for a DAC on a single daughterboard, the output channels of the DAC can be divided into several groups, with each group receiving a reference voltage signal. Taking a DAC with 40 output channels as an example, the 40 output channels can be divided into 5 groups, with 8 output channels in each group.

[0084] For high-precision voltage reference chips, there are certain limits to their load capacity.

[0085] Specifically, the total load of the reference voltage signals required by the DAC output channels of all DAC daughterboards is greater than the rated load of a voltage reference chip, or the total load of the reference voltage signals required by the DAC output channels of each DAC daughterboard is equal to the rated load of a voltage reference chip. This load can be expressed in terms of power.

[0086] For example, if five daughterboards are set up to achieve 200-channel DC source output, at least 25 reference voltage signals would be required. This clearly exceeds the load range of the voltage reference chip. Therefore, it is impossible to set up a voltage reference chip on the FPGA motherboard to ensure the output voltage consistency of each output channel on each daughterboard. In contrast, in the implementation scheme of this application, a separate voltage reference chip is set on each daughterboard, and the reference voltage signals are introduced in groups. This reduces the load on a single voltage reference chip and a single reference voltage signal, and reduces the impact on the accuracy of voltage control.

[0087] For voltages with the same parameters, such as a voltage reference chip planned to output a voltage of 5V, the voltage value output by each output channel will fluctuate with 5V as the nominal voltage value.

[0088] In one embodiment of the present invention, each DAC daughterboard is equipped with a temperature monitoring device;

[0089] A temperature monitoring device is used to monitor the temperature of the voltage reference chip on the DAC daughterboard where the temperature monitoring device is installed. If the monitored temperature change exceeds a preset temperature threshold, the measured voltage value of the reference voltage signal installed on the same DAC daughterboard is updated. If the monitored temperature change does not exceed the preset temperature threshold, the measured voltage value of the reference voltage signal installed on the same DAC daughterboard is used.

[0090] like Figure 2 As shown, the temperature monitoring device is the temperature sampling chip in the figure. When the temperature exceeds the temperature threshold, a signal is transmitted through the motherboard connector, so that the voltage compensation module provides a comparison result based on the updated measured voltage value, triggering the DAC module to update the compensation voltage code according to the above formula. Thus, the specified output channel can be refreshed using the updated compensation voltage code.

[0091] The temperature sampling chip can also send temperature data to the voltage reference chip, so that the voltage reference chip can calculate the output voltage value based on the temperature drift coefficient.

[0092] Because the components connected to the DAC daughterboard and the voltage reference chip are affected by temperature, their electrical parameters change, which also affects the output of the voltage reference chip to some extent. Therefore, by monitoring the temperature, the specified output channel is refreshed when the temperature changes significantly, thereby reducing the impact of abnormal temperature on the voltage value of the output current.

[0093] In the above scheme, if the time interval between the execution time of controlling the output current of the specified output channel according to the reference voltage signal and the refresh time using the compensation voltage code is too long, the voltage reference chip drift change at the actual output time of the DC source's output channel will not be accurately compensated.

[0094] In this case, the measured voltage value of the reference voltage signal for each DAC daughterboard is acquired at certain intervals. The latest measured voltage value of the reference voltage signal is then used to compensate for the initial voltage encoding performed on that DAC daughterboard. In this way, by controlling the period length, the aforementioned time interval can be avoided from being too long.

[0095] Continue using the above Figure 3In one embodiment, the high-precision ADC and the reference voltage chips of different sub-boards are sequentially turned on in one cycle, and the latest measured values ​​of the reference voltage signals of each sub-board are recorded. The output voltage codes of each channel that need to be input to the sub-board are compensated by calculating the compensation voltage code. For example, if the measured value changes, the above refresh step is used to compensate, which can improve the consistency of the output of each channel of the DC source to a certain extent.

[0096] In one embodiment, the aforementioned period is set to be less than the shortest variation interval of the output parameters of all DAC output channels of the DAC daughterboard.

[0097] For example, the factors influencing the shortest change interval are: the shortest operation cycle or the preset working period.

[0098] For output channels with high time resolution output voltage operation, the control cycle is less than the shortest operation cycle, where the operation cycle refers to the execution cycle of the output voltage operation. Each output voltage operation adjusts the voltage value of the output current of the output channel once.

[0099] If an output channel maintains a stable value throughout the working period, the output parameter refresh period can be set to be less than or equal to the working period.

[0100] In one embodiment, the system includes a system clock chip, and the period is generated based on a local clock signal provided by the system clock chip.

[0101] The FPGA motherboard controls the local clock signal and the external clock signal to be correlated.

[0102] In one embodiment of the present invention, an ion trap quantum computing DC electrode system is also provided, including a voltage control system for the multi-channel DC source of any of the above embodiments.

[0103] In one embodiment of the present invention, an ion trap quantum computing system is also provided, including a voltage control system for the multi-channel DC source of any of the above embodiments.

[0104] The following examples illustrate how the FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

[0105] In one embodiment of the present invention, a clock control system is provided, see [link to relevant documentation]. Figure 5 The FPGA motherboard, synchronous sampling source and system clock chip are used for quantum measurement and control. The FPGA motherboard includes a time interval measurement module and a PID control module.

[0106] The system clock chip is used to provide a local clock signal to the time interval measurement module.

[0107] A synchronous sampling source is used to provide a measurement clock signal to the time interval measurement module;

[0108] The time interval measurement module is used to obtain frequency and / or phase information of external clock signals and local clock signals based on the measured clock signal;

[0109] The PID control module is used to output a clock adjustment signal based on the frequency and / or phase information of the external clock signal and the local clock signal;

[0110] The system clock chip is also used to adjust the frequency and / or phase of the local clock signal according to the clock adjustment signal.

[0111] The aforementioned quantum measurement and control process includes multi-channel DC source control based on ion trap quantum computing, with an FPGA motherboard used to output the output parameters of each channel of the DC source; the system also includes a DAC daughterboard for executing the output parameters;

[0112] The local clock signal is used to control the timing of the output parameters of each channel of the DC source.

[0113] In one embodiment, the output parameters include the output voltage, and the DAC daughterboard refreshes the output voltage of each channel of the DC source at a certain period.

[0114] The period is generated based on the local clock signal output by the clock control system.

[0115] This embodiment is similar to the aforementioned voltage control system and will not be described in detail here. Figure 4 In the process, the voltage compensation module, motherboard connector, and high-precision ADC of the FPGA motherboard are related to the aforementioned Figure 1 The same principle applies in the embodiments, such as... Figure 4 The diagram shows how to process measured voltage values ​​V. REFn The compensated voltage code is obtained. The motherboard connector is also connected to a power supply.

[0116] A clock signal is a periodically changing electrical signal, which can be represented by alternating high and low levels. In the system described above, the local clock signal and the measurement clock signal are provided by the system clock chip and the synchronous sampling source, respectively.

[0117] The period is set to be less than the shortest interval between changes in the output parameters of each channel of the DC source.

[0118] External clock signal refers to the clock signal of an ion trap monitoring or signal detection system.

[0119] Given both the measurement clock signal and the local clock signal, the phase information can include the phase difference between them. This phase difference reflects the timing deviation between the two clock signals. The phase difference between the two clock signals can be measured using DDMTD (Digital Dual-Mixing Time-to-Digital Converter). DDMTD employs fully digital processing and can implement algorithms such as Kalman filtering on an FPGA motherboard to suppress burst noise. DDMTD supports nanosecond-level real-time phase adjustment, such as temperature drift compensation. It can simultaneously measure the phase difference of multiple clock signals, enabling synchronization of cluster devices. Therefore, this architecture is particularly suitable for boards used in quantum manipulation systems.

[0120] The phase difference can be obtained by calculating the delay time of the local clock signal edge relative to the measured clock signal. Once the phase difference is obtained, the frequency of the local clock signal can be derived from the phase difference and the frequency of the measured clock signal. In this embodiment, a synchronous sampling source can be configured to output a clock signal at a fixed frequency, thereby calculating the frequency and / or phase information of the local clock signal, as well as the frequency and / or phase information of the external clock signal, using a unified standard.

[0121] The calculation method for the frequency and phase information of the external clock signal is similar to that of the local clock signal, with the only difference being the substitution of names such as external clock signal and local clock signal.

[0122] Figure 4 This is a schematic diagram of the overall structure of the FPGA motherboard in the solution provided by the embodiment of the present invention. The synchronous sampling source directly outputs a measurement clock signal to the time interval measurement module.

[0123] The system also includes a frequency synthesizer that outputs an external clock signal to the time interval measurement module. The frequency synthesizer receives and adjusts the external clock signal to match the local clock signal, thereby outputting an external clock signal with the same frequency as the local clock signal.

[0124] A frequency synthesizer can generate a clock signal with a target frequency through PLL (Phase-Locked Loop) feedback regulation or DDS (Direct Digital Synthesizer) phase accumulation. By setting the target frequency to the frequency of the local clock signal, an external clock signal with the same frequency as the local clock signal can be output.

[0125] The core of DDMTD is to measure the phase difference between two clock signals using a dual-mixer structure. However, this technique requires the two input signals to have strictly identical frequencies. If the external clock signal and the local clock signal have different frequencies, a difference frequency signal will be generated after mixing, making it impossible to directly quantize the phase difference. A frequency synthesizer converts the external clock to the local clock frequency domain—that is, to achieve the same frequency—so that the two signals meet the conditions for phase difference detection.

[0126] Figure 4 In this context, PID stands for PID control module. According to the requirements of quantum measurement and control, if it is necessary to adjust the local clock signal to be in phase with the external clock signal, the phase information of the external clock signal and the local clock signal is used.

[0127] Specifically, the phase difference between the local clock signal and the external clock signal can be calculated using the phase information of the external clock signal and the local clock signal. The clock adjustment signal is a PID control signal output based on the phase difference. By constructing a PID formula for the phase difference and the output and tuning the parameters to control the relationship between the output and the phase difference, the PID control signal is obtained and then converted into a reference clock signal.

[0128] Alternatively, if it is necessary to adjust the local clock signal to be in phase and frequency with the external clock signal, the phase information of the external clock signal and the local clock signal, as well as the frequency of the external clock signal and the local clock signal, are used as inputs to the PID control, thereby outputting a PID control signal.

[0129] In this way, the two clock signals can be at the same frequency and have a constant phase difference, or the two clock signals can be at different frequencies, but the change in phase difference conforms to a trigonometric function relationship or other functional relationship, thereby realizing the coherence between the local clock signal and the external clock signal.

[0130] The system clock chip can be a high-performance clock generator chip such as LMK04828 or HMC7044. By setting an additional system clock chip, it is not necessary to develop a module that provides local clock signals on the FPGA motherboard, thereby reducing development costs.

[0131] In the above embodiment, the specific implementation of the PID control module controlling the system clock chip is as follows: the PID control module outputs a PID control signal as a clock adjustment signal to control the voltage-controlled crystal oscillator. See also... Figure 4 The clock control system also includes: a second DAC and a voltage-controlled crystal oscillator;

[0132] A voltage-controlled crystal oscillator is used to provide a reference clock signal to the system clock chip, so as to control the system clock chip to adjust the frequency and / or phase of the local clock signal;

[0133] The second DAC is used to convert the clock adjustment signal into an analog signal to control the voltage-controlled crystal oscillator to output a reference clock signal.

[0134] The term "second" in the second DAC is used only to distinguish it from the DAC sub-board in the foregoing embodiments, indicating that they are different DAC devices.

[0135] The frequency and / or phase information of the local clock signal output by the system clock chip is controlled by a voltage-controlled crystal oscillator (VCO), which in turn is controlled by a clock adjustment signal. Since the VCO is controlled by an analog signal, and the PID control module, as part of the FPGA, outputs a digital signal, a DAC is needed to convert the digital signal into an analog signal.

[0136] In one embodiment of the present invention, the clock control system further includes a first crystal oscillator;

[0137] The first crystal oscillator is used to provide the system configuration clock signal to the FPGA motherboard, so that the FPGA motherboard can start running and establish an SPI connection with the system clock chip to obtain the local clock signal.

[0138] The FPGA circuit board refers to the FPGA motherboard in the above embodiments. The system configuration clock signal is a clock signal with a preset frequency. By providing the system configuration clock signal to the FPGA circuit board and the same system configuration clock signal to the system clock chip, it is possible to control the FPGA circuit board and the system clock chip to communicate in a consistent timing sequence.

[0139] The clock control system includes a synchronous sampling source and a first crystal oscillator. The reason for repeatedly setting up independent clock signal sources is that DDMTD achieves high-precision alignment by measuring the phase difference between the two clocks. If the first crystal oscillator is used directly as the sampling clock, internal logic noise such as power supply jitter and cross-clock domain interference will contaminate the measurement results, leading to phase noise degradation. Setting up an independent synchronous sampling source can avoid FPGA digital noise from entering the measurement link. Furthermore, the first crystal oscillator, which serves as the system configuration clock, has a large clock path delay and is susceptible to temperature / voltage drift, which cannot meet the stringent requirements of DDMTD for sampling clock phase consistency.

[0140] In one embodiment of the present invention, the clock control system further includes a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) for storing quantum measurement and control instructions received by the communication module;

[0141] The system clock chip is also used to provide a local clock signal to the DDR, so that the DDR can perform data processing operations based on the local clock signal.

[0142] In one embodiment, the clock control system further includes:

[0143] The FLASH memory is used to store the system firmware. After the system is powered on, the system firmware is loaded from the FLASH memory to the FPGA motherboard.

[0144] The clock control system also includes an EEPROM for storing the version number and serial number of the hardware and software.

[0145] like Figure 4 As shown, the FPGA motherboard is connected to FLASH (flash memory), DDR, and EEPROM (Electrically Erasable Programmable Read-Only Memory). The FLASH can be NAND FLASH (Not AND Flash), used as a high-capacity storage device. DDR can be any RAM (Random Access Memory) device, used as a system runtime cache. The EEPROM can be any ROM device or NOR FLASH (or Not AND Flash), used as a system firmware device. Specifically, the FLASH can store the system firmware, which is loaded from the FLASH onto the FPGA motherboard after the system powers on. The DDR can store the timing information for the output voltage of the multi-channel DC source.

[0146] The instructions issued by DDR memory directly serve the quantum computing task. The DDR controller uses the local clock signal provided by the system clock chip for control, ensuring that the data read and write operations of DDR are synchronized with the quantum measurement and control core. Using the same clock domain can guarantee low-latency synchronization between instruction reading and quantum measurement and control, avoid data errors or performance bottlenecks caused by clock switching, and reduce timing risks caused by cross-clock domains. It also simplifies the data path design inside the FPGA, such as the depth control of the FIFO buffer, and improves the overall system efficiency.

[0147] In one embodiment, the local clock signal provided by the system clock chip includes a parallel coherent measurement signal, a system global signal, and a DDR control signal;

[0148] The coherent measurement signal is provided to the time interval measurement module;

[0149] The system's global signals are used to control quantum measurement and control operations;

[0150] DDR control signals are used to provide power to the DDR.

[0151] Figure 4 In the system clock chip, four lines are provided. The SPI connection is used to connect to the FPGA. The measurement line sends a coherent measurement signal to measure whether the local clock signal is coherent with the external clock signal. If they are not coherent, the PID control module is used to adjust the local clock signal until coherence is achieved, as shown in the above embodiment. The Global connection represents the system's global signal.

[0152] The coherent measurement signal is parallel and isolated from other signals, so that the measurement process is as free from noise interference from other signals as possible.

[0153] DDR stands for DDR control signal, and its purpose is:

[0154] The output processing operations performed by the DDR interface, including read / write operations, require strict clock and data alignment. Due to path delay differences, the global clock signal is difficult to directly meet the setup / hold time requirements of the DDR interface, and its phase needs to be adjusted independently through a dedicated clock network. The duty cycle of the DDR clock needs to be close to 50%, while the global clock may suffer waveform distortion due to load changes during long-distance transmission. In contrast, providing a separate local clock signal can reduce such distortion by setting a local clock buffer (such as BUFR). In addition, an independent DDR clock path can reduce crosstalk of high-speed switching signals to the global clock network and improve system stability.

[0155] In one embodiment of the present invention, the clock control system further includes a communication module;

[0156] The first crystal oscillator is also used to provide the system configuration clock signal to the communication module.

[0157] The communication module includes an Ethernet port and a serial transceiver connected to the Ethernet port based on a communication protocol. The system configuration clock signal is provided to the serial transceiver.

[0158] The communication module can be Figure 4 The serial transceiver and Ethernet port communicate based on the SGMII (Serial Gigabit Media Independent Interface) communication protocol.

[0159] The system configuration clock is used for SPI connections and Ethernet serial transceiver-to-physical layer operations, which are low-priority or asynchronous communication tasks. Because data communication is typically less time-dependent with DC source output operations, and the clock signal provided by the crystal oscillator does not require coherent adjustment, its frequency and phase are relatively stable, ensuring stable and smooth data communication.

[0160] like Figure 4 The first crystal oscillator divides the system configuration clock signal into two paths through the clock distribution module: one path is provided to the FPGA motherboard, and the other path is provided to the serial transceiver.

[0161] In one embodiment of the present invention, an ion trap quantum computing DC electrode system is also provided, including the clock control system described in any of the above embodiments.

[0162] In one embodiment of the present invention, an ion trap quantum computing system is also provided, including the clock control system described in any of the above embodiments.

[0163] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0164] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0165] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0166] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0167] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0168] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0169] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0170] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A clock control system, characterized in that, The system includes an FPGA motherboard for quantum measurement and control, a synchronous sampling source, and a system clock chip. The FPGA motherboard includes a time interval measurement module and a PID control module. The system clock chip is used to provide a local clock signal to the time interval measurement module; The synchronous sampling source is used to provide a measurement clock signal to the time interval measurement module; The time interval measurement module is used to obtain frequency and / or phase information of the external clock signal and the local clock signal based on the measurement clock signal; The PID control module is used to output a clock adjustment signal based on the frequency and / or phase information of the external clock signal and the local clock signal; The system clock chip is also used to adjust the frequency and / or phase of the local clock signal according to the clock adjustment signal.

2. The system according to claim 1, characterized in that, The system also includes a frequency synthesizer for outputting the external clock signal to the time interval measurement module, the frequency synthesizer being used to receive and adjust the external clock signal to match the local clock signal.

3. The system according to claim 1, characterized in that, The system also includes: a second DAC and a voltage-controlled crystal oscillator; The voltage-controlled crystal oscillator is used to provide a reference clock signal to the system clock chip, so as to control the system clock chip to adjust the frequency and / or phase of the local clock signal; The second DAC is used to convert the clock adjustment signal into an analog signal to control the voltage-controlled crystal oscillator to output the reference clock signal.

4. The system according to claim 1, characterized in that, The system also includes a first crystal oscillator; The first crystal oscillator is used to provide a system configuration clock signal to the FPGA motherboard, so that the FPGA motherboard starts running and establishes an SPI connection with the system clock chip to obtain the local clock signal.

5. The system according to claim 4, characterized in that, The system also includes a communication module; The first crystal oscillator is also used to provide the system configuration clock signal to the communication module.

6. The system according to claim 5, characterized in that, The communication module includes an Ethernet port and a serial transceiver connected to the Ethernet port based on a communication protocol. The system configuration clock signal is provided to the serial transceiver.

7. The system according to claim 5, characterized in that, The system also includes a DDR for storing quantum measurement and control commands received by the communication module; The system clock chip is also used to provide the local clock signal to the DDR, so that the DDR performs data processing operations based on the local clock signal.

8. The system according to claim 7, characterized in that, The local clock signals provided by the system clock chip include parallel coherent measurement signals, system global signals, and DDR control signals. The coherent measurement signal is provided to the time interval measurement module; The system's global signal is used to control quantum measurement and control operations; The DDR control signal is used to provide to the DDR.

9. The system according to claim 1, characterized in that, The system also includes: The FLASH memory is used to store the system firmware. After the system is powered on, the system firmware is loaded from the FLASH memory to the FPGA motherboard. The system also includes an EEPROM for storing the version number and serial number of the software and hardware.

10. The system according to claim 1, characterized in that, The quantum measurement and control includes multi-channel DC source control based on ion trap quantum computing, and the FPGA motherboard is used to output the output parameters of each channel of the DC source. The system also includes a DAC subboard for executing the output parameters; The local clock signal is used to control the timing of the output parameters of each channel of the DC source.

11. The system according to claim 10, characterized in that, The output parameters include the output voltage, and the DAC daughterboard refreshes the output voltage of each channel of the DC source at a certain period. The period is generated based on the local clock signal output by the clock control system.

12. The system according to claim 11, characterized in that, The period is set to be less than the shortest interval of change of the output parameter in each channel of the DC source.

13. An ion trap quantum computing DC electrode system, characterized in that, The clock control system includes any one of claims 1-11.

14. An ion trap quantum computing system, characterized in that, The clock control system includes any one of claims 1-11.

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