Accessing system and electronic device

Abstract

The application provides a memory access system and electronic equipment. A transmitting slot transmits analysis information of instructions to a load-store queue or a load queue. The load-store queue and the load queue generate corresponding memory access requests according to the obtained analysis information, and write the generated memory access requests into corresponding channels. An arbitration module transmits the memory access requests in the channels in an occupied state to a storage unit according to a preset priority rule. A single super-long word instruction is allowed to contain multiple memory access operations, such as two load operations or one load operation and one store operation. Two memory access operations can be executed in parallel by a first transmitting slot and a second transmitting slot in a same clock cycle. The structure can improve memory access efficiency while realizing low hardware complexity.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processors, in particular to a memory access system and an electronic device. BACKGROUND

[0002] In recent years, artificial intelligence technology has developed rapidly, and with it, there is an increasingly high demand for processor computing performance. The efficiency of data loading and storage is one of the bottlenecks of processor computing performance. In the traditional pipeline architecture design, the memory access operation is divided into multiple stages of pipeline such as value taking, decoding, and execution, and the memory access efficiency is improved by stage overlap. The cost and time of data transfer during the execution of the memory access instruction are relatively high, so a cache is usually used to speed up data access. When the instruction memory access instruction is executed, the memory access module parses the received instruction to obtain the specific memory access address and access the cache. When the cache receives the access request, it determines whether the access hits. If it hits, the data is read from the hit cache line or the input data is written to the hit cache line. If it does not hit, i.e. the cache line is missing, the corresponding cache line needs to be read from the secondary cache or the memory and written to the corresponding cache line of the primary cache. This method can reduce the frequency of accessing external storage to some extent, thereby reducing the consumption of memory access instructions and improving efficiency to some extent. However, it still cannot meet the current increasingly high demand for processor computing performance. SUMMARY

[0003] The present application aims to provide a memory access system and an electronic device to improve the above problems.

[0004] To achieve the above-mentioned purpose, the technical solution adopted by the embodiments of the present application is as follows:

[0005] In a first aspect, the embodiments of the present application provide a memory access system, which comprises an arbitration module, a storage unit, a first transmission slot, a second transmission slot, a load-store queue, and a load queue. The load-store queue is provided with at least two storage channels and at least two first load channels, and the load queue is provided with at least two second load channels.

[0006] The first transmission slot is used to transmit the parsing information of the instruction therein to the load-store queue under the condition that the write condition is met, wherein the parsing information comprises the micro-operation code, the source operand, and the destination register number of the instruction.

[0007] The load-store queue is used to generate a corresponding memory access request according to the obtained parsing information. When the type of the memory access request is a load instruction, the memory access request and its corresponding destination register number are written to the first load channel in an idle state. When the type of the memory access request is a store instruction, the memory access request is written to the storage channel in an idle state.

[0008] The second emission slot is configured to transmit the parsed information of the instruction to the load queue when a write condition is met.

[0009] The load queue is configured to generate a corresponding memory access request according to the parsed information, and write the memory access request and a corresponding destination register number thereof into a second load channel in an idle state.

[0010] The arbitration module is configured to transmit the memory access request in the channel in the occupied state to the storage unit according to a preset priority rule.

[0011] In a second aspect, an electronic device is provided, which comprises the memory access system.

[0012] Compared with the prior art, the memory access system and the electronic device provided by the embodiments of the present application have the following advantages: the first emission slot and the second emission slot transmit the parsed information of the instruction to the load storage queue or the load queue when a write condition is met; the load storage queue generates a corresponding memory access request according to the parsed information, and when the type of the memory access request is a load instruction, writes the memory access request and a corresponding destination register number thereof into a first load channel in an idle state; when the type of the memory access request is a store instruction, writes the memory access request into a storage channel in an idle state; the load queue generates a corresponding memory access request according to the parsed information, and writes the memory access request and a corresponding destination register number thereof into a second load channel in an idle state; and the arbitration module transmits the memory access request in the channel in the occupied state to the storage unit according to a preset priority rule. A single super-long word instruction is allowed to contain multiple memory access operations, such as two load operations or one load operation and one store operation, and the two memory access operations can be executed in parallel by the first emission slot and the second emission slot in the same clock cycle. The structure can improve the memory access efficiency while achieving low hardware complexity, so as to meet the increasing demand for processor computing performance.

[0013] In order to make the above objectives, features and advantages of the present application more apparent, clear and easy to understand, the following will specifically describe the preferred embodiments of the present application with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0015] Figure 1 The structure diagram of the memory access system provided by the embodiments of the present application.

[0016] Figure 2 One of the port state schematic diagrams provided for the embodiment of the present application.

[0017] Figure 3 The second port state schematic diagram provided for the embodiment of the present application.

[0018] Figure 4 The third port state schematic diagram provided for the embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0021] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms “first”, “second” and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0022] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms “first”, “second” and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0023] In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present application is usually placed, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0024] In the description of the present application, it should be noted that the terms "set", "connected" should be understood broadly unless otherwise specified and limited, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0026] The embodiment of the present application provides a memory access system, please refer to Figure 1 , Figure 1 The structure diagram of the memory access system provided by the embodiment of the present application.

[0027] The memory access system comprises an arbitration module, a storage unit, a first launch slot, a second launch slot, a load-store queue and a load queue. The load-store queue is provided with at least two storage channels and at least two first load channels, and the load queue is provided with at least two second load channels.

[0028] The first launch slot is used to transmit the parsing information of the instruction (in the first launch slot) to the load-store queue under the condition that the write condition is met, wherein the parsing information comprises the micro-operation code of the instruction, the source operand and the destination register number. The micro-operation code comprises the instruction type (load instruction or store instruction) and the data length, the source operand comprises the base address read from the source address register, the offset address carried by the instruction, and if the instruction type is a store instruction, the source operand further comprises the target storage data read from the source data register; when the instruction in the first launch slot is a load instruction, the destination register number in the parsing information is valid; if the instruction in the first launch slot is a store instruction, the destination register number is empty or invalid.

[0029] It should be noted that the first launch slot satisfies the write-in condition, which means that there is a free channel in the load-store queue that matches the instruction in the first launch slot, the load instruction matches the load channel, the store instruction matches the store channel, and the instruction in the first launch slot is a load instruction or a store instruction.

[0030] The load-store queue is configured to generate a corresponding memory access request according to the obtained parsing information, and when the memory access request is a load instruction, the memory access request and the corresponding destination register number are written into a first load channel in an idle state; when the memory access request is a store instruction, the memory access request is written into a store channel in an idle state.

[0031] In an optional embodiment, each channel in the load-store queue and the load queue is numbered, and there are N channels in the load-store queue and M channels in the load queue. In order to ensure the order of the transmission of the memory access request, when the memory access request is a load instruction, the load-store queue writes the memory access request and the corresponding destination register number into a first load channel with the smallest number and in an idle state; when the memory access request is a store instruction, the load-store queue writes the memory access request into a store channel with the smallest number and in an idle state.

[0032] The second launch slot is configured to transmit the parsing information of the instruction (in the second launch slot) to the load queue when the write-in condition is satisfied.

[0033] It should be noted that the first launch slot satisfies the write-in condition, which means that there is a free channel in the load-store queue that matches the instruction in the first launch slot, the load instruction matches the load channel, the store instruction matches the store channel, and the instruction in the first launch slot is a load instruction or a store instruction.

[0034] The load queue is configured to generate a corresponding memory access request according to the obtained parsing information, and write the memory access request and the corresponding destination register number into a second load channel in an idle state.

[0035] Optionally, the load queue writes the memory access request and the corresponding destination register number into a second load channel with the smallest number and in an idle state.

[0036] The arbitration module is configured to transmit the memory access request in the channel (the first load channel, the second load channel, or the store channel) in an occupied state to the storage unit according to a preset priority rule.

[0037] The channel in an occupied state can be the first load channel, the second load channel, or the store channel, and the preset priority rule can be that the priority of the channel in the load-store queue is higher than the priority of the channel in the load queue.

[0038] The memory access system provided in the embodiment of the application is applicable to a VLIW (Very Long Instruction Word) architecture, allows a single super-long word instruction to contain multiple memory access operations, such as two load operations or one load operation and one store operation, and the two memory access operations can be executed in parallel by a first emission slot and a second emission slot in the same clock cycle, so that the memory access efficiency is improved while the hardware complexity is low.

[0039] On the basis of the foregoing, the embodiment of the application further provides an optional implementation of how the arbitration module transmits the memory access request to the storage unit, which is described below.

[0040] When any one of the channels in the load-store queue is in the first-order occupied state (the first-order occupied state refers to a state in which there is a valid memory access request in the channel and no hit signal corresponding to the instruction in the channel is received from the storage unit), it can also be understood that when the number of the channels in the load-store queue in the first-order occupied state is greater than or equal to 1, the arbitration module is configured to determine a first target channel from the channels in the load-store queue in the first-order occupied state, and determine a second target channel from the remaining channels (all the channels in the load queue except the first target channel and the other channels in the load-store queue); the second target channel is a channel in the first-order occupied state and does not conflict with the first target channel. Here, the non-conflict means that the target address carried by the memory access request in the first target channel belongs to a different address block from the target address carried by the memory access request in the second target channel.

[0041] When none of the channels in the load-store queue is in the first-order occupied state, the arbitration module is configured to determine a first target channel from the channels in the load queue in the first-order occupied state, and determine a second target channel from the remaining channels (all the channels in the load queue except the first target channel).

[0042] When the first target channel and the second target channel exist, the arbitration module is configured to connect the first target channel with a first port of the storage unit, and connect the second target channel with a second port of the storage unit; the first port is a memory request interaction port corresponding to an address block to which the target address carried by the memory access request in the first target channel belongs, the second port is a memory request interaction port corresponding to an address block to which the target address carried by the memory access request in the second target channel belongs, and the address block corresponding to the first port is different from the address block corresponding to the second port.

[0043] The first target channel and the second target channel are configured to transmit the memory access requests corresponding thereto to the storage unit through the memory request paths provided by the arbitration module.

[0044] When only the first target channel exists, the arbitration module is configured to connect the first target channel with the first port of the storage unit.

[0045] Please refer to Figure 2 , Figure 2 One of the port state diagrams provided for embodiments of the present application. In Figure 2 , A2 and A4 are third ports, and A5 and A6 are register write ports.

[0046] Figure 2 At the corresponding k clock, at this time, the first target channel is the third channel in the load store queue (the first load channel), the second target channel is the first channel in the load queue (the second load channel), A1 represents the first port, and A3 represents the second port.

[0047] In an optional embodiment, when a memory access request transmitted by a target channel (which can be a first target channel or a second target channel) hits, the storage unit can feed back a hit signal to the target channel through a memory access request path provided by the arbitration module. The hit signal and the received memory access request are at the same clock.

[0048] When the storage unit obtains a memory access request of a storage instruction, the target storage data in the memory access request is written to the corresponding target address.

[0049] The storage unit parses the tag field (tag field) and set field (set field) of the target address in the instruction, reads the corresponding tag field after parsing, and matches the tag field. If the matching result is a hit, when the type of the memory access request is a load instruction, in the case of a hit, and the corresponding cache line state is valid, the data storage area is read, the data is returned to the memory access module, and the history access record (the cache line hit by the tag field) is updated. The history access record can be used to determine the replacement line.

[0050] When the type of the memory access request in the target channel is a storage instruction, the target channel is used to switch to an idle state when a hit signal is received.

[0051] When the type of the memory access request in the target channel is a load instruction, the target channel is used to switch to a second-order occupied state when a hit signal is received. The second-order occupied state is a state in which a hit signal corresponding to the instruction in the channel is received from the storage unit, and the load data fed back by the storage unit has not been received.

[0052] If the target channel does not receive a hit signal after sending a memory access request, it remains in a first-order occupied state, and in the queue to which the hit failure channel belongs, the hit failure channel has the lowest priority in sending a memory access request to the storage unit in the next clock.

[0053] In an alternative embodiment, the arbitration module is further configured to connect a third target channel in a second-occupied state to a third port of the memory unit; the third port is a data interaction port corresponding to an address block of a target address carried by a memory access request in the third target channel.

[0054] At a certain clock, there can be two third target channels, or only one, or none.

[0055] When the third port of the memory unit is connected to the third target channel, the memory unit is configured to feed back corresponding load data of the third target channel to the third target channel through a data path provided by the arbitration module (the third target channel enters a third-occupied state when receiving the load data, i.e., a state of receiving the load data and not yet writing the load data into a destination register), wherein the load data is data corresponding to a target address carried by a memory access request in the third target channel (which can be understood as data stored in the memory at the target address).

[0056] Please refer to Figure 3 , Figure 3 Port state diagram two provided for the embodiment of the application. Figure 3 At a corresponding k+1 clock, the first target channel at the k clock is the third channel in the load storage queue, and the second target channel at the k clock is the first channel in the load queue, both of which receive a hit signal and switch to a second-occupied state as third target channels at the k+1 clock, and are connected to the third ports A2 and A4, respectively. It should be noted that, at the k+1 clock, the first target channel is the third channel in the load storage queue, and the second target channel is the first channel in the load queue. Figure 3 At a corresponding k+1 clock, the first target channel is the fifth channel in the load storage queue (a storage channel), and the second target channel is the first channel in the load storage queue (a first load channel), A1 represents the second port, and A3 represents the first port.

[0057] The arbitration module is further configured to connect a fourth target channel in a third-occupied state to a corresponding register write port, wherein the third-occupied state indicates that the channel receives load data and has not yet written the load data into a destination register.

[0058] After the fourth target channel is connected to the corresponding register write port, the fourth target channel is configured to write the load data therein into a destination register (a register corresponding to a destination register number) through a register interaction path provided by the arbitration module.

[0059] Please refer to Figure 4 , Figure 4 Port state diagram three provided for the embodiment of the application. Figure 4Corresponding to the k+2 clock, the third target channel is the third channel in the load-store queue and the first channel in the load queue, and the load data fed back by the storage unit is received at the k+1 clock. The fourth target channel of the k+2 clock is the third channel in the load-store queue and the first channel in the load queue, which are connected with the register write ports A5 and A6 respectively. It should be noted that the first target channel of the k+1 clock is the fifth channel in the load-store queue (the storage channel), which is directly switched to the idle state after obtaining the hit information, so it will not be the third target channel of the k+2 clock. Figure 3 Corresponding to the k+1 clock, the first target channel is the fifth channel in the load-store queue (the storage channel), which is directly switched to the idle state after obtaining the hit information, so it will not be the third target channel of the k+2 clock. In Figure 3 Corresponding to the k+1 clock, the second target channel is the first channel in the load-store queue (the first load channel), which will be the third target channel of the k+2 clock, connected with the third port A2.

[0060] On the basis of the foregoing, regarding the specific process of determining the target channel, the embodiment of the application further provides an alternative implementation, please refer to the following. The process of determining the first target channel from the channels in the load-store queue in the first-order occupation state and the second target channel from the remaining channels by the arbitration module is as follows.

[0061] The arbitration module determines whether the ith channel in the load-store queue is in the idle state.

[0062] The ith channel can be the first load channel or the storage channel, and the initial value of i is 1.

[0063] If the ith channel in the load-store queue is in the first-order occupation state, the ith channel in the load-store queue is taken as the first target channel.

[0064] After the ith channel in the load-store queue is taken as the first target channel, it is determined whether the iith channel in the load-store queue is in the first-order occupation state.

[0065] The iith channel can be the first load channel or the storage channel, and the initial value of ii is 1, ii is not equal to i.

[0066] If the iith channel in the load-store queue is in the first-order occupation state, it is determined whether the memory access request in the iith channel conflicts with the memory access request in the ith channel.

[0067] The target addresses of the two memory access requests do not belong to the same address block in the memory, that is, there is no conflict.

[0068] If the memory access request in the iith channel does not conflict with the memory access request in the ith channel, the iith channel in the load-store queue is taken as the second target channel.

[0069] If the memory access request in the ii-th channel conflicts with the memory access request in the i-th channel, or the ii-th channel in the load-store queue is not in the first-order occupied state (may be an idle state, or a memory access request of the load type, after receiving the hit signal corresponding to the instruction in the channel of the storage unit feedback, but not yet written into the corresponding destination register state), then ii = ii + 1, determine whether ii is equal to i, if equal, then ii = ii + 1, then determine whether ii is greater than N, if true, then ii = ii - N, repeat to determine whether the ii-th channel in the load-store queue is in the first-order occupied state.

[0070] If it is determined through polling that the remaining channels in the load-store queue except the i-th channel cannot be used as the second target channel, it is determined whether the jj-th channel in the load queue is in the first-order occupied state.

[0071] Wherein, the jj-th channel is the second load channel, and the initial value of jj is 1.

[0072] If the jj-th channel in the load queue is in the first-order occupied state, it is determined whether the memory access request in the jj-th channel (in the load queue) conflicts with the memory access request in the i-th channel (in the load-store queue).

[0073] If the memory access request in the jj-th channel does not conflict with the memory access request in the i-th channel, the jj-th channel in the load queue is used as the second target channel.

[0074] If the memory access request in the jj-th channel conflicts with the memory access request in the i-th channel, or the jj-th channel in the load queue is not in the first-order occupied state (may be an idle state, or a memory access request of the load type, after receiving the hit signal corresponding to the instruction in the channel of the storage unit feedback, but not yet written into the corresponding destination register state), then jj = jj + 1, then determine whether jj is greater than M, if true, then jj = jj - N, (after jj is less than or equal to M, or after jj = jj - N, ) repeat to determine whether the jj-th channel in the load queue is in the first-order occupied state, wherein M represents the total number of channels in the load queue.

[0075] If it is determined through polling that the channels in the load queue cannot be used as the second target channel, it is determined that the current clock does not set the second target channel.

[0076] If the i-th channel in the load-store queue is not in the first-occupy state, i = i + 1 is executed, it is determined whether i is greater than N, if yes, i = i - N is executed; when i is less than or equal to N, or after i = i - N is executed, it is repeatedly determined whether the i-th channel in the load-store queue is in the first-occupy state, wherein N represents the total number of channels in the load-store queue.

[0077] Optionally, the arbitration module determines the first target channel from the channels in the load queue in the first-occupy state, and determines the second target channel from the remaining channels as follows.

[0078] When it is determined through polling that the N channels in the load-store queue are not in the first-occupy state, it is determined whether the j-th channel in the load queue is in the first-occupy state.

[0079] The j-th channel is the second load channel, and the initial value of j is 1.

[0080] If the j-th channel in the load queue is in the first-occupy state, the j-th channel in the load queue is taken as the first target channel.

[0081] After the j-th channel in the load queue is taken as the first target channel, it is determined whether the jj-th channel (jj is not equal to j) in the load-store queue is in the first-occupy state.

[0082] If the jj-th channel in the load queue is in the first-occupy state, it is determined whether the memory access request in the ii-th channel conflicts with the memory access request in the j-th channel.

[0083] If the memory access request in the jj-th channel does not conflict with the memory access request in the j-th channel, the jj-th channel in the load queue is taken as the second target channel.

[0084] If the memory access request in the jj-th channel conflicts with the memory access request in the j-th channel, or the jj-th channel in the load queue is not in the first-occupy state, jj = jj + 1 is executed, it is determined whether jj is equal to j, if yes, jj = jj + 1 is executed, and then it is determined whether jj is greater than M, if yes, jj = jj - M is executed, and it is repeatedly determined whether the jj-th channel in the load queue is in the first-occupy state.

[0085] If it is determined through polling that the remaining channels in the load queue except the j-th channel cannot be taken as the second target channel, it is determined that the current clock does not set the second target channel.

[0086] If the jth channel in the load queue is not in the first occupancy state, then j = j + 1, and it is determined whether j is greater than M, where M represents the total number of channels in the load queue. If yes, then j = j - M. When j is less than or equal to M, or after j = j - M, it is repeatedly determined whether the jth channel in the load queue is in the first occupancy state.

[0087] If it is determined through polling that the M channels in the load queue are all in the non-idle state, then it is determined that the current clock does not need to send a memory access request to the storage unit.

[0088] When the first target channel is the ith channel in the load store queue, if a miss occurs, then i = i + 1. When the second target channel is the ii th channel in the load store queue, if a miss occurs, then ii = ii + 1.

[0089] When the first target channel is the jth channel in the load queue, if a miss occurs, then j = j + 1. When the second target channel is the jjth channel in the load queue, if a miss occurs, then jj = jj + 1.

[0090] Please continue to refer to Figure 1 The load store queue further comprises a first register group, a first request generation unit, and a first arbitration unit. The first register group is provided with a first micro-operation code register, a first source operand register, and a first number register.

[0091] The first emission slot is used to write the parsing information of the instruction (in the first emission slot) to the first register group under the condition that the write condition is met. Optionally, the micro-operation code is written to the first micro-operation code register, the source operand is written to the first source operand register, and the destination register number is written to the first number register when the current instruction is a load instruction.

[0092] The first request generation unit is used to read the micro-operation code and the source operand in the first register group to generate a memory access request, and send the memory access request to the first arbitration unit. The memory access request generated by the first request generation unit comprises the corresponding instruction type and target address. When the instruction type is a store instruction, the memory access request generated by the first request generation unit further comprises target storage data.

[0093] The first arbitration unit is used to read the destination register number in the first register group. When the memory access request of the load instruction is obtained, the destination register number and the memory access request are written to any storage channel in the idle state, or the first load channel with the smallest number and in the idle state. When the memory access request of the store instruction is obtained, the memory access request is written to any storage channel in the idle state, or the storage channel with the smallest number and in the idle state.

[0094] Optionally, the first request generating unit is configured to determine the target address according to the base address and the offset address in the obtained source operand, and take the instruction type in the obtained micro-operation code as the instruction type corresponding to the memory access request; and when the instruction type is a store instruction, add the target storage data in the obtained source operand to the memory access request.

[0095] Optionally, the load-store queue further comprises a second register group, a second request generating unit and a second arbitration unit. The second register group is provided with a second micro-operation code register, a second source operand register and a second number register.

[0096] The second emission slot is configured to write the parsed information of the instruction (in the second emission slot) to the second register group when the write condition is met, and optionally, write the micro-operation code to the second micro-operation code register, write the source operand to the second source operand register, and when the current instruction is a load instruction, write the destination register number to the second number register.

[0097] The second request generating unit is configured to read the micro-operation code and the source operand in the second register group to generate a memory access request, and send the generated memory access request to the second arbitration unit, wherein the memory access request generated by the second request generating unit comprises the instruction type and the target address corresponding to the memory access request;

[0098] The second arbitration unit is configured to read the destination register number in the second register group, and write the obtained destination register number and the memory access request to any second load channel in an idle state or the second load channel with the smallest number and in an idle state.

[0099] The memory access system provided by the embodiment of the present application comprises a RISC-V memory access module and a storage unit implemented using a VLIW architecture, wherein one instruction comprises a plurality of RISC-V micro-operations, a plurality of memory access operations and operation operations are executed in parallel in each cycle to improve memory access efficiency, the dependency between different micro-operations in one instruction is guaranteed by a compiler, thereby reducing the hardware overhead of the VLIW architecture; in addition, when there is no dependency between a plurality of instructions, the multi-channel structure can be executed in parallel, thereby further improving the efficiency. Assuming that the RISC-V processor executes at most 4 micro-operations in each cycle and there is no dependency between the micro-operations in the figure, if the two load (ld) operations of cycle 1 miss, a miss refill event is generated, the memory access module can still accept the storage operation of the launch slot in cycle 2, and the idle storage channel performs memory access in the miss refill period of the storage unit after the load storage queue responds, if a hit occurs, the storage operation is executed normally, if a miss still occurs, a new miss refill event is generated, and similarly, as long as there is an idle channel and there is no dependency between the previous instructions, subsequent memory access instructions can still be accepted by the memory access module. In this way, the memory access parallelism between a plurality of instructions can be improved, thereby improving the memory access efficiency.

[0100] The embodiment of the present application further provides an electronic device comprising the memory access system.

[0101] To sum up, the memory access system and the electronic device provided by the embodiment of the present application comprise the following steps: the first launch slot and the second launch slot transmit the analysis information of the instructions in the first launch slot and the second launch slot to the load storage queue or the load queue under the condition that the write-in condition is met; the load storage queue generates a corresponding memory access request according to the obtained analysis information, and writes the memory access request and the corresponding destination register number of the memory access request into an idle first load channel; when the type of the memory access request is a load instruction, the memory access request is written into an idle storage channel; the load queue generates a corresponding memory access request according to the obtained analysis information, and writes the memory access request and the corresponding destination register number of the memory access request into an idle second load channel; and the arbitration module transmits the memory access request in the channel in the occupied state to the storage unit according to a preset priority rule. One single super-long word instruction is allowed to comprise a plurality of memory access operations, such as two load operations or one load operation and one storage operation, and the two memory access operations can be executed in parallel by the first launch slot and the second launch slot in the same clock cycle, so that the memory access efficiency can be improved while the hardware complexity is low.

[0102] The above merely describes the preferred embodiments of the present application but should not be used to limit the present application. Various modifications and changes can be made by those skilled in the art within the spirit and principle of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall fall within the protection scope of the present application.

[0103] It will be apparent to those skilled in the art that the application is not limited to the details of the above-exemplified embodiments and that the present application can be implemented in other particular forms without departing from the spirit or essential characteristics thereof. The embodiments should therefore be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the above description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims with respect to the figures of the patent document.

Claims

1. A memory access system, comprising: The memory access system comprises an arbitration module, a storage unit, a first emission slot, a second emission slot, a load-store queue and a load queue, the load-store queue is provided with at least two storage channels and at least two first load channels, and the load queue is provided with at least two second load channels; The first emission slot is configured to transmit the parsed information of the instruction in the first emission slot to the load-store queue under the condition that the write condition is met, wherein the parsed information comprises the micro-operation code, the source operand and the destination register number of the instruction; The load-store queue is configured to generate a corresponding memory access request according to the parsed information, and write the memory access request and the corresponding destination register number into the first load channel in the idle state when the type of the memory access request is a load instruction, and write the memory access request into the storage channel in the idle state when the type of the memory access request is a store instruction; The second emission slot is configured to transmit the parsed information of the instruction in the second emission slot to the load queue under the condition that the write condition is met; The load queue is configured to generate a corresponding memory access request according to the parsed information, and write the memory access request and the corresponding destination register number into the second load channel in the idle state; The arbitration module is configured to transmit the memory access request in the channel in the occupied state to the storage unit according to a preset priority rule.

2. The memory access system of claim 1, wherein, When any channel in the load-store queue is in a first-order occupied state, the arbitration module is configured to determine a first target channel from the channels in the first-order occupied state in the load-store queue, and determine a second target channel from the remaining channels; wherein the second target channel is a channel in the first-order occupied state and does not conflict with the first target channel; When none of the channels in the load-store queue is in the first-order occupied state, the arbitration module is configured to determine a first target channel from the channels in the first-order occupied state in the load queue, and determine a second target channel from the remaining channels; When the first target channel and the second target channel exist, the arbitration module is configured to connect the first target channel with a first port of the storage unit, and connect the second target channel with a second port of the storage unit; wherein the first port is a memory request interaction port corresponding to an address block to which a target address carried by the memory access request in the first target channel belongs, and the second port is a memory request interaction port corresponding to an address block to which a target address carried by the memory access request in the second target channel belongs; The first target channel and the second target channel are configured to transmit the corresponding memory access request to the storage unit through the memory request path provided by the arbitration module.

3. The memory access system of claim 2, wherein, The storage unit is configured to feed back a hit signal to the target channel when the memory access request transmitted by the target channel hits; When the type of the memory access request in the target channel is a store instruction, the target channel is configured to switch to the idle state when the hit signal is received; When the type of the memory access request in the target channel is a load instruction, the target channel is configured to switch to a second-order occupied state when the hit signal is received; The arbitration module is further configured to connect a third target channel in a second occupation state to a third port of the storage unit; the third port is a data interaction port corresponding to an address block of a target address carried by a memory access request in the third target channel; When the third port of the storage unit is connected to the third target channel, the storage unit is configured to feed back corresponding load data to the third target channel; the load data is data corresponding to the target address carried by the memory access request in the third target channel; The arbitration module is further configured to connect a fourth target channel in a third occupation state to a corresponding register write port; the third occupation state represents a state in which a channel receives load data and has not written the load data into a target register; After the fourth target channel is connected to the corresponding register write port, the fourth target channel is configured to write the load data in the fourth target channel into the target register through a register interaction path provided by the arbitration module.

4. The memory access system of claim 2, wherein, The process of determining the first target channel from the channels in the first occupation state in the load storage queue and determining the second target channel from the remaining channels includes: determining whether an ith channel in the load storage queue is in an idle state; if the ith channel in the load storage queue is in the first occupation state, the ith channel in the load storage queue is taken as the first target channel; after the ith channel in the load storage queue is taken as the first target channel, determining whether an ii th channel in the load storage queue is in the first occupation state; if the ii th channel in the load storage queue is in the first occupation state, determining whether a memory access request in the ii th channel conflicts with a memory access request in the ith channel; if the memory access request in the ii th channel does not conflict with the memory access request in the ith channel, the ii th channel in the load storage queue is taken as the second target channel; if the memory access request in the ii th channel conflicts with the memory access request in the ith channel, or the ii th channel in the load storage queue is not in the first occupation state, ii = ii + 1 is set, it is determined whether ii is equal to i, if yes, ii = ii + 1 is set, it is determined whether ii > N is true, if yes, ii = ii – N is set, and the process of determining whether the ii th channel in the load storage queue is in the first occupation state is repeated; if it is determined that the remaining channels except the ith channel in the load storage queue cannot be taken as the second target channel after a round of polling, it is determined whether a jj th channel in the load queue is in the first occupation state; if the jj th channel in the load queue is in the first occupation state, it is determined whether a memory access request in the jj th channel conflicts with a memory access request in the ith channel; if the memory access request in the jj th channel does not conflict with the memory access request in the ith channel, the jj th channel in the load queue is taken as the second target channel; If the memory access request in the jjth channel conflicts with the memory access request in the ith channel, or the jjth channel in the load queue is not in the first-occupied state, then let jj = jj + 1, and determine whether jj is greater than M, if yes, then let jj = jj - N, and repeat the determination of whether the jjth channel in the load queue is in the first-occupied state, wherein M represents the total number of channels in the load queue; If it is determined through polling that none of the channels in the load queue can be the second target channel, then it is determined that the current clock does not set the second target channel; If the ith channel in the load storage queue is not in the first-occupied state, then let i = i + 1, and determine whether i is greater than N, if yes, then let i = i - N; when i is less than or equal to N, or after i = i - N, repeat the determination of whether the ith channel in the load storage queue is in the first-occupied state, wherein N represents the total number of channels in the load storage queue.

5. The memory access system of claim 4, wherein, The process of determining the first target channel from the channels in the load queue that are in the first-occupied state and determining the second target channel from the remaining channels by the arbitration module includes: When it is determined through polling that none of the N channels in the load storage queue is in the first-occupied state, determine whether the jth channel in the load queue is in the first-occupied state; If the jth channel in the load queue is in the first-occupied state, then the jth channel in the load queue is taken as the first target channel; After the jth channel in the load queue is taken as the first target channel, determine whether the jjth channel in the load storage queue is in the first-occupied state; If the jjth channel in the load queue is in the first-occupied state, then determine whether the memory access request in the ii th channel conflicts with the memory access request in the jth channel; If the memory access request in the jjth channel does not conflict with the memory access request in the jth channel, then the jjth channel in the load queue is taken as the second target channel; If the memory access request in the jjth channel conflicts with the memory access request in the jth channel, or the jjth channel in the load queue is not in the first-occupied state, then let jj = jj + 1, and determine whether jj is equal to j, if yes, then let jj = jj + 1, and then determine whether jj is greater than M, if yes, then let jj = jj - M, and repeat the determination of whether the jjth channel in the load queue is in the first-occupied state; If it is determined through polling that none of the remaining channels in the load queue except the jth channel can be the second target channel, then it is determined that the current clock does not set the second target channel; If the jth channel in the load queue is not in the first-occupied state, then let j = j + 1, and determine whether j is greater than M, if yes, then let j = j - M, wherein M represents the total number of channels in the load queue; when j is less than or equal to M, or after j = j - M, repeat the determination of whether the jth channel in the load queue is in the first-occupied state; If it is determined that the M channels in the load queue are all in a non-idle state after polling a round, it is determined that the current clock does not need to send a memory access request to the storage unit.

6. The memory access system of claim 1, wherein, The load store queue further comprises a first register group, a first request generation unit, and a first arbitration unit. The first emission slot is configured to write the parsed information of the instruction in the first emission slot to the first register group if a write condition is met. The first request generation unit is configured to read the micro-operation code and the source operand in the first register group to generate a memory access request and send the memory access request to the first arbitration unit, wherein the memory access request generated by the first request generation unit comprises the instruction type and the target address corresponding to the memory access request, and when the instruction type is a store instruction, the memory access request generated by the first request generation unit further comprises target storage data. The first arbitration unit is configured to read the destination register number in the first register group, write the destination register number and the memory access request to the first load channel in an idle state when the memory access request of the load instruction is obtained, and write the memory access request to the storage channel in an idle state when the memory access request of the store instruction is obtained.

7. The memory access system of claim 6, wherein, The first register group is provided with a first micro-operation code register, a first source operand register, and a first number register.

8. The memory access system of claim 6, wherein, The first request generation unit is configured to determine the target address according to the base address and the offset address in the obtained source operand, and take the instruction type in the obtained micro-operation code as the instruction type corresponding to the memory access request, and when the instruction type is a store instruction, add the target storage data in the obtained source operand to the memory access request.

9. The memory access system of claim 1, wherein, The load store queue further comprises a second register group, a second request generation unit, and a second arbitration unit. The second emission slot is configured to write the parsed information of the instruction in the second emission slot to the second register group if a write condition is met. The second request generation unit is configured to read the micro-operation code and the source operand in the second register group to generate a memory access request and send the memory access request to the second arbitration unit, wherein the memory access request generated by the second request generation unit comprises the instruction type and the target address corresponding to the memory access request. The second arbitration unit is configured to read the destination register number in the second register group and write the obtained destination register number and the memory access request to the second load channel in an idle state.

10. An electronic device, comprising: The memory access system comprises any one of claims 1-9. The memory access system comprises any one of claims 1-9.

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