Method for realizing multiplication operation based on FPGA (Field Programmable Gate Array), computer equipment and storage medium

Abstract

The invention discloses a method for realizing multiplication operation based on an FPGA, computer equipment and a storage medium, and the method comprises the steps: traversing each multiplication unit in a circuit netlist, obtaining an input signal and an output signal of each multiplication unit, comparing the bit width of the input signal, and determining a multiplier signal; traversing the multiplier signal according to a sequence from low to high, wherein each continuous three-bit signal of the multiplier signal generates a corresponding coding logic unit; each continuous three-bit signal of the multiplier signal generates a corresponding partial product signal, and the partial product signal is stored in a partial product signal set C; performing iterative summation on the partial product signals in the partial product signal set C; carrying out traveling wave carry addition on partial product signals in the partial product signal set C; and deleting the multiplication unit in the circuit netlist. The multiplication units in the circuit netlist are processed through FPGA traversal, multiplication operation in the circuit is achieved, consumption of basic logic resources is reduced, and the application performance of the circuit is improved.

Description

Technical Field

[0001] This invention belongs to the field of FPGA software design technology, and in particular relates to a method, computer device and storage medium for implementing multiplication operations based on FPGA. Background Technology

[0002] Logic synthesis is a crucial step in the FPGA EDA software design flow. It transforms user-input behavioral-level or register-transfer-level (RTL) Verilog / VHDL circuit files into netlist files composed of basic FPGA logic units such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis comprises two stages: synthesis and mapping. Synthesis converts the behavioral-level or RTL circuit file into a logic netlist composed of gate circuits; mapping maps the logic netlist composed of gate circuits into a netlist file composed of basic FPGA logic units.

[0003] Multiplication is a common operation in digital circuit design. FPGA synthesis tools typically use the digital processing unit (DSP) within the FPGA chip to implement multiplication operations in application circuits. However, due to the limited resources of the DSP in an FPGA chip, for circuits with large-scale multiplication operations, the synthesis tool needs to implement some multiplication operations using basic logic units (BLEs). If the method of implementing multiplication operations using BLEs is not handled properly, it will consume a large amount of basic logic resources, affecting the performance of the synthesized application circuit. Therefore, it is necessary to consider implementing multiplication operations in application circuits with as few basic logic resources as possible. This helps reduce the number of basic logic resources after synthesis and plays an important role in reducing the FPGA synthesis area.

[0004] A full adder is a digital logic circuit used to perform a complete addition operation between two binary signals. A full adder consists of three input signals and two output signals. The inputs include signals A and B, and the carry signal Cin generated at the previous position. The outputs are the sum S of the binary digits and the carry signal Cout generated at the next position. Summary of the Invention

[0005] This application provides a method, computer device, and storage medium for implementing multiplication operations based on FPGA. By traversing the multiplication units in the circuit netlist through the FPGA, multiplication operations in the circuit are realized, reducing the consumption of basic logic resources and improving the application performance of the circuit.

[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.

[0007] To achieve one or more of the above objectives or other objectives, the present invention provides a method, computer device and storage medium for implementing multiplication operations based on FPGA.

[0008] A method for implementing multiplication operations based on FPGA includes: Traverse each multiplication unit in the circuit netlist, obtain the input and output signals of each multiplication unit, and compare the bit width of the input signals to determine the multiplier signal; The multiplier signals are traversed in ascending order, and each consecutive three bits of the multiplier signals generate a corresponding coded logic unit. Each consecutive three bits of the multiplier signal generate a corresponding partial product signal and are stored in the partial product signal set C. Iterative summation is performed on the partial product signals within the set C of the partial product signals; Then, a ripple carry addition is performed on the partially product signal after iterative summation to realize the multiplication operation. Delete the multiplication unit from the circuit netlist.

[0009] Traverse each multiplication unit in the circuit netlist and obtain the input A terminal signal sig_a, the input B terminal signal sig_b, and the output Y terminal signal sig_y for each multiplication unit; The multiplier signal is determined by comparing the bit widths of the input A signal sig_a and the input B signal sig_b.

[0010] If the bit width of the input A signal sig_a is smaller than the bit width of the input B signal sig_b, then the input A signal sig_a is used as the multiplier signal; otherwise, the input B signal sig_b is used as the multiplier signal, and the input A signal sig_a is used as the multiplicand signal. The multiplier signal is padded with a 0 bit in the least significant bit.

[0011] The specific process of generating coded logic units is as follows: Generate the first XOR gate unit g1, the input signals of the first XOR gate unit g1 are the i-th bit multiplication signal and the (i+1)-th bit multiplication signal; Generate the first XNOR gate unit g2, where the input signals of the first XNOR gate unit g2 are the i-th bit multiplication signal and the (i+1)-th bit multiplication signal; Generate a second XOR gate unit g3, the input signals of the second XOR gate unit g3 being the i-th bit multiplication signal and the (i+2)-th bit multiplication signal; A first AND gate unit g4 is generated, wherein the input signals of the first AND gate unit g4 are the output signals of the first XOR gate unit g2 and the output signals of the second XOR gate unit g3.

[0012] The specific process of generating the partial product signal is as follows: Generate a second AND gate unit g5, the input signal of the second AND gate unit g5 being the output signal of the first XOR gate unit g1 and the multiplicand signal in the multiplication operation; A first signal sig1 is generated as the multiplicand signal in the multiplication operation, and the multiplicand signal is padded with 1 bit 0 in the least significant bit; A third AND gate unit g6 is generated, wherein the input signal of the third AND gate unit g6 is the output signal of the first AND gate unit g4 and the first signal sig1; Generate a first OR gate unit g7, wherein the input signal of the first OR gate unit g7 is the output signal of the first XOR gate unit g1 and the output signal of the first AND gate unit g4; A first multiplexer unit g8 is generated. The data signal input to the A terminal of the first multiplexer unit g8 is the output signal of the second AND gate unit g5, the data signal input to the B terminal is the output signal of the third AND gate unit g6, and the selection signal input to the S terminal is the output signal of the first AND gate unit g4. A second multiplexer unit g9 is generated. The input data signal at terminal A of the second multiplexer unit g9 is a constant 0, the input data signal at terminal B is the output signal of the first multiplexer unit g8, and the input selection signal at terminal S is the output signal of the first OR gate unit g7.

[0013] The specific process of generating the partial product signal also includes: Generate a second signal sig2 as the output signal of the second multiplexer unit g9, determine whether the (i+2)th bit multiplier signal is true, if it is true, invert the second signal sig2 and add 1, and save the second signal sig2 into the partial product signal set C; If false, the second signal sig2 is directly saved into the partial product signal set C.

[0014] The specific process of iterative summation is as follows: Iterate through each index j in the set of partially multiplied signals C, and perform a carry-and-add operation on every three consecutive signals C[j], C[j+1], and C[j+2] to calculate the sum and carry of the three signals.

[0015] The signal C[j+1] is padded with 2 bits of 0 in the least significant bit, the signal C[j+2] is padded with 4 bits of 0 in the least significant bit, and the signal C[j] and the signal C[j+1] are expanded to the size of the signal C[j+2]. Based on each bit k of the signal C[j], a corresponding full adder unit is generated. The input signal at the A end of the full adder unit is C[j][k], the input signal at the B end is C[j+1][k], and the input signal at the Cin end is C[j+2][k]. The output signals of the Cout terminals of k full adder units are combined into a third signal sig3; The output signals of the S terminals of k full adder units are combined into a fourth signal sig4; Insert the third signal sig3 and the fourth signal sig4 into the signal set C', insert the remaining signals in the partial product signal set C into the signal set C', and set C=C' to perform the next iteration of summation.

[0016] The termination condition for the iterative summation loop is that the number of signals in the partial product signal set C is less than 3.

[0017] The specific process of ripple carry addition is as follows: Add 1 0 bit to the least significant bit of signal C[0], and expand signal C[1] to the size of signal C[0]. Generate a fifth signal sig5, the bit width of which is the bit width of signal C[0], and pad the least significant bit of the fifth signal sig5 with 1 bit 0; Iterate through each bit k of the signal C[0] to generate the corresponding full adder unit. The input signal at the A end of the full adder unit is C[0][k], the input signal at the B end is C[1][k], the input signal at the Cin end is sig5[k], the output signal at the Cout end is sig5[k+1], and the output signal at the S end is the kth bit sig_y[k] of the output signal at the Y end of the multiplication unit.

[0018] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for implementing multiplication operations based on FPGA as described above.

[0019] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method for implementing multiplication operations based on FPGA as described above.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include: This application implements multiplication operations in the circuit by traversing the multiplication units in the circuit netlist using an FPGA, thereby reducing the consumption of basic logic resources and improving the application performance of the circuit.

[0021] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic flowchart of a method for implementing multiplication operations based on FPGA, provided in Embodiment 1 of this application.

[0024] Figure 2 This is a schematic diagram of the generation encoding logic unit provided in Embodiment 1 of this application.

[0025] Figure 3 This is a schematic diagram of the process for generating a partially multiplied signal provided in Embodiment 1 of this application.

[0026] Figure 4 This is a schematic diagram of the iterative summation process provided in Embodiment 1 of this application.

[0027] Figure 5 This is a schematic diagram of the wavy carry addition process provided in Embodiment 1 of this application. Detailed Implementation

[0028] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Example 1 like Figure 1 As shown, a method for implementing multiplication operations based on FPGA includes: Traverse each multiplication unit in the circuit netlist, obtain the input and output signals of each multiplication unit, and compare the bit width of the input signals to determine the multiplier signal; The multiplier signals are traversed in ascending order, and each consecutive three bits of the multiplier signal generate a corresponding coded logic unit. Each consecutive three bits of the multiplier signal generate a corresponding partial product signal, which is then stored in the partial product signal set C. Iteratively sum the partial product signals within the set C of partial product signals; Then, perform ripple carry addition on the partial product signals within the partial product signal set C; Delete the multiplication unit from the circuit netlist.

[0031] Specifically, such as Figure 1 As shown, traverse each multiplication unit m in the circuit netlist, and for each multiplication unit m, perform the following steps: Figure 1 As shown, specifically: Obtain the input signal sig_a at input A, the input signal sig_b at input B, and the output signal sig_y at output Y of the multiplication unit m; if the bit width of sig_a is smaller than the bit width of sig_b, then sig_a is used as the multiplier signal and sig_b is used as the multiplicand signal in the multiplication operation; otherwise, sig_b is used as the multiplier signal and sig_a is used as the multiplicand signal in the multiplication operation; and pad the least significant bit of the multiplier signal with 1 bit of 0. Iterate through each bit i of the multiplier signal, and for every three consecutive bits (i, i+1, i+2) in order from least significant bit to most significant bit, perform the following steps: Figure 2 As shown, an encoding logic unit is generated based on every 3 consecutive bits (i, i+1, i+2) of the multiplier signal; Specifically, firstly, an XOR gate unit g1 is generated, whose input signals are the i-th multiplication signal and the (i+1)-th multiplier signal; then, an XNOR gate unit g2 is generated, whose input signals are the i-th multiplication signal and the (i+1)-th multiplier signal; next, an XOR gate unit g3 is generated, whose input signals are the i-th multiplication signal and the (i+2)-th multiplier signal; finally, an AND gate unit g4 is generated, whose input signals are the output signals of the XNOR gate unit g2 and the XOR gate unit g3.

[0032] like Figure 3 As shown, a partial product signal is generated based on every 3 consecutive bits (i, i+1, i+2) of the multiplier signal; Specifically, first, an AND gate unit g5 is generated, whose input signals are the output signal of the XOR gate unit g1 and the multiplicand signal in the multiplication operation; a signal sig1 is generated, which is equal to the multiplicand signal in the multiplication operation, and the least significant bit of the signal sig1 is padded with 1 bit of 0; then, an AND gate unit g6 is generated, whose input signals are the output signal of the AND gate unit g4 and the signal sig1; an OR gate unit g7 is generated, whose input signals are the output signal of the XOR gate unit g1 and the output signal of the AND gate unit g4; finally, a multiplexer unit g8 is generated, whose A terminal receives data. The signal is the output signal of AND gate unit g5, the B-terminal input data signal is the output signal of AND gate unit g6, and the S-terminal input selection signal is the output signal of AND gate unit g4; a multiplexer unit g9 is generated, the A-terminal input data signal of this multiplexer unit is a constant 0, the B-terminal input data signal is the output signal of AND multiplexer unit g8, and the S-terminal input selection signal is the output signal of OR gate unit g7; a signal sig2 is generated that is equal to the output signal of multiplexer unit g9. If the (i+2)th bit multiplier signal is true, then the signal sig2 is inverted and incremented by 1; the signal sig2 is stored in the partial product signal set C.

[0033] like Figure 4 As shown, for the signals in the partial product signal set C, an iterative summation operation is performed. For each index j of set C, the carry-saving addition operation is performed on every three consecutive signals C[j], C[j+1] and C[j+2] to calculate the sum and carry of the three signals. Specifically, first, the least significant bit of signal C[j+1] is padded with 2 bits of 0, and the least significant bit of signal C[j+2] is padded with 4 bits of 0. Then, signals C[j] and C[j+1] are expanded to the size of signal C[j+2]. For each bit k of signal C[j], a full adder unit is generated. The input signal at the A terminal of this full adder unit is C[j][k], the input signal at the B terminal is C[j+1][k], and the input signal at the Cin terminal is C[j+2][k]. The output signals at the Cout terminal of the generated k full adder units are combined into signal sig3, and the output signals at the S terminal of the k full adder units are combined into signal sig4. Signals sig3 and sig4 are then inserted into a new signal set C'. Since the number of signals in set C is not necessarily a multiple of 3, after performing carry-and-save addition operations on every three consecutive signals C[j], C[j+1], and C[j+2], the remaining signals in set C are also inserted into set C'. Set C = C' and proceed to the next iteration summation operation. The iteration loop ends when the number of signals in set C is less than 3.

[0034] like Figure 5As shown, a ripple carry addition operation is performed on the signals in the partial product signal set C; Specifically, first, the least significant bit of signal C[0] is padded with 1 bit 0, and signal C[1] is expanded to the size of signal C[0]. A signal sig5 is generated, the bit width of sig5 is set to the bit width of signal C[0], and the least significant bit of signal sig5 is padded with 1 bit 0. Each bit k of signal C[0] is traversed to generate a full adder unit. The input signal at the A end of the full adder unit is C[0][k], the input signal at the B end is C[1][k], the input signal at the Cin end is sig5[k], the output signal at the Cout end is sig5[k+1], and the output signal at the S end is the kth bit sig_y[k] of the output signal at the Y end of the multiplication unit m. Finally, remove the multiplication unit m from the circuit netlist.

[0035] Example 2 Embodiment 2 of this application provides a computer device for implementing the steps of the above-described method for multiplication operations based on FPGA. This computer device may include: a processor, a communication interface, a memory, and a communication bus. The processor, communication interface, and memory communicate with each other via the communication bus. The processor can call logical instructions from the memory. These logical instructions can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0036] Example 3 Embodiment 3 of this application provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by the computer, the computer can perform the steps of the above-described method for implementing multiplication operations based on FPGA.

[0037] Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0038] Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of the embodiments.

[0039] In summary, this application implements multiplication operations in the circuit by traversing the multiplication units in the circuit netlist using an FPGA, thereby reducing the consumption of basic logic resources and improving the application performance of the circuit.

[0040] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not intended to be limiting or specific. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0041] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for implementing multiplication operations based on FPGA, characterized in that, include: Traverse each multiplication unit in the circuit netlist, obtain the input and output signals of each multiplication unit, and compare the bit width of the input signals to determine the multiplier signal; The multiplier signals are traversed in ascending order, and each consecutive three bits of the multiplier signals generate a corresponding coded logic unit. Each consecutive three bits of the multiplier signal generate a corresponding partial product signal and are stored in the partial product signal set C. Iterative summation is performed on the partial product signals within the set C of the partial product signals; Then, a ripple carry addition is performed on the partially product signal after iterative summation to realize the multiplication operation. Delete the multiplication unit from the circuit netlist.

2. The method for implementing multiplication operations based on FPGA according to claim 1, characterized in that, Traverse each multiplication unit in the circuit netlist and obtain the input A terminal signal sig_a, the input B terminal signal sig_b, and the output Y terminal signal sig_y for each multiplication unit; The multiplier signal is determined by comparing the bit widths of the input A signal sig_a and the input B signal sig_b.

3. The method for implementing multiplication operations based on FPGA according to claim 2, characterized in that, If the bit width of the input A signal sig_a is smaller than the bit width of the input B signal sig_b, then the input A signal sig_a is used as the multiplier signal; otherwise, the input B signal sig_b is used as the multiplier signal, and the input A signal sig_a is used as the multiplicand signal. The multiplier signal is padded with a 0 bit in the least significant bit.

4. The method for implementing multiplication operations based on FPGA according to claim 1, characterized in that, The specific process of generating coded logic units is as follows: Generate the first XOR gate unit g1, the input signals of the first XOR gate unit g1 are the i-th bit multiplication signal and the (i+1)-th bit multiplication signal; Generate the first XNOR gate unit g2, where the input signals of the first XNOR gate unit g2 are the i-th bit multiplication signal and the (i+1)-th bit multiplication signal; Generate a second XOR gate unit g3, the input signals of the second XOR gate unit g3 being the i-th bit multiplication signal and the (i+2)-th bit multiplication signal; A first AND gate unit g4 is generated, wherein the input signals of the first AND gate unit g4 are the output signals of the first XOR gate unit g2 and the output signals of the second XOR gate unit g3.

5. The method for implementing multiplication operations based on FPGA according to claim 3, characterized in that, The specific process of generating the partial product signal is as follows: Generate a second AND gate unit g5, the input signal of the second AND gate unit g5 being the output signal of the first XOR gate unit g1 and the multiplicand signal in the multiplication operation; A first signal sig1 is generated as the multiplicand signal in the multiplication operation, and the multiplicand signal is padded with 1 bit 0 in the least significant bit; A third AND gate unit g6 is generated, wherein the input signal of the third AND gate unit g6 is the output signal of the first AND gate unit g4 and the first signal sig1; Generate a first OR gate unit g7, wherein the input signal of the first OR gate unit g7 is the output signal of the first XOR gate unit g1 and the output signal of the first AND gate unit g4; A first multiplexer unit g8 is generated. The data signal input to the A terminal of the first multiplexer unit g8 is the output signal of the second AND gate unit g5, the data signal input to the B terminal is the output signal of the third AND gate unit g6, and the selection signal input to the S terminal is the output signal of the first AND gate unit g4. A second multiplexer unit g9 is generated. The input data signal at terminal A of the second multiplexer unit g9 is a constant 0, the input data signal at terminal B is the output signal of the first multiplexer unit g8, and the input selection signal at terminal S is the output signal of the first OR gate unit g7.

6. The method for implementing multiplication operations based on FPGA according to claim 5, characterized in that, The specific process of generating the partial product signal also includes: Generate a second signal sig2 as the output signal of the second multiplexer unit g9, determine whether the (i+2)th bit multiplier signal is true, if it is true, invert the second signal sig2 and add 1, and save the second signal sig2 into the partial product signal set C; If false, the second signal sig2 is directly saved into the partial product signal set C.

7. The method for implementing multiplication operations based on FPGA according to claim 1, characterized in that, The specific process of iterative summation is as follows: Iterate through each index j in the set of partially multiplied signals C, and perform a carry-and-add operation on every three consecutive signals C[j], C[j+1], and C[j+2] to calculate the sum and carry of the three signals.

8. The method for implementing multiplication operations based on FPGA according to claim 7, characterized in that, The signal C[j+1] is padded with 2 bits of 0 in the least significant bit, the signal C[j+2] is padded with 4 bits of 0 in the least significant bit, and the signal C[j] and the signal C[j+1] are expanded to the size of the signal C[j+2]. Based on each bit k of the signal C[j], a corresponding full adder unit is generated. The input signal at the A end of the full adder unit is C[j][k], the input signal at the B end is C[j+1][k], and the input signal at the Cin end is C[j+2][k]. The output signals of the Cout terminals of k full adder units are combined into a third signal sig3; The output signals of the S terminals of k full adder units are combined into a fourth signal sig4; Insert the third signal sig3 and the fourth signal sig4 into the signal set C', insert the remaining signals in the partial product signal set C into the signal set C', and set C=C' to perform the next iteration of summation.

9. A method for implementing multiplication operations based on FPGA according to claim 8, characterized in that, The termination condition for the iterative summation loop is that the number of signals in the partial product signal set C is less than 3.

10. A method for implementing multiplication operations based on FPGA according to claim 2, characterized in that, The specific process of ripple carry addition is as follows: Add 1 0 bit to the least significant bit of signal C[0], and expand signal C[1] to the size of signal C[0]. Generate a fifth signal sig5, the bit width of which is the bit width of signal C[0], and pad the least significant bit of the fifth signal sig5 with 1 bit 0; Iterate through each bit k of the signal C[0] to generate the corresponding full adder unit. The input signal at the A end of the full adder unit is C[0][k], the input signal at the B end is C[1][k], the input signal at the Cin end is sig5[k], the output signal at the Cout end is sig5[k+1], and the output signal at the S end is the kth bit sig_y[k] of the output signal at the Y end of the multiplication unit.

11. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method for implementing multiplication operations based on FPGA as described in any one of claims 1 to 10.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for implementing multiplication operations based on FPGA as described in any one of claims 1 to 10.

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