Display driving circuit, display driving method and display device

Abstract

The invention provides a display driving circuit, a display driving method and a display device. According to the technical scheme provided by the embodiment of the invention, shift registers are arranged in groups, a first multiplexer switch and a second multiplexer switch are arranged, and the first multiplexer switch is connected between the shift registers and a latch and is used for controlling the connection state of the shift registers and the latch; and the second multiplexer switch is connected between the output end of the latch and the input end of the display panel, so that the display data is alternately latched and output through multiple groups of shift registers, the data processing quantity in the same time can be increased under the condition of not increasing display driving chips, the physical space in the electronic equipment is saved, and the display efficiency is improved. And meanwhile, the display data are alternately latched, so that the power supply noise caused by the latched data can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driving circuit, a display driving method, and a display device. Background Technology

[0002] In related technologies, display device driving schemes typically rely on the TCON chip on the logic board to split a line of display data into multiple groups. Existing display driver ICs are all designed with one communication channel per line. The number of output pins in existing display driver chips is limited; therefore, increasing the resolution requires increasing the number of display driver chips. For space-constrained electronic devices such as laptops, it is difficult to provide sufficient space to deploy these chips, thus affecting resolution improvements. Furthermore, the data latching schemes in related technologies use a three-level latch design. As display resolution increases, the latches need to latch a large amount of display data simultaneously, potentially generating instantaneous current, increasing power supply noise, and affecting the operational stability of the electronic device. Therefore, it is evident that related technologies face numerous limitations in improving display resolution and other display effects. Summary of the Invention

[0003] This application provides a display driving circuit, a display driving method, and a display device to improve the display resolution of electronic devices without occupying additional space or increasing power supply noise.

[0004] In a first aspect, embodiments of this application provide a display driving circuit for driving a display panel, wherein each communication channel of the display driving circuit includes:

[0005] A shift register is used to generate timing control signals for row scanning. The shift register is connected to both the clock signal terminal and the start signal terminal.

[0006] Multiple sets of latches, one set of the latches is connected to one of the shift registers, and the set of latches includes at least one first latch and at least one second latch, the first latch and the second latch being used to latch display data for different pixel rows respectively;

[0007] A first multiplexer switch is connected between the shift register and the latch, and is used to control the connection state of the shift register and the latch;

[0008] The second multiplexer switch is connected between the output terminal of the latch and the input terminal of the display panel, and is used to control the output state of the latch;

[0009] Each row of the display driver circuit includes multiple communication channels, and the multiple communication channels in each row are configured to be turned on sequentially.

[0010] In some of these embodiments, each row of channels includes four communication channels.

[0011] In some embodiments, a ground control switch is also included, and the latch is also connected to the ground wire through the ground control switch.

[0012] Secondly, embodiments of this application provide a display device, including a display panel and a display driving circuit as described in any one of the first aspects.

[0013] Thirdly, embodiments of this application provide a display driving method applied to the display device described in the second aspect, the method comprising the following steps:

[0014] In the first time period, the shift register is connected to the first latch by the first multiplexer switch to latch the first display data, and the shift register is disconnected from the second latch by the second multiplexer switch; the output terminal of the first latch is disconnected from the input terminal of the display panel by the second multiplexer switch, and the output terminal of the second latch is connected to the input terminal of the display panel by the second multiplexer switch.

[0015] In the second time period, the shift register is disconnected from the first latch by the first multiplexer switch, and the shift register is connected to the second latch to latch the second display data; the output terminal of the first latch and the input terminal of the display panel are connected by the second multiplexer switch, and the output terminal of the second latch and the input terminal of the display panel are disconnected.

[0016] In some embodiments, each row of channels includes multiple communication channels, and the method further includes:

[0017] Control multiple communication channels included in the same row to sequentially start output display data.

[0018] In some embodiments, the display device includes a ground control switch connecting the latch and a ground wire, and the method further includes:

[0019] If the data latched by the target latch in one of the multiple sets of latches is empty, the target latch is grounded by the grounding control switch.

[0020] In some embodiments, the first time period and the second time period are set alternately.

[0021] Fourthly, embodiments of this application provide a display device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method as described in any one of the second aspects.

[0022] Fifthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method as described in any one of the second aspects.

[0023] The technical solution provided by this invention sets shift registers in groups and sets a first multiplexer switch and a second multiplexer switch. The first multiplexer switch is connected between the shift register and the latch to control the connection state of the shift register and the latch. The second multiplexer switch is connected between the output terminal of the latch and the input terminal of the display panel. In this way, by alternately latching and outputting display data by multiple groups of shift registers, the amount of data processed in the same time can be increased without increasing the display driver chip, saving physical space in the electronic device. At the same time, the alternate latching of display data can reduce power supply noise caused by latching data. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a display driving circuit according to an embodiment of this application;

[0026] Figure 2 This is yet another schematic diagram of a display driving circuit according to an embodiment of this application;

[0027] Figure 3 This is a timing diagram of a shift register in one embodiment of this application;

[0028] Figure 4 This is a timing diagram of the latch and multiplexer in one embodiment of this application;

[0029] Figure 5 This is a schematic diagram of channel selection in one embodiment of this application;

[0030] Figure 6 This is a schematic diagram of channel selection logic in one embodiment of this application;

[0031] Figure 7 This is a schematic diagram of power supply noise according to an embodiment of this application;

[0032] Figure 8 This is a schematic diagram of power supply noise in related technologies;

[0033] Figure 9 This is a schematic diagram of the structure of a display device in one embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] The terms "first," "second," etc., used in the embodiments of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Additionally, the use of "and / or" in this application indicates at least one of the connected objects, such as A and / or B and / or C, representing seven possibilities: including A alone, B alone, C alone, and the presence of both A and B, both B and C, both A and C, and the presence of A, B, and C.

[0036] This application provides a display driving circuit for driving a display panel, and also provides a display device including the display driving circuit and the display panel.

[0037] In related technologies, the current driver solution can only support up to 1 line 3 communication channels (1 line 3 GATE) driver. The main way to achieve this is by splitting one line of display data into three lines of data through TCON.

[0038] The display driver chips in related technologies are all designed with a single-row 1GATE driver. Due to the limitations of current chip packaging technology, the display driver chip design can only support up to 1920 rows of pins on one side. Therefore, when driving high-resolution modules, more display driver chips are required.

[0039] For example, driving a 2560RGB*1440 resolution requires 2560*3 = 7680 sets of data. Here, 2560 refers to 2560 rows, and 3 refers to the three sets of RGB data. Since 1920*4 = 7680, and each display driver chip supports 1920 rows, four display driver chips are needed. Similarly, supporting a 3840RGB*2560 resolution requires six display driver chips. This not only increases circuit costs, but also, in size-constrained electronic devices such as laptops, an excessive number of display driver chips can lead to a higher bonding failure rate.

[0040] Meanwhile, the data latching scheme in related technologies is a three-stage latch design. The second-stage latch latches the entire row of data simultaneously, while the third-stage latch considers data delay and data matching, and the entire row of data is divided into 4 or 8 segments for simultaneous latching. According to the 1920 channel design, the entire row of data is 1920 * 8 bits = 15360. In this way, a large number of latches simultaneously latch the display data, and there will be a momentary current at the power supply when the display data changes. The more data changes at the same time, the greater the pull on the power supply and the greater the noise.

[0041] In one embodiment, such as Figure 1 As shown, the display driving circuit includes a shift register 101, multiple latches, a first multiplexer switch 1031, and a second multiplexer switch 1032.

[0042] The shift register (SR) 101 is used to generate the timing control signal for row scanning. The shift register 101 is connected to the clock signal terminal and the start signal terminal respectively to obtain the clock signal CLK and the start signal STV, and further generates the shift signal SROUT based on the clock signal CLK and the start signal STV.

[0043] Each set of latches is connected to a shift register 101. Each set of latches includes at least one first latch 1021 and at least one second latch 1022. In this embodiment, each set of latches is only described by way of example, which includes one first latch 1021 and one second latch 1022.

[0044] The first latch 1021 and the second latch 1022 are used to latch display data for different pixel rows, respectively. For example, the first latch 1021 can be used to latch odd-numbered row data, while the second latch 1022 is used to latch even-numbered row data.

[0045] The first multiplexer switch 1031 is connected between the shift register 101 and the latch, and is used to control the connection state of the shift register 101 and the latch; the second multiplexer switch 1032 is connected between the output terminal of the latch and the input terminal of the display panel, and is used to control the output state of the latch.

[0046] This application also provides a display driving method applied to the above-mentioned display device, the method comprising the following steps:

[0047] In the first time period, the shift register is connected to the first latch by the first multiplexer switch to latch the first display data, and the shift register is disconnected from the second latch by the second multiplexer switch; the output terminal of the first latch is disconnected from the input terminal of the display panel by the second multiplexer switch, and the output terminal of the second latch is connected to the input terminal of the display panel by the second multiplexer switch.

[0048] In the second time period, the shift register is disconnected from the first latch by the first multiplexer switch, and the shift register is connected to the second latch to latch the second display data; the output terminal of the first latch and the input terminal of the display panel are connected by the second multiplexer switch, and the output terminal of the second latch and the input terminal of the display panel are disconnected.

[0049] Please continue reading. Figure 1 In one embodiment, the clock signal terminal and the start signal terminal are connected, providing the clock signal CLK and the start signal STV to the shift register 101. The output terminal of the shift register 101 is selected by the first multiplexer switch 1031 to output to the first latch 1021 or the second latch 1022 according to the clock signal CLK and the start signal STV.

[0050] For example, in the first time period, such as Figure 1 As shown, under the control of the first multiplexer 1031 and the second multiplexer 1032, the shift register 101 is turned on with the first latch 1021 on the left, the gate output channel of the first latch 1021 is closed, the shift register 101 is disconnected from the second latch 1022 on the right, and the gate output channel of the second latch 1022 is opened.

[0051] At this time, the first latch 1021 latches the D0 data of the odd-numbered rows, and the second latch 1022 outputs the display data of the even-numbered rows.

[0052] Next, in the second time period, the switching states of the first multiplexer 1031 and the second multiplexer 1032 are switched, which is the opposite of the first time period. The first latch 1021 outputs the display data of the odd-numbered rows that were previously latched. After the D0 data is output to the boost module (Level shift), it is transmitted to the digital-to-analog converter (DAV) to further control the amplifier (OP) to output grayscale. The second latch 1022 latches the even-numbered rows D6 data.

[0053] In some embodiments, each row of the display driver circuit includes multiple communication channels (GATEs), which are configured to be enabled sequentially. For example, such as... Figure 2 As shown, each row of channels includes four communication channels G1 to G4.

[0054] In some embodiments, the method further includes:

[0055] Multiple sets of latches corresponding to the same communication channel are controlled to sequentially open and output display data.

[0056] like Figure 2 As shown in the technical solution of this embodiment, each row of channels can be configured with multiple communication channels, and multiple communication channels work in sequence. The control method of each communication channel is the same as that in the above embodiment. In this way, each row of communication channels can achieve multiple outputs in one row.

[0057] like Figure 2 As shown, for example, when each row of channels is configured with four communication channels (4GATE), each row of 12 CHs (channels) forms a cycle. Each CH outputs 8 bytes of data (8 bits).

[0058] Please continue reading. Figure 2 The diagram illustrates how the latches in the first row (L1) and the second row (L2) of each data channel alternately latch and output data. Each channel (CH) has four sets of latches, and the output of each latch is controlled by a multiplexer. This can also be understood as the timing of each data channel consisting of multiple consecutive, alternately set first and second time periods, thus enabling the two rows of latches to alternately latch and output data.

[0059] Please continue reading. Figure 2 , Figure 2The operating sequence of the multiplexers is MUX1&MUX5→MUX2&MUX6→MUX3&MUX7→MUX4&MUX8. Each row of 12 channels has a latch unit, with a total of 12*4 groups within the loop unit. The latch input signals are provided by 16 groups of shift registers 101. Shift register 101SR1 outputs to 1CH, 2CH, 5CH, and 6CH, shift register 101SR2 outputs to 3CH and 4CH, and so on.

[0060] This can be understood as follows: the multiplexer switches corresponding to the four communication channels work sequentially in the manner described above, enabling output through four communication channels in one row. This improves the control effect, reduces the amount of data that needs to be latched at the same time, and thus reduces the application of display driver chips.

[0061] In some embodiments, a ground control switch 104 is also included, and the latch is also connected to the ground wire via the ground control switch 104.

[0062] In some embodiments, the display device includes a ground control switch connecting the latch and a ground wire, and the method further includes:

[0063] When the data latched by the target latch in one of the multiple sets of latches is empty, the target latch is grounded by the grounding control switch 104.

[0064] It should be understood that the technical solution of this embodiment can not only output data simultaneously from each group of latches in sequence, but also enable a portion of the latch groups to work.

[0065] For example, with four sets of latches, the technical solution of this embodiment supports a maximum of 1 line of 4GATE output, but it can also support 1 line of 1GATE, 1 line of 2GATE and 1 line of 3GATE output.

[0066] Specifically, if it is necessary to achieve 1 line of 3GATE output, the target latch is grounded by the ground control switch 104 when it is not in operation, thus pulling down the level of the target latch. In this way, the target latch does not perform data latching, while the other latches still work normally, and 3GATE data can be output.

[0067] like Figure 2 As shown, for example, SR7 / 8 and SR15 / 16 signals are always grounded and pulled low. There are a total of 12*3 groups of latches in the 12CH. The last communication channel G4 is pulled low and no data latching is performed. The latches of the other 3 communication channels work normally. The signal sequence of the multiplexer is adjusted to MUX1&MUX6→MUX2&MUX5→MUX3&MUX8, which can realize the output of three signals.

[0068] Similar to the above process, when two communication channels need to be output, the SR5 / 6 / 7 / 8 and SR13 / 14 / 15 / 16 signals are always pulled low, the number of 12CH latches is 12*2 groups, the latches of the third communication channel G3 and the fourth communication channel G4 are grounded and pulled low, and no data latching is performed, the first communication channel G1 and the second communication channel G2 work normally, and the signal sequence of the multiplexer is MUX1&MUX5→MUX2&MUX6, which can realize the output of two signals.

[0069] Similar to the above process, when one communication channel output is required, the SR3 / 4 / 5 / 6 / 7 / 8 and SR11 / 12 / 13 / 14 / 15 / 16 signals are always pulled low. There are 12 groups of 12CH latches. Only the first communication channel G1 works normally, and the multiplexer signal sequence is MUX1&MUX6→MUX1&MUX6.

[0070] like Figure 3 As shown, shift register 101 generates shift signal SROUT based on clock signal CLK and start signal STV.

[0071] Please also refer to Figure 2 and Figure 3 The shift signals of the 16 shift registers 101 control the input of the 12CH latch, and the first loop unit 12CH latch input SROUT. <1> Then the second loop unit 12CH latch input SROUT <2> Then, input SROUT to the 12CH latch. <3> And so on.

[0072] like Figure 4 As shown, a single latch inputs SROUT and D0 signals, and latches the D0 signal on the falling edge of SROUT. When the multiplexer is pulled high, the latched D0 data is output.

[0073] Please continue to refer to the diagram. Figure 5 In this embodiment, 7 CHs within the 8CH channel can be selectively grounded. Thus, by adjusting the number of grounded CHs, multiple channel number selections can be supported. When performing channel selection CH SEL, all CH outputs before the selected CH are disconnected, and the next-stage inputs are all connected to GND. When the input signal of shift register 101 is given from the middle to the left and right shift registers 101, considering the left and right connection order, the left forward scan is from left to middle, and the right forward scan is from middle to right.

[0074] like Figure 6 As shown, the channel selection switch circuits on the left and right sides are different. The CH SEL function supports channel selection under forward and reverse scan inputs of shift register 101.

[0075] like Figure 7 and Figure 8 As shown, compared with traditional design solutions, the latch in this embodiment can simultaneously latch a maximum of 32 bits of data, while the latch in related solutions can simultaneously latch a maximum of 1920*8 bits. The larger the number of data latched simultaneously, the greater the number of simultaneous data changes, resulting in a greater pull on the power supply and a larger transient voltage change. In contrast, the solution in this embodiment extends the latch time by one line, while simultaneously latching a smaller number of data bits, minimizing the impact of transient power supply pulls and reducing noise.

[0076] The display device provided in this application includes all the technical solutions of the above-described display driving circuit embodiments, and therefore can achieve at least all of the above-described technical effects, which will not be repeated here.

[0077] like Figure 9 As shown, this application embodiment also provides a display device, including a processor 901, a memory 902, and a program 903 or instructions stored in the memory 902 and executable on the processor. When the program 903 or instructions are executed by the processor 901, they implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0078] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0079] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0080] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0082] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A display driving circuit for driving a display panel, characterized in that, Each communication channel of the display driver circuit includes: A shift register is used to generate timing control signals for row scanning. The shift register is connected to both the clock signal terminal and the start signal terminal. Multiple sets of latches, one set of the latches is connected to one of the shift registers, and the set of latches includes at least one first latch and at least one second latch, the first latch and the second latch being used to latch display data for different pixel rows respectively; A first multiplexer switch is connected between the shift register and the latch, and is used to control the connection state of the shift register and the latch; The second multiplexer switch is connected between the output terminal of the latch and the input terminal of the display panel, and is used to control the output state of the latch; Each row of the display driver circuit includes multiple communication channels, and the multiple communication channels in each row are configured to be turned on sequentially.

2. The display driving circuit according to claim 1, characterized in that, Each row of channels includes four communication channels.

3. The display driving circuit according to claim 1 or 2, characterized in that, It also includes a grounding control switch, and the latch is also connected to the ground wire through the grounding control switch.

4. A display device, characterized in that, It includes a display panel and a display driving circuit according to any one of claims 1 to 3.

5. A display driving method, applied to the display device of claim 4, characterized in that, The method includes the following steps: In the first time period, the shift register is connected to the first latch by the first multiplexer switch to latch the first display data, and the shift register is disconnected from the second latch by the second multiplexer switch; the output terminal of the first latch is disconnected from the input terminal of the display panel by the second multiplexer switch, and the output terminal of the second latch is connected to the input terminal of the display panel by the second multiplexer switch. In the second time period, the shift register is disconnected from the first latch by the first multiplexer switch, and the shift register is connected to the second latch to latch the second display data; the output terminal of the first latch and the input terminal of the display panel are connected by the second multiplexer switch, and the output terminal of the second latch and the input terminal of the display panel are disconnected.

6. The method according to claim 5, characterized in that, Each row of channels includes multiple communication channels, and the method further includes: Control multiple communication channels included in the same row to sequentially start output display data.

7. The method according to claim 6, characterized in that, The display device includes a grounding control switch connected to the latch and a ground wire, and the method further includes: If the data latched by the target latch in one of the multiple sets of latches is empty, the target latch is grounded by the grounding control switch.

8. The method according to claim 5, characterized in that, The first time period and the second time period are set alternately.

9. A display device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method as described in any one of claims 6-8.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the method as described in any one of claims 6-8.

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