Pixel circuit, display device including same, and electronic device including same

Abstract

The invention provides a pixel circuit, a display device and an electronic device. The pixel circuit includes a first circuit including: a seventh transistor connected to a fourth node, a fifth node, and a sixth node; an eighth transistor for receiving a second write gate signal and connected to the fifth node and the fourth node; a ninth transistor for receiving a second write gate signal and a data current, and connected to a fifth node; a tenth transistor for receiving a second initialization gate signal and a first initialization voltage, and connected to a seventh node; an eleventh transistor for receiving a transmission signal and a second power voltage, and connected to a fifth node; a twelfth transistor connected to the seventh node and the fourth node and configured to receive a second power voltage or a second initialization voltage; a thirteenth transistor for receiving an anode initialization gate signal and a second initialization voltage, and connected to a sixth node; and a light-emitting element.

Description

Technical Field

[0001] Embodiments of the present invention relate to a pixel circuit, a display device including the pixel circuit, and an electronic device including the pixel circuit. More specifically, embodiments of the present invention relate to a pixel circuit, a display device including the pixel circuit, and an electronic device including the pixel circuit, wherein the pixel circuit is driven by a pulse width modulation method, and the pixel circuit performs internal or external compensation of the threshold voltage of the driving transistor in a constant current generation circuit by current writing. The pixel circuit includes fewer transistors, therefore, the pixel circuit can be applied to ultra-high resolution display devices. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver, a data driver, and a drive controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The drive controller controls the gate driver and the data driver.

[0003] A conventional pixel circuit driven by a pulse width modulation method and internally compensated for the threshold voltage may include nineteen or more transistors and three or more capacitors. When a pixel circuit includes nineteen or more transistors and three or more capacitors, it may not be applicable to ultra-high resolution display devices due to integration limitations. Summary of the Invention

[0004] Embodiments of the present invention provide a pixel circuit driven by a pulse width modulation method. The pixel circuit performs internal or external compensation of the threshold voltage of the driving transistor in a constant current generation circuit by current writing. The pixel circuit includes fewer transistors, and therefore, the pixel circuit can be applied to ultra-high resolution display devices.

[0005] Embodiments of the present invention also provide a display device including the pixel circuit.

[0006] Embodiments of the present invention also provide an electronic device including the pixel circuit.

[0007] In an embodiment of the pixel circuit according to the present invention, the pixel circuit includes a first circuit. The first circuit includes: a seventh transistor, including a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; an eighth transistor, including a control electrode configured to receive a second write gate signal, a first electrode connected to the fifth node, and a second electrode connected to the fourth node; a ninth transistor, including a control electrode configured to receive the second write gate signal, a first electrode configured to receive a data current, and a second electrode connected to the fifth node; a tenth transistor, including a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the seventh node; an eleventh transistor, including a control electrode configured to receive a transmit signal, a first electrode configured to receive a second power voltage, and a second electrode connected to the fifth node; a twelfth transistor, including a control electrode connected to the seventh node, a first electrode configured to receive a second power voltage or a second initialization voltage, and a second electrode connected to the fourth node; a thirteenth transistor, including a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the sixth node; and a light-emitting element, including a first electrode connected to the sixth node and a second electrode configured to receive a third power voltage.

[0008] In an embodiment, the first circuit may further include: a second capacitor, including a first electrode connected to a fourth node and a second electrode connected to a sixth node; and a third capacitor, including a first electrode connected to a seventh node and a second electrode connected to a first electrode of a twelfth transistor.

[0009] In an embodiment, the pixel circuit may further include a second circuit. The second circuit includes: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a first write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the second node; a third transistor including a control electrode configured to receive the first write gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth transistor including a control electrode configured to receive a transmit signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node; a fifth transistor including a control electrode configured to receive a transmit signal, a first electrode connected to the third node, and a second electrode connected to a seventh node; and a sixth transistor including a control electrode configured to receive a first initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the first node.

[0010] In an embodiment, the second circuit may further include: a first capacitor, including a first electrode configured to receive a sweep frequency signal and a second electrode connected to the first node.

[0011] In this embodiment, the first, fourth, fifth, eighth, ninth, eleventh, twelfth, and thirteenth transistors may be P-type transistors. The second, third, sixth, and tenth transistors may be N-type transistors.

[0012] In this embodiment, the seventh transistor may be an N-type transistor. The first electrode of the twelfth transistor may be configured to receive a second initialization voltage.

[0013] In this embodiment, the seventh transistor may be a P-type transistor. The first electrode of the twelfth transistor may be configured to receive a second electrical voltage.

[0014] In an embodiment, the second power voltage may be greater than the first power voltage.

[0015] In this embodiment, the first initialization gate signal may sequentially have an active level and an inactive level during a first time period. The second initialization gate signal may sequentially have an inactive level and an active level during the first time period. The first write gate signal may have an inactive level during the first time period. The second write gate signal may have an inactive level during the first time period. The transmit signal may have an inactive level during the first time period. The sweep signal may have a high level during the first time period. The first initialization voltage may have a low level during the first time period. The data current may have a low level during the first time period. The anode initialization gate signal may have an active level during the first time period.

[0016] In this embodiment, the first initialization gate signal may have an inactive level during a second time period following the first time period. The second initialization gate signal may have an inactive level during the second time period. The first write gate signal may have an active pulse during the second time period. The second write gate signal may have an inactive level during the second time period. The transmit signal may have an inactive level during the second time period. The sweep signal may have a high level during the second time period. The first initialization voltage may have a low level during the second time period. The data current may have a low level during the second time period. The anode initialization gate signal may have an inactive level during the second time period.

[0017] In this embodiment, the first initialization gate signal may have an inactive level in a third time period following the second time period. The second initialization gate signal may have an active pulse in the third time period. The first write gate signal may have an inactive level in the third time period. The second write gate signal may have an active pulse in the third time period. The transmit signal may have an inactive level in the third time period. The sweep signal may have a high level in the third time period. The first initialization voltage may have a high pulse in the third time period. The data current may have a high level in the third time period. The anode initialization gate signal may have an active level in the third time period.

[0018] In this embodiment, the first initialization gate signal may have an inactive level in the fourth period after the third period and in the fifth period after the fourth period. The second initialization gate signal may have an inactive level in the fourth and fifth periods. The first write gate signal may have an inactive level in the fourth and fifth periods. The second write gate signal may have an inactive level in the fourth and fifth periods. The transmit signal may have an active level in the fourth and fifth periods. The sweep signal may gradually decrease from a high level in the fourth and fifth periods. The first initialization voltage may have a low level in the fourth and fifth periods. The data current may have a low level in the fourth and fifth periods. The anode initialization gate signal may have an inactive level in the fourth and fifth periods.

[0019] In one embodiment, a data voltage may be applied to the first transistor, and the light-emitting element may emit light during the write frame. A first initialization gate signal may sequentially have active and inactive levels during a first period of the write frame. A second initialization gate signal may sequentially have inactive and active levels during the first period of the write frame. The first write gate signal may have an active pulse during a second period of the write frame. Alternatively, the data voltage may not be applied to the first transistor, and the light-emitting element may emit light during the hold frame. The first and second initialization gate signals may have inactive levels during the first period of the hold frame. The first write gate signal may have inactive levels during the second period of the hold frame.

[0020] In an embodiment of the display device according to the present invention, the display device includes a first circuit. The first circuit includes: a first transistor including a control electrode connected to a first node, a first electrode configured to receive a first electrical voltage, and a second electrode connected to a second node; a second transistor including a control electrode configured to receive a sensing control signal, a first electrode connected to a third node, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a sensing control signal, a first electrode connected to the third node, and a second electrode connected to the second node; a fourth transistor including a control electrode configured to receive a transmission signal, a first electrode connected to the second node, and a second electrode connected to a first electrode of a light-emitting element; a first capacitor including a first electrode configured to receive a first electrical voltage and a second electrode connected to the first node; and a light-emitting element including a first electrode connected to the second electrode of the fourth transistor and a second electrode configured to receive a second electrical voltage.

[0021] In one embodiment, the first circuit may further include a second capacitor, the second capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node. The display device may also include a second circuit. The second circuit may include: a fifth transistor including a control electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to the fourth node; and a third capacitor including a first electrode configured to receive a frequency sweep signal and a second electrode connected to the fourth node.

[0022] In this embodiment, the first and fourth transistors may be P-type transistors. The second, third, and fifth transistors may be N-type transistors.

[0023] In this embodiment, the scan signal may have a valid pulse in the first time period. The sensing control signal may have a valid pulse in the first time period. The transmit signal may have an inactive level in the first time period. The sweep signal may have a low level in the first time period. The data voltage may have a reference level in the first time period. The scan signal may have an inactive level in the second time period after the first time period. The sensing control signal may have a valid pulse in the second time period. The transmit signal may have an inactive level in the second time period. The sweep signal may have a low level in the second time period. The scan signal may have a valid pulse in the third time period after the second time period. The sensing control signal may have an inactive level in the third time period. The transmit signal may have an inactive level in the third time period. The sweep signal may have a low level in the third time period. The data voltage may have pulse width modulated data in the third time period. The scan signal may have an inactive level in the fourth time period after the third time period and in the fifth time period after the fourth time period. The sensing control signal may have an inactive level in the fourth and fifth time periods. The transmit signal may have a valid level in the fourth and fifth time periods. The frequency sweep signal can gradually increase from a low level during the fourth and fifth time periods.

[0024] In an embodiment, the first circuit may further include: a sixth transistor, including a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the first electrode of the light-emitting element.

[0025] In this embodiment, the scan signal may have an inactive level in the first time period. The sensing control signal may have an active pulse in the first time period. The transmit signal may have an inactive level in the first time period. The sweep signal may have a low level in the first time period. The scan signal may have an inactive level in the second time period following the first time period. The sensing control signal may have an active pulse in the second time period. The transmit signal may have an inactive level in the second time period. The sweep signal may have a low level in the second time period. The scan signal may have an active pulse in the third time period following the second time period. The sensing control signal may have an inactive level in the third time period. The transmit signal may have an inactive level in the third time period. The sweep signal may have a low level in the third time period. The data voltage may sequentially have a reference level and pulse width modulation data in the third time period. The scan signal may have an inactive level in the fourth time period following the third time period and in the fifth time period following the fourth time period. The sensing control signal may have an inactive level in the fourth and fifth time periods. The transmit signal may have an active level in the fourth and fifth time periods. The sweep signal gradually increases from a low level in the fourth and fifth time periods.

[0026] In one embodiment, a data voltage may be applied to the first transistor, and the light-emitting element emits light during the write frame. A scan signal may have valid pulses during the first and third periods of the write frame. Alternatively, the data voltage may not be applied to the first transistor, and the light-emitting element emits light during the hold frame. The scan signal may have inactive levels during the first and third periods of the hold frame.

[0027] In an embodiment, the display device may further include a third circuit. The third circuit may include: a first current-applying transistor including a first electrode for receiving data current and a second electrode connected to ground; a second current-applying transistor including a first electrode connected to a third node and a second electrode connected to ground; and a third current-applying transistor including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the third node. The control electrodes of the first and second current-applying transistors may be connected to each other. The first and second current-applying transistors may be N-type transistors. The third current-applying transistor may be a P-type transistor.

[0028] In an embodiment, the display device may further include a third circuit. The third circuit may include: a first current-applying transistor, including a first electrode for receiving data current and a second electrode connected to ground; a second current-applying transistor, including a first electrode connected to a third node and a second electrode connected to ground; and a third current-applying transistor, including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the third node. The control electrodes of the first and second current-applying transistors may be connected to each other. The first, second, and third current-applying transistors may be P-type transistors.

[0029] In an embodiment, the first circuit may further include a fifth transistor, the fifth transistor including a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the first electrode of the light-emitting element. The display device may further include a second circuit. The second circuit may include: a sixth transistor including a control electrode connected to the fourth node, a first electrode configured to receive a second power voltage, and a second electrode connected to the fifth node; a seventh transistor including a control electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to the sixth node; an eighth transistor including a control electrode configured to receive a compensation gate signal, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; a ninth transistor including a control electrode configured to receive a transmission signal, a first electrode connected to the fifth node, and a second electrode connected to the first node; a second capacitor including a first electrode configured to receive a sweep frequency signal and a second electrode connected to the fourth node; and a third capacitor including a first electrode connected to the sixth node and a second electrode connected to the fourth node.

[0030] In this embodiment, the first, fourth, fifth, sixth, and ninth transistors may be P-type transistors. The second, third, seventh, and eighth transistors may be N-type transistors.

[0031] In this embodiment, the scan signal may have a valid pulse in the first time period. The sensing control signal may have a valid pulse in the first time period. The transmit signal may have an inactive level in the first time period. The sweep signal may have a high level in the first time period. The anode initialization gate signal may have a valid level in the first time period. The data voltage may have a reference level in the first time period. The scan signal may have an inactive level in the second time period after the first time period. The sensing control signal may have a valid pulse in the second time period. The transmit signal may have an inactive level in the second time period. The sweep signal may have a high level in the second time period. The anode initialization gate signal may have a valid level in the second time period. The scan signal may have a valid pulse in the third time period after the second time period. The sensing control signal may have an inactive level in the third time period. The transmit signal may have an inactive level in the third time period. The sweep signal may have a high level in the third time period. The anode initialization gate signal may have a valid level in the third time period. The data voltage may have pulse width modulated data in the third time period. The scan signal may have an inactive level in the fourth time period after the third time period and in the fifth time period after the fourth time period. The sensing control signal can be inactive during the fourth and fifth time periods. The transmit signal can be active during the fourth and fifth time periods. The sweep signal gradually decreases from a high level during the fourth and fifth time periods. The anode initialization gate signal can be inactive during the fourth and fifth time periods.

[0032] In one embodiment, a data voltage may be applied to the sixth transistor, and the light-emitting element may emit light during the write frame. A scan signal may have valid pulses during the first and third periods of the write frame. Alternatively, the data voltage may not be applied to the sixth transistor, and the light-emitting element may emit light during the hold frame. The scan signal may have inactive levels during the first and third periods of the hold frame.

[0033] In an embodiment, the display device may further include a second circuit. The second circuit may include: a sixth transistor including a control electrode connected to a fourth node, a first electrode configured to receive a second power voltage, and a second electrode connected to a fifth node; a seventh transistor including a control electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to the sixth node; an eighth transistor including a control electrode configured to receive a compensation gate signal, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; a ninth transistor including a control electrode configured to receive a transmit signal, a first electrode connected to the fifth node, and a second electrode connected to the first node; a second capacitor including a first electrode configured to receive a sweep frequency signal and a second electrode connected to the fourth node; and a third capacitor including a first electrode connected to the sixth node and a second electrode connected to the fourth node.

[0034] In an embodiment of the display device according to the present invention, the display device includes a display panel, a data driver, a gate driver, and an emitter driver. The display panel includes pixels. The data driver is configured to output a data voltage to the pixels. The gate driver is configured to output a gate signal to the pixels. The emitter driver is configured to output an emitter signal to the pixels. The pixels include first circuitry. The first circuit includes: a seventh transistor, including a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; an eighth transistor, including a control electrode configured to receive a second write gate signal, a first electrode connected to a fifth node, and a second electrode connected to a fourth node; a ninth transistor, including a control electrode configured to receive a second write gate signal, a first electrode configured to receive a data current, and a second electrode connected to a fifth node; a tenth transistor, including a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to a seventh node; an eleventh transistor, including a control electrode configured to receive a transmit signal, a first electrode configured to receive a second power voltage, and a second electrode connected to a fifth node; a twelfth transistor, including a control electrode connected to a seventh node, a first electrode configured to receive a second power voltage or a second initialization voltage, and a second electrode connected to a fourth node; a thirteenth transistor, including a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to a sixth node; and a light-emitting element, including a first electrode connected to a sixth node and a second electrode configured to receive a third power voltage.

[0035] In an embodiment of the electronic device according to the present invention, the electronic device includes a display panel, a data driver, a gate driver, a transmitter driver, a drive controller, and a processor. The display panel includes pixels. The data driver is configured to output a data voltage to the pixels. The gate driver is configured to output a gate signal to the pixels. The transmitter driver is configured to output a transmitter signal to the pixels. The drive controller is configured to control the data driver, the gate driver, and the transmitter driver. The processor is configured to output input image data and input control signals to the drive controller. The pixels include first circuitry. The first circuit includes: a seventh transistor, including a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; an eighth transistor, including a control electrode configured to receive a second write gate signal, a first electrode connected to a fifth node, and a second electrode connected to a fourth node; a ninth transistor, including a control electrode configured to receive a second write gate signal, a first electrode configured to receive a data current, and a second electrode connected to a fifth node; a tenth transistor, including a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to a seventh node; an eleventh transistor, including a control electrode configured to receive a transmit signal, a first electrode configured to receive a second power voltage, and a second electrode connected to a fifth node; a twelfth transistor, including a control electrode connected to a seventh node, a first electrode configured to receive a second power voltage or a second initialization voltage, and a second electrode connected to a fourth node; a thirteenth transistor, including a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to a sixth node; and a light-emitting element, including a first electrode connected to a sixth node and a second electrode configured to receive a third power voltage.

[0036] The pixel circuit, the display device including the pixel circuit, and the electronic device including the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor in the constant current generation circuit can be compensated internally or externally through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0037] Furthermore, at least one transistor in the pulse width modulation circuit and at least one transistor in the constant current generation circuit can be an N-type transistor, which can reduce power consumption. Attached Figure Description

[0038] The above and other features and advantages of the invention will become clearer by referring to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention; Figure 2 It is shown Figure 1 The circuit diagram of the pixel circuit of the display panel; Figure 3 It is shown Figure 2 A circuit diagram showing the operation of the pixel circuit in the first time period of the driving timing; Figure 4 It is shown that it was applied to in the first time period Figure 2 The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 5 It is shown Figure 2 The circuit diagram of the pixel circuit operation in the second time period of the driving timing; Figure 6 It is shown that it was applied to in the second time period Figure 2 The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 7 It is shown Figure 2 The circuit diagram of the operation of the pixel circuit in the third time period of the driving timing; Figure 8 This shows that it was applied to the third time period. Figure 2 The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 9 It is shown Figure 2 The circuit diagram of the operation of the pixel circuit in the fourth stage of the driving timing; Figure 10 This shows that it was applied to in the fourth time period. Figure 2 The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 11 It is shown Figure 2 The circuit diagram of the operation of the pixel circuit in the fifth stage of the driving timing; Figure 12 This shows that it was applied to in the fifth time period. Figure 2 The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 13 This is a circuit diagram illustrating the pixel circuitry of a display panel of a display device according to an embodiment of the present invention; Figure 14 This shows the application applied in the write frame. Figure 2The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 15 This shows the application to the holding frame. Figure 2 The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 16 It shows that it is applied to Figure 2 The input signal of the pixel circuit and Figure 2 A timing diagram of an example of the output signal of a pixel circuit; Figure 17 This is a circuit diagram illustrating the pixel circuit of the display panel of a display device according to an embodiment of the present invention, the data driver of the display panel driver of the display device, and the constant current application circuit; Figure 18 It is shown Figure 17 The operation of the pixel circuit in the first period of the driving timing and Figure 17 A circuit diagram showing the operation of the constant current application circuit during the first phase of the drive timing. Figure 19 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit in the first time period; Figure 20 It is shown Figure 17 The operation of the pixel circuit in the second stage of the driving timing and Figure 17 A circuit diagram showing the operation of the constant current application circuit during the second phase of the drive timing. Figure 21 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit in the second time period; Figure 22 It is shown Figure 17 The operation of the pixel circuit in the third stage of the driving timing and Figure 17 A circuit diagram showing the operation of the constant current application circuit in the third phase of the drive timing. Figure 23 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit in the third time period; Figure 24 It is shown Figure 17 The operation of the pixel circuit in the fourth stage of the driving timing and Figure 17A circuit diagram showing the operation of the constant current application circuit in the fourth phase of the drive timing. Figure 25 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit in the fourth time period; Figure 26 It is shown Figure 17 The operation of the pixel circuit in the fifth stage of the driving timing and Figure 17 A circuit diagram showing the operation of the constant current application circuit in the fifth stage of the drive timing. Figure 27 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit in the fifth time period; Figure 28 This is a circuit diagram illustrating the pixel circuit of the display panel of a display device according to an embodiment of the present invention, the data driver of the display panel driver of the display device, and the constant current application circuit; Figure 29 It is shown Figure 28 pixel circuits and Figure 28 Timing diagram of an example of the input and output signals of a constant current application circuit; Figure 30 This is a circuit diagram illustrating the pixel circuit of the display panel of a display device according to an embodiment of the present invention, the data driver of the display panel driver of the display device, and the constant current application circuit; Figure 31 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit; Figure 32 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit in a written frame; Figure 33 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of a constant current application circuit for input and output signals in a holding frame; Figure 34 It is shown Figure 17 pixel circuits and Figure 17 Timing diagram of an example of the input and output signals of a constant current application circuit; Figure 35This is a circuit diagram illustrating the pixel circuit of the display panel of a display device according to an embodiment of the present invention, the data driver of the display panel driver of the display device, and the constant current application circuit; Figure 36 It is shown Figure 35 The operation of the pixel circuit in the first period of the driving timing and Figure 35 A circuit diagram showing the operation of the constant current application circuit during the first phase of the drive timing. Figure 37 It is shown Figure 35 pixel circuits and Figure 35 Timing diagram of an example of the input and output signals of a constant current application circuit in the first time period; Figure 38 It is shown Figure 35 The operation of the pixel circuit in the second stage of the driving timing and Figure 35 A circuit diagram showing the operation of the constant current application circuit during the second phase of the drive timing. Figure 39 It is shown Figure 35 pixel circuits and Figure 35 Timing diagram of an example of the input and output signals of a constant current application circuit in the second time period; Figure 40 It is shown Figure 35 The operation of the pixel circuit in the third stage of the driving timing and Figure 35 A circuit diagram showing the operation of the constant current application circuit in the third phase of the drive timing. Figure 41 It is shown Figure 35 pixel circuits and Figure 35 Timing diagram of an example of the input and output signals of a constant current application circuit in the third time period; Figure 42 It is shown Figure 35 The operation of the pixel circuit in the fourth stage of the driving timing and Figure 35 A circuit diagram showing the operation of the constant current application circuit in the fourth phase of the drive timing. Figure 43 It is shown Figure 35 pixel circuits and Figure 35 Timing diagram of an example of the input and output signals of a constant current application circuit in the fourth time period; Figure 44 It is shown Figure 35 The operation of the pixel circuit in the fifth stage of the driving timing and Figure 35 A circuit diagram showing the operation of the constant current application circuit in the fifth stage of the drive timing. Figure 45 It is shown Figure 35pixel circuits and Figure 35 Timing diagram of an example of the input and output signals of a constant current application circuit in the fifth time period; Figure 46 This is a circuit diagram illustrating the pixel circuit of the display panel of a display device according to an embodiment of the present invention, the data driver of the display panel driver of the display device, and the constant current application circuit; Figure 47 It is shown Figure 35 pixel circuits and Figure 35 Timing diagram of an example of the input and output signals of a constant current application circuit in a written frame; Figure 48 It is shown Figure 35 pixel circuits and Figure 35 Timing diagram of an example of a constant current application circuit for input and output signals in a holding frame; Figure 49 It is shown Figure 35 pixel circuits and Figure 35 Timing diagram of an example of the input and output signals of a constant current application circuit; Figure 50 This is a block diagram illustrating an electronic device according to an embodiment of the present invention; Figure 51 It is shown that Figure 50 A diagram illustrating an example of an electronic device implemented as a smartphone; and Figure 52 It is shown that Figure 50 The diagram shows an example of an electronic device implemented as a smartwatch. Detailed Implementation

[0039] It will be understood that when an element is referred to as being "connected to" another element, it can be directly connected to said other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly connected to" another element, there is no intermediary element.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both singular and plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising” and / or “including” and variations thereof are used in this specification, they indicate the presence of the stated features, regions, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integrals, steps, operations, elements, components, and / or groups thereof.

[0041] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0042] The invention will be explained in detail below with reference to the accompanying drawings.

[0043] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0044] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver may also include a transmitter driver 600.

[0045] The display panel 100 has a display area in which an image is displayed and a peripheral area adjacent to the display area.

[0046] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 that intersects the first direction D1.

[0047] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0048] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0049] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0050] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0051] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0052] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0053] The drive controller 200 generates a fourth control signal CONT4 based on the input control signal CONT for controlling the operation of the transmitter driver 600, and outputs the fourth control signal CONT4 to the transmitter driver 600.

[0054] The gate driver 300 generates a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0055] In an embodiment of the present invention, the gate driver 300 may be integrated in the peripheral region of the display panel 100. Alternatively, the gate driver 300 may be mounted on the peripheral region of the display panel 100.

[0056] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0057] In an embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0058] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL.

[0059] In an embodiment of the present invention, the data driver 500 may be integrated into the peripheral area of ​​the display panel 100. Alternatively, the data driver 500 may be mounted on the peripheral area of ​​the display panel 100.

[0060] The transmitter driver 600 generates a transmission signal EM in response to a fourth control signal CONT4 received from the drive controller 200. The transmitter driver 600 can output the transmission signal EM to the display panel 100.

[0061] In an embodiment of the present invention, the transmitter driver 600 may be integrated into the peripheral area of ​​the display panel 100. Alternatively, the transmitter driver 600 may be mounted on the peripheral area of ​​the display panel 100.

[0062] Figure 2 It is shown Figure 1 The circuit diagram of the pixel circuit of the display panel 100.

[0063] Reference Figure 1 and Figure 2 The pixel circuit may include a first circuit CC and a second circuit PC.

[0064] The first circuit CC can be a "constant current generation circuit" for constant current generation ("CCG"). The second circuit PC can be a "pulse width modulation circuit" for pulse width modulation ("PWM").

[0065] The first circuit CC includes: a seventh transistor T7, including a control electrode connected to the fourth node N4, a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6; an eighth transistor T8, including a control electrode for receiving a second write gate signal GW2, a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4; a ninth transistor T9, including a control electrode for receiving the second write gate signal GW2, a first electrode for receiving data current IDATA, and a second electrode connected to the fifth node N5; and a tenth transistor T10, including a control electrode for receiving a second initialization gate signal GI2, a first electrode for receiving a first initialization voltage VINT, and a second electrode connected to the seventh node N7; The eleventh transistor T11 includes a control electrode for receiving the transmitted signal EM, a first electrode for receiving the second power voltage VDD2 (DC), and a second electrode connected to the fifth node N5; the twelfth transistor T12 includes a control electrode connected to the seventh node N7, a first electrode for receiving the second power voltage VDD2 (DC) or the second initialization voltage VAINT, and a second electrode connected to the fourth node N4; the thirteenth transistor T13 includes a control electrode for receiving the anode initialization gate signal GB, a first electrode for receiving the second initialization voltage VAINT, and a second electrode connected to the sixth node N6; and a light-emitting element EE includes a first electrode connected to the sixth node N6 and a second electrode for receiving the third power voltage VSS. Here, DC refers to direct current.

[0066] The first circuit CC may also include a second capacitor C2 and a third capacitor C3. The second capacitor C2 includes a first electrode connected to the fourth node N4 and a second electrode connected to the sixth node N6. The third capacitor C3 includes a first electrode connected to the seventh node N7 and a second electrode connected to the first electrode of the twelfth transistor T12.

[0067] The second circuit PC may include: a first transistor T1, including a control electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3; a second transistor T2, including a control electrode for receiving a first write gate signal GWC1[n], a first electrode for receiving a data voltage VDATA, and a second electrode connected to the second node N2; a third transistor T3, including a control electrode for receiving the first write gate signal GWC1[n], a first electrode connected to the first node N1, and a second electrode connected to the third node N3; a fourth transistor T4, including a control electrode for receiving a transmit signal EM, a first electrode for receiving a first power voltage VDD1 (DC), and a second electrode connected to the second node N2; a fifth transistor T5, including a control electrode for receiving the transmit signal EM, a first electrode connected to the third node N3, and a second electrode connected to the seventh node N7; and a sixth transistor T6, including a control electrode for receiving a first initialization gate signal GI1, a first electrode for receiving a first initialization voltage VINT, and a second electrode connected to the first node N1.

[0068] The second circuit PC may also include a first capacitor C1, which includes a first electrode for receiving the sweep frequency signal SWEEP and a second electrode connected to the first node N1.

[0069] As mentioned above, a pixel circuit may include thirteen transistors and three capacitors.

[0070] In this embodiment, some of the transistors in the pixel circuit can be P-type transistors, and some of the transistors in the pixel circuit can be N-type transistors. For example, a P-type transistor can be a low-temperature polycrystalline silicon (“LTPS”) transistor. For example, an N-type transistor can be an oxide semiconductor transistor.

[0071] For example, transistors T1, T4, T5, T8, T9, T11, T12, and T13 can be P-type transistors. Transistors T2, T3, T6, and T10 can be N-type transistors.

[0072] In this embodiment, the seventh transistor T7 can be an N-type transistor. The first electrode of the twelfth transistor T12 can receive the second initialization voltage VAINT.

[0073] For example, the first transistor T1 may further include a second control electrode for receiving a first power voltage VDD1 (DC). For example, the second transistor T2 may further include a second control electrode connected to the control electrode of the second transistor T2. For example, the third transistor T3 may further include a second control electrode connected to the control electrode of the third transistor T3. For example, the sixth transistor T6 may further include a second control electrode connected to the control electrode of the sixth transistor T6. For example, the seventh transistor T7 may further include a second control electrode for receiving the power voltage VDD. For example, the tenth transistor T10 may further include a second control electrode connected to the control electrode of the tenth transistor T10.

[0074] The light-emitting element EE can emit light based on the data voltage VDATA and the data current IDATA.

[0075] The data voltage VDATA can have a voltage level that varies according to the light emission intensity of each pixel. For example, the data voltage VDATA can have a first current level for red pixels, a second current level for green pixels that is different from the first current level, and a third current level for blue pixels that is different from the first and second current levels.

[0076] For example, the second power voltage VDD2 can be a high power voltage used to determine the light emission level of the light-emitting element EE, and the third power voltage VSS can be a low power voltage used to determine the light emission level of the light-emitting element EE. The second power voltage VDD2 can be greater than the third power voltage VSS.

[0077] For example, the second power voltage VDD2 can be greater than the first power voltage VDD1. The first power voltage VDD1 can be the voltage used to turn on the twelfth transistor T12. The twelfth transistor T12 is a P-type transistor, which allows the first power voltage VDD1 to be less than the second power voltage VDD2.

[0078] When the first transistor T1 is off and the seventh transistor T7 is on during the light emission period, the light-emitting element EE can emit light. When the first transistor T1 is on, and therefore the first power voltage VDD1 is applied to the control electrode of the twelfth transistor T12 during the light emission cutoff period, the twelfth transistor T12 can be turned on. When the twelfth transistor T12 is on, the second initialization voltage VAINT is applied to the fourth node N4 through the twelfth transistor T12, causing the seventh transistor T7 to be turned off, and the light-emitting element EE can stop emitting light.

[0079] For example, the second initialization voltage VAINT can be less than the third power voltage VSS. When the second initialization voltage VAINT is less than the third power voltage VSS, leakage current can be prevented from flowing through the light-emitting element EE. Therefore, the black characteristics of the pixel circuit can be enhanced.

[0080] In this embodiment, the first write gate signal GWC1[n] can be a row-by-row scan signal with different timings for pixel rows. Here, [n] can represent the nth pixel row. The signal used to receive the first write gate signal GWC1[n] is... Figure 2 The pixel circuit can be a pixel circuit included in the nth pixel row.

[0081] The first initialization gate signal GI1, the second initialization gate signal GI2, the second write gate signal GW2, and the anode initialization gate signal GB can be global scan signals with the same timing, independent of pixel rows. Similarly, the transmit signal EM can be a global scan signal with the same timing, independent of pixel rows.

[0082] The first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, and the second initialization voltage VAINT can be DC voltages. Conversely, the first initialization voltage VINT can be an AC voltage. For example, the first initialization voltage VINT can have a first level and a second level.

[0083] Figure 3 It is shown Figure 2 The circuit diagram shows the operation of the pixel circuits CC and PC in the first time period of the driving timing. Figure 4 It is shown that it was applied to in the first time period Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC. Figure 5 It is shown Figure 2 The circuit diagram shows the operation of the pixel circuits CC and PC in the second time period of the driving timing. Figure 6 It is shown that it was applied to in the second time period Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC. Figure 7 It is shown Figure 2 The circuit diagram shows the operation of the pixel circuits CC and PC in the third time period of the driving timing. Figure 8 This shows that it was applied to the third time period. Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC. Figure 9 It is shown Figure 2The circuit diagram shows the operation of the pixel circuits CC and PC in the fourth time period of the driving timing. Figure 10 This shows that it was applied to in the fourth time period. Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC. Figure 11 It is shown Figure 2 The circuit diagram shows the operation of the pixel circuits CC and PC in the fifth stage of the driving timing. Figure 12 This shows that it was applied to the fifth time period. Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC.

[0084] Reference Figures 1 to 12 In the driving timing (e.g., a frame time), the first time period DR1 can be the initialization period, the second time period DR2 can be the pulse width modulation data writing and compensation period, the third time period DR3 can be the constant current voltage writing period, the fourth time period DR4 can be the optical emission period, and the fifth time period DR5 can be the optical emission cutoff period.

[0085] The width of the fourth period DR4, which is the optical emission period, can be determined by the level of the data voltage VDATA (e.g., pulse width modulation data PWM DATA).

[0086] The sweep frequency signal SWEEP can have a constant high level in the first time period DR1, the second time period DR2 and the third time period DR3, and can gradually decrease in the fourth time period DR4 and the fifth time period DR5.

[0087] Reference Figure 3 and Figure 4 In the first time period DR1, the first initialization gate signal GI1 can sequentially have an active level and an inactive level, the second initialization gate signal GI2 can sequentially have an inactive level and an active level, the first write gate signal GWC1[n] can have an inactive level, the second write gate signal GW2 can have an inactive level, the transmit signal EM can have an inactive level, the sweep signal SWEEP can have a high level, the first initialization voltage VINT can have a low level, the data current IDATA can have a low level, and the anode initialization gate signal GB can have an active level.

[0088] Here, when the transistor used to receive the first initialization gate signal GI1, the second initialization gate signal GI2, the first write gate signal GWC1[n], the second write gate signal GW2, the transmit signal EM, and the anode initialization gate signal GB is a P-type transistor, the effective level can be low, and the inactive level can be high. Conversely, when the transistor used to receive the first initialization gate signal GI1, the second initialization gate signal GI2, the first write gate signal GWC1[n], the second write gate signal GW2, the transmit signal EM, and the anode initialization gate signal GB is an N-type transistor, the effective level can be high, and the inactive level can be low.

[0089] The first time period DR1 can be the initialization period. During the initialization period DR1, the sixth transistor T6, the tenth transistor T10, the twelfth transistor T12, and the thirteenth transistor T13 can be turned on.

[0090] During the initialization period DR1, the control electrode (first node N1) of the first transistor T1 can be initialized by the first initialization voltage VINT through the sixth transistor T6. The first initialization voltage VINT can be the level at which the first transistor T1 is turned on.

[0091] During the initialization period DR1, the control electrode (seventh node N7) of the twelfth transistor T12 can be initialized by the first initialization voltage VINT through the tenth transistor T10. The first initialization voltage VINT can be the level at which the twelfth transistor T12 is turned on.

[0092] During the initialization period DR1, the control electrode (fourth node N4) of the seventh transistor T7 can be initialized by the second initialization voltage VAINT through the twelfth transistor T12. The second initialization voltage VAINT can be the level at which the seventh transistor T7 is turned off.

[0093] During the initialization period DR1, the anode electrode of the light-emitting element EE can be initialized by the second initialization voltage VAINT through the thirteenth transistor T13.

[0094] Reference Figure 5 and Figure 6 In the second time period DR2 following the first time period DR1, the first initialization gate signal GI1 may have an inactive level, the second initialization gate signal GI2 may have an inactive level, the first write gate signal GWC1[n] may have an active pulse, the second write gate signal GW2 may have an inactive level, the transmit signal EM may have an inactive level, the sweep signal SWEEP may have a high level, the first initialization voltage VINT may have a low level, the data current IDATA may have a low level, and the anode initialization gate signal GB may have an inactive level.

[0095] The second time period DR2 can be the pulse width modulation data writing and compensation period. During the pulse width modulation data writing and compensation period DR2, the second transistor T2 can be turned on by the first write gate signal GWC1[n], the first transistor T1 can be turned on by the first initialization voltage VINT during the initialization period DR1, and the third transistor T3 can be turned on by the first write gate signal GWC1[n].

[0096] During the pulse width modulation data writing and compensation period DR2, the data voltage VDATA can be applied to the control electrode (first node N1) of the first transistor T1 along the path of the second transistor T2, the first transistor T1, and the third transistor T3. The threshold voltage of the first transistor T1 can be compensated in the data voltage VDATA through the diode-connected third transistor T3.

[0097] Reference Figure 7 and Figure 8 In the third time period DR3 after the second time period DR2, the first initialization gate signal GI1 can have an inactive level, the second initialization gate signal GI2 can have an active pulse, the first write gate signal GWC1[n] can have an inactive level, the second write gate signal GW2 can have an active pulse, the transmit signal EM can have an inactive level, the sweep signal SWEEP can have a high level, the first initialization voltage VINT can have a high pulse, the data current IDATA can have a high level, and the anode initialization gate signal GB can have an active level.

[0098] The third time period DR3 can be a constant current voltage write period. During the constant current voltage write period DR3, the ninth transistor T9 can be turned on by the second write gate signal GW2.

[0099] During the constant current-voltage write phase DR3, the data current IDATA can flow through the ninth transistor T9, the seventh transistor T7, and the thirteenth transistor T13. When the data current IDATA flows through the seventh transistor T7, the gate-source voltage can be stored in the second capacitor C2. The data current IDATA can be the target current corresponding to the target brightness of the light-emitting element EE. When the target current flows through the seventh transistor T7, the threshold voltage of the seventh transistor T7 can be compensated.

[0100] Reference Figures 9 to 12In the fourth period DR4 and the fifth period DR5 after the third period DR3, the first initialization gate signal GI1 can have an inactive level, the second initialization gate signal GI2 can have an inactive level, the first write gate signal GWC1[n] can have an inactive level, the second write gate signal GW2 can have an inactive level, the transmit signal EM can have an active level, the sweep signal SWEEP can gradually decrease from a high level, the first initialization voltage VINT can have a low level, the data current IDATA can have a low level, and the anode initialization gate signal GB can have an inactive level.

[0101] The fourth time period DR4 can be the light emission period. In the light emission period DR4, the fourth transistor T4, the fifth transistor T5, and the eleventh transistor T11 can be turned on by the emission signal EM, and the seventh transistor T7 can be turned on by the gate-source voltage set in the third time period DR3.

[0102] During the light emission period DR4, the current IEE can flow along the path of the eleventh transistor T11, the seventh transistor T7, and the light-emitting element EE, allowing the light-emitting element EE to emit light.

[0103] The fifth period, DR5, following the fourth period DR4, can be the optical emission cutoff period. As the sweep signal SWEEP decreases, the first transistor T1 can be turned on at a specific time point. The specific time point at which the first transistor T1 is turned on can be determined by the data voltage VDATA applied to the control electrode of the first transistor T1 (e.g., the data voltage VDATA applied to the first node N1 during the second period DR2).

[0104] When the first transistor T1 is turned on, the first power voltage VDD1 is applied to the control electrode of the twelfth transistor T12 along the path of the fourth transistor T4, the first transistor T1, and the fifth transistor T5.

[0105] When the first power voltage VDD1 is applied to the control electrode of the twelfth transistor T12, the twelfth transistor T12 can be turned on, allowing the second initialization voltage VAINT to be applied to the control electrode of the seventh transistor T7. When the second initialization voltage VAINT is applied to the control electrode of the seventh transistor T7, the seventh transistor T7 can be turned off, and the light-emitting element EE can stop emitting light.

[0106] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor T7 in the constant current generation circuit CC can be internally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0107] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0108] Figure 13 This is a circuit diagram illustrating the pixel circuitry of a display panel 100 of a display device according to an embodiment of the present invention.

[0109] Except that the seventh transistor T7 is a P-type transistor and the second power voltage VDD2 is applied to the first electrode of the twelfth transistor T12, the pixel circuit according to this embodiment is similar to the reference. Figure 2 The pixel circuitry of the previously described embodiments is substantially the same. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0110] In this embodiment, the seventh transistor T7 can be a P-type transistor. The first electrode of the twelfth transistor T12 can receive the second power voltage VDD2.

[0111] Figure 14 This shows the application applied in the write frame. Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC. Figure 15 This shows the application to the holding frame. Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC.

[0112] In addition to driving the display panel 100 at a variable frequency, the driving timing and reference of the pixel circuit according to this embodiment... Figure 4 , Figure 6 , Figure 8 , Figure 10 and Figure 12 The driving timing is substantially the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0113] Reference Figure 1 , Figure 2 , Figure 14 and Figure 15 It can drive the display panel 100 at a variable frequency.

[0114] The driving timing of a display device that supports a variable frequency driving method may include a write frame when the data voltage VDATA is written to the pixel and a hold frame when the light-emitting element EE emits light without writing the data voltage VDATA to the pixel.

[0115] During the write frame, the data voltage VDATA can be applied to the first transistor T1, and the light-emitting element EE can emit light. During the first time period DR1 of the write frame, the first initialization gate signal GI1 can sequentially have active and inactive levels, and the second initialization gate signal GI2 can sequentially have inactive and active levels. During the second time period DR2 of the write frame, the first write gate signal GWC1[n] can have active pulses.

[0116] During the hold frame, the data voltage VDATA may not be applied to the first transistor T1, and the light-emitting element EE may emit light. During the first time period DR1 of the hold frame, the first initialization gate signal GI1 and the second initialization gate signal GI2 may have inactive levels. During the second time period DR2 of the hold frame, the first write gate signal GWC1[n] may have inactive levels.

[0117] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor T7 in the constant current generation circuit CC can be internally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0118] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0119] Furthermore, in this embodiment, the pixel circuit can support a variable frequency driving method, which can reduce the power consumption of the display device.

[0120] Figure 16 It shows that it is applied to Figure 2 The input signals of the pixel circuits CC and PC and Figure 2 A timing diagram of the output signals of the pixel circuits CC and PC.

[0121] Except that the display panel 100 is driven by a progressive scan method, the driving timing of the pixel circuit according to this embodiment is basically the same as that of the reference. Figure 4 , Figure 6 , Figure 8 , Figure 10 and Figure 12The driving timing is the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0122] Reference Figure 1 , Figure 2 and Figure 16 The display panel 100 can be driven by a progressive light emission driving method.

[0123] In the driving timing, the first time period DR1 can be the initialization period, the second time period DR2 can be the pulse width modulation data writing and compensation period, the third time period DR3 can be the constant current voltage writing period, the fourth time period DR4 can be the optical emission period, and the fifth time period DR5 can be the optical emission cutoff period.

[0124] In this embodiment, the first write gate signal GWC1[n], the first initialization gate signal GI1, the second initialization gate signal GI2, the second write gate signal GW2, the anode initialization gate signal GB, and the transmit signal EM can be line-by-line scan signals with different timings for the pixel rows.

[0125] The first write gate signal GWC1[n], the first initialization gate signal GI1, the second initialization gate signal GI2, the second write gate signal GW2, the anode initialization gate signal GB, and the transmit signal EM can be applied to the pixel row by row.

[0126] In addition, the data voltage VDATA and the first initialization voltage VINT can be applied to the pixel row by row.

[0127] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor T7 in the constant current generation circuit CC can be internally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0128] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0129] Furthermore, in this embodiment, the pixel circuit can be driven using a progressive light emission driving method.

[0130] Figure 17 This is a circuit diagram illustrating the pixel circuits CC and PC of the display panel 100 of the display device according to an embodiment of the present invention, the data driver 500 of the display panel driver of the display device, and the constant current application circuit CMC.

[0131] Reference Figure 1 and Figure 17 The pixel circuit may include a first circuit CC and a second circuit PC.

[0132] The first circuit CC can be a constant current generation circuit for constant current generation (CCG). The second circuit PC can be a pulse width modulation circuit for pulse width modulation (PWM).

[0133] The first circuit CC includes: a first transistor TA1, including a control electrode connected to a first node NA1, a first electrode for receiving a first power voltage VDDA, and a second electrode connected to a second node NA2; a second transistor TA2, including a control electrode for receiving a sensing control signal SENSE[n], a first electrode connected to a third node NA3, and a second electrode connected to the first node NA1; a third transistor TA3, including a control electrode for receiving a sensing control signal SENSE[n], a first electrode connected to the third node NA3, and a second electrode connected to the second node NA2; a fourth transistor TA4, including a control electrode for receiving a transmission signal EM, a first electrode connected to the second node NA2, and a second electrode connected to the first electrode of a light-emitting element EEA; a first capacitor CA1, including a first electrode for receiving the first power voltage VDDA and a second electrode connected to the first node NA1; and a light-emitting element EEA, including a first electrode connected to the second electrode of the fourth transistor TA4 and a second electrode for receiving a second power voltage VSSA.

[0134] The first circuit CC may also include a second capacitor CA2, which includes a first electrode connected to the fourth node NA4 and a second electrode connected to the first node NA1.

[0135] The second circuit PC may include: a fifth transistor TA5, including a control electrode for receiving the scan signal SCAN[n] and a data voltage VDATA (see...). Figure 17 The first electrode of VDATA[n]) and the second electrode connected to the fourth node NA4; and the third capacitor CA3, including a first electrode for receiving the sweep frequency signal SWEEP and a second electrode connected to the fourth node NA4.

[0136] As mentioned above, a pixel circuit may include five transistors and three capacitors.

[0137] In this embodiment, some of the transistors in the pixel circuit can be P-type transistors, and some of the transistors in the pixel circuit can be N-type transistors.

[0138] For example, the first transistor TA1 and the fourth transistor TA4 can be P-type transistors. The second transistor TA2, the third transistor TA3, and the fifth transistor TA5 can be N-type transistors.

[0139] The display device may also include a constant current application circuit CMC (in other words, a "third circuit"). The third circuit CMC can apply the data current IDATA to the first circuit CC.

[0140] For example, the third circuit CMC can be integrated in the peripheral area of ​​the display panel 100. Alternatively, the third circuit CMC can be formed by the display panel 100 itself.

[0141] The third circuit CMC may include: a first current-applying transistor ICT1, including a first electrode for receiving data current IDATA and a second electrode connected to ground GND; a second current-applying transistor ICT2, including a first electrode connected to the third node NA3 and a second electrode connected to ground GND; and a third current-applying transistor ICT3, including a control electrode for receiving an initialization gate signal GI, a first electrode for receiving a first initialization voltage VINTA, and a second electrode connected to the third node NA3.

[0142] In this embodiment, the control electrode of the first current-applying transistor ICT1, the first electrode of the first current-applying transistor ICT1, and the control electrode of the second current-applying transistor ICT2 can be connected to each other.

[0143] In this embodiment, the first current-applying transistor ICT1 and the second current-applying transistor ICT2 can be N-type transistors. The third current-applying transistor ICT3 can be a P-type transistor.

[0144] When the data current IDATA flows through the first current-applying transistor ICT1, the pixel current IPIX can flow through the second current-applying transistor ICT2. For example, the data current IDATA can be substantially the same as the pixel current IPIX. Alternatively, the data current IDATA can be proportional to the pixel current IPIX, but it can be different from the pixel current IPIX.

[0145] The ratio of data current IDATA to pixel current IPIX can be determined by the W / L ratio of the first current-applied transistor ICT1 and the W / L ratio of the second current-applied transistor ICT2.

[0146] The light-emitting element EEA can emit light based on the data voltage VDATA and the data current IDATA.

[0147] Figure 18 It is shown Figure 17 The operation of the pixel circuits CC and PC in the first stage of the driving timing DRA1 and Figure 17 The circuit diagram shows the operation of the constant current application circuit CMC in the first period DRA1 of the drive timing. Figure 19 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 A timing diagram of an example of the input and output signals of the constant current application circuit CMC in the first time period DRA1. Figure 20 It is shown Figure 17 The operation of the pixel circuits CC and PC in the second stage of the driving timing, DRA2, and Figure 17 The circuit diagram shows the operation of the constant current application circuit CMC in the second period DRA2 of the drive timing. Figure 21 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 A timing diagram of the input and output signals of the constant current application circuit CMC in the second time period DRA2. Figure 22 It is shown Figure 17 The operation of the pixel circuits CC and PC in the third stage of the driving timing, DRA3, and Figure 17 The circuit diagram shows the operation of the constant current application circuit CMC in the third stage of the drive timing, DRA3. Figure 23 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 A timing diagram of the input and output signals of the constant current application circuit CMC in the third time period DRA3. Figure 24 It is shown Figure 17 The operation of the pixel circuits CC and PC in the fourth stage of the driving timing, DRA4, and Figure 17 The circuit diagram shows the operation of the constant current application circuit CMC in the fourth stage of the drive timing, DRA4. Figure 25 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 A timing diagram of the input and output signals of the constant current application circuit CMC in the fourth time period DRA4. Figure 26 It is shown Figure 17 The operation of the pixel circuits CC and PC in the fifth stage of the driving timing, DRA5, and Figure 17 The circuit diagram shows the operation of the constant current application circuit CMC in the fifth stage of the drive timing, DRA5. Figure 27 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 A timing diagram of the input and output signals of the constant current application circuit CMC in the fifth time period DRA5.

[0148] Reference Figure 1 as well as Figures 17 to 27 In the driving timing, the first time period DRA1 can be the initialization period, the second time period DRA2 can be the constant current sensing period, the third time period DRA3 can be the pulse width modulation data writing period, the fourth time period DRA4 can be the light emission period, and the fifth time period DRA5 can be the light emission cutoff period.

[0149] The width of DRA4, the fourth period of the light emission phase, can be determined by the level of the data voltage VDATA (e.g., pulse width modulation data PWM DATA).

[0150] The sweep signal SWEEP can have a constant low level in the first time period DRA1, the second time period DRA2 and the third time period DRA3, and can gradually increase in the fourth time period DRA4 and the fifth time period DRA5.

[0151] Reference Figure 18 and Figure 19 In the first time period DRA1, the scan signal SCAN[n] can have a valid pulse, the sensing control signal SENSE[n] can have a valid pulse, the transmit signal EM can have an invalid level, the sweep signal SWEEP can have a low level, and the data voltage VDATA can have a reference level VREF. In the first time period DRA1, the initialization gate signal GI can have a valid pulse.

[0152] In the first time period DRA1, the reference level VREF can be applied to the fourth node NA4 through the fifth transistor TA5. In the first time period DRA1, the first initialization voltage VINTA can be applied to the first node NA1 through the third current-applying transistor ICT3 and the second transistor TA2. In the first time period DRA1, the first initialization voltage VINTA can be applied to the second node NA2 through the third current-applying transistor ICT3 and the third transistor TA3.

[0153] Reference Figure 20 and Figure 21 In the second time period DRA2 following the first time period DRA1, the scan signal SCAN[n] can have an inactive level, the sensing control signal SENSE[n] can have an active pulse, the transmit signal EM can have an inactive level, and the sweep signal SWEEP can have a low level. In the second time period DRA2, the data current IDATA can have an active level.

[0154] During the second time period DRA2, the first current application transistor ICT1 and the second current application transistor ICT2 can be turned on, so that the pixel current IPIX corresponding to the data current IDATA flows through the third transistor TA3 and the first transistor TA1.

[0155] When the pixel current IPIX flows through the first transistor TA1, the gate-source voltage can be stored in the first capacitor CA1. The pixel current IPIX can be the target current corresponding to the target brightness of the light-emitting element EEA. When the target current flows through the first transistor TA1, the threshold voltage of the first transistor TA1 can be compensated.

[0156] Reference Figure 22 and Figure 23 In the third time period DRA3, following the second time period DRA2, the scan signal SCAN[n] can have a valid pulse, the sensing control signal SENSE[n] can have an invalid level, the transmit signal EM can have an invalid level, the sweep signal SWEEP can have a low level, and the data voltage VDATA can have pulse width modulation data PWMDATA. In the third time period DRA3, the initialization gate signal GI can have an invalid level. In the third time period DRA3, the data current IDATA can have an invalid level.

[0157] In the third time period DRA3, the fifth transistor TA5 is turned on, so that the data voltage VDATA corresponding to the pulse width modulation data PWM DATA can be applied to the fourth node NA4.

[0158] Reference Figures 24 to 27 In the fourth and fifth time periods, DRA4 and DRA5, following the third time period DRA3, the scan signal SCAN[n] can have an inactive level, the sensing control signal SENSE[n] can have an inactive level, the transmit signal EM can have an active level, and the sweep signal SWEEP can gradually increase from a low level.

[0159] The fourth time period, DRA4, can be the optical emission period. During the optical emission period, DRA4, the fourth transistor, TA4, can be turned on by the emission signal EM, and the first transistor, TA1, can be turned on by the gate-source voltage set after the second time period, DRA2.

[0160] During the light emission period DRA4, the current IEEA can flow along the path of the first transistor TA1, the fourth transistor TA4, and the light-emitting element EEA, allowing the light-emitting element EEA to emit light.

[0161] The fifth period, DRA5, following the fourth period DRA4, can be the optical emission cutoff period. As the sweep signal SWEEP increases, the first transistor TA1 can be cut off at a specific time point. The specific time point at which the first transistor TA1 is cut off can be determined by the data voltage VDATA applied to the fourth node NA4.

[0162] When the first transistor TA1 is turned off, the light-emitting element EEA can stop emitting light.

[0163] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TA1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0164] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0165] Figure 28 This is a circuit diagram illustrating the pixel circuits CC and PC of the display panel 100 of the display device according to an embodiment of the present invention, the data driver 500 of the display panel driver of the display device, and the constant current application circuit CMC. Figure 29 It is shown Figure 28 Pixel circuits CC and PC and Figure 28 Timing diagrams of the input and output signals of a constant current application circuit (CMC).

[0166] In addition to the pixel circuit, the display device and reference according to this embodiment also include a sixth transistor TA6. Figure 17 The display device explained in the previous embodiment is substantially the same. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiment, and any repeated explanations of the above elements will be omitted.

[0167] Reference Figure 1 , Figure 28 and Figure 29 The first circuit CC may also include a sixth transistor TA6, which includes a control electrode for receiving an anode initialization gate signal GB, a first electrode for receiving a second initialization voltage VAINTA, and a second electrode connected to the first electrode of the light-emitting element EEA.

[0168] In addition to the driving timing, which also includes the anode initialization gate signal GB, the driving timing of the pixel circuit according to this embodiment is in accordance with the reference... Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 The driving timing is substantially the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0169] The anode initialization gate signal GB can be active during the first time period DRA1, the second time period DRA2, and the third time period DRA3. Conversely, the anode initialization gate signal GB can be inactive during the fourth time period DRA4 and the fifth time period DRA5.

[0170] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TA1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0171] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0172] Figure 30 This is a circuit diagram illustrating the pixel circuits CC and PC of the display panel 100 of the display device according to an embodiment of the present invention, the data driver 500 of the display panel driver of the display device, and the constant current application circuit CMC.

[0173] Except that the first current-applying transistor ICT1 and the second current-applying transistor ICT2 are P-type transistors, the display device according to this embodiment is basically the same as the reference. Figure 17 The display device explained is the same as that in the previous embodiment. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiment, and any repeated explanations of the above elements will be omitted.

[0174] Reference Figure 1 and Figure 30 The third circuit CMC may include: a first current-applying transistor ICT1, including a first electrode for receiving data current IDATA and a second electrode connected to ground GND; a second current-applying transistor ICT2, including a first electrode connected to the third node NA3 and a second electrode connected to ground GND; and a third current-applying transistor ICT3, including a control electrode for receiving an initialization gate signal GI, a first electrode for receiving a first initialization voltage VINTA and a second electrode connected to the third node NA3.

[0175] In this embodiment, the control electrode of the first current-applying transistor ICT1, the second electrode of the first current-applying transistor ICT1, and the control electrode of the second current-applying transistor ICT2 can be connected to each other.

[0176] In this embodiment, the first current-applying transistor ICT1, the second current-applying transistor ICT2, and the third current-applying transistor ICT3 can be P-type transistors.

[0177] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TA1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0178] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0179] Figure 31 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 Timing diagrams of the input and output signals of a constant current application circuit (CMC).

[0180] In addition to the waveforms of the data voltage VDATA and the scan signal SCAN[n], the driving timing of the pixel circuit according to this embodiment is also related to the reference. Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 The driving timing is substantially the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0181] Reference Figure 1 , Figure 17 and Figure 31In the first time period DRA1, the scan signal SCAN[n] can have an inactive level, the sensing control signal SENSE[n] can have an active pulse, the transmit signal EM can have an inactive level, and the sweep signal SWEEP can have a low level. In the second time period DRA2 following the first time period DRA1, the scan signal SCAN[n] can have an inactive level, the sensing control signal SENSE[n] can have an active pulse, the transmit signal EM can have an inactive level, and the sweep signal SWEEP can have a low level. In the third time period DRA3 following the second time period DRA2, the scan signal SCAN[n] can have an active pulse, the sensing control signal SENSE[n] can have an inactive level, the transmit signal EM can have an inactive level, the sweep signal SWEEP can have a low level, and the data voltage VDATA can sequentially have a reference level VREF and pulse width modulation data PWM DATA that is higher than the reference level VREF. In the fourth and fifth time periods, DRA4 and DRA5, following the third time period DRA3, the scan signal SCAN[n] can have an inactive level, the sensing control signal SENSE[n] can have an inactive level, the transmit signal EM can have an active level, and the sweep signal SWEEP can gradually increase from a low level.

[0182] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TA1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0183] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0184] Figure 32 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 Timing diagram of the input and output signals of the constant current application circuit CMC in the write frame. Figure 33 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 A timing diagram of an example of the input and output signals of a constant current application circuit (CMC) in a holding frame.

[0185] In addition to driving the display panel 100 at a variable frequency, the driving timing and reference of the pixel circuit according to this embodiment... Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 The driving timing is substantially the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0186] Reference Figure 1 , Figure 17 , Figure 32 and Figure 33 It can drive the display panel 100 at a variable frequency.

[0187] The driving timing of a display device that supports a variable frequency driving method may include a write frame when the data voltage VDATA is written to the pixel and a hold frame when the light-emitting element EEA emits light without writing the data voltage VDATA to the pixel.

[0188] During the write frame, the data voltage VDATA can be applied to the first transistor TA1, and the light-emitting element EEA can emit light. During the first time period DRA1 and the third time period DRA3 of the write frame, the scan signal SCAN[n] can have valid pulses.

[0189] During the hold frame, the data voltage VDATA may not be applied to the first transistor TA1, and the light-emitting element EEA may emit light. During the first time period DRA1 and the third time period DRA3 of the hold frame, the scan signal SCAN[n] may have an inactive level.

[0190] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TA1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0191] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0192] Furthermore, in this embodiment, the pixel circuit can support a variable frequency driving method, which can reduce the power consumption of the display device.

[0193] Figure 34 It is shown Figure 17 Pixel circuits CC and PC and Figure 17 Timing diagrams of the input and output signals of a constant current application circuit (CMC).

[0194] In addition to the display panel 100 being driven by a progressive scan method, the driving timing and reference of the pixel circuit according to this embodiment are as follows: Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 The driving timing is substantially the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0195] Reference Figure 1 , Figure 17 and Figure 34 The display panel 100 can be driven by a progressive light emission driving method.

[0196] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TA1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0197] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0198] Figure 35 This is a circuit diagram illustrating the pixel circuits CC and PC of the display panel 100 of the display device according to an embodiment of the present invention, the data driver 500 of the display panel driver of the display device, and the constant current application circuit CMC.

[0199] Reference Figure 1 and Figure 35 The pixel circuit may include a first circuit CC and a second circuit PC.

[0200] The first circuit CC can be a constant current generation circuit for constant current generation (CCG). The second circuit PC can be a pulse width modulation circuit for pulse width modulation (PWM).

[0201] The first circuit CC includes: a first transistor TB1, including a control electrode connected to a first node NB1, a first electrode for receiving a first power voltage VDD2B, and a second electrode connected to a second node NB2; a second transistor TB2, including a control electrode for receiving a sensing control signal SENSE[n], a first electrode connected to a third node NB3, and a second electrode connected to the first node NB1; a third transistor TB3, including a control electrode for receiving a sensing control signal SENSE[n], a first electrode connected to the third node NB3, and a second electrode connected to the second node NB2; a fourth transistor TB4, including a control electrode for receiving a transmission signal EM, a first electrode connected to the second node NB2, and a second electrode connected to the first electrode of a light-emitting element EEB; a first capacitor CB1, including a first electrode for receiving the first power voltage VDD2B and a second electrode connected to the first node NB1; and a light-emitting element EEB, including a first electrode connected to the second electrode of the fourth transistor TB4 and a second electrode for receiving a second power voltage VSSB.

[0202] In this embodiment, the first circuit CC may further include a fifth transistor TB5. The fifth transistor TB5 includes a control electrode for receiving the anode initialization gate signal GB, a first electrode for receiving the second initialization voltage VAINTB, and a second electrode connected to the first electrode of the light-emitting element EEB.

[0203] The second circuit PC may include: a sixth transistor TB6, including a control electrode connected to the fourth node NB4, a first electrode for receiving the second power voltage VDD1B, and a second electrode connected to the fifth node NB5; and a seventh transistor TB7, including a control electrode for receiving the scan signal SCAN[n], and a second electrode for receiving the data voltage VDATA (see...). Figure 35 The first electrode of VDATA[n] in the capacitor and the second electrode connected to the sixth node NB6; the eighth transistor TB8 includes a control electrode for receiving the compensation gate signal GC[n], a first electrode connected to the fourth node NB4 and a second electrode connected to the fifth node NB5; the ninth transistor TB9 includes a control electrode for receiving the transmit signal EM, a first electrode connected to the fifth node NB5 and a second electrode connected to the first node NB1; the second capacitor CB2 includes a first electrode for receiving the sweep frequency signal SWEEP and a second electrode connected to the fourth node NB4; and the third capacitor CB3 includes a first electrode connected to the sixth node NB6 and a second electrode connected to the fourth node NB4.

[0204] As mentioned above, a pixel circuit may include nine transistors and three capacitors.

[0205] In this embodiment, some of the transistors in the pixel circuit can be P-type transistors, and some of the transistors in the pixel circuit can be N-type transistors.

[0206] For example, the first transistor TB1, the fourth transistor TB4, the fifth transistor TB5, the sixth transistor TB6, and the ninth transistor TB9 can be P-type transistors. The second transistor TB2, the third transistor TB3, the seventh transistor TB7, and the eighth transistor TB8 can be N-type transistors.

[0207] For example, the first transistor TB1 may further include a second control electrode for receiving the first power voltage VDD2B. For example, the second transistor TB2 may further include a second control electrode connected to the control electrode of the second transistor TB2. For example, the third transistor TB3 may further include a second control electrode connected to the control electrode of the third transistor TB3. For example, the sixth transistor TB6 may further include a second control electrode for receiving the second power voltage VDD1B. For example, the seventh transistor TB7 may further include a second control electrode connected to the control electrode of the seventh transistor TB7. For example, the eighth transistor TB8 may further include a second control electrode connected to the control electrode of the eighth transistor TB8.

[0208] The display device may also include a third circuit CMC. The third circuit CMC can apply the data current IDATA to the first circuit CC.

[0209] For example, the third circuit CMC can be integrated in the peripheral area of ​​the display panel 100. Alternatively, the third circuit CMC can be formed by the display panel 100 itself.

[0210] The third circuit CMC may include: a first current-applying transistor ICT1, including a first electrode for receiving data current IDATA and a second electrode connected to ground GND; a second current-applying transistor ICT2, including a first electrode connected to the third node NB3 and a second electrode connected to ground GND; and a third current-applying transistor ICT3, including a control electrode for receiving an initialization gate signal GI, a first electrode for receiving a first initialization voltage VINTB, and a second electrode connected to the third node NB3.

[0211] The light-emitting element EEB can emit light based on the data voltage VDATA and the data current IDATA.

[0212] Figure 36 It is shown Figure 35 The operation of the pixel circuits CC and PC in the first stage of the driving timing DRB1 and Figure 35 The circuit diagram shows the operation of the constant current application circuit CMC in the first period DRB1 of the drive timing. Figure 37 It is shown Figure 35 Pixel circuits CC and PC and Figure 35 A timing diagram of an example of the input and output signals of the constant current application circuit CMC in the first time period DRB1. Figure 38 It is shown Figure 35 The operation of the pixel circuits CC and PC in the second stage of the driving timing DRB2 and Figure 35 The circuit diagram shows the operation of the constant current application circuit CMC in the second period of the drive timing, DRB2. Figure 39 It is shown Figure 35 Pixel circuits CC and PC and Figure 35 A timing diagram of an example of the input and output signals of the constant current application circuit CMC in the second time period DRB2. Figure 40 It is shown Figure 35 The operation of the pixel circuits CC and PC in the third stage of the driving timing, DRB3, and Figure 35 The circuit diagram shows the operation of the constant current application circuit CMC in the third stage of the drive timing, DRB3. Figure 41 It is shown Figure 35 Pixel circuits CC and PC and Figure 35 A timing diagram of the input and output signals of the constant current application circuit CMC in the third time period DRB3. Figure 42 It is shown Figure 35 The operation of the pixel circuits CC and PC in the fourth stage of the driving timing, DRB4, and Figure 35 The circuit diagram shows the operation of the constant current application circuit CMC in the fourth stage of the drive timing, DRB4. Figure 43 It is shown Figure 35 Pixel circuits CC and PC and Figure 35 A timing diagram of the input and output signals of the constant current application circuit CMC in the fourth time period DRB4. Figure 44 It is shown Figure 35 The operation of the pixel circuits CC and PC in the fifth stage of the driving timing, DRB5, and Figure 35 The circuit diagram shows the operation of the constant current application circuit CMC in the fifth stage of the drive timing, DRB5. Figure 45 It is shown Figure 35 Pixel circuits CC and PC and Figure 35 A timing diagram of the input and output signals of the constant current application circuit CMC in the fifth time period DRB5.

[0213] Reference Figure 1 as well as Figures 35 to 45In the driving timing, the first time period DRB1 can be the initialization period, the second time period DRB2 can be the constant current sensing period, the third time period DRB3 can be the pulse width modulation data writing period, the fourth time period DRB4 can be the optical emission period, and the fifth time period DRB5 can be the optical emission cutoff period.

[0214] The width of DRB4, the fourth period of optical emission, can be determined by the level of the data voltage VDATA (e.g., pulse width modulation data PWM DATA).

[0215] The sweep frequency signal SWEEP can have a constant high level in the first time period DRB1, the second time period DRB2 and the third time period DRB3, and can gradually decrease in the fourth time period DRB4 and the fifth time period DRB5.

[0216] Reference Figure 36 and Figure 37 In the first time period DRB1, the scan signal SCAN[n] can have a valid pulse, the sensing control signal SENSE[n] can have a valid pulse, the transmit signal EM can have an invalid level, the sweep signal SWEEP can have a high level, the anode initialization gate signal GB can have a valid level, and the data voltage VDATA can have a reference level VREF. In the first time period DRB1, the initialization gate signal GI can have a valid pulse.

[0217] During the first time period DRB1 to the fifth time period DRB5, the compensation gate signal GC[n] can have the same waveform and timing as the scan signal SCAN[n].

[0218] In the first time period DRB1, the reference level VREF can be applied to the sixth node NB6 through the seventh transistor TB7. In the first time period DRB1, the second power voltage VDD1B can be applied to the fourth node NB4 through the sixth transistor TB6 and the eighth transistor TB8. In the first time period DRB1, the first initialization voltage Vintb can be applied to the first node NB1 through the third current-applying transistor ICT3 and the second transistor TB2. In the first time period DRB1, the first initialization voltage Vintb can be applied to the second node NB2 through the third current-applying transistor ICT3 and the third transistor TB3.

[0219] Reference Figure 38 and Figure 39In the second time period DRB2, following the first time period DRB1, the scan signal SCAN[n] can have an inactive level, the sensing control signal SENSE[n] can have an active pulse, the transmit signal EM can have an inactive level, the sweep signal SWEEP can have a high level, and the anode initialization gate signal GB can have an active level. In the second time period DRB2, the initialization gate signal GI can have an inactive level. In the second time period DRB2, the data current IDATA can have an active level.

[0220] During the second time period DRB2, the first current application transistor ICT1 and the second current application transistor ICT2 can be turned on, so that the pixel current IPIX corresponding to the data current IDATA flows through the third transistor TB3 and the first transistor TB1.

[0221] When the pixel current IPIX flows through the first transistor TB1, the gate-source voltage can be stored in the first capacitor CB1. The pixel current IPIX can be the target current corresponding to the target brightness of the light-emitting element EEB. When the target current flows through the first transistor TB1, the threshold voltage of the first transistor TB1 can be compensated.

[0222] Reference Figure 40 and Figure 41 In the third time period, DRB3, following the second time period DRB2, the scan signal SCAN[n] can have a valid pulse, the sensing control signal SENSE[n] can have an invalid level, the transmit signal EM can have an invalid level, the sweep signal SWEEP can have a high level, the anode initialization gate signal GB can have a valid level, and the data voltage VDATA can have pulse width modulation data PWM DATA. In the third time period DRB3, the initialization gate signal GI can have an invalid level. In the third time period DRB3, the data current IDATA can have an invalid level.

[0223] In the third time period DRB3, the seventh transistor TB7 is turned on, so that the data voltage VDATA corresponding to the pulse width modulation data PWM DATA can be applied to the sixth node NA6, and the voltage level of the fourth node NB4 can be changed through the coupling of the third capacitor CB3.

[0224] Reference Figures 42 to 45 In the fourth and fifth time periods DRB4 and DRB5 following the third time period DRB3, the scan signal SCAN[n] can have an inactive level, the sensing control signal SENSE[n] can have an inactive level, the transmit signal EM can have an active level, the sweep frequency signal SWEEP can gradually decrease from a high level, and the anode initialization gate signal GB can have an inactive level.

[0225] The fourth time period, DRB4, can be the optical emission period. During the optical emission period, DRB4, the fourth transistor TB4 can be turned on by the emission signal EM, and the first transistor TB1 can be turned on by the gate-source voltage set after the second time period, DRB2.

[0226] During the light emission period DRB4, the current IEEB can flow along the path of the first transistor TB1, the fourth transistor TB4 and the light-emitting element EEB, so that the light-emitting element EEB can emit light.

[0227] The fifth period, DRB5, following the fourth period DRB4, can be the optical emission cutoff period. As the sweep signal SWEEP decreases, the sixth transistor TB6 can turn on at a specific time. The specific time at which the sixth transistor TB6 turns on can be determined by the data voltage VDATA applied to the sixth node NB6.

[0228] When the sixth transistor TB6 is turned on, the second power voltage VDD1B can be applied to the control electrode of the first transistor TB1 through the sixth transistor TB6 and the ninth transistor TB9.

[0229] When the second power voltage VDD1B is applied to the control electrode of the first transistor TB1, the first transistor can be turned off, and the light-emitting element EEB can stop emitting light.

[0230] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TB1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0231] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0232] Figure 46 This is a circuit diagram illustrating the pixel circuits CC and PC of the display panel 100 of the display device according to an embodiment of the present invention, the data driver 500 of the display panel driver of the display device, and the constant current application circuit CMC.

[0233] Except for the first circuit CC, which does not include the fifth transistor TB5, the display device according to this embodiment is basically the same as the reference. Figure 35The display device explained is the same as that in the previous embodiment. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiment, and any repeated explanations of the above elements will be omitted.

[0234] Reference Figure 1 and Figure 46 The first circuit CC includes: a first transistor TB1, including a control electrode connected to a first node NB1, a first electrode for receiving a first power voltage VDD2B, and a second electrode connected to a second node NB2; a second transistor TB2, including a control electrode for receiving a sensing control signal SENSE[n], a first electrode connected to a third node NB3, and a second electrode connected to the first node NB1; a third transistor TB3, including a control electrode for receiving a sensing control signal SENSE[n], a first electrode connected to the third node NB3, and a second electrode connected to the second node NB2; a fourth transistor TB4, including a control electrode for receiving a transmission signal EM, a first electrode connected to the second node NB2, and a second electrode connected to the first electrode of a light-emitting element EEB; a first capacitor CB1, including a first electrode for receiving the first power voltage VDD2B and a second electrode connected to the first node NB1; and a light-emitting element EEB, including a first electrode connected to the second electrode of the fourth transistor TB4 and a second electrode for receiving a second power voltage VSSB.

[0235] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TB1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0236] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0237] Figure 47 It is shown Figure 35 Pixel circuits CC and PC and Figure 35 Timing diagram of the input and output signals of the constant current application circuit CMC in the write frame. Figure 48 It is shown Figure 35 Pixel circuits CC and PC and Figure 35 A timing diagram of an example of the input and output signals of a constant current application circuit (CMC) in a holding frame.

[0238] In addition to driving the display panel 100 at a variable frequency, the driving timing and reference of the pixel circuit according to this embodiment... Figure 37 , Figure 39 , Figure 41 , Figure 43 and Figure 45 The driving timing is substantially the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0239] Reference Figure 1 , Figure 35 , Figure 47 and Figure 48 It can drive the display panel 100 at a variable frequency.

[0240] The driving timing of a display device that supports a variable frequency driving method may include a write frame when the data voltage VDATA is written to the pixel and a hold frame when the light-emitting element EEB emits light without writing the data voltage VDATA to the pixel.

[0241] During the write frame, the data voltage VDATA can be applied to the sixth transistor TB6, and the light-emitting element EEB can emit light. During the first time period DRB1 and the third time period DRB3 of the write frame, the scan signal SCAN[n] can have valid pulses.

[0242] During the hold frame, the data voltage VDATA may not be applied to the sixth transistor TB6, and the light-emitting element EEB may emit light. During the first time period DRB1 and the third time period DRB3 of the hold frame, the scan signal SCAN[n] may have an inactive level.

[0243] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TB1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0244] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0245] Furthermore, in this embodiment, the pixel circuit can support a variable frequency driving method, which can reduce the power consumption of the display device.

[0246] Figure 49 It is shown Figure 35 Pixel circuits CC and PC and Figure 35Timing diagrams of the input and output signals of a constant current application circuit (CMC).

[0247] In addition to the display panel 100 being driven by a progressive scan method, the driving timing and reference of the pixel circuit according to this embodiment are as follows: Figure 37 , Figure 39 , Figure 41 , Figure 43 and Figure 45 The driving timing is substantially the same as that of the previous embodiments explained. Therefore, the same reference numerals will be used to refer to components that are the same as or similar to those described in the previous embodiments, and any repeated explanations of the above elements will be omitted.

[0248] Reference Figure 1 , Figure 35 and Figure 49 The display panel 100 can be driven by a progressive light emission driving method.

[0249] According to this embodiment, the pixel circuit can be driven using a pulse width modulation method. The threshold voltage of the driving transistor TB1 in the constant current generation circuit CC can be externally compensated through current writing. Compared to conventional pixel circuits, this pixel circuit can include relatively fewer transistors, enabling high integration. Therefore, this pixel circuit is suitable for ultra-high resolution display devices.

[0250] Furthermore, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0251] Figure 50 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Figure 51 It is shown that Figure 50 A diagram illustrating an example of an electronic device 1000 implemented as a smartphone.

[0252] Reference Figure 50 and Figure 51 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be... Figure 1 The display device. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0253] In an embodiment, such as Figure 51As shown, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, and head-mounted display (HMD) device, etc.

[0254] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be integrated with other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be integrated with expansion buses such as peripheral component interconnect (PCI) bus.

[0255] Processor 1010 can output input image data IMG and input control signal CONT to Figure 1 The drive controller 200.

[0256] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0257] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, and CD-ROM devices, etc. I / O device 1040 may include input devices (such as keyboards, keypads, mice, touchpads, and touchscreens) and output devices (such as printers and speakers). In some embodiments, display device 1060 may be included in I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be connected to other components via a bus or other communication link.

[0258] Figure 52 It is shown that Figure 50 The diagram shows an example of an electronic device 1000 implemented as a smartwatch.

[0259] Reference Figure 50and Figure 52 The electronic device 1000 can be implemented as a smartwatch. A smartwatch can be an example of an electronic device 1000 that requires an ultra-high resolution display panel.

[0260] According to the pixel circuit, display device, and electronic device of the present invention as described above, an ultra-high resolution display device can be realized using a pixel circuit with high integration.

[0261] The foregoing is illustrative of the invention and should not be construed as limiting the invention. Although some embodiments of the invention have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. In the claims, the means plus function clauses are intended to cover the structures described herein that perform the stated functions, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the invention and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the claims and their equivalents, which are incorporated herein by reference.

Claims

1. A pixel circuit, the pixel circuit comprising a first circuit, the first circuit comprising: The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node; The eighth transistor includes a control electrode configured to receive a second write gate signal, a first electrode connected to the fifth node, and a second electrode connected to the fourth node; The ninth transistor includes a control electrode configured to receive the second write gate signal, a first electrode configured to receive data current, and a second electrode connected to the fifth node; The tenth transistor includes a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the seventh node; The eleventh transistor includes a control electrode configured to receive a transmitted signal, a first electrode configured to receive a second electrical voltage, and a second electrode connected to the fifth node; The twelfth transistor includes a control electrode connected to the seventh node, a first electrode configured to receive the second power voltage or the second initialization voltage, and a second electrode connected to the fourth node; The thirteenth transistor includes a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the sixth node; as well as The light-emitting element includes a first electrode connected to the sixth node and a second electrode configured to receive a third electrical voltage.

2. The pixel circuit according to claim 1, wherein, The first circuit further includes: The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the sixth node; and The third capacitor includes a first electrode connected to the seventh node and a second electrode connected to the first electrode of the twelfth transistor.

3. The pixel circuit according to claim 1, further comprising a second circuit, the second circuit comprising: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor includes a control electrode configured to receive a first write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the second node. The third transistor includes a control electrode configured to receive the first write gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; The fourth transistor includes a control electrode configured to receive the transmitted signal, a first electrode configured to receive a first electrical voltage, and a second electrode connected to the second node; The fifth transistor includes a control electrode configured to receive the transmitted signal, a first electrode connected to the third node, and a second electrode connected to the seventh node; as well as The sixth transistor includes a control electrode configured to receive a first initialization gate signal, a first electrode configured to receive the first initialization voltage, and a second electrode connected to the first node.

4. The pixel circuit according to claim 3, wherein, The second circuit also includes: The first capacitor includes a first electrode configured to receive a swept frequency signal and a second electrode connected to the first node.

5. The pixel circuit according to claim 3, wherein, The first transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor are P-type transistors, and The second transistor, the third transistor, the sixth transistor, and the tenth transistor are N-type transistors.

6. The pixel circuit according to claim 3, wherein, The seventh transistor is an N-type transistor, and The first electrode of the twelfth transistor is configured to receive the second initialization voltage.

7. The pixel circuit according to claim 3, wherein, The seventh transistor is a P-type transistor, and The first electrode of the twelfth transistor is configured to receive the second electrical voltage.

8. The pixel circuit according to claim 3, wherein, The second power voltage is greater than the first power voltage.

9. The pixel circuit according to claim 4, wherein, The first initialization gate signal sequentially has active and inactive levels during the first time period. The second initialization gate signal sequentially has an inactive level and an active level during the first time period. The first write gate signal has an inactive level during the first time period. The second write gate signal has an inactive level during the first time period. The transmitted signal has an ineffective level during the first time period. The frequency sweep signal has a high level during the first time period. The first initialization voltage is at a low level during the first time period. The data current has a low level during the first time period, and The anode initialization gate signal has an effective level during the first time period.

10. The pixel circuit according to claim 9, wherein, The first initialization gate signal has an inactive level during the second time period following the first time period. The second initialization gate signal has an inactive level during the second time period. The first write gate signal has a valid pulse during the second time period. The second write gate signal has an inactive level during the second time period. The transmitted signal has an ineffective level during the second time period. The frequency sweep signal has a high level during the second time period. The first initialization voltage is at a low level during the second time period. The data current is at a low level during the second time period, and The anode initialization gate signal has an inactive level during the second time period.

11. The pixel circuit according to claim 10, wherein, The first initialization gate signal has an inactive level in the third time period after the second time period. The second initialization gate signal has a valid pulse during the third time period. The first write gate signal has an inactive level during the third time period. The second write gate signal has a valid pulse during the third time period. The transmitted signal has an ineffective level during the third time period. The frequency sweep signal is high during the third time period. The first initialization voltage has a high pulse during the third time period. The data current is high during the third time period, and The anode initialization gate signal has an effective level during the third time period.

12. The pixel circuit according to claim 11, wherein, The first initialization gate signal has an inactive level during the fourth time period after the third time period and the fifth time period after the fourth time period. The second initialization gate signal has an inactive level during the fourth and fifth time periods. The first write gate signal has an inactive level during the fourth and fifth time periods. Specifically, the second write gate signal has an inactive level during the fourth and fifth time periods. The transmitted signal has an effective level during the fourth and fifth time periods. The frequency sweep signal gradually decreases from a high level during the fourth and fifth time periods. The first initialization voltage is low during the fourth and fifth time periods. The data current is low during the fourth and fifth time periods, and The anode initialization gate signal has an inactive level during the fourth and fifth time periods.

13. The pixel circuit according to claim 3, wherein, The data voltage is applied to the first transistor, and the light-emitting element emits light during the write frame. In this context, the first initialization gate signal sequentially has active and inactive levels during the first time period of the write frame. In this context, the second initialization gate signal sequentially has an inactive level and an active level during the first time period of the write frame. The first write gate signal has a valid pulse during the second time period of the write frame. In this configuration, the data voltage is not applied to the first transistor, and the light-emitting element emits light during the holding frame. Wherein, the first initialization gate signal and the second initialization gate signal have inactive levels during the first time period of the holding frame, and The first write gate signal has an inactive level during the second period of the holding frame.

14. A display device, the display device comprising a first circuit, the first circuit comprising: The first transistor includes a control electrode connected to a first node, a first electrode configured to receive a first electrical voltage, and a second electrode connected to a second node. The second transistor includes a control electrode configured to receive a sensing control signal, a first electrode connected to a third node, and a second electrode connected to the first node. The third transistor includes a control electrode configured to receive the sensing control signal, a first electrode connected to the third node, and a second electrode connected to the second node; The fourth transistor includes a control electrode configured to receive a transmission signal, a first electrode connected to the second node, and a second electrode connected to the first electrode of the light-emitting element; The first capacitor includes a first electrode configured to receive the first electrical voltage and a second electrode connected to the first node; as well as The light-emitting element includes a first electrode connected to the second electrode of the fourth transistor and a second electrode configured to receive a second electrical voltage.

15. The display device according to claim 14, wherein, The first circuit further includes a second capacitor, which includes a first electrode connected to the fourth node and a second electrode connected to the first node. The display device further includes a second circuit, which includes: The fifth transistor includes a control electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to the fourth node; and The third capacitor includes a first electrode configured to receive a sweep frequency signal and a second electrode connected to the fourth node.

16. The display device according to claim 15, wherein, The first transistor and the fourth transistor are P-type transistors, and The second transistor, the third transistor, and the fifth transistor are N-type transistors.

17. The display device according to claim 15, wherein, The scanning signal has valid pulses in the first time period. The sensing control signal has valid pulses during the first time period. The transmitted signal has an ineffective level during the first time period. The frequency sweep signal has a low level during the first time period. The data voltage has a reference level during the first time period. The scanning signal has an inactive level during the second time period following the first time period. The sensing control signal has valid pulses during the second time period. The transmitted signal has an ineffective level during the second time period. The frequency sweep signal has a low level during the second time period. The scanning signal has valid pulses in the third time period following the second time period. The sensing control signal has an inactive level during the third time period. The transmitted signal has an ineffective level during the third time period. The frequency sweep signal is at a low level during the third time period. The data voltage in the third time period has pulse width modulation data. The scanning signal has an inactive level during the fourth time period following the third time period and the fifth time period following the fourth time period. The sensing control signal has an inactive level during the fourth and fifth time periods. The transmitted signal has an effective level during the fourth and fifth time periods, and The frequency sweep signal gradually increases from a low level during the fourth and fifth time periods.

18. The display device according to claim 15, wherein, The first circuit further includes: The sixth transistor includes a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the first electrode of the light-emitting element.

19. The display device according to claim 15, wherein, The scanning signal has an inactive level during the first time period. The sensing control signal has valid pulses during the first time period. The transmitted signal has an ineffective level during the first time period. The frequency sweep signal has a low level during the first time period. The scanning signal has an inactive level during the second time period following the first time period. The sensing control signal has valid pulses during the second time period. The transmitted signal has an ineffective level during the second time period. The frequency sweep signal has a low level during the second time period. The scanning signal has valid pulses in the third time period following the second time period. The sensing control signal has an inactive level during the third time period. The transmitted signal has an ineffective level during the third time period. The frequency sweep signal is at a low level during the third time period. The data voltage sequentially includes a reference level and pulse width modulation data during the third time period. The scanning signal has an inactive level during the fourth time period following the third time period and the fifth time period following the fourth time period. The sensing control signal has an inactive level during the fourth and fifth time periods. The transmitted signal has an effective level during the fourth and fifth time periods, and The frequency sweep signal gradually increases from a low level during the fourth and fifth time periods.

20. The display device according to claim 15, wherein, The data voltage is applied to the first transistor, and the light-emitting element emits light during the write frame. The scanning signal has valid pulses in the first time period and the third time period of the write frame. In this configuration, the data voltage is not applied to the first transistor, and the light-emitting element emits light during the holding frame. The scanning signal has an inactive level during the first time period of the holding frame and the third time period of the holding frame.

21. The display device according to claim 14, further comprising a third circuit, the third circuit comprising: The first current-applying transistor includes a first electrode for receiving data current and a second electrode connected to ground; The second current-applying transistor includes a first electrode connected to the third node and a second electrode connected to the ground; as well as The third current-applying transistor includes a control electrode configured to receive an initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the third node. The control electrode of the first current-applying transistor, the first electrode of the first current-applying transistor, and the control electrode of the second current-applying transistor are connected to each other. Wherein, the first current-applying transistor and the second current-applying transistor are N-type transistors, and The third current-applying transistor is a P-type transistor.

22. The display device according to claim 14, further comprising a third circuit, the third circuit comprising: The first current-applying transistor includes a first electrode for receiving data current and a second electrode connected to ground; The second current-applying transistor includes a first electrode connected to the third node and a second electrode connected to the ground; as well as The third current-applying transistor includes a control electrode configured to receive an initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the third node. Wherein, the control electrode of the first current-applying transistor, the second electrode of the first current-applying transistor, and the control electrode of the second current-applying transistor are connected to each other, and The first current-applying transistor, the second current-applying transistor, and the third current-applying transistor are P-type transistors.

23. The display device according to claim 14, wherein, The first circuit further includes a fifth transistor, the fifth transistor comprising a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the first electrode of the light-emitting element. The display device further includes a second circuit, which includes: The sixth transistor includes a control electrode connected to the fourth node, a first electrode configured to receive a second electrical voltage, and a second electrode connected to the fifth node; The seventh transistor includes a control electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to the sixth node; The eighth transistor includes a control electrode configured to receive a compensation gate signal, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; The ninth transistor includes a control electrode configured to receive the transmitted signal, a first electrode connected to the fifth node, and a second electrode connected to the first node; The second capacitor includes a first electrode configured to receive a swept frequency signal and a second electrode connected to the fourth node; and The third capacitor includes a first electrode connected to the sixth node and a second electrode connected to the fourth node.

24. The display device according to claim 23, wherein, The first transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the ninth transistor are P-type transistors, and The second transistor, the third transistor, the seventh transistor, and the eighth transistor are N-type transistors.

25. The display device according to claim 23, wherein, The scanning signal has valid pulses in the first time period. The sensing control signal has valid pulses during the first time period. The transmitted signal has an ineffective level during the first time period. The frequency sweep signal has a high level during the first time period. The anode initialization gate signal has an effective level during the first time period. The data voltage has a reference level during the first time period. The scanning signal has an inactive level during the second time period following the first time period. The sensing control signal has valid pulses during the second time period. The transmitted signal has an ineffective level during the second time period. The frequency sweep signal has a high level during the second time period. The anode initialization gate signal has an effective level during the second time period. The scanning signal has valid pulses in the third time period following the second time period. The sensing control signal has an inactive level during the third time period. The transmitted signal has an ineffective level during the third time period. The frequency sweep signal is high during the third time period. The anode initialization gate signal has an effective level during the third time period. The data voltage in the third time period has pulse width modulation data. The scanning signal has an inactive level during the fourth time period following the third time period and the fifth time period following the fourth time period. The sensing control signal has an inactive level during the fourth and fifth time periods. The transmitted signal has an effective level during the fourth and fifth time periods. The frequency sweep signal gradually decreases from a high level during the fourth and fifth time periods, and The anode initialization gate signal has an inactive level during the fourth and fifth time periods.

26. The display device according to claim 23, wherein, The data voltage is applied to the sixth transistor, and the light-emitting element emits light during the write frame. The scanning signal has valid pulses in the first time period and the third time period of the write frame. In this configuration, the data voltage is not applied to the sixth transistor, and the light-emitting element emits light during the holding frame. The scanning signal has an inactive level during the first time period of the holding frame and the third time period of the holding frame.

27. The display device according to claim 14, further comprising a second circuit, the second circuit comprising: The sixth transistor includes a control electrode connected to the fourth node, a first electrode configured to receive a second electrical voltage, and a second electrode connected to the fifth node; The seventh transistor includes a control electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to the sixth node; The eighth transistor includes a control electrode configured to receive a compensation gate signal, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; The ninth transistor includes a control electrode configured to receive the transmitted signal, a first electrode connected to the fifth node, and a second electrode connected to the first node; The second capacitor includes a first electrode configured to receive a swept frequency signal and a second electrode connected to the fourth node; as well as The third capacitor includes a first electrode connected to the sixth node and a second electrode connected to the fourth node.

28. A display device, the display device comprising: Display panel, including pixels; A data driver is configured to output a data voltage to the pixel; A gate driver is configured to output a gate signal to the pixel; as well as A transmit driver is configured to output a transmit signal to the pixel. The pixel includes a first circuit, which includes: The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node; The eighth transistor includes a control electrode configured to receive a second write gate signal, a first electrode connected to the fifth node, and a second electrode connected to the fourth node; The ninth transistor includes a control electrode configured to receive the second write gate signal, a first electrode configured to receive data current, and a second electrode connected to the fifth node; The tenth transistor includes a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the seventh node; The eleventh transistor includes a control electrode configured to receive the transmitted signal, a first electrode configured to receive a second electrical voltage, and a second electrode connected to the fifth node; The twelfth transistor includes a control electrode connected to the seventh node, a first electrode configured to receive the second power voltage or the second initialization voltage, and a second electrode connected to the fourth node; The thirteenth transistor includes a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the sixth node; and The light-emitting element includes a first electrode connected to the sixth node and a second electrode configured to receive a third electrical voltage.

29. An electronic device, the electronic device comprising: Display panel, including pixels; A data driver is configured to output a data voltage to the pixel; A gate driver is configured to output a gate signal to the pixel; A transmit driver is configured to output a transmit signal to the pixel; A drive controller is configured to control the data driver, the gate driver, and the transmit driver; as well as The processor is configured to output input image data and input control signals to the drive controller. The pixel includes a first circuit, which includes: The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node; The eighth transistor includes a control electrode configured to receive a second write gate signal, a first electrode connected to the fifth node, and a second electrode connected to the fourth node; The ninth transistor includes a control electrode configured to receive the second write gate signal, a first electrode configured to receive data current, and a second electrode connected to the fifth node; The tenth transistor includes a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the seventh node; The eleventh transistor includes a control electrode configured to receive the transmitted signal, a first electrode configured to receive a second electrical voltage, and a second electrode connected to the fifth node; The twelfth transistor includes a control electrode connected to the seventh node, a first electrode configured to receive the second power voltage or the second initialization voltage, and a second electrode connected to the fourth node; The thirteenth transistor includes a control electrode configured to receive an anode initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the sixth node; and The light-emitting element includes a first electrode connected to the sixth node and a second electrode configured to receive a third electrical voltage.

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