Display method, shift register, scan driving circuit, display panel and electronic device

Abstract

The application provides a display method, a shift register, a scanning driving circuit, a display panel and an electronic device, relates to the technical field of electronic devices, and is used for reducing the power consumption of the electronic device. The method comprises the following steps: in a display process of a display panel, a picture of a first display area is refreshed at a first refresh rate, and a picture of a second display area is refreshed at a second refresh rate; the first refresh rate is less than the second refresh rate.

Description

[0001] This application is a divisional application. The original application has the application number 202410307066.9 and the original application date is March 15, 2024. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic device technology, and in particular to a display method, a shift register, a scan driving circuit, a display panel, and an electronic device. Background Technology

[0003] Mobile phones, tablets, and other electronic devices are ubiquitous in people's daily work and life. Among them, the display panel is one of the main power-consuming components of electronic devices, and how to reduce the power consumption of the display panel is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a display method, a shift register, a scan driving circuit, a display panel, and an electronic device to solve the problem of high power consumption in display panels.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] Firstly, a display method is provided. This method is applied to an electronic device having a display panel, the display panel including a first display area and a second display area, the first display area and the second display area not overlapping. The method includes: during the display process of the display panel, refreshing the image of the first display area at a first refresh rate, and refreshing the image of the second display area at a second refresh rate; the first refresh rate is less than the second refresh rate.

[0007] In this application, by reducing the refresh rate of the areas where the image remains unchanged on the display panel while maintaining the refresh rate of the areas where the image changes, the display effect of the changing areas can be guaranteed, while the refresh power consumption of the areas where the image remains unchanged can be reduced. This reduces the power consumption of the display panel, and consequently, the power consumption of the electronic device, while ensuring the display effect.

[0008] In one possible implementation of the first aspect, the display panel includes a plurality of scan signal lines, each extending along a first direction, and the plurality of scan signal lines are arranged side by side along a second direction. The first direction and the second direction intersect. In the second direction, a first display area is located on at least one side of a second display area.

[0009] In another possible implementation of the first aspect, the plurality of scan signal lines include a first scan signal line and a second scan signal line, wherein the first scan signal line is at least partially located in a first display area, and the second scan signal line is at least partially located in a second display area. Refreshing the image in the first display area at a first refresh rate and refreshing the image in the second display area at a second refresh rate includes: within one frame refresh cycle of the display panel, the second scan signal line controls a plurality of connected sub-pixels to emit light based on data signals received in the current cycle, and the first scan signal line controls a plurality of connected sub-pixels to emit light based on data signals received in previous cycles.

[0010] In this application, within one frame refresh cycle of the display panel, sub-pixels in areas with reduced refresh rates are controlled to emit light according to the previous data signal, mirroring the light emitted in the previous frame cycle. Conversely, sub-pixels in areas maintaining the refresh rate are controlled to emit light according to the data signal received in the current frame. This ensures reliable light emission from each sub-pixel in the display panel, preventing display panel anomalies and improving the reliability of the display panel and electronic devices.

[0011] In another possible implementation of the first aspect, the first refresh rate is less than or equal to 10Hz. The smaller the first refresh rate, the greater the reduction in power consumption of the display panel, thereby enabling a greater reduction in the power consumption of both the display panel and the electronic devices.

[0012] Secondly, this application provides a shift register. The shift register includes a first output circuit and a second output circuit. The first output circuit is coupled to an input signal terminal, a first clock signal terminal, a second clock signal terminal, a first voltage terminal, and a second voltage terminal. The first output circuit is configured to output a first output signal under the joint control of the input signal output from the input signal terminal, the first clock signal output from the first clock signal terminal, and the second clock signal output from the second clock signal terminal. The second output circuit is coupled to the first output circuit, a third voltage terminal, a fourth voltage terminal, and a control signal terminal. The second output circuit is configured to output a second output signal under the control of at least the signal provided by the first output circuit and the control signal output from the control signal terminal. The change state of the second output signal is the same as the change state of the first output signal, or the second output signal is an invalid signal.

[0013] In this application, the second output circuit of the shift register is controlled by a control signal terminal to output a second output signal that is the same as the first output signal or an invalid signal. When the second output signal is the same as the first output signal, the shift register can control the connected sub-pixels to refresh normally, maintaining the refresh frequency of the sub-pixels; when the second output signal is an invalid signal, the shift register can control the connected sub-pixels to stop refreshing, reducing the refresh frequency of the sub-pixels.

[0014] In this way, the shift register can flexibly control the refresh rate of connected sub-pixels according to actual needs; and while reducing the refresh rate of sub-pixels, it avoids changes in the level of the first node in the pixel circuit inside the sub-pixel, ensuring that the sub-pixel can emit the same light as the previous frame, thus improving the reliability of the display panel and electronic devices.

[0015] In another possible implementation of the second aspect, the second output circuit includes a logic sub-circuit and an output sub-circuit. The logic sub-circuit is coupled at least to a control signal terminal and a first node of the first output circuit. The logic sub-circuit is configured to output a logic signal under the control of a control signal output from the control signal terminal and a level signal provided by the first node. The output sub-circuit is coupled to a third voltage terminal, the fourth voltage terminal, the logic sub-circuit, and a second node of the first output circuit. The output sub-circuit is configured to output a second output signal under the control of a logic signal output from the logic sub-circuit and a level signal provided by the second node.

[0016] In another possible implementation of the second aspect, the logic sub-circuit is coupled to the control signal terminal, the output terminal of the first output circuit, the first voltage terminal, and the first node, respectively; the logic sub-circuit is configured to output a logic signal under the control of the first output signal output by the first output circuit, the control signal provided by the control signal terminal, and the level signal provided by the first node.

[0017] In another possible implementation of the second aspect, the logic sub-circuit includes a first logic transistor, a second logic transistor, and a third logic transistor. The first terminal of the first logic transistor is coupled to a first voltage terminal, and its control terminal is coupled to the output terminal of the first output circuit. The first terminal of the second logic transistor is coupled to a second voltage terminal, its control terminal is coupled to a first node of the first output circuit, and its second terminal is coupled to a fourth node. The first terminal of the third logic transistor is coupled to the second terminal of the first logic transistor, its control terminal is coupled to a control signal terminal, and its second terminal is coupled to the fourth node.

[0018] In another possible implementation of the second aspect, the logic sub-circuit is coupled to the control signal terminal, the first node and the third node of the first output circuit, and the second voltage terminal, respectively; the logic sub-circuit is configured to output a logic signal under the control of the control signal provided by the control signal terminal, the level signal provided by the first node, and the level signal provided by the third node.

[0019] In another possible implementation of the second aspect, the logic sub-circuit includes a fourth logic transistor and a fifth logic transistor. The first terminal of the fourth logic transistor is coupled to the third node of the first output circuit, the control terminal of the fourth logic transistor is coupled to a control signal terminal, and the second terminal of the fourth logic transistor is coupled to the fourth node. The first terminal of the fifth logic transistor is coupled to a second voltage terminal, the control terminal of the fifth logic transistor is coupled to the first node of the first output circuit, and the second terminal of the fifth logic transistor is coupled to the fourth node.

[0020] In another possible implementation of the second aspect, the output sub-circuit includes a first output transistor and a second output transistor. The first terminal of the first output transistor is coupled to a fourth voltage terminal, the control terminal of the first output transistor is coupled to a fourth node, and the second terminal of the first output transistor is coupled to the output terminal of the second output circuit. The first terminal of the second output transistor is coupled to a third voltage terminal, the control terminal of the second output transistor is coupled to a second node of the first output circuit, and the second terminal of the second output transistor is coupled to the output terminal of the second output circuit.

[0021] Thirdly, this application provides a scan driving circuit. The scan driving circuit includes a plurality of cascaded shift registers. The shift registers are any of the shift registers described in the second aspect above.

[0022] Fourthly, this application provides a display panel. The display panel includes a plurality of sub-pixels and a scan driving circuit. The plurality of sub-pixels are arranged in a multi-row, multi-column array. The scan driving circuit is coupled to the plurality of sub-pixels through a plurality of scan signal lines, each scan signal line being coupled to a plurality of sub-pixels located in the same row. The scan driving circuit includes the scan driving circuit described in the third aspect above.

[0023] Fifthly, this application provides an electronic device. The electronic device includes a display panel and a battery. The display panel includes the display panel described in the fourth aspect above. The battery is coupled to the display panel. The battery is used to supply power to the display panel.

[0024] It is understood that the beneficial effects achieved by the scanning drive circuit described in the third aspect, the display panel described in the fourth aspect, and the electronic device described in the fifth aspect can be referred to the beneficial effects in the second aspect and any of its possible design embodiments, and will not be repeated here.

[0025] A sixth aspect provides an electronic device. The electronic device includes a display panel, a memory, a processor, and a computer program stored in the memory, the processor executing the computer program to implement the steps of the method described in any of the first aspects above.

[0026] In a seventh aspect, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program / instructions that, when executed by a processor, implement the method described in any one of the first aspects.

[0027] Eighthly, a computer program product comprising instructions is provided. The computer program product includes a computer program / instructions that, when executed by a processor, implement the method described in any one of the first aspects above.

[0028] Ninthly, embodiments of this application provide a chip including a processor, the processor being configured to invoke a computer program in memory to perform a method as described in any of the first aspects.

[0029] It is understood that the beneficial effects achieved by the electronic device described in the sixth aspect, the computer-readable storage medium described in the seventh aspect, the computer program product described in the eighth aspect, and the chip described in the ninth aspect can be referred to the beneficial effects in the first aspect and any of its possible design embodiments, and will not be repeated here. Attached Figure Description

[0030] Figure 1 A schematic diagram of two screens displayed by a video playback application in a child device;

[0031] Figure 2 This is a schematic diagram of the structure of a display panel provided in some embodiments of this application;

[0032] Figure 3 for Figure 2 Circuit diagram of a sub-pixel within region AA;

[0033] Figure 4 for Figure 3 The diagram shown is a timing diagram of multiple signals for a sub-pixel under normal refresh conditions within a single frame refresh cycle.

[0034] Figure 5 for Figure 2 A schematic diagram of the structure of the second scanning drive circuit;

[0035] Figure 6 This is a schematic diagram of the structure of a shift register provided in some embodiments of this application;

[0036] Figure 7 for Figure 6 A schematic diagram of the structure of a first output circuit;

[0037] Figure 8 for Figure 6 The diagram shows a possible structure of a shift register.

[0038] Figure 9 for Figure 8 The diagram shows a possible structure of a shift register.

[0039] Figure 10 A timing diagram of a shift register;

[0040] Figure 11 for Figure 6 The diagram shows another possible structure of the shift register.

[0041] Figure 12 for Figure 11 The diagram shows a possible structure of a shift register.

[0042] Figure 13 This is another timing diagram of the shift register.

[0043] Figure 14 This is another timing diagram of a shift register.

[0044] Figure 15 This is a schematic diagram illustrating the working timing of the signals output by multiple shift registers in the display panel within one frame refresh cycle.

[0045] Figure 16 This is a schematic diagram of signal transmission between multiple shift registers and multiple rows of sub-pixels in the AA area within one frame refresh cycle;

[0046] Figure 17 A timing diagram illustrating the operation of the control signal terminal in three scenarios;

[0047] Figure 18 This is a schematic diagram of a possible structure of an electronic device involved in some embodiments of this application;

[0048] Figure 19 This is a schematic diagram of a possible structure of the controller involved in some embodiments of this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0050] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0051] Furthermore, in this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and may change accordingly depending on the orientation of the components in the accompanying drawings.

[0052] In describing some embodiments, the terms "connected," "linked," and their derivative expressions may be used. For example, the term "connected" may be used to indicate that two or more components are in direct or indirect physical contact with each other. For example, "A and B are connected" can mean that A and B are connected directly, or it can mean that A and B are connected through other components. Furthermore, the term "coupled" can refer to an electrical connection that enables signal transmission; coupling can indicate direct coupling or indirect coupling.

[0053] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0054] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0056] The transistors mentioned in the text can be thin film transistors (TFTs), triodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), etc., and are not limited here.

[0057] Furthermore, the terms "high-level signal" and "low-level signal" mentioned in the text are only relative concepts. A high-level signal can be a signal greater than 0V or a signal less than 0V; similarly, a low-level signal can be a signal greater than 0V or a signal less than 0V.

[0058] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0059] Figure 1 This diagram illustrates two images displayed by a video playback application on an electronic device.

[0060] Currently, display panels refresh at the same frequency across the entire display panel when displaying images. For example, when the display panel displays... Figure 1 (a) screen to display Figure 1 In the middle (b) screen, although only the video playback area 01 has a change in the picture, the information display area 02, where the picture does not change, is also refreshed at the same frequency as the video playback area 01 because the entire display panel refreshes at the same frequency.

[0061] Therefore, as Figure 1 The high refresh rate (e.g., 60Hz or 120Hz) applied to areas where the image remains unchanged will cause unnecessary power consumption waste on the display panel.

[0062] Based on this, embodiments of this application provide a shift register, a scan driving circuit, a display panel, an electronic device, and a display method applied to the electronic device, by reducing, for example... Figure 1 The refresh rate shown is for areas of the image where there is no change. This is used to reduce the power consumption of the display panel.

[0063] The structure of the display panel is described below.

[0064] Figure 2 This is a schematic diagram of the structure of a display panel according to some embodiments. For example, such as... Figure 2As shown, the display panel includes a display area (i.e., a pixel array area) AA and a peripheral area SA located on at least one side (e.g., the left, right, or all four sides) of the display area AA. The display area AA may include: multiple rows and columns of sub-pixels arranged in an array, and multiple scan signal lines connected to the multiple rows of sub-pixels respectively. For example, the multiple scan signal lines include multiple enable signal lines L-EM connected to the multiple rows of sub-pixels respectively, multiple first reset signal lines L-ResetN connected to the multiple rows of sub-pixels respectively, multiple second reset signal lines L-ResetP connected to the multiple rows of sub-pixels respectively, multiple first gate lines L-GateP connected to the multiple rows of sub-pixels respectively, and multiple second gate lines L-GateN connected to the multiple rows of sub-pixels respectively.

[0065] The display area AA may also include multiple data signal lines L-Data that are connected to multiple columns of sub-pixels respectively.

[0066] Each sub-pixel may include pixel circuits and light-emitting elements with circuit structures such as 7T1C, 7T2C, 8T1C, 8T2C or 4T1C, which are available in the art.

[0067] It should be noted that the direction indicated by the above rows is the same as... Figure 2 The first direction X is the same as the first direction X. The directions represented by the above columns are the same as the first direction X. Figure 2 The second direction Y is the same. Any one of the following lines extends along the first direction X: enable signal line L-EM, first reset signal line L-ResetN, second reset signal line L-ResetP, first gate line L-GateP, and second gate line L-GateN, and multiple lines are arranged side by side along the second direction Y.

[0068] in addition, Figure 2 The example described uses the first direction X and the second direction Y as being perpendicular to each other. In other examples, the first direction X and the second direction Y may also be an angle forming 80°, 75° or other angles, which is not limited here.

[0069] like Figure 2 As shown, the surrounding area SA may include a first scan driving circuit 21, a second scan driving circuit 22, a third scan driving circuit 23, a fourth scan driving circuit 24, and a fifth scan driving circuit 25.

[0070] In some examples, the first scan driving circuit 21 can be connected to multiple enable signal lines L-EM to provide enable signals to multiple rows of sub-pixels respectively. Since the first scan driving circuit 21 is used to drive the enable sub-circuit of the sub-pixels, the first scan driving circuit 21 can also be called the emission gate driver onarray (EM GOA) circuit.

[0071] In some examples, the second scan driving circuit 22 may be located on the side of the first scan driving circuit 21 near the display area AA and connected to multiple reset signal lines L-ResetN to provide first reset signals to multiple rows of sub-pixels respectively. The second scan driving circuit 22 is used to drive the N-type thin film transistors (TFTs) in the sub-pixels; therefore, the second scan driving circuit 22 can also be called the N-type reset scan driving circuit Reset-N GOA.

[0072] In some examples, the third scan driving circuit 23 may be located on the side of the second scan driving circuit 22 near the display area AA and connected to multiple first gate lines L-GateP to provide first gate signals to multiple rows of sub-pixels respectively. For example, the third scan driving circuit 23 provides first gate signals to the P-type transistors in the sub-pixels, so the third scan driving circuit 23 may also be called the P-type gate scan driving circuit Gate-P GOA.

[0073] In some examples, the peripheral area SA may also include a fourth scan driving circuit 24. The fourth scan driving circuit 24 is located on the side of the display area AA away from the first scan driving circuit 21. The fourth scan driving circuit 24 may be connected to multiple second reset signal lines L-ResetP to provide second reset signals to multiple rows of sub-pixels respectively. The fourth scan driving circuit 24 is used to drive the P-type thin-film transistors in the sub-pixels; therefore, the fourth scan driving circuit 24 may also be referred to as a P-type reset scan driving circuit Reset-P GOA.

[0074] In some examples, the peripheral area SA may also include a fifth scan driving circuit 25. The fifth scan driving circuit 25 is located on the side of the fourth scan driving circuit 24 near the display area AA and is connected to multiple second gate lines L-GateN to provide second gate signals to multiple rows of sub-pixels respectively. For example, the fifth scan driving circuit 25 provides second gate signals to N-type transistors in the sub-pixels; therefore, the fifth scan driving circuit 25 may also be referred to as an N-type gate scan driving circuit Gate-N GOA.

[0075] like Figure 2 As shown, in some examples, the third scan driving circuit 23 may also be located partly between the first scan driving circuit 21 and the display area AA, and partly between the fourth scan driving circuit 24 and the display area AA.

[0076] like Figure 2As shown, the non-display area SA may also include a source integrated circuit (Source IC) 26. The source driving circuit 26 is coupled to a data line L-Data passing through the AA area in a second direction, providing data signals to multiple sub-pixels in the AA area via the data line L-Data. One data line L-Data provides data signals to a column of sub-pixels arranged in an array, and multiple data lines L-Data provide data signals to different columns of sub-pixels. For example, the pixel circuit in the sub-pixel operates under the control of the data signals transmitted via the data lines and the gate signals and enable signals transmitted via the scan signal lines to drive the light-emitting element to emit light, thereby achieving operations such as display. The light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and the embodiments of this disclosure are not limited thereto.

[0077] like Figure 2 As shown, the non-display area SA may also include a control line L-Ctrl. The control line L-Ctrl may pass through the non-display area SA in a second direction. For example, the control line L-Ctrl may be coupled to an N-type reset scan drive circuit Reset-N GOA, and the control line L-Ctrl may also be coupled to an N-type gate scan drive circuit.

[0078] Figure 3 for Figure 2 The circuit structure diagram of a sub-pixel within region AA. (Example) Figure 3 As shown, sub-pixel P includes a light-emitting element E and a pixel circuit M that drives the light-emitting element E to emit light. The pixel circuit M includes a driving sub-circuit 71, a data writing sub-circuit 72, a compensation sub-circuit 73, a reset sub-circuit 74, an enable sub-circuit 75, and a storage capacitor Cst.

[0079] The reset sub-circuit 74 includes a first reset sub-circuit 741, which includes a first reset transistor BT1. The compensation sub-circuit 73 includes a compensation transistor BT2. The drive sub-circuit 71 includes a drive transistor BT3. The data writing sub-circuit 72 includes a data writing transistor BT4. The enable sub-circuit 75 includes a first enable sub-circuit 751 and a second enable sub-circuit 752, wherein the first enable sub-circuit 751 includes a first enable transistor BT5, and the second enable sub-circuit 752 includes a second enable transistor BT6. The reset sub-circuit 74 also includes a second reset sub-circuit 742, which includes a second reset transistor BT7. The reset sub-circuit 74 may also include a third reset sub-circuit 743, which includes a third reset transistor BT8. For example, the first reset transistor BT1 and the compensation transistor BT2 are N-type transistors, and the data writing transistor BT4 and the second reset transistor BT7 are P-type transistors. The connection relationship and working principle of the pixel units in this embodiment are merely examples; the pixel units can also adopt other structures as needed, and this disclosure does not limit this.

[0080] like Figure 3 As shown, in some embodiments, the pixel circuit M is described in its entirety:

[0081] The control electrode of the first reset transistor BT1 is coupled to the reset signal line L-ResetN, and the first electrode of the first reset transistor BT1 is coupled to the first initial signal line L-Vinit1. The first reset transistor BT1 is configured to transmit the first initial signal provided by the first initial signal line L-Vinit1 to the first node N1 under the control of the first reset signal provided by the reset signal line L-ResetN.

[0082] The control electrode of the compensation transistor BT2 is coupled to the second gate line L-GateN, the first electrode of the compensation transistor BT2 is coupled to the third node N3, and the second electrode of the compensation transistor BT2 is coupled to the first node N1. The compensation transistor BT2 is configured to form a path between the first node N1 and the third node N3 under the control of the second gate signal provided by the second gate line L-GateN.

[0083] The control electrode of the driving transistor BT3 is coupled to the first node N1, the first electrode of the driving transistor BT3 is coupled to the second node N2, and the second electrode of the driving transistor BT3 is coupled to the third node N3. The driving transistor BT3 is configured to form a path between the second node N2 and the third node N3 under the control of the potential of the first node N1.

[0084] The control electrode of the data write transistor BT4 is coupled to the first gate line L-GateP, the first electrode of the data write transistor BT4 is coupled to the data line L-Data, and the second electrode of the data write transistor BT4 is coupled to the second node N2. The data write transistor BT4 is configured to transmit the data signal provided by the data line L-Data to the second node N2 under the control of the first gate signal provided by the first gate line L-GateP.

[0085] The control electrode of the first enabling transistor BT5 is coupled to the enable signal line L-EM, the first electrode of the first enabling transistor BT5 is coupled to the first power supply line L-VDD, and the second electrode of the first enabling transistor BT5 is coupled to the second node N2. The first enabling transistor BT5 is configured to transmit the first power supply signal provided by the first power supply line L-VDD to the second node N2 under the control of the enable signal provided by the enable signal line L-EM.

[0086] The control electrode of the second enabling transistor BT6 is coupled to the enable signal line L-EM, the first electrode of the second enabling transistor BT6 is coupled to the third node N3, and the second electrode of the second enabling transistor BT6 is coupled to the fourth node N4. The second enabling transistor BT6 is configured to form a path between the third node N3 and the fourth node N4 under the control of the enable signal provided by the enable signal line L-EM.

[0087] The control electrode of the second reset transistor BT7 is coupled to the second reset signal line L-ResetP, the first electrode of the second reset transistor BT7 is coupled to the second initial signal line L-Vinit2, and the second electrode of the second reset transistor BT7 is coupled to the fourth node N4. The second reset transistor BT7 is configured to transmit the second initial signal provided by the second initial signal line L-Vinit2 to the fourth node N4 under the control of the second reset signal provided by the second reset signal line L-ResetP.

[0088] The control electrode of the third reset transistor BT8 is coupled to the second reset signal line L-ResetP, the first electrode of the third reset transistor BT8 is coupled to the third initial signal line L-Vinit3, and the second electrode of the third reset transistor BT8 is coupled to the second node N2. The third reset transistor BT8 is configured to transmit the third initial signal provided by the third initial signal line L-Vinit3 to the fourth node N2 under the control of the second reset signal provided by the second reset signal line L-ResetP.

[0089] In some embodiments, any scan driving circuit includes a plurality of cascaded shift registers, each shift register being used to drive one or more rows of subpixels. This disclosure describes embodiments using each shift register to drive one row of subpixels as an example, but this is not intended to limit the scope of the embodiments.

[0090] For example, the surrounding area may also include a first voltage signal line ( Figure 2 (not shown) and second voltage signal line ( Figure 2 (Not shown), a first voltage signal line is configured to provide a first voltage signal, and a second voltage signal line is configured to provide a second voltage signal. The level value of the first voltage signal is less than the level value of the second voltage signal. A first scan drive circuit 21 is coupled to the first voltage signal line to output the first voltage signal as a first part of an enable signal. For example, the first voltage signal line is connected to multiple first shift registers in the first scan drive circuit 21. The first part of the enable signal is, for example, a low-potential portion of the enable signal. For example, this low-potential portion of the enable signal can cause the first enable transistor BT5 and the second enable transistor BT6 to be in a conducting state during the light-emitting phase. The first scan drive circuit 21 is also coupled to the second voltage signal line to output the second voltage as a second part of the enable signal. For example, the second voltage signal line is coupled to multiple first shift registers in the first scan drive circuit 21. The second part of the enable signal is, for example, a high-potential portion of the enable signal. For example, this high-potential portion of the enable signal can cause the first enable transistor BT5 and the second enable transistor BT6 to be in a cut-off state during the light-emitting phase.

[0091] Figure 4 It shows Figure 3 The diagram shown illustrates the timing of multiple signals for a sub-pixel during normal refresh within a single frame refresh cycle. The following section combines... Figure 4 The timing sequences of the multiple signals shown are for Figure 3 The operation of the sub-pixel within one frame refresh cycle is illustrated below. It can be seen that the pixel circuit M has five stages within one frame refresh cycle.

[0092] In the first stage P1: the enable signal EM is high, and both the first enable transistor BT5 and the second enable transistor BT6 are off. The first reset signal Reset-N is low, and the first reset transistor BT1 is also off. The second reset signal Reset-P is low, and the second reset transistor BT7 is on. The second initialization signal Vinit2 initializes the fourth node N4, and the third reset transistor BT8 is on. The third initialization signal Vinit3 initializes the second node N2. The first gate signal Gate-P is high, and the data write transistor BT4 is off. The second gate signal Gate-N is high, and the compensation transistor BT2 is on. The first node N1 and the third node N3 are on.

[0093] At this time, the first node N1 is at a low level, and the control driving transistor BT3 is in the on state. The second node N2 is connected to the third node N3 through the driving transistor BT3. Since the first node N1 is connected to the third node N3, the third initialization signal Vinit3 will flow through the second node N2 and the third node N3 in sequence and then into the first node N1.

[0094] In the first stage P1, the third initialization signal Vinit3 gradually increases the level of the first node N1. Simultaneously, the conduction level of the driving transistor BT3 gradually decreases. This continues until the level of the first node N1 equals the level of the third initialization signal Vinit3, at which point the driving transistor BT3 is in the off state.

[0095] In the second stage P2: the enable signal EM is high, and the first enable transistor BT5 and the second enable transistor BT6 remain off. The first reset signal Reset-N is high, the first reset transistor BT1 is on, and the first initialization signal Vinit1 enters the first node N1, pulling down the level of the first node N1 to be equal to the level of the first initialization signal Vinit1. The second reset signal Reset-P is high, and the second reset transistor BT7 and the third reset transistor BT8 are both off. The first gate signal Gate-P is high, and the data write transistor BT4 is off. The second gate signal Gate-N is low, and the compensation transistor BT2 is off.

[0096] During the process of pulling down the level of the first node N1, the first node N1 can control the driving transistor BT3 to be in the conducting state, and the second node N2 and the third node N3 are turned on.

[0097] In the third stage P3: the enable signal EM is high, and the first enable transistor BT5 and the second enable transistor BT6 remain off. The first reset signal Reset-N is low, and the first reset transistor BT1 is also off. The second reset signal Reset-P is high, and the second reset transistor BT7 and the third reset transistor BT8 are both off. The first gate signal Gate-P is low, the data write transistor BT4 is on, and the data signal Data is written to the second node N2. The second gate signal Gate-N is high, the compensation transistor BT2 is on, and the third node N3 is connected to the first node N1.

[0098] In the second stage (P2), the first node N1 controls the driving transistor BT3 to be turned on, and the second node N2 and the third node N3 are also turned on. Therefore, after the data signal Data is written to the second node N2 in the third stage (P3), it can flow through the third node N3 and enter the first node N1 for storage. Therefore, the third stage (P3) can also be called the data writing stage.

[0099] In stage P4: the enable signal EM is high, and the first enable transistor BT5 and the second enable transistor BT6 remain off. The first reset signal Reset-N is low, and the first reset transistor BT1 is also off. The second reset signal Reset-P is low, and the second reset transistor BT7 is on. The second initialization signal Vinit2 initializes the fourth node N4, and the third reset transistor BT8 is on. The third initialization signal Vinit3 initializes the second node N2. The first gate signal Gate-P is high, and the data write transistor BT4 is off. The second gate signal Gate-N is low, and the compensation transistor BT2 is off.

[0100] In stage P5: the enable signal EM is low, and both the first enable transistor BT5 and the second enable transistor BT6 are in the ON state. The first reset signal Reset-N is low, and the first reset transistor BT1 is in the OFF state. The second reset signal Reset-P is high, and both the second reset transistor BT7 and the third reset transistor BT8 are in the OFF state. The first gate signal Gate-P is high, and the data write transistor BT4 is in the OFF state. The second gate signal Gate-N is low, and the compensation transistor BT2 is in the OFF state.

[0101] In the fifth stage P5, the first enabling transistor BT5, the second enabling transistor BT6, and the driving transistor BT3 are all in the on state, thus connecting the second voltage source VDD with the light-emitting device E, thereby injecting current into the light-emitting device E and driving it to emit light. Therefore, the fifth stage P5 can also be called the light-emitting stage.

[0102] In the fifth stage P5, the conduction degree of the driving transistor BT3 is related to the data signal previously written to the first node N1, so the data signal can control the magnitude of the current injected into the light-emitting device E.

[0103] It should be noted that, Figure 3The pixel circuit M shown is only one example; in some other examples, the pixel circuit M may not have the third reset transistor BT8. In the case where the pixel circuit M does not have the third reset transistor BT8, the pixel circuit M may also skip the aforementioned fourth stage P4.

[0104] Figure 3 The pixel circuit M shown utilizes stage P4 primarily for initializing the voltage levels of the second node N2 and the fourth node N4. In different pixel circuits, due to differences in the previous frame image display, the voltage levels of the second node N2 and the fourth node N4 can affect the performance of the driving transistor BT3, resulting in poor uniformity of the performance of the driving transistor BT3 across different pixel circuits. Initializing the voltage levels of the second node N2 and the fourth node N4 through stage P4 improves the uniformity of the performance of the driving transistor BT3 across different pixel circuits, thereby enhancing the uniformity of the display panel's display effect.

[0105] Understandably, in the fourth stage, P4 does not initialize the levels of the second node N2 and the fourth node N4. Similarly, in the fifth stage, the first enable transistor BT5, the second enable transistor BT6, and the driving transistor BT3 can all be in the on state, and current is injected into the light-emitting device E to drive the light-emitting device E to emit light.

[0106] Currently, some solutions aim to reduce power consumption by refreshing only a portion of the sub-pixels on the display panel within a single frame refresh cycle, while leaving others unrefreshed. A common approach is for the Source IC to control the data line L-Data to stop providing data signals to the sub-pixels that do not need refreshing, and only provide the data signal for the current frame refresh cycle to the sub-pixels that do need refreshing. This reduces the output signal of the Source IC, thereby lowering the power consumption of the display panel and electronic devices.

[0107] However, in combination with the above... Figure 2 and Figure 3 The explanation of the operation of the pixel circuit within a frame refresh cycle reveals that during the writing phase P3, if the pixel circuit M does not receive a new data signal, the voltage level of the first node N1 in pixel circuit M will change because it is connected to the data line L-Data (which does not provide data signals) via the third node N3 and the second node N2. Consequently, sub-pixels without data signals cannot emit the same light as in the previous frame, resulting in abnormal display images on the display panel.

[0108] The shift register and scan drive circuit provided in the embodiments of this application can keep the level of the first node N1 in the sub-pixel unchanged when the source IC controls the data line L-Data to stop providing data signals to the sub-pixels that do not need to be refreshed. This allows the sub-pixels of the data signal to emit the same light in the current frame as in the previous frame, reducing the power consumption of the source IC while ensuring that the display screen does not show any abnormalities.

[0109] The structure of the second scan drive circuit 22, which provides the first reset signal to the first reset transistor BT1 in the pixel circuit M, and the fifth scan drive circuit 25, which provides the second gate signal to the compensation transistor BT2 in the pixel circuit M, will be described in detail below.

[0110] Please see Figure 5 , Figure 5 A schematic diagram of the structure of a second scan drive circuit provided in some embodiments of this application is shown.

[0111] The second scan drive circuit 22 includes n cascaded shift registers (RS1, RS2...RS(n)); in this case, the display panel includes N cascaded shift registers (RS1, RS2...RS(n)) that are respectively coupled to n first reset signal lines (L-ResetN).

[0112] In addition, such as Figure 5 As shown, in some embodiments of this disclosure, the shift registers (RS1, RS2...RS(n)) of the second scan driving circuit 22 are further provided with an input signal terminal Vin, a first clock signal terminal CK, a second clock signal terminal CB, a first voltage terminal VGL, a second voltage terminal VGH, a control signal terminal Ctrl, a first output terminal OUT, and a second output terminal OUT-N. Furthermore, the circuit structures of each shift register in the second scan driving circuit 22 can be the same.

[0113] Based on this, in the second scan driving circuit 22 described above, the signal input terminal Vin of the previous stage or multiple stages of shift registers is coupled to the frame start signal terminal STV. Except for the shift register coupled to the frame start signal terminal STV, the signal input terminal Vin of the subsequent stage shift register is coupled to the signal input terminal OUT of the previous stage shift register. Here, the previous stage shift register and the subsequent stage shift register can be shift registers located in adjacent stages, or they can be shift registers not located in adjacent stages.

[0114] For example, such as Figure 5As shown, in the second scan driving circuit 22 described above, the signal input terminal Vin of the first-stage shift register RS1 is coupled to the frame start signal terminal STV, the signal input terminal Vin of the second-stage shift register RS2 is coupled to the signal output terminal OUT of the first-stage shift register RS1, and the signal output terminal Oput of the i-th stage shift register RSi is coupled to the signal input terminal Vin of the (i+1)-th stage shift register RS(i+1), where 2≤i≤N-1 positive integers.

[0115] For example, such as Figure 5 As shown, the first clock signal terminal CK of the shift register is coupled to the first system clock signal line L-CK extending along the second direction Y; the second clock signal terminal CB of the shift register is coupled to the second system clock signal line L-CB extending along the second direction Y; the first voltage terminal VGL of the shift register is coupled to the first voltage line L-VGL extending along the second direction Y; the second voltage terminal VGH of the shift register is coupled to the second voltage line L-VGH extending along the second direction Y; and the control signal terminal Ctrl of the shift register is coupled to the control signal line L-Ctrl extending along the second direction Y.

[0116] The structure of the fifth scan drive circuit 25 is basically the same as that of the second scan drive circuit 22, and will not be described in detail here.

[0117] The shift register provided in this application embodiment can be used with... Figure 3 The pixel circuit is coupled to control the transistors in the pixel circuit to be in the on or off state.

[0118] The following is about Figure 6 The structure of the shift register shown is explained in detail.

[0119] Figure 6 The diagram shows a schematic representation of the shift register provided in some embodiments of this application; Figure 7 It shows Figure 6 A schematic diagram of the structure of a first output circuit 31; Figure 8 It shows Figure 6 The diagram shows a schematic of one type of shift register.

[0120] Please see Figure 6 The shift register 30 may include a first output circuit 31 and a second output circuit 32. The second output circuit 32 is coupled to the first output circuit 31.

[0121] The first output circuit 31 can be an 8T2C, 9T2C, 11T3C, 14T3C, 16T3C, or 17T3C circuit structure, etc., and the embodiments of this application are not limited to this. For ease of understanding, the first output circuit 31 will be described using the 17T3C circuit structure as an example. However, it should be understood that other circuit structures are also applicable to the first output circuit 31.

[0122] Please see Figure 7 , Figure 7 It shows Figure 6 The diagram shows the structure of the first output circuit 31. The first output circuit 31 may include 17 transistors (T1, T2...T17) and 3 capacitors (C1, C2 and C3). The 17 transistors are described using P-type transistors as an example.

[0123] The first terminal of the first transistor T1 is coupled to the input signal terminal Vin, the control terminal of the first transistor T1 is coupled to the first clock signal terminal CK, and the second terminal of the first transistor T1 is coupled to the first node S1. The input signal terminal Vin is used to receive the first output signal from the first output circuit 31 in the previous stage shift register as an input signal, or to receive the frame start signal STV.

[0124] The first terminal of the second transistor T2 is coupled to the first voltage terminal VGL, and the control terminal of the second transistor T2 is coupled to the first clock signal terminal CK.

[0125] The first terminal of the third transistor T3 is coupled to the first clock signal terminal CK, and the control terminal of the third transistor T3 is coupled to the first node S1.

[0126] The first terminal of the fourth transistor T4 is coupled to the second terminal of the third transistor T3, the control terminal of the fourth transistor T4 is coupled to the first node S1, and the second terminal of the fourth transistor T4 is coupled to the second terminal of the second transistor T2.

[0127] The first terminal of the fifth transistor T5 is coupled to the second voltage terminal VGH, and the control terminal of the fifth transistor T5 is coupled to the second terminal of the second transistor T2.

[0128] The first terminal of the sixth transistor T6 is coupled to the second clock signal terminal CB, and the second terminal of the sixth transistor T6 is coupled to the second terminal of the fifth transistor T5.

[0129] The first terminal of the seventh transistor T7 is coupled to the second clock signal CB, and the control terminal of the seventh transistor T7 is coupled to the second terminal of the second transistor T2.

[0130] The first plate of the first capacitor C1 is coupled to the control electrode of the seventh transistor T7, and the second plate of the first capacitor C1 is coupled to the second electrode of the seventh transistor T7.

[0131] The first terminal of the eighth transistor T8 is coupled to the second terminal of the seventh transistor T7, the control terminal of the eighth transistor T8 is coupled to the second clock signal CB, and the second terminal of the eighth transistor T8 is coupled to the third node S3.

[0132] The first terminal of the ninth transistor T9 is coupled to the second voltage terminal VGH, the control terminal of the ninth transistor T9 is coupled to the first node S1, and the second terminal of the ninth transistor T9 is coupled to the third node S3.

[0133] The first terminal of the tenth transistor T10 is coupled to the second voltage terminal VGH, the control terminal of the tenth transistor T10 is coupled to the third node S3, and the second terminal of the tenth transistor T10 is coupled to the output terminal OUT of the first output circuit 31. The output terminal OUT of the first output circuit 31 is... Figure 5 The intermediate shift register is used as the output port to provide the input signal Vin to the next level shift register.

[0134] The first plate of the second capacitor C2 is coupled to the second voltage terminal VGH, and the second plate of the second capacitor C2 is coupled to the third node S3.

[0135] The first terminal of the eleventh transistor T11 is coupled to the first voltage terminal VGL, the control terminal of the eleventh transistor T11 is coupled to the second node S2, and the second terminal of the eleventh transistor T11 is coupled to the output terminal OUT of the first output circuit 31.

[0136] The first terminal of the twelfth transistor T12 is coupled to the second terminal of the second transistor T2. The control terminal of the twelfth transistor T12 is coupled to the first voltage terminal VGL. The second terminal of the twelfth transistor T12 is coupled to the control terminal of the seventh transistor T7.

[0137] The first terminal of the thirteenth transistor T13 is coupled to the first node S1, the control terminal of the thirteenth transistor T13 is coupled to the first voltage terminal VGL, and the second terminal of the thirteenth transistor T13 is coupled to the second node S2.

[0138] The first terminal of the fourteenth transistor T14 is coupled to the second voltage terminal VGH, the control terminal of the fourteenth transistor T14 is coupled to the protection signal terminal BH, and the second terminal of the fourteenth transistor T14 is coupled to the first node S1.

[0139] The first terminal of the fifteenth transistor T15 is coupled to the input signal terminal Vin, and the control terminal of the first transistor T1 is coupled to the first clock signal terminal CK.

[0140] The first terminal of the sixteenth transistor T16 is coupled to the second terminal of the fifteenth transistor T15, and the control terminal of the sixteenth transistor T16 is coupled to the first voltage terminal.

[0141] The first terminal of the seventeenth transistor T17 is coupled to the second terminal of the sixteenth transistor T16, the control terminal of the seventeenth transistor T17 is coupled to the control terminal of the sixth transistor T6, and the second terminal of the seventeenth transistor T17 is coupled to the second node S2.

[0142] The first plate of the third capacitor C3 is coupled to the second plate of the sixth transistor T6, and the second plate of the third capacitor C3 is simultaneously coupled to the control electrode of the sixth transistor T6 and the first plate of the seventeenth transistor T17.

[0143] Based on this, and based on the circuit structure of 17T3C, the first output circuit 31 in some embodiments may also have some modified structures.

[0144] In some embodiments, both the third transistor T3 and the fourth transistor T4 are P-type transistors, and are configured to control the conduction or disconnection between the first clock signal terminal and the second terminal of the second transistor T2 under the control of the level of the first node S1. In this case, only one of the third transistor T3 and the fourth transistor T4 needs to be retained, which will not affect the scheme and can save the cost of electronic devices.

[0145] In some embodiments, the twelfth transistor T12 remains continuously on under the control of a low-level signal provided by the first voltage terminal VGL. If the circuit does not have a twelfth transistor T12, directly coupling the second terminal of the second transistor T2 to the control terminal of the seventh transistor T7 achieves the same effect as having a twelfth transistor T12. Therefore, in Figure 7 The twelfth transistor T12 can be omitted in the first output circuit 31 shown.

[0146] Similarly, the thirteenth transistor T13 remains continuously turned on under the control of the low-level signal provided by the first voltage terminal VGL. Therefore, Figure 7 The thirteenth transistor T13 can also be omitted in the first output circuit 31 shown.

[0147] Similarly, the sixteenth transistor T16 remains continuously turned on under the control of the low-level signal provided by the first voltage terminal VGL. Therefore, Figure 7 The sixteenth transistor T16 can also be omitted in the first output circuit 31 shown.

[0148] In some embodiments, the fourteenth transistor T14 is a P-type transistor. The specific function of the protection signal terminal BH and the fourteenth transistor T14 is that before the display panel is lit, the protection signal terminal BH provides a low-level signal to the fourteenth transistor T14, so that the high-level signal provided by the second voltage terminal VGH pulls up the level of the first node S1, controls the eleventh transistor T11 to be in the off state, and prevents the first output circuit 31 from outputting a low-level signal.

[0149] During the image refresh process on the display panel, the protection signal terminal BH continuously outputs a high-level signal, keeping the fourteenth transistor T14 in the off state. This does not affect the implementation of the first output circuit 31. Therefore, this only applies to the image refresh process on the display panel. Figure 7 The fourteenth transistor T14 and the protection signal terminal BH can also be omitted in the first output circuit 31 shown.

[0150] The embodiments of this application are not limited to variations of the first output circuit 31 described above. Figure 7 This is just an example of a first output circuit 31.

[0151] The second output circuit 32 is coupled to the third voltage terminal VGL', the fourth voltage terminal VGH', the first output circuit 31, and the control signal terminal Ctrl. When the corresponding control signal is obtained, the second output circuit 32 outputs the second output signal.

[0152] For example, the control signal output from the control signal terminal Ctrl can be used to control the change state of the second output signal output by the second output circuit 32, which is the same as the change state of the first output signal output by the first output circuit 31. The change state includes the trend of change (level increase or level decrease) and the time point of change. For example, if both signals increase in level simultaneously at the same time point, it indicates that the two signals have the same change state.

[0153] Alternatively, the control signal output from the control signal terminal Ctrl can control the second output signal output by the second output circuit 32 to be a failure signal. Here, a failure signal refers to a signal that controls the transistor to be in the off state; correspondingly, a signal that controls the transistor to be in the on state can be called a valid signal.

[0154] It should be noted that the third voltage terminal VGL' can have the same voltage level as the first voltage terminal VGL, and the fourth voltage terminal VGH' can have the same voltage level as the second voltage terminal VGH. Alternatively, the third voltage terminal VGL' can have a different voltage level than the first voltage terminal VGL; or the fourth voltage terminal VGH' can have a different voltage level than the second voltage terminal VGH. For example, the first voltage terminal VGL is -7V, the second voltage terminal VGH is +7V; the third voltage terminal VGL' is -10V, and the fourth voltage terminal VGH' is +7V.

[0155] For ease of understanding, we will continue to use the first voltage terminal VGL as the third voltage terminal VGL' and the second voltage terminal VGH as the fourth voltage terminal VGH' as examples. However, this should not be regarded as a limitation on the third voltage terminal VGL' and the fourth voltage terminal VGH'.

[0156] like Figure 8 As shown, the second output circuit 32 may include a logic sub-circuit 321 and an output sub-circuit 322. The logic sub-circuit 321 is coupled to the first output circuit 31 and the control signal terminal, respectively. When the logic sub-circuit 321 receives the corresponding control signal Ctrl, it outputs a logic signal to the output sub-circuit 322.

[0157] Meanwhile, the output sub-circuit 322 is also coupled to the first output circuit 31. The output sub-circuit 322 outputs a second output signal based on the signal provided by the first output circuit 31 and the logic signal provided by the logic sub-circuit 321.

[0158] In some examples, such as Figure 8 As shown, logic sub-circuit 321 is coupled to the output terminal OUT and the first node S1 of the first output circuit 31, as well as the control signal terminal Ctrl. Logic sub-circuit 321 is configured to output a logic signal under the control of the first output signal output from the output terminal OUT of the first output circuit 31, the level provided by the first node S1, and the control signal provided by the control signal terminal Ctrl.

[0159] The output sub-circuit 322 is coupled to the logic sub-circuit 321 and the second node S2 of the first output circuit 31. The output sub-circuit 322 is configured to output a second output signal under the control of the logic signal output by the logic sub-circuit 321 and the level provided by the second node S2, so that the output terminal OUT-N of the second output circuit 32 outputs the second output signal.

[0160] Please see Figure 9 , Figure 9 for Figure 8 The diagram shows a schematic of one type of shift register. Figure 9The output sub-circuit 322 includes the eighteenth transistor T18, the nineteenth transistor T19, and the fourth capacitor C4. The logic sub-circuit 321 includes the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22. For ease of explanation, the following description will use the twentieth transistor T20 as an N-type transistor and the other transistors (T18, T19, T21, and T22) as P-type transistors.

[0161] The first terminal of the twentieth transistor T20 is coupled to the first voltage terminal VGL, and the control terminal of the twentieth transistor T20 is coupled to the output terminal OUT of the first output circuit 31. That is, the twentieth transistor T20 is the first logic transistor.

[0162] The first terminal of the twenty-first transistor T21 is coupled to the second terminal of the twentieth transistor T20. The control terminal of the twenty-first transistor T21 is coupled to the control signal terminal Ctrl. The second terminal of the twenty-first transistor T21 is coupled to the fourth node S4. That is, the twenty-first transistor T21 is the third logic transistor.

[0163] The first terminal of the twenty-second transistor T22 is coupled to the second voltage terminal VGH, the control terminal of the twenty-second transistor T22 is coupled to the first node S1 in the first output circuit 31, and the second terminal of the twenty-second transistor T22 is coupled to the fourth node S4. That is, the twenty-second transistor T22 is the second logic transistor.

[0164] The first terminal of the eighteenth transistor T18 is coupled to the second voltage terminal VGH, the control terminal of the eighteenth transistor T18 is coupled to the fourth node S4, and the second terminal of the eighteenth transistor T18 is coupled to the output terminal OUT-N of the second output circuit 32. That is, the eighteenth transistor T18 is the first output transistor.

[0165] The first plate of the fourth capacitor C4 is coupled to the second voltage terminal VGH, and the second plate of the fourth capacitor C4 is coupled to the fourth node S4.

[0166] The first terminal of the nineteenth transistor T19 is coupled to the first voltage terminal VGL, the control terminal of the nineteenth transistor T19 is coupled to the second node S2 in the first output circuit 31, and the second terminal of the nineteenth transistor T19 is coupled to the output terminal OUT-N of the second output circuit 32. The nineteenth transistor T19 is the second output transistor.

[0167] The following is about Figure 9 The shift register shown provides a detailed explanation of its operation during image display on the display panel.

[0168] Please see Figure 10 , Figure 10 This is a timing diagram of a shift register. Figure 10 The diagram shows the timing changes of the input signal terminal Vin, the first clock signal terminal CK, the second clock signal terminal CB, the control signal terminal Ctrl, the third node S3, the second node S2, the output terminal OUT of the first output circuit 31, the first node S1, the fourth node S4, and the output terminal OUT-N of the second output circuit 32.

[0169] like Figure 10 As shown, Figure 9 The shift register shown has multiple operating stages. It should be noted that, as previously explained, the protection signal terminal BH always provides a high-level signal during the display panel image display process; therefore, the fourteenth transistor T14 remains in the off state. The state of the fourteenth transistor T14 will not be described further in subsequent stages.

[0170] In the first stage H1, the first clock signal CK is high, causing the first transistor T1, the second transistor T2, and the fifteenth transistor T15 to be in the off state. Therefore, no new signal is written to the first node S1, and the first node S1 and the second node S2 remain at the low level of the previous stage.

[0171] The first node S1 will turn on the third transistor T3 and the fourth transistor T4. The high-level signal will be transmitted to the control electrode of the seventh transistor T7 and the control electrode of the fifth transistor T5, causing the seventh transistor T7 and the fifth transistor T5 to also be turned off.

[0172] The first node S1 also turns on the ninth transistor T9. With the ninth transistor T9 on, a high-level signal at the second voltage terminal VGH is written to the third node S3. The high-level signal at the third node S3 then controls the tenth transistor T10 to be off. The low-level signal at the second node S2 controls the eleventh transistor T11 to be on. Thus, the output terminal OUT of the first output circuit 31 is connected to the first voltage terminal VGL, and the output terminal OUT of the first output circuit 31 outputs a low-level signal.

[0173] The first output circuit 31 outputs a low-level signal at its output terminal OUT to control the twentieth transistor T20 to be in the off state, and the control signal terminal Ctrl provides a high-level signal to control the twentieth transistor T21 to be in the off state.

[0174] The first node S1 also controls the twenty-second transistor T22 to be in the conducting state. When the twenty-second transistor T22 is in the conducting state, the high-level signal provided by the second voltage terminal is written to the fourth node S4, causing the eighteenth transistor T18 to be in the cut-off state.

[0175] The second node S2 controls the nineteenth transistor T19 to be in the conducting state, and the first voltage terminal is connected to the output terminal OUT-N of the second output circuit 32. The output terminal OUT-N of the second output circuit 32 outputs a low-level signal.

[0176] In the second stage H2, the first clock signal CK is a low-level signal, causing the first transistor T1, the second transistor T2, and the fifteenth transistor T15 to all be in the conducting state. Therefore, at this time, the input signal, which is a high-level signal, is written into the first node S1, the second node S2, and the first terminal of the seventeenth transistor T17.

[0177] The first node S1 will turn off the third transistor T3 and the fourth transistor T4. The low-level signal provided by the first voltage terminal VGL will turn on the fifth transistor T5 and the seventh transistor T7. With the fifth transistor T5 on, the high-level signal provided by the second voltage terminal VGH will be transmitted to the first plate of the third capacitor C3. The seventh transistor T7 is on, but because the second clock signal CB is high, the eighth transistor T8 is off, and the second clock signal CB cannot be transmitted to the third node S3.

[0178] The first node S1 also keeps the ninth transistor T9 in the off state. Since both the eighth transistor T8 and the ninth transistor T9 are in the off state, no new signal is written to the third node S3, so the third node S3 maintains the high level of the first stage H1. In this way, the third node S3 controls the tenth transistor T10 to be in the off state. The high-level second node S2 also controls the eleventh transistor T11 to be in the off state. Thus, the output terminal OUT of the first output circuit 31 continues to output a low-level signal while maintaining the first stage H1.

[0179] The first output circuit 31 outputs a low-level signal at its output terminal OUT to control the twentieth transistor T20 to be in the off state, and the control signal terminal Ctrl provides a high-level signal to control the twentieth transistor T21 to be in the off state.

[0180] The first node S1 also controls the twenty-second transistor T22 to be in the off state. Since no new signal is written to the fourth node S4, the fourth node S4 maintains the high level of the first stage H1, causing the eighteenth transistor T18 to be in the off state.

[0181] The second node S2 controls the nineteenth transistor T19 to be in the off state. Thus, the output terminal OUT-N of the second output circuit 32 maintains the low-level signal output of the first stage H1.

[0182] In the third stage H3, the first clock signal CK is high, causing the first transistor T1, the second transistor T2, and the fifteenth transistor T15 to be in the off state. Therefore, no new signal is written to the first node S1, and the first node S1 and the second node S2 maintain the high level of the second stage H2.

[0183] The first node S1 will turn off the third transistor T3 and the fourth transistor T4. No new signal is written to the second terminal of the fourth transistor T4, thus maintaining the low level of the second stage H2, controlling the fifth transistor T5 and the seventh transistor T7 to be on. With the fifth transistor T5 on, the high-level signal provided by the second voltage terminal will be written to the first plate of the third capacitor C3. With the seventh transistor T7 on and the second clock signal CB low, the eighth transistor T8 is turned on, causing the second clock signal CB to be written to the third node S3, making the third node S3 low.

[0184] The second node S2 is at a high level, causing the eleventh transistor T11 to be in the off state. The third node S3 is at a low level, controlling the tenth transistor T10 to be in the conducting state. Thus, the output terminal OUT of the first output circuit 31 outputs a high-level signal provided by the second voltage terminal VGH.

[0185] The first output circuit 31 outputs a high-level signal at its output terminal OUT, controlling the twentieth transistor T20 to be in the conducting state. Simultaneously, the control signal terminal Ctrl outputs a low-level signal, causing the twenty-first transistor T21 to be in the conducting state. Therefore, the low-level signal provided by the first voltage terminal VGL can be transmitted to the fourth node S4.

[0186] The first node S1 also controls the twenty-second transistor T22 to be in the off state. The fourth node S4 only receives a low-level signal, therefore it is at a low level, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. The output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs a high-level signal provided by the second voltage terminal VGH.

[0187] In the fourth stage H4, the first clock signal CK is a low-level signal, causing the first transistor T1, the second transistor T2, and the fifteenth transistor T15 to all be in the conducting state. Therefore, at this time, the input signal, which is a high-level signal, is written into the first node S1, the second node S2, and the first terminal of the seventeenth transistor T17.

[0188] The first node S1 will turn off the third transistor T3 and the fourth transistor T4. The low-level signal provided by the first voltage terminal VGL will turn on the fifth transistor T5 and the seventh transistor T7. With the fifth transistor T5 on, the high-level signal provided by the second voltage terminal VGH will be transmitted to the first plate of the third capacitor C3. With the seventh transistor T7 on, the second clock signal CB is high, the eighth transistor T8 is off, and the second clock signal CB cannot be transmitted to the third node S3.

[0189] The first node S1 also keeps the ninth transistor T9 in the off state. Since both the eighth transistor T8 and the ninth transistor T9 are in the off state, no new signal is written to the third node S3, so the third node S3 maintains the low level of the third stage H3. In this way, the third node S3 controls the tenth transistor T10 to be in the conducting state. The high-level second node S2 also controls the eleventh transistor T11 to be in the off state. In this way, the output terminal OUT of the first output circuit 31 is connected to the second voltage terminal VGH, and the output terminal OUT of the first output circuit 31 outputs the high-level signal provided by the second voltage terminal VGH.

[0190] The first output circuit 31 outputs a high-level signal at its output terminal OUT, controlling the twentieth transistor T20 to be in the conducting state. Simultaneously, the control signal terminal Ctrl first outputs a low-level signal to turn on the twentieth transistor T21, and the fourth node S4 writes the low-level signal provided by the first voltage terminal VGL. Afterwards, the control signal terminal Ctrl first outputs a high-level signal to turn off the twentieth transistor T21.

[0191] Since the first node S1 controls the twenty-second transistor T22 to be in the off state, the fourth node S4 will not write a new signal, so the fourth node S4 remains at a low level, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. In this way, the output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs a high-level signal provided by the second voltage terminal VGH.

[0192] In the fifth stage H5, the operation of the first output circuit 31 is basically the same as that in the third stage H3, and will not be described again here.

[0193] The first output circuit 31 outputs a high-level signal at its output terminal OUT, controlling the twentieth transistor T20 to be in the conducting state. Simultaneously, the control signal terminal Ctrl outputs a high-level signal, causing the twenty-first transistor T21 to be in the cutoff state. Therefore, the low-level signal provided by the first voltage terminal VGL cannot be transmitted to the fourth node S4.

[0194] The first node S1 also controls the twenty-second transistor T22 to be in the off state. No new signal is written to the fourth node S4, therefore the fourth node S4 maintains the low level of the fourth stage H4, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. The output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs a high-level signal provided by the second voltage terminal VGH.

[0195] In the sixth stage H6, the operation of the first output circuit 31 is basically the same as that in the fourth stage H4, and will not be described again here.

[0196] The first output circuit 31 outputs a high-level signal at its output terminal OUT, controlling the twentieth transistor T20 to be in the conducting state. Simultaneously, the control signal terminal Ctrl outputs a high-level signal, causing the twenty-first transistor T21 to be in the cutoff state. Therefore, the low-level signal provided by the first voltage terminal VGL cannot be transmitted to the fourth node S4.

[0197] The first node S1 also controls the twenty-second transistor T22 to be in the off state. No new signal is written to the fourth node S4, therefore the fourth node S4 maintains the low level of the fourth stage H4, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. The output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs a high-level signal provided by the second voltage terminal VGH.

[0198] In stage H7, the operation of shift register 30 is basically the same as that in stage H5, so it will not be described again here.

[0199] In stage H8, the operation of shift register 30 is basically the same as that in stage H6, so it will not be described again here.

[0200] In stage H9, the operation of shift register 30 is basically the same as that in stage H5, so it will not be described again here.

[0201] In the tenth stage H10, the first clock signal CK is a low-level signal, causing the first transistor T1, the second transistor T2, and the fifteenth transistor T15 to all be in the conducting state. Therefore, at this time, the low-level input signal is written into the first node S1, the second node S2, and the first terminal of the seventeenth transistor T17.

[0202] The first node S1 will turn on the third transistor T3 and the fourth transistor T4. The low-level signal provided by the first voltage terminal VGL will turn on the fifth transistor T5 and the seventh transistor T7. With the fifth transistor T5 on, the high-level signal provided by the second voltage terminal VGH will be transmitted to the first plate of the third capacitor C3. With the seventh transistor T7 on, the second clock signal CB is a high-level signal, and the eighth transistor T8 is off, so the second clock signal CB cannot be transmitted to the third node S3.

[0203] The first node S1 also turns on the ninth transistor T9. With the ninth transistor T9 on, the high-level signal provided by the second voltage terminal VGH is written to the third node S3, thus making the third node S3 high. In this way, the third node S3 controls the tenth transistor T10 to be off. The low-level second node S2 controls the eleventh transistor T11 to be on. Thus, the output terminal OUT of the first output circuit 31 is connected to the first voltage terminal VGL, and the output terminal OUT of the first output circuit 31 outputs the low-level signal provided by the first voltage terminal VGL.

[0204] The first output circuit 31 outputs a low-level signal at its output terminal OUT, controlling the twentieth transistor T20 to be in the off state. Simultaneously, the control signal terminal Ctrl outputs a high-level signal, causing the twenty-first transistor T21 to be in the off state. Therefore, the low-level signal provided by the first voltage terminal VGL cannot be transmitted to the fourth node S4.

[0205] The first node S1 also controls the twenty-second transistor T22 to be in the conducting state. A high-level signal provided by the second voltage terminal VGH is written to the fourth node S4, therefore the fourth node S4 is at a high level, controlling the eighteenth transistor T18 to be in the off state. The second node S2 controls the nineteenth transistor T19 to be in the conducting state. The output terminal OUT-N of the second output circuit 32 is connected to the first voltage terminal VGL, and the output terminal OUT-N of the second output circuit 32 outputs a low-level signal provided by the first voltage terminal VGL.

[0206] After the tenth stage H10, the working process of the tenth stage H10 is maintained until the input signal of the next frame arrives, and then the cycle from the first stage H1 to the tenth stage H10 is restarted.

[0207] Please see Figure 11 , Figure 11 for Figure 6 The diagram shows another possible structure of the shift register. Figure 12 for Figure 11 The diagram shows a schematic of one type of shift register.

[0208] In some examples, such as Figure 11As shown, logic sub-circuit 321 is coupled to the third node S3 and the first node S1 of the first output circuit 31, as well as the control signal terminal Ctrl. Logic sub-circuit 321 is configured to output logic signals under the control of the level provided by the third node S3 of the first output circuit 31, the level provided by the first node S1, and the control signal provided by the control signal terminal Ctrl.

[0209] The output sub-circuit 322 is coupled to the logic sub-circuit 321 and the second node S2 of the first output circuit 31. The output sub-circuit 322 is configured to output a second output signal under the control of the logic signal output by the logic sub-circuit 321 and the level provided by the second node S2, so that the output terminal OUT-N of the second output circuit 32 outputs the second output signal.

[0210] like Figure 12 As shown, the output sub-circuit 322 includes the eighteenth transistor T18, the nineteenth transistor T19, and the fourth capacitor C4, and the logic sub-circuit 321 includes the twenty-fourth transistor T24 and the twenty-fifth transistor T25. For ease of explanation, the following description will assume that the eighteenth transistor T18, the nineteenth transistor T19, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 are all P-type transistors.

[0211] The first terminal of the 24th transistor T24 is coupled to the third node S3 of the first output circuit 31, the control terminal of the 24th transistor T24 is coupled to the control signal terminal Ctrl, and the second terminal of the 24th transistor T24 is coupled to the fourth node S4. The 24th transistor T24 is the fourth logic transistor.

[0212] The first terminal of the 25th transistor T25 is coupled to the second voltage terminal VGH, the control terminal of the 25th transistor T25 is coupled to the first node S1 in the first output circuit 31, and the second terminal of the 25th transistor T25 is coupled to the fourth node S4. The 25th transistor T25 is the fifth logic transistor.

[0213] The first terminal of the eighteenth transistor T18 is coupled to the second voltage terminal VGH, the control terminal of the eighteenth transistor T18 is coupled to the fourth node S4, and the second terminal of the eighteenth transistor T18 is coupled to the output terminal OUT-N of the second output circuit 32. That is, the eighteenth transistor T18 is the first output transistor.

[0214] The first plate of the fourth capacitor C4 is coupled to the second voltage terminal VGH, and the second plate of the fourth capacitor C4 is coupled to the fourth node S4.

[0215] The first terminal of the nineteenth transistor T19 is coupled to the first voltage terminal VGL, the control terminal of the nineteenth transistor T19 is coupled to the second node S2 in the first output circuit 31, and the second terminal of the nineteenth transistor T19 is coupled to the output terminal OUT-N of the second output circuit 32. That is, the nineteenth transistor T19 is the second output transistor.

[0216] The following is about Figure 12 The shift register shown provides a detailed explanation of its operation during the image display process on the display panel. Please refer to [link / reference]. Figure 10 , Figure 10 This is a timing diagram of a shift register. Figure 10 The diagram shows the timing changes of the input signal terminal Vin, the first clock signal terminal CK, the second clock signal terminal CB, the control signal terminal Ctrl, the third node S3, the second node S2, the output terminal OUT of the first output circuit 31, the first node S1, the fourth node S4, and the output terminal OUT-N of the second output circuit 32.

[0217] like Figure 10 As shown, Figure 12 The shift register shown has multiple operating stages. It should be noted that... Figure 12 The working process of the first output circuit 31 in each stage (H1-H10) and Figure 9 The operation of the first output circuit 31 in each stage (H1-H10) is basically the same, and will not be described again here. Only the operation of the second output circuit 32 in each stage (H1-H10) will be described.

[0218] In the first stage H1, the output terminal OUT of the first output circuit 31 outputs a low-level signal.

[0219] The high-level signal provided by the control signal terminal Ctrl controls the twenty-fourth transistor T24 to be in the off state. The first node S1 of the first output circuit 31 is at a low level, controlling the twenty-fifth transistor T25 to be in the conducting state. The high-level signal provided by the second voltage terminal VGH is written to the fourth node S4, controlling the eighteenth transistor T18 to be in the off state.

[0220] When the second node S2 of the first output circuit 31 is at a low level, the nineteenth transistor T19 is turned on, and the first voltage terminal VGL is connected to the output terminal OUT-N of the second output circuit 32. The output terminal OUT-N of the second output circuit 32 outputs the low-level signal provided by the first voltage terminal VGL.

[0221] In the second stage H2, the output terminal OUT of the first output circuit 31 continues to output a low-level signal, maintaining the output of the first stage H1.

[0222] The high-level signal provided by the control signal terminal Ctrl controls the twenty-fourth transistor T24 to be in the off state. The first node S1 of the first output circuit 31 is at a high level, controlling the twenty-fifth transistor T25 to be in the off state. Since no new signal is written to the fourth node S4, the first stage H1 remains at a high level, controlling the eighteenth transistor T18 to be in the off state.

[0223] When the second node S2 of the first output circuit 31 is at a high level, it controls the nineteenth transistor T19 to be in the off state. No new signal is written to the output terminal OUT-N of the second output circuit 32, maintaining the low-level signal of the first stage H1.

[0224] In the third stage H3, the output terminal OUT of the first output circuit 31 outputs a high-level signal provided by the second voltage terminal VGH.

[0225] When the second node S2 of the first output circuit 31 is at a high level, it controls the nineteenth transistor T19 to be in the off state.

[0226] When the first node S1 of the first output circuit 31 is at a high level, it controls the twenty-fifth transistor T25 to be in the off state. The low-level signal provided by the control signal terminal Ctrl controls the twenty-fourth transistor T24 to be in the on state. The third node S3 and the fourth node S4 of the first output circuit 31 are connected. When the third node S3 is at a low level, the fourth node S4 is also at a low level, controlling the eighteenth transistor T18 to be in the on state. In this way, the second voltage terminal VGH is connected to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal output by the second voltage terminal VGH.

[0227] In the fourth stage H4, the output terminal OUT of the first output circuit 31 outputs a high-level signal provided by the second voltage terminal VGH.

[0228] When the second node S2 of the first output circuit 31 is at a high level, it controls the nineteenth transistor T19 to be in the off state.

[0229] The control signal terminal Ctrl first provides a low-level signal, controlling the twenty-fourth transistor T24 to be in the conducting state. The third node S3 and the fourth node S4 of the first output circuit 31 are connected; the third node S3 being low causes the fourth node S4 to also be low. Then, the control signal terminal Ctrl provides a high-level signal, controlling the twenty-fourth transistor T24 to be in the cutoff state. The first node S1 of the first output circuit 31 is high, controlling the twenty-fifth transistor T25 to be in the cutoff state. Thus, the fourth node S4 is low, controlling the eighteenth transistor T18 to be in the conducting state. In this way, the second voltage terminal VGH is connected to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal from the second voltage terminal VGH.

[0230] In the fifth stage H5, the output terminal OUT of the first output circuit 31 outputs a high-level signal provided by the second voltage terminal VGH.

[0231] When the second node S2 of the first output circuit 31 is at a high level, it controls the nineteenth transistor T19 to be in the off state.

[0232] The high-level signal provided by the control signal terminal Ctrl controls the twenty-fourth transistor T24 to be in the off state. The first node S1 of the first output circuit 31 is at a high level, controlling the twenty-fifth transistor T25 to be in the off state. Thus, no new signal is written to the fourth node S4, and the fourth node S4 maintains the low level of the fourth stage S4, controlling the eighteenth transistor T18 to be in the conducting state. In this way, the second voltage terminal VGH is connected to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal output by the second voltage terminal VGH.

[0233] In stages H6, H7, H8, and H9, the operation of the second output circuit 32 is basically the same as that in stage H5, and will not be described again here.

[0234] In the tenth stage H10, the output terminal OUT of the first output circuit 31 outputs a low-level signal provided by the first voltage terminal VGL.

[0235] The high-level signal provided by the control signal terminal Ctrl controls the twenty-fourth transistor T24 to be in the off state. The first node S1 of the first output circuit 31 is at a low level, controlling the twenty-fifth transistor T25 to be in the conducting state. The high-level signal of the second voltage terminal VGH is written to the fourth node S4, controlling the eighteenth transistor T18 to be in the off state.

[0236] When the second node S2 of the first output circuit 31 is at a low level, the nineteenth transistor T19 is turned on. The first voltage terminal VGL is coupled to the output terminal OUT-N of the second output circuit 32. The output terminal OUT-N of the second output circuit 32 outputs the low-level signal provided by the first voltage terminal VGL.

[0237] After the tenth stage H10, the working process of the tenth stage H10 is maintained until the input signal of the next frame arrives, and then the cycle from the first stage H1 to the tenth stage H10 is restarted.

[0238] The above is Figure 9 and Figure 12 The shift register shown corresponds to Figure 10 The timing diagram shown illustrates the specific workflow within a single frame refresh cycle. It illustrates a scenario where a portion of the sub-pixels in the display panel are refreshed while another portion remains unchanged. Figure 10 The timing diagram shown is the timing diagram of the shift register corresponding to the sub-pixel refresh.

[0239] Please read Figure 13 and Figure 14 , Figure 13 This is another timing diagram of the shift register. Figure 14 This is another timing diagram of a shift register. Among them, Figure 13 The control signals provided by the Ctrl terminal in the middle control signal terminal are all high-level signals. Figure 14 The control signals provided by the Ctrl terminal in the shift register are all low-level signals. The level changes of the third node S3, the second node S2, the first node S1, and the output terminal OUT in the shift register, which belong to the first output circuit 31, are related to... Figure 10 The meanings are consistent, and will not be elaborated further here.

[0240] in, Figure 13 The corresponding timing diagram is for the shift register of the sub-pixel that is not refreshed in the display panel. By setting the control signal provided by the control signal terminal Ctrl to a high level, the fourth node S4 in the second output circuit 32 is kept at a high level, controlling the eighteenth transistor T18 to be in the off state. In this way, the output terminal OUT-N of the second output circuit 32 continuously outputs a low level signal.

[0241] Figure 14 The corresponding timing diagram is the timing diagram of the shift register corresponding to the refreshed sub-pixel in the display panel. By setting the control signal provided by the control signal terminal Ctrl to a low level, the fourth node S4 in the second output circuit 32 is synchronized with the third node S3 in the first output circuit 31. In this way, the output terminal OUT-N of the second output circuit 32 and the output terminal OUT of the first output circuit 31 are continuously synchronized.

[0242] As can be seen, the control signal provided by the Ctrl terminal is mainly used to influence the level change of the fourth node S4. For example... Figure 13 As shown, when all control signals are high-level signals, Figure 9 The twenty-first transistor T21 or Figure 12 The twenty-fourth transistor T24 is always in the off state, and the fourth node S4 cannot be written with a low-level signal, thus it is always in a high-level state controlling the eighteenth transistor T18 to be in the off state. Therefore, the output terminal OUT-N of the second output circuit 32 cannot be written with a high-level signal, thus it is always in a low-level state.

[0243] And such Figure 14 As shown, when all control signals are low, the voltage level of the fourth node S4 is the same as that of the third node S3. Thus, Figure 7 and Figure 9 The eighteenth transistor T18 and the tenth transistor T10 are simultaneously turned on or off, and the nineteenth transistor T19 and the eleventh transistor T11 are synchronously turned on or off (because they are all controlled by the second node S2 in the first output circuit 31). This makes the output terminal OUT of the first output circuit 31 and the output terminal OUT-N of the second output circuit 32 output the same level.

[0244] When the output terminal OUT-N of the second output circuit 32 in the second scan drive circuit 22 and the fifth scan drive circuit outputs a low level, such as Figure 3 In the pixel circuit M shown, both the first reset transistor BT1 and the compensation transistor BT2 are in the off state.

[0245] Figure 9 and Figure 12 The shift register shown can be the shift register of the second scan drive circuit 22. In this case, the output terminal OUT-N of the second output circuit 32 in the shift register can be connected to the first reset line L-ResetN. Figure 3 The control electrode of the first reset transistor BT1 in the pixel circuit shown is coupled.

[0246] in addition, Figure 9 The shift register shown can also be the shift register of the fifth scan drive circuit 25. In this case, the output terminal OUT-N of the second output circuit 32 in the shift register can be connected to the second gate line L-GateN. Figure 3 The control electrode of the compensation transistor BT2 in the pixel circuit shown is coupled.

[0247] The following section compares the normal refresh condition with the low-level output of the output terminal OUT-N of the second output circuit 32 under the working process of the pixel circuit M, to illustrate the impact of the low-level output signal of the output terminal OUT-N of the second output circuit 32 on the sub-pixel refresh.

[0248] In the first stage P1: under normal refresh conditions, the second node N2 will be connected to the third node N3, and the third node N3 will be connected to the first node N1. Thus, the third initialization signal Vinit3 will simultaneously initialize the second node N2, the third node N3, and the first node N1. However, because the second gate signal output from the output terminal OUT-N of the second output circuit 32 in the fifth scan drive circuit 25 is a low-level signal, the compensation transistor BT2 is in the off state, and the first node N1 is disconnected from the third node N3. Therefore, the third initialization signal Vinit3 cannot initialize the first node N1.

[0249] In the second stage P2: Under normal refresh conditions, the first transistor BT1 will be turned on, and the first initialization signal Vinit1 will be written to the first node N1 to initialize it. However, since the first reset signal output from the output terminal OUT-N of the second output circuit 32 in the second scan drive circuit 22 is a low-level signal, the first reset transistor BT1 is turned off, the first node N1 is disconnected from the first initialization signal terminal, and the first initialization signal Vinit1 cannot initialize the first node N1.

[0250] In the third stage P3: normal refresh, the second node N2 is connected to the third node N3, and the third node N3 is connected to the first node N1. Thus, the data signal is sequentially written to the first node N1 through the second node N2 and the third node N3. However, because the second gate signal output from the output terminal OUT-N of the second output circuit 32 in the fifth scan drive circuit 25 is a low-level signal, the compensation transistor BT2 is in the off state, and the data signal from the second node N1 cannot be written to the first node N1.

[0251] In the fourth stage P4: normal refresh, the compensation transistor BT2 is in the off state, so it is consistent with the normal refresh process and has no impact.

[0252] In the fifth stage (P5): during normal refresh, the data signal written to the first node N1 by the third stage (P3) is needed to control the magnitude of the current injected into the light-emitting device E. However, since no new signals are written to the first node N1 in the previous four stages, the first node N1 retains the data signal from the previous frame. This results in the light-emitting device E receiving approximately the same current as in the previous frame, causing the light-emitting device E to emit the same light as in the previous frame.

[0253] Understandably, the second scan driving circuit 22 and the fifth scan driving circuit 25 jointly output a low-level signal, which will cause the first node N1 in the pixel circuit M to maintain the level of the previous frame. The actual light emission of the sub-pixel is not significantly different from the previous frame, thereby realizing that the display panel does not refresh the display image of part of the display area.

[0254] Based on the explanation above that the control signal provided by the control signal terminal Ctrl can control the second output terminal OUT-N of a single shift register to output a high-level signal or a low-level signal, and since the n shift registers in the scan drive circuit operate sequentially, by adjusting the duration of the low-level signal in the control signal provided by the control signal terminal Ctrl, it is possible to control a portion of the n shift registers in the scan drive circuit to output a low-level signal, thus preventing some row sub-pixels on the display panel from refreshing; and to control another portion of the shift registers in the scan drive circuit to output a high-level signal, thus preventing another portion of the row sub-pixels on the display panel from refreshing.

[0255] Figure 15 This diagram illustrates the timing of signals output by multiple shift registers in the display panel within one frame refresh cycle. Figure 15 The diagram shows the timing changes of the input signal terminal Vin, the first clock signal terminal CK, the second clock signal terminal CB, the control signal terminal Ctrl, the third node S3, the second node S2, the output terminal OUT of the first output circuit 31, the first node S1, the fourth node S4, and the output terminal OUT-N of the second output circuit 32.

[0256] Figure 15 In this context, OUT(i) is the first output signal output by the first output circuit 31 in the i-th shift register, and OUT-N(i) is the second output signal output by the second output circuit 32 in the i-th shift register. Similarly, OUT(j) is the first output signal output by the first output circuit 31 in the j-th shift register, and OUT-N(j) is the second output signal output by the second output circuit 32 in the j-th shift register. i and j are positive integers and are not equal to each other.

[0257] from Figure 15It can be observed that when the rising edge of the first output signal from the first output circuit 31 in the shift register is at a low level, the second output signal from the second output circuit 32 exhibits the same change as the first output signal. When the rising edge of the first output signal from the first output circuit 31 in the shift register is at a high level, the second output signal from the second output circuit 32 is at a low level. Since the shift register controls the N-type transistor in the pixel circuit M, a low-level signal cannot turn on the transistor; therefore, the low-level signal output by the second output circuit 32 can also be considered an invalid signal.

[0258] Based on this, by adjusting the timing of the control signal, a high-level control signal can cover the rising edge of the shift register corresponding to the sub-pixel row that does not need to be refreshed, and a low-level control signal can cover the rising edge of the shift register corresponding to the sub-pixel row that needs to be refreshed. This allows the sub-pixels of some rows in the display panel to be refreshed, while the sub-pixels of the remaining rows are not refreshed.

[0259] Figure 16 This diagram illustrates the signal transmission between multiple shift registers and multiple rows of sub-pixels in the AA region within a single frame refresh cycle. Thick lines represent the signal lines connected to the shift register RS, indicating that the second output signal from the second output circuit 32 in the shift register is a high-level signal; thin lines represent the signal lines connected to the shift register RS, indicating that the second output signal from the second output circuit 32 in the shift register is a low-level signal.

[0260] In this way, by adjusting the timing of the low-level and high-level signals in the control signal, the first scan signal line (e.g., the second gate line or the first reset signal line) L1, which is at least partially located in the first display area FL of the display panel, can be controlled to provide a low-level signal, so that the sub-pixels in the first display area FL are not refreshed and continue to display the content displayed in the previous frame; the control signal can also control the second scan signal line (e.g., the second gate line or the first reset signal line) L2, which is at least partially located in the second display area FH of the display panel, to provide a high-level signal, so that the sub-pixels in the second display area FH are refreshed, thereby displaying a new picture based on the data signal received in the current frame period.

[0261] Each scan signal line is coupled to the sub-pixels of the same row in area AA. Therefore, the refresh rates of sub-pixels in the same row are equal, while the refresh rates of sub-pixels in different rows may differ. Thus, the first display area FL and the second display area FH do not overlap in the second direction Y.

[0262] In some embodiments, the refresh rate of the sub-pixels in the first display area FL is lower than the refresh rate of the sub-pixels in the second display area FH.

[0263] For example, the refresh rate of the sub-pixels in the first display area FL can be 1Hz, 10Hz, 20Hz, or 30Hz. The refresh rate of the first sub-pixels in the second display area FL can be 60Hz or 120Hz.

[0264] It should be noted that when the refresh rate of the subpixels in the first display area FL is 30Hz, such as Figure 3 In the pixel circuit M shown, the first reset transistor BT1 and the compensation transistor BT2 can be low-temperature poly-silicon (LTPS) transistors. When the refresh frequency of the sub-pixels in the first display area FL is less than 30Hz, in order to reduce the impact of transistor leakage current on the first node N1, the first reset transistor BT1 and the compensation transistor BT2 in the pixel circuit M can be low-temperature polycrystalline oxide (LTPO) transistors.

[0265] in addition, Figure 16 This example illustrates the concept of two display areas with different refresh rates. In other examples, based on the same control of the shift register, three or more display areas can be configured with different refresh rates, which is not limited here.

[0266] As previously explained, when the rising edge of the first output signal from the first output circuit 31 in the shift register is at a low level, the second output signal from the second output circuit 32 exhibits the same change as the first output signal. Based on the premise that when the rising edge of the first output signal from the first output circuit 31 in the shift register is at a high level, the second output signal from the second output circuit 32 is invalid. The following section will explain the timing changes of the control signal output from the Ctrl terminal, using a specific application scenario of the display panel.

[0267] Scenario 1: All sub-pixels of the display panel refresh at 60Hz. For details on the timing changes of the control signal output from the Ctrl control terminal, please refer to [link / reference needed]. Figure 17 The timing changes of the control signals corresponding to the high refresh rate in full-screen mode.

[0268] The electronic device can set the control signal output by the control signal terminal Ctrl to a low level signal in each frame refresh cycle. This ensures that the second output signal output by the second output circuit 32 in all shift registers changes in the same way as the first output signal within each frame refresh cycle. Consequently, all sub-pixels of the display panel are refreshed in each frame refresh cycle, and the corresponding light is emitted based on the data signal received in the current cycle. This achieves a refresh rate of 60Hz for all sub-pixels of the display panel.

[0269] Scenario 2: All sub-pixels of the display panel refresh at 1Hz. For details on the timing changes of the control signal output from the Ctrl terminal, please refer to [link / reference needed]. Figure 17 The timing changes of the control signals corresponding to the low refresh rate in full-screen mode.

[0270] The electronic device can refresh all sub-pixels of the display panel in the first frame refresh cycle by setting the control signal output of the control signal terminal Ctrl to a low level signal. This ensures that the second output signals output by the second output circuit 32 in all shift registers change in the same way as the first output signal during the first frame refresh cycle. Subsequently, the electronic device can set the control signal output of the control signal terminal Ctrl to a high level signal from the second frame refresh cycle to the sixtieth frame refresh cycle. This ensures that the second output signals output by the second output circuit 32 in all shift registers are invalid during the second to sixtieth frame refresh cycles, thus preventing all sub-pixels of the display panel from refreshing during the second to sixtieth frame refresh cycles and maintaining the same emission level as in the first frame. This achieves a refresh rate of 1Hz for all sub-pixels of the display panel.

[0271] Scenario 3: The first display area FL in the display panel refreshes at 1Hz, and the second display area FH refreshes at 60Hz. For the timing changes of the control signal output from the control signal terminal Ctrl, please refer to [link / reference needed]. Figure 17 The timing changes of the control signal corresponding to the local low refresh rate.

[0272] The electronic device can refresh all sub-pixels of the display panel in the first frame refresh cycle by setting the control signal output from the control signal terminal Ctrl to a low-level signal. This ensures that the second output signals output by the second output circuit 32 in all shift registers change in the same way as the first output signals during the first frame refresh cycle. Subsequently, the electronic device can set the control signal output from the control signal terminal Ctrl to a high-level signal for a portion of the time and a low-level signal for another portion of the time during the second to sixtieth frame refresh cycles. This ensures that during each frame refresh cycle from the second to the sixtieth frame refresh cycles, the second output signals output by the second output circuit 32 in the shift register corresponding to the second display area FH change in the same way as the first output signals, while the second output signals output by the second output circuit 32 in the shift register corresponding to the first display area FL are invalid. Sub-pixels in the first display area FL do not refresh during the second to sixtieth frame refresh cycles, maintaining the same illumination as in the first frame; sub-pixels in the second display area FH refresh in each frame refresh cycle, illuminating according to the data signal received in the current cycle. In this way, it is possible to achieve a refresh rate of 1Hz for the first display area FL and a refresh rate of 60Hz for the second display area FH in each refresh cycle from the second frame refresh cycle to the sixtieth frame refresh cycle.

[0273] From the above three scenarios, it can be determined that, based on the shift register including the second output circuit 32, by adjusting the timing of the control signal output by a control signal terminal Ctrl, it is possible to flexibly control all sub-pixels of the display panel to be refreshed at a higher or lower frequency, as well as some sub-pixels to be refreshed at a higher frequency and other sub-pixels to be refreshed at a lower frequency.

[0274] In this way, the electronic device can flexibly control the refresh rate of each display area of ​​the display panel. With at least some parts of the display image remaining unchanged, the refresh rate of sub-pixels in the areas where the display image remains unchanged can be reduced by cooperating with the Source IC. This can achieve the effect of reducing the display power consumption of the display panel and increasing the reliability of the display image.

[0275] This application also provides an electronic device. The electronic device may include a battery and a display panel as described above. The battery can power the display panel, thereby enabling the display panel to emit light and display an image.

[0276] Electronic devices may include at least one of the following: mobile phones, foldable electronic devices, tablet computers, desktop computers, laptop computers, handheld computers, laptops, ultra-mobile personal computers (UMPCs), netbooks, cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices, or smart city devices. This application does not impose any special limitations on the specific type of the electronic device 100.

[0277] Figure 18 A possible structural schematic diagram of the electronic device involved in the above embodiments is shown. Figure 18 The electronic device 2100 shown includes a controller 201 and a storage module 203.

[0278] The controller 201 can be a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The controller may include an application processor and a baseband processor. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The controller can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc. The storage module 203 can be a memory, such as a register.

[0279] Figure 19 A schematic diagram of a possible structure of the controller involved in the above embodiments is shown.

[0280] This application also provides a controller (e.g., a SoC), such as Figure 19As shown, the controller may include at least one processor 701 and at least one interface circuit 702. The processor 701 and the interface circuit 702 are interconnected via wiring. For example, the interface circuit 702 may be used to receive signals from other devices (e.g., a storage module of an electronic device). As another example, the interface circuit 702 may be used to send signals to other devices (e.g., the processor 701 or an antenna assembly). Exemplarily, the interface circuit 702 may read instructions stored in a memory and send those instructions to the processor 701. When the instructions are executed by the processor 701, the electronic device may perform the steps described in the above embodiments. Of course, the controller may also include other discrete components, which are not specifically limited in this application embodiment.

[0281] This application also provides a computer-readable storage medium including computer instructions that, when executed on the electronic device, cause the electronic device to perform various functions or steps performed by the electronic device in the above method embodiments.

[0282] This application also provides a computer program product that, when run on a computer, causes the computer to perform the various functions or steps performed by the electronic device in the above method embodiments. For example, the computer may be the aforementioned electronic device.

[0283] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0284] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0285] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0286] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0287] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0288] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0289] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, include: The first output circuit is coupled to the input signal terminal, the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and the second voltage terminal. The first output circuit is configured to output a first output signal under the joint control of the input signal output from the input signal terminal, the first clock signal output from the first clock signal terminal, and the second clock signal output from the second clock signal terminal. The second output circuit is coupled to the first output circuit, the third voltage terminal, the fourth voltage terminal, and the control signal terminal; the second output circuit is configured to output a second output signal under the control of at least the signal provided by the first output circuit and the control signal output by the control signal terminal; Wherein, the change state of the second output signal is the same as the change state of the first output signal, or the second output signal is an invalid signal; The second output circuit includes a logic sub-circuit and an output sub-circuit; The logic sub-circuit is coupled to the control signal terminal, the first and third nodes of the first output circuit, and the second voltage terminal, respectively. The logic sub-circuit is configured to output a logic signal to the output sub-circuit under the control of the control signal provided by the control signal terminal, the level signal provided by the first node, and the level signal provided by the third node. The logic sub-circuit includes: a fourth logic transistor, the first terminal of which is coupled to the third node of the first output circuit, the control terminal of which is coupled to the control signal terminal, and the second terminal of which is coupled to the fourth node; a fifth logic transistor, the first terminal of which is coupled to the second voltage terminal, the control terminal of which is coupled to the first node of the first output circuit, and the second terminal of which is coupled to the fourth node; or... The logic sub-circuit is coupled to the control signal terminal, the first voltage terminal, and the first node, respectively; the logic sub-circuit is configured to output a logic signal to the output sub-circuit under the control of the control signal provided by the control signal terminal and the level signal provided by the first node; the logic sub-circuit includes: a second logic transistor, the first terminal of the second logic transistor is coupled to the second voltage terminal, the control terminal of the second logic transistor is coupled to the first node of the first output circuit, and the second terminal of the second logic transistor is coupled to the fourth node.

2. The shift register according to claim 1, characterized in that, At some stages, the logic sub-circuit is configured such that, under the control of the control signal provided at the control signal terminal, the level signal provided by the third node is output to the output sub-circuit as the logic signal through the fourth logic transistor and the fourth node; In other stages, the logic sub-circuit is configured such that, under the control of the level signal provided by the first node, the second voltage signal provided by the second voltage terminal is output to the output sub-circuit as the logic signal through the fifth logic transistor and the fourth node.

3. The shift register according to claim 1 or 2, characterized in that, The output sub-circuit is coupled to the third voltage terminal, the fourth voltage terminal, the logic sub-circuit, and the second node of the first output circuit; the output sub-circuit is configured to output the second output signal under the control of the logic signal output by the logic sub-circuit and the level signal provided by the second node.

4. The shift register according to claim 3, characterized in that, The output sub-circuit includes: The first output transistor has a first terminal coupled to the fourth voltage terminal, a control terminal coupled to the fourth node, and a second terminal coupled to the output terminal of the second output circuit. The second output transistor has its first terminal coupled to the third voltage terminal, its control terminal coupled to the second node of the first output circuit, and its second terminal coupled to the output terminal of the second output circuit.

5. The shift register according to claim 4, characterized in that, At some stages, the output sub-circuit is configured such that, under the control of the logic signal provided by the logic sub-circuit, the level signal provided by the fourth voltage terminal is output as the second output signal through the first output transistor; In other stages, the output sub-circuit is configured such that, under the control of the level signal provided by the second node, the level signal provided by the third voltage terminal is output as the second output signal through the second output transistor.

6. A scanning drive circuit, characterized in that, It includes multiple cascaded shift registers, wherein the shift registers are shift registers as described in any one of claims 1-5.

7. A display panel, characterized in that, include: Multiple sub-pixels, wherein the multiple sub-pixels are arranged in a multi-row, multi-column array; A scan driving circuit is coupled to the plurality of sub-pixels via multiple scan signal lines, each scan signal line being coupled to the plurality of sub-pixels located in the same row; wherein, the scan driving circuit includes the scan driving circuit as described in claim 6.

8. An electronic device, characterized in that, include: The display panel includes the display panel as described in claim 7; A battery is coupled to the display panel; the battery is used to supply power to the display panel.

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