Display panel and display device

Abstract

This application discloses a display panel and a display device, relating to the field of display technology. The display panel includes a first display area and a second display area. The first display area includes at least a shift register circuit and a first transparent area. At least a portion of the first transparent area overlaps with the shift register circuit along a first direction, which is parallel to the plane of the display panel. That is, the shift register circuit is disposed in the display area to achieve a borderless display panel, and the area of ​​the first transparent area is set to S1. Taking the second display area as a reference, the second display area includes at least a pixel circuit and a second transparent area. The second transparent area overlaps with the pixel circuit along the first direction, and the area of ​​the second transparent area is S2. By setting these components, the difference in the proportion of transparent areas between the first and second display areas in the display panel is reduced, the uniformity of the transmittance and reflectance of the display panel is improved, and the display effect is enhanced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In existing borderless transparent display panels, in order to place the shift register circuit in the display area, the layout space of the shift register circuit and pixel circuit is usually compressed in the border area of ​​the display panel. This results in a significant increase in the density of metal wiring in the border area of ​​the display panel, a decrease in the proportion of transparent area, and obvious metal lines that are visible to the naked eye. Even when blocked by a light-shielding layer, black lines can still be seen, causing visual differences and affecting the display effect. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a display panel and display device to reduce the difference in the proportion of transparent areas in different display areas of the display panel, improve the uniformity of transmittance and reflectance of the transparent display panel, and thus enhance the display effect.

[0004] To achieve the above objectives, this application provides the following technical solution:

[0005] In a first aspect, this application provides a display panel, the display panel including a first display area and a second display area, the first display area including at least a shift register circuit, and the second display area including at least a pixel circuit;

[0006] The first display area includes a first transparent area, and at least a portion of the first transparent area overlaps with the shift register circuit along a first direction; the second display area includes a second transparent area, and the second transparent area overlaps with the pixel circuit along the first direction, wherein the first direction is parallel to the plane of the display panel.

[0007] The area of ​​the first transparent region is S1, and the area of ​​the second transparent region is S2. .

[0008] Optionally, along the second direction, the width of the first transparent area is L1, and the width of the second transparent area is L2. The second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction.

[0009] Optionally, a plurality of the pixel circuits are arranged in a row along the second direction, and multiple rows of the pixel circuits are arranged along the first direction. The second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction.

[0010] The maximum dimension of the shift register circuit along the second direction is greater than the maximum dimension of the shift register circuit along the first direction.

[0011] Optionally, the first display area also includes pixel circuitry, and along the first direction, a portion of the first transparent area overlaps with the pixel circuitry.

[0012] The shift register circuit, the pixel circuit in the first display area, and the pixel circuit in the second display area are arranged along a second direction, which is parallel to the plane where the display panel is located and intersects with the first direction.

[0013] The pixel circuit arrangement density in the first display area is greater than that in the second display area.

[0014] Optionally, the first display area also includes pixel circuitry, and along the first direction, a portion of the first transparent area overlaps with the pixel circuitry.

[0015] The second display area further includes a redundant pixel circuit. The shift register circuit, the pixel circuit in the first display area, and the pixel circuit and the redundant pixel circuit in the second display area are arranged along the second direction, which is parallel to the plane of the display panel and intersects the first direction.

[0016] Optionally, the pixel circuit arrangement density in the first display area is the same as the pixel circuit and the redundant pixel circuit arrangement density in the second display area.

[0017] Optionally, a plurality of the pixel circuits are arranged in a row along the second direction, and multiple rows of the pixel circuits are arranged along the first direction. The second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction.

[0018] The shift register circuit is located on at least one side of a row of pixel circuits along the second direction;

[0019] Alternatively, the shift register circuit may be located between two pixel circuits in a row of pixel circuits.

[0020] Optionally, both the first display area and the second display area include pixel units and light-emitting element groups, the pixel units and the light-emitting element groups are arranged correspondingly, and the arrangement period length of the pixel units along a direction parallel to the plane of the display panel is equal to the arrangement period length of the light-emitting element groups along the same direction;

[0021] The pixel unit includes a transparent area and a non-transparent area; in the first display area, the transparent area of ​​the pixel unit includes the first transparent area; in the second display area, the transparent area of ​​the pixel unit includes the second transparent area;

[0022] In the first display area and the second display area, the relative positions of the transparent area and the non-transparent area of ​​the pixel unit are the same.

[0023] Optionally, in the first display area and the second display area, the pattern formed by the transparent area and the non-transparent area of ​​the pixel unit is the same.

[0024] Optionally, the non-transparent area of ​​the pixel unit includes a circuit area and a trace area. The trace area extends along the first direction, and the circuit area extends along the second direction. The circuit area and the trace area overlap. The second direction is parallel to the plane of the display panel and intersects with the first direction.

[0025] Optionally, a plurality of the pixel units are arranged in a row along the second direction, the circuit area of ​​each pixel unit in a row is arranged along the second direction, and multiple rows of the pixel units are arranged along the first direction;

[0026] Along a direction perpendicular to the plane of the display panel, the circuit area in the pixel unit overlaps with the corresponding light-emitting element group.

[0027] Optionally, in the pixel unit, the trace area is located on one side of the transparent area along the second direction;

[0028] Alternatively, in the pixel unit, the trace area is located on opposite sides of the transparent area along the second direction;

[0029] Alternatively, in the pixel unit, the transparent area is located on opposite sides of the trace area along the second direction.

[0030] Optionally, the circuit area includes a first sub-circuit area and a second sub-circuit area arranged along the second direction, and the routing area includes a first sub-routing area and a second sub-routing area arranged at intervals along the second direction, wherein the first sub-circuit area and the first sub-routing area overlap, and the second sub-circuit area and the second sub-routing area overlap.

[0031] Optionally, in the pixel unit, the circuit area is located on one side of the transparent area along the first direction;

[0032] Alternatively, in the pixel unit, the transparent area is located on opposite sides of the circuit area along the first direction.

[0033] Optionally, in the first display area, the circuit area includes a third sub-circuit area and a fourth sub-circuit area arranged along the first direction, the wiring area overlaps with the third sub-circuit area, and the wiring area overlaps with the fourth sub-circuit area.

[0034] Optionally, in the second display area, the circuit area of ​​the pixel unit includes at least a pixel circuit group, and the pixel circuit group is electrically connected to the corresponding light-emitting element group;

[0035] The pixel unit of the first display area includes a first pixel unit and a second pixel unit. The circuit area of ​​the first pixel unit includes the shift register circuit, and the circuit area of ​​the second pixel unit includes two sets of pixel circuit groups.

[0036] In the second pixel unit, one group of pixel circuits is electrically connected to the corresponding light-emitting element group, and another group of pixel circuits is electrically connected to the light-emitting element group corresponding to the first pixel unit through a connecting line.

[0037] Optionally, the display panel includes a substrate and a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked on one side of the substrate in a direction away from the substrate;

[0038] The third metal layer includes a first power supply voltage line, and the fourth metal layer includes a second power supply voltage line. The first power supply voltage line is electrically connected to the pixel circuit group, and the second power supply voltage line is electrically connected to the light-emitting element group. The connection line is located in the first metal layer.

[0039] Alternatively, the second metal layer includes a first power supply voltage line, the fourth metal layer includes a second power supply voltage line, the first power supply voltage line is electrically connected to the pixel circuit group, and the second power supply voltage line is electrically connected to the light-emitting element group; the connection line is located in the third metal layer.

[0040] Optionally, in the second display area, the circuit area of ​​the pixel unit includes at least a pixel circuit group, and the pixel circuit group is electrically connected to the corresponding light-emitting element group;

[0041] The pixel unit of the first display area includes a third pixel unit, and the circuit area of ​​the third pixel unit includes not only part of the shift register circuit, but also the pixel circuit group; the shift register circuit is distributed in the circuit areas of at least two adjacent third pixel units along the second direction.

[0042] Optionally, within the third pixel unit, a portion of the shift register circuit and the pixel circuit group are arranged along the first direction.

[0043] Optionally, both the first display area and the second display area include pixel units and light-emitting element groups. The pixel unit includes two sub-pixel units arranged along a second direction, which is parallel to the plane of the display panel and intersects the first direction. The sub-pixel units and the light-emitting element groups are correspondingly arranged, and the arrangement period length of the sub-pixel units along a direction parallel to the plane of the display panel is equal to the arrangement period length of the light-emitting element groups along the same direction.

[0044] The sub-pixel unit includes a transparent area and a non-transparent area; in the first display area, the transparent area of ​​the sub-pixel unit includes the first transparent area; in the second display area, the transparent area of ​​the sub-pixel unit includes the second transparent area; the non-transparent area of ​​the sub-pixel unit includes a circuit area and a wiring area, the wiring area extends along the first direction, the circuit area extends along the second direction, and the circuit area and the wiring area overlap.

[0045] Multiple pixel units are arranged in a column along the first direction, and the trace areas of each pixel unit in a column are arranged along the first direction. Multiple columns of pixel units are arranged along the second direction. In the two columns of sub-pixel units of a column of pixel units, the trace areas of one column of sub-pixel units are adjacent to the trace areas of the other column of sub-pixel units.

[0046] In the first display area and the second display area, the relative positions of the transparent area and the non-transparent area of ​​the pixel unit are the same.

[0047] Optionally, a group of light-emitting elements is electrically connected to a group of pixel circuits. The group of light-emitting elements includes a first light-emitting element and a second light-emitting element. The group of pixel circuits includes a first pixel circuit and a second pixel circuit. The first pixel circuit is electrically connected to the first light-emitting element, and the second pixel circuit is electrically connected to the second light-emitting element.

[0048] The area of ​​the first pixel circuit projected onto the plane of the display panel is different from the area of ​​the second pixel circuit projected onto the plane of the display panel.

[0049] Optionally, the first pixel circuit and the second pixel circuit are arranged along a second direction, the width of the first pixel circuit along the second direction is different from the width of the second pixel circuit along the second direction, the second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction.

[0050] Optionally, the first light-emitting element is a red light-emitting element, and the second light-emitting element is a green light-emitting element or a blue light-emitting element;

[0051] Alternatively, the first light-emitting element may be a green light-emitting element, and the second light-emitting element may be a blue light-emitting element.

[0052] Optionally, the display panel includes a light-shielding layer that covers the non-transparent area of ​​the pixel unit and exposes the transparent area of ​​the pixel unit and the light-emitting element group.

[0053] Optionally, the light-shielding layer includes multiple light-shielding units, and the light-shielding units and the pixel units are correspondingly arranged;

[0054] The light-shielding unit has a first opening that exposes the transparent area of ​​the pixel unit.

[0055] Optionally, the non-transparent area of ​​the pixel unit includes a circuit area and a trace area, the trace area extends along the first direction, the circuit area extends along the second direction, the circuit area and the trace area overlap, the second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction;

[0056] The light-shielding unit includes an overlapping first light-shielding area and a second light-shielding area, the first light-shielding area covering the circuit area and the second light-shielding area covering the wiring area.

[0057] Optionally, the wiring area includes wiring extending along the first direction, the wiring density in the wiring area of ​​the second display area is less than the wiring density in the wiring area of ​​the first display area, and the width of the second light-shielding area of ​​the second display area along the second direction is equal to the width of the second light-shielding area of ​​the first display area along the second direction.

[0058] Secondly, this application provides a display device, which includes any of the above-mentioned display panels.

[0059] Compared with existing technologies, the above technical solution has the following advantages:

[0060] The display panel and display device provided in this application include a first display area and a second display area. The first display area includes at least a shift register circuit and a first transparent area. At least a portion of the first transparent area overlaps with the shift register circuit along a first direction, which is parallel to the plane of the display panel. That is, by placing the shift register circuit in the display area, a borderless display panel is achieved. Simultaneously, by reasonably arranging the shift register circuit in the first display area, the area of ​​the first transparent area is S1. Furthermore, with the second display area as a reference, the second display area includes at least a pixel circuit and a second transparent area. The second transparent area overlaps with the pixel circuit along the first direction, and the area of ​​the second transparent area is S2, ensuring... That is, the difference between the area S2 of the second transparent area in the second display area and the area S1 of the first transparent area in the first display area is less than 0.3 times the area S2 of the second transparent area in the second display area. In other words, by reducing the difference between the area S1 of the first transparent area in the first display area and the area S2 of the second transparent area in the second display area, the difference in the proportion of transparent areas of the first display area and the second display area in the display panel is reduced, thereby improving the uniformity of the transmittance and reflectance of the display panel and thus improving the display effect. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a top view diagram of an existing frameless transparent display panel.

[0063] Figure 2 This is a partial cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0064] Figure 3 This is a partial layout diagram of a driving circuit layer in a display panel provided in an embodiment of this application;

[0065] Figure 4 This is a partial layout diagram of the driving circuit layer and the light-shielding layer in a display panel provided in an embodiment of this application;

[0066] Figure 5 This is a partial layout diagram of a metal layer and a light-shielding layer in a display panel provided in an embodiment of this application.

[0067] Figure 6 A partial layout diagram of the driving circuit layer and the light-shielding layer in another display panel provided in an embodiment of this application;

[0068] Figure 7 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to an embodiment of this application.

[0069] Figure 8 This is a schematic diagram illustrating the arrangement of a row of pixel units in another display panel provided in an embodiment of this application;

[0070] Figure 9 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0071] Figure 10 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0072] Figure 11 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0073] Figure 12 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0074] Figure 13 This is a schematic diagram of the layout structure of a pixel unit located in the driving circuit layer;

[0075] Figure 14 This is a schematic diagram illustrating the arrangement of a row of light-shielding units in a display panel according to an embodiment of this application.

[0076] Figure 15 This is a schematic diagram illustrating the arrangement of a row of pixel units in another display panel provided in an embodiment of this application;

[0077] Figure 16 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0078] Figure 17 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0079] Figure 18 This is a schematic diagram of the layout structure of the fourth metal layer and the first metal layer of the first pixel unit and the second pixel unit in the first display area of ​​a display panel provided in an embodiment of this application.

[0080] Figure 19 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0081] Figure 20 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0082] Figure 21 This is a schematic diagram illustrating the arrangement of a row of pixel units in a display panel according to another embodiment of this application.

[0083] Figure 22 This is a schematic diagram of the structure of two pixel units in the first display area of ​​a display panel provided in an embodiment of this application;

[0084] Figure 23This is a schematic diagram of the structure of two pixel units in the first display area of ​​another display panel provided in an embodiment of this application;

[0085] Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0086] Explanation of reference numerals in the attached figures:

[0087] Circuit compression region CC; Substrate sub; Driving circuit layer 100; Active layer q; Metal layers M0, M1, MC, MG, M2, M3 and RE; Light-shielding layer BM; Shift register circuit VSR; Pixel circuit PL1; Light-emitting element layer 200; Light-emitting element 201; First display area AA1; Second display area AA2; First direction Y; Second direction X; First transparent area 10; Second transparent area 20; First electrode T1; Second electrode T2; Light-emitting structure LY; First power supply voltage line PVDD; Second power supply voltage line PVEE; First opening K1; Second opening K2; Light-emitting element group 210; Pixel unit 220; Transparent area 221; Non-transparent area 222; Circuit area P1; Wiring area P2; Redundant pixel circuit PL2; Scanning circuit SCAN; Light emission control Circuit EMIT; First sub-circuit area P11; Second sub-circuit area P12; First sub-routing area P21; Second sub-routing area P22; Light-shielding unit BM0; First light-shielding area BM1; Second light-shielding area BM2; First pixel unit 220-1; Second pixel unit 220-2; Third pixel unit 220-3; Connecting lines R1, R2, R3; Sub-pixel unit 220A; First light-emitting element 211; Second light-emitting element 212; First pixel circuit 111; Second pixel circuit 112; Red light-emitting element R; Green light-emitting element G; Blue light-emitting element B; Trigger signal line STV; First level signal line CK; First level signal line VGH; Second level signal line XCK; Second level signal line VGL; Output signal line Out; Data signal line data. Detailed Implementation

[0088] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0089] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0090] As described in the background section, in existing borderless transparent display panels, in order to place the shift register circuit in the display area, the arrangement space of the shift register circuit and pixel circuit is usually compressed in the border area of ​​the display panel. This results in a significant increase in the metal wiring density in the border area of ​​the display panel, a decrease in the transparent area ratio, and clearly visible metal lines, specifically as follows: Figure 1 As shown in the circuit compression area CC of the existing frameless transparent display panel, even when blocked by a light-shielding layer, black lines can still be seen, causing visual differences and thus affecting the display effect.

[0091] In view of this, embodiments of this application provide a display panel, Figure 2 This illustration shows a partial cross-sectional structural diagram of a display panel provided in an embodiment of this application, as shown below. Figure 2 As shown, the display panel includes a substrate sub and a driving circuit layer 100 located on one side of the substrate sub. The driving circuit layer 100 includes an active layer q located on one side of the substrate sub and a multilayer metal layer located on the side of the active layer q away from the substrate sub. The multilayer metal layer is, for example, metal layer M1, metal layer MC, metal layer MG, metal layer M2, metal layer M3 and metal layer RE stacked along the direction away from the substrate sub. The driving circuit layer 100 includes a shift register circuit VSR and a pixel circuit PL1. The shift register circuit VSR is used to provide a driving signal to the pixel circuit PL1. A metal layer, such as metal layer M0, can also be disposed on the side of the active layer q facing the substrate sub. The display panel also includes a light-emitting element layer 200 located on the side of the driving circuit layer 100 away from the substrate sub. The light-emitting element layer 200 includes a plurality of light-emitting elements 201. The pixel circuit PL1 is electrically connected to the light-emitting elements 201 to drive the corresponding light-emitting elements 201 to emit light.

[0092] Figure 3 This illustration shows a partial layout diagram of the driving circuit layer 100 in a display panel according to an embodiment of this application. Figure 2 and Figure 3As shown, the display panel includes a first display area AA1 and a second display area AA2. The first display area AA1 includes at least a shift register circuit VSR, i.e., the shift register circuit VSR is placed in the display area to achieve a borderless display panel. Furthermore, the first display area AA1 includes a first transparent area 10. Along the first direction Y, at least a portion of the first transparent area 10 overlaps with the shift register circuit VSR, and the first direction Y is parallel to the plane of the display panel. Optionally, along the first direction Y, at least a portion of the first transparent area 10 and the shift register circuit VSR are arranged alternately. It is understood that because the shift register circuit VSR includes circuit structures such as thin-film transistors, the area where the shift register circuit VSR is located is a non-transparent area. Since at least a portion of the first transparent area 10 overlaps with the shift register circuit VSR along the first direction Y, the first display area AA1 can visually appear as a continuously transparent area without obvious circuit traces. By reasonably setting the shift register circuit VSR in the first display area AA1, the area of ​​the first transparent area 10 is S1.

[0093] The second display area AA2 is a conventional display area. The second display area AA2 includes at least a pixel circuit PL1, and the second display area AA2 includes a second transparent area 20. Along the first direction Y, the second transparent area 20 overlaps with the pixel circuit PL1. Optionally, along the first direction Y, the second transparent area 20 and the pixel circuit PL1 are arranged alternately. It is understood that because the pixel circuit PL1 includes circuit structures such as thin-film transistors, the area where the pixel circuit PL1 is located is also a non-transparent area. The second transparent area 20 overlaps with the pixel circuit PL1 along the first direction Y, so that the second display area AA2 can also appear as a continuous transparent area with no obvious circuit traces. With the second display area AA2 as a reference, the area of ​​the second transparent area 20 is S2.

[0094] It should be noted that, as Figure 2 As shown, the display panel also includes a light-shielding layer BM located on the side of the light-emitting element layer 200 opposite to the substrate sub; Figure 4 This illustration shows a partial layout diagram of the driving circuit layer 100 and the light-shielding layer BM in a display panel according to an embodiment of this application. Figure 2 and Figure 4As shown, the light-shielding layer BM covers non-transparent areas with circuit structures such as the shift register circuit VSR and the pixel circuit PL1, as well as other non-transparent areas such as those with metal traces. Furthermore, the light-shielding layer BM has multiple first openings K1, some of which correspond to the first transparent area 10, and others correspond to the second transparent area 20. In other words, the first transparent area 10 and the second transparent area 20 are the areas exposed by the first openings K1 of the light-shielding layer BM in the display panel. The first transparent area 10 and the second transparent area 20 do not have circuit structures or metal traces and can be transmitted by light. The light transmittance of the transparent area is greater than that of the non-transparent area on the panel, so that the display panel presents an overall transparent visual effect.

[0095] Unlike existing borderless transparent display panels where the transparent area of ​​the border region with a shift register circuit is significantly reduced, the display panel provided in this application embodiment has a first transparent area 10 with a shift register circuit VSR in the first display area AA1 with an area of ​​S1, and a second transparent area 20 with an area of ​​S2 in the second display area AA2, which is a conventional display area. By reasonably setting the shift register circuit VSR in the first display area AA1, it is ensured that... That is, the difference between the area S2 of the second transparent area 20 in the second display area AA2 and the area S1 of the first transparent area 10 in the first display area AA1 is less than 0.3 times the area S2 of the second transparent area 20 in the second display area AA2. In other words, by reducing the difference between the area S1 of the first transparent area 10 in the first display area AA1 and the area S2 of the second transparent area 20 in the second display area AA2, the difference in the proportion of transparent areas of the first display area AA1 and the second display area AA2 in the display panel is reduced, thereby improving the uniformity of the transmittance and reflectance of the display panel and thus improving the display effect.

[0096] Optionally, in some embodiments of this application, such as Figure 3 and Figure 4 As shown, along the second direction X, the width of the first transparent area 10 is L1, and the width of the second transparent area 20 is L2. This can be achieved by setting... The second direction X is parallel to the plane of the display panel, and the second direction X intersects the first direction Y, thereby making In other words, by reducing the difference between the width L1 of the first transparent area 10 in the first display area AA1 along the second direction X and the width L2 of the second transparent area 20 in the second display area AA2 along the second direction X, the difference between the area S1 of the first transparent area 10 in the first display area AA1 and the area S2 of the second transparent area 20 in the second display area AA2 can be reduced. This reduces the difference in the proportion of transparent areas in the first display area AA1 and the second display area AA2 in the display panel, improves the uniformity of the transmittance and reflectance of the display panel, and thus enhances the display effect.

[0097] Alternatively, in some embodiments of this application, such as Figure 3 and Figure 4 As shown, along the first direction Y, the length of the first transparent area 10 is D1, and the length of the second transparent area 20 is D2. This can be achieved by setting... Therefore, In other words, by reducing the difference between the length D1 of the first transparent area 10 in the first display area AA1 along the first direction Y and the length D2 of the second transparent area 20 in the second display area AA2 along the first direction Y, the difference between the area S1 of the first transparent area 10 in the first display area AA1 and the area S2 of the second transparent area 20 in the second display area AA2 can be reduced. This reduces the difference in the proportion of transparent areas in the first display area AA1 and the second display area AA2 in the display panel, improves the uniformity of the transmittance and reflectance of the display panel, and thus enhances the display effect.

[0098] Alternatively, in some embodiments of this application, such as Figure 3 and Figure 4 As shown, along the second direction X, the width of the first transparent area 10 is L1, and the width of the second transparent area 20 is L2; ​​along the first direction Y, the length of the first transparent area 10 is D1, and the length of the second transparent area 20 is D2; at this time, it is possible to set simultaneously , Therefore, In other words, by reducing both the difference between the width L1 of the first transparent area 10 along the second direction X in the first display area AA1 and the width L2 of the second transparent area 20 along the second direction X in the second display area AA2, and the difference between the length D1 of the first transparent area 10 along the first direction Y in the first display area AA1 and the length D2 of the second transparent area 20 along the first direction Y in the second display area AA2, the difference between the area S1 of the first transparent area 10 in the first display area AA1 and the area S2 of the second transparent area 20 in the second display area AA2 can be reduced. This reduces the difference in the proportion of transparent areas in the first display area AA1 and the second display area AA2 in the display panel, improves the uniformity of the transmittance and reflectance of the display panel, and thus enhances the display effect.

[0099] Further optional, in some embodiments of this application, such as Figure 3 and Figure 4As shown, the width L1 of the first transparent area 10 along the first direction Y can be set to be equal to the width L2 of the second transparent area 20 along the first direction Y, i.e., L2=L1; and / or, the length D1 of the first transparent area 10 along the second direction X can be set to be equal to the length D2 of the second transparent area 20 along the second direction X, i.e., D2=D1. Thus, the difference between the area S1 of the first transparent area 10 in the first display area AA1 and the area S2 of the second transparent area 20 in the second display area AA2 can be further reduced, thereby further reducing the difference in the proportion of transparent areas of the first display area AA1 and the second display area AA2 in the display panel, improving the uniformity of the transmittance and reflectance of the display panel, and thus improving the display effect.

[0100] Regarding the arrangement of the shift register circuit VSR within the first display area AA1, optionally, in some embodiments of this application, such as... Figure 3 and Figure 4 As shown, considering that multiple pixel circuits PL1 are arranged in a row along the second direction X, and multiple rows of pixel circuits PL1 are arranged along the first direction Y, that is, each row of pixel circuits PL1 extends along the first direction Y and is arranged along the second direction X. Both the first direction Y and the second direction X are parallel to the plane where the display panel is located, and the second direction X intersects the first direction Y. Therefore, the maximum size of the shift register circuit VSR along the second direction X can be set to be greater than the maximum size of the shift register circuit VSR along the first direction Y. It can be understood that because each row of pixel circuits PL1 extends along the first direction Y, and the shift register circuit VSR is used to provide driving signals to one or more rows of pixel circuits PL1, the shift register circuit VSR is set along the second direction X, so that the shift register circuit VSR along the second direction X... The maximum size of the shift register circuit VSR is greater than the maximum size of the shift register circuit VSR along the first direction Y. In this way, the shift register circuit VSR can be arranged in the same row as the pixel circuit PL1, and the circuit density of the shift register circuit VSR can be close to the circuit density of the pixel circuit PL1 in the same row. This is beneficial to reducing the difference in circuit density between the first display area AA1 and the second display area AA2. On the other hand, it is beneficial to arrange the first transparent area 10 of the first display area AA1 and the second transparent area 20 of the second display area AA2 in the same row along the second direction X. This further helps to reduce the area difference between the first transparent area 10 of the first display area AA1 and the second transparent area 20 of the second display area AA2, which can further improve the uniformity of the transmittance and reflectance of the display panel, and thus further improve the display effect.

[0101] like Figure 2As shown, the light-emitting element 201 can be a light-emitting diode. In this case, the light-emitting element 201 includes a first electrode T1, a second electrode T2, and a light-emitting structure LY. The light-emitting structure LY can include a first type semiconductor layer, a quantum well layer, and a second type semiconductor layer stacked together. The first type semiconductor layer is electrically connected to the first electrode T1, and the second type semiconductor layer is electrically connected to the second electrode T2. The driving circuit layer 100 also includes a first power supply voltage line PVDD (e.g., located in the metal layer M3) and a second power supply voltage line PVEE (e.g., located in the metal layer RE). The first power supply voltage line PVDD is used to provide a first power supply voltage, and the second power supply voltage line PVEE is used to provide a second power supply voltage. The first power supply voltage line PVDD is electrically connected to the pixel circuit PL1, and then the pixel circuit PL1 is electrically connected to the first electrode T1 of the light-emitting element 201. The second power supply voltage line PVEE is electrically connected to the second electrode T2 of the light-emitting element 201.

[0102] Figure 5 This illustration shows a partial layout diagram of a metal layer (RE) and a light-shielding layer BM in a display panel according to an embodiment of this application. Figure 2 and Figure 5 As shown, the light-shielding layer BM also has multiple second openings K2, which expose the light-emitting element 201. It should be noted that... Figure 5 The position of the second opening K2 in the light-shielding layer BM represents the light-emitting element 201.

[0103] Understandably, in combination Figures 3-5As shown, the first display area AA1 includes not only the shift register circuit VSR, but also multiple light-emitting elements 201. To drive the light-emitting elements 201 in the first display area AA1 to emit light, the first display area AA1 also includes a pixel circuit PL1, which facilitates electrical connection with the light-emitting elements 201 in the first display area AA1, driving the light-emitting elements 201 in the first display area AA1 to emit light. Furthermore, along the first direction Y, a portion of the first transparent area 10 overlaps with the pixel circuit PL1 in the first display area AA1. Optionally, along the first direction Y, a portion of the first transparent area 10 and the pixel circuit PL1 in the first display area AA1 are arranged alternately. That is, in the first display area AA1, a portion of the first transparent area 10 overlaps with the shift register circuit VSR along the first direction Y, and another portion of the first transparent area 10 overlaps with the pixel circuit PL1 in the first display area AA1. A portion of the first transparent area 10 overlaps with the pixel circuit PL1 along the first direction Y. Therefore, the shift register circuit VSR in the first display area AA1, the pixel circuit PL1, and the pixel circuit PL1 in the second display area AA2 can be arranged in the same row along the second direction X. Both the first direction Y and the second direction X are parallel to the plane of the display panel, and the second direction X intersects the first direction Y. This facilitates the arrangement of the first transparent area 10 of the first display area AA1 and the second transparent area 20 of the second display area AA2 along the second direction X, thereby reducing the area difference between the first transparent area 10 of the first display area AA1 and the second transparent area 20 of the second display area AA2. This further improves the uniformity of the transmittance and reflectance of the display panel, and thus further enhances the display effect.

[0104] Understandably, in combination Figures 3-4 As shown, because a shift register circuit VSR is set in the first display area AA1, the setting space of the pixel circuit PL1 is reduced. Therefore, it is necessary to compress the arrangement density of the pixel circuit PL1 in the first display area AA1 and arrange the pixel circuit PL1 in the first display area AA1 tightly. Thus, optionally, the arrangement density of the pixel circuit PL1 in the first display area AA1 is greater than the arrangement density of the pixel circuit PL1 in the second display area AA2.

[0105] It should be noted that, in combination Figures 3-5As shown, the display panel includes multiple light-emitting element groups 210, such as red, green, and blue light-emitting elements. The light-emitting element groups 210 are arranged in an array along the first direction Y and the second direction X in the display area of ​​the display panel. The display panel also includes pixel circuit groups 110, such as three pixel circuits PL1. The pixel circuit groups 110 are electrically connected to the light-emitting element groups 210. Specifically, the pixel circuits PL1 in the pixel circuit group 110 are electrically connected to the light-emitting elements 201 in the light-emitting element group 210 in a one-to-one correspondence. In this application, the arrangement density of the pixel circuits PL1 in the first display area AA1 can be reduced by reducing the spacing between two adjacent groups of pixel circuit groups 110 along the second direction X in the first display area AA1, or by reducing the spacing between two adjacent pixel circuits PL1 along the second direction X in the first display area AA1. In other words, this application sets the pixel circuit PL1 in the first display area AA1 to be greater than the pixel circuit PL1 in the second display area AA2. This can be achieved by the spacing between two adjacent groups of pixel circuits 110 along the second direction X in the first display area AA1 being smaller than the spacing between two adjacent groups of pixel circuits 110 along the second direction X in the second display area AA2, or by the spacing between two adjacent pixel circuits PL1 along the second direction X in the first display area AA1 being smaller than the spacing between two adjacent pixel circuits PL1 along the second direction X in the second display area AA2, depending on the specific circumstances. Figure 3 and Figure 4 Only the case where the spacing between two adjacent groups of pixel circuits 110 along the second direction X in the first display area AA1 is smaller than the spacing between two adjacent groups of pixel circuits 110 along the second direction X in the second display area AA2 is shown.

[0106] It should also be noted that, in combination Figures 3-5As shown, both the first display area AA1 and the second display area AA2 of the display panel include pixel units 220 and light-emitting element groups 210. The pixel units 220 and the light-emitting element groups 210 are correspondingly arranged. Specifically, the arrangement period length of the pixel units 220 along a direction parallel to the plane of the display panel is equal to the arrangement period length of the light-emitting element groups 210 along the same direction. It can be understood that in the display area of ​​the display panel, the light-emitting element groups 210 are arranged in an array along the first direction Y and the second direction X. Therefore, with the arrangement period length W11 of the light-emitting element groups 210 along the first direction Y and the arrangement period length W11 along the second direction X, the arrangement period length of the light-emitting element groups 210 along the first direction Y is equal to the arrangement period length of the light-emitting element groups 210 along the second direction X. The arrangement period length W12 in the second direction X is the side length, which can divide the display area of ​​the display panel into pixel units 220 arranged along the first direction Y and the second direction X. The arrangement period length W21 of the pixel unit 220 along the first direction Y is equal to the arrangement period length W11 of the light-emitting element group 210 along the first direction Y, and the arrangement period length W22 of the pixel unit 220 along the second direction X is equal to the arrangement period length W12 of the light-emitting element group 210 along the second direction X. Optionally, if W11=W12=W21=W22, then the shape of the pixel unit 220 is square.

[0107] Combination Figures 3-5 As shown, pixel unit 220 includes a transparent area 221 and a non-transparent area 222; in the first display area AA1, the transparent area 221 of pixel unit 220 may include a first transparent area 10, and the non-transparent area 222 of pixel unit 220 may include a shift register circuit VSR and / or a pixel circuit PL1; in the second display area AA2, the transparent area 221 of pixel unit 220 may include a second transparent area 20, and the non-transparent area 222 of pixel unit 220 may include a pixel circuit PL1.

[0108] It is understood that this application does not limit the specific division area of ​​the pixel unit 220. As long as the arrangement period length W11 of the light-emitting element group 210 along the first direction Y and the arrangement period length W12 along the second direction X are used as the side lengths, the pixel unit 220 arranged in the first direction Y and the second direction X can be arbitrarily divided within the display area of ​​the display panel. For ease of understanding, combined with Figures 3-5As shown, the division area of ​​pixel unit 220 can be selected such that in the first display area AA1, the transparent area 221 of pixel unit 220 includes the first transparent area 10; in the second display area AA2, the transparent area 221 of pixel unit 220 includes the second transparent area 20; and in the first display area AA1 and the second display area AA2, the non-transparent area 222 of pixel unit 220 includes a circuit area P1 and a wiring area P2. Circuit area P1 is used to set circuit structures, such as shift register circuits and / or pixel circuits, and wiring area P2 is used to set metal wiring. Wiring area P2 extends along the first direction Y, and circuit area P1 extends along the second direction X. Because the metal wiring of wiring area P2 is electrically connected to the circuit structure of circuit area P1, circuit area P1 and wiring area P2 overlap. The first direction Y and the second direction X are both parallel to the plane where the display panel is located, and the second direction X intersects the first direction Y.

[0109] It should be noted that, Figures 3-4 For ease of annotation, a rectangle outlines the approximate areas of the shift register circuit VSR and the pixel circuit PL1. However, in reality, the circuit diagrams of VSR and PL1 are irregular. Furthermore, VSR and PL1 are electrically connected to the metal traces transmitting signals to them. Therefore, it can be understood that there is no clear boundary between circuit area P1 and trace area P2; they are electrically connected in the overlapping area. Similar situations in other figures of this application will not be repeated.

[0110] Further optional, combined Figures 3-5 As shown, some pixel units 220 in the first display area AA1 (such as the second pixel unit on the left side along the second direction X) may include two sets of pixel circuit groups 110, that is, the pixel circuit groups 110 in the first display area AA1 are arranged relatively densely. Among these pixel units 220, one set of pixel circuit groups 110 is electrically connected to the light-emitting element group 210 corresponding to its own pixel unit 220, and the other set of pixel circuit groups 110 can be electrically connected to the light-emitting element group 210 corresponding to the adjacent pixel unit 220, which includes the shift register circuit VSR. In the second display area AA2, a pixel unit 220 may include a set of pixel circuit groups 110, that is, the pixel circuit groups 110 in the second display area AA2 are arranged relatively sparsely. This set of pixel circuit groups 110 can be electrically connected to the light-emitting element group 210 corresponding to its own pixel unit 220.

[0111] In the first display area AA1, which also includes pixel circuit PL1, and along the first direction Y, where a portion of the first transparent area 10 overlaps with pixel circuit PL1, another optional feature is to combine... Figure 5 and Figure 6 As shown, Figure 6This illustration shows a partial layout diagram of the driving circuit layer 100 and the light-shielding layer BM in another display panel provided in this application embodiment. It can be seen that the second display area AA2 may further include a redundant pixel circuit PL2, i.e., a redundant pixel circuit PL2 is added to the second display area AA2. The redundant pixel circuit PL2 may have the same circuit structure as the pixel circuit PL1, but the redundant pixel circuit PL2 is not electrically connected to the light-emitting element 201. Therefore, the shift register circuit VSR and pixel circuit PL1 in the first display area AA1, and the pixel circuit PL1 and redundant pixel circuit PL2 in the second display area AA2, can move along the path of the first... The two directions X are arranged in parallel, with the first direction Y and the second direction X both parallel to the plane of the display panel, and the second direction X intersecting the first direction Y. This not only helps the first transparent area 10 of the first display area AA1 and the second transparent area 20 of the second display area AA2 to be arranged in the same direction X, thus reducing the area difference between the first transparent area 10 of the first display area AA1 and the second transparent area 20 of the second display area AA2, but also makes the circuit density of the first display area AA1 and the second display area AA2 more consistent, which can further improve the uniformity of the transmittance and reflectance of the display panel, and thus further improve the display effect.

[0112] It is understandable that the redundant pixel circuit PL2 can have the same circuit structure as the pixel circuit PL1. Therefore, when the pixel circuit PL1 in the second display area AA2 of the display panel fails, the faulty pixel circuit PL1 can be disconnected from the corresponding light-emitting element 201, while the adjacent redundant pixel circuit PL2 can be electrically connected to the corresponding light-emitting element 201, thereby achieving repair.

[0113] It is also understandable that Figure 6 In the diagram, for ease of labeling, a rectangle is used to outline the approximate area of ​​the redundant pixel circuit PL2. However, in reality, the redundant pixel circuit PL2 is similar to the pixel circuit PL1, and its circuit diagram is also irregular. Furthermore, the redundant pixel circuit PL2 may also be electrically connected to the metal traces that transmit signals to it.

[0114] Based on the addition of redundant pixel circuit PL2 to the second display area AA2, further optional features include, for example... Figure 6As shown, the arrangement density of pixel circuit PL1 in the first display area AA1 can be the same as the arrangement density of pixel circuit PL1 and redundant pixel circuit PL2 in the second display area AA2. Optionally, the arrangement spacing of pixel circuit PL1 in the first display area AA1 can be the same as the arrangement spacing of pixel circuit PL1 and redundant pixel circuit PL2 in the second display area AA2. For example, some pixel units 220 in the first display area AA1 may include two sets of pixel circuit groups 110, that is, the pixel circuit groups 110 in the first display area AA1 are arranged relatively densely. Among these pixel units 220, one set of pixel circuit groups 110 is electrically connected to the light-emitting element group 210 corresponding to its own pixel unit 220, and the other set of pixel circuit groups 110 can be electrically connected to the light-emitting element group 210 corresponding to the adjacent pixel unit 220, which includes a shift register circuit VSR. In the second display area AA2, a pixel unit 220 may include a set of pixel circuit groups 110 and a set of redundant pixel circuit groups 120. The number of redundant pixel circuits PL2 included in the redundant pixel circuit group 120 and the number of pixel circuits PL1 included in the pixel circuit group 110 can be the same, and the circuit structure of the redundant pixel circuits PL2 and the pixel circuits PL1 can be the same. In this way, the circuit density of the first display area AA1 and the second display area AA2 tends to be consistent, which can further improve the uniformity of the transmittance and reflectance of the display panel, and thus further improve the display effect.

[0115] As is known from the foregoing, such as Figure 3 , Figure 4 as well as Figure 6 As shown, multiple pixel circuits PL1 are arranged in a row along the second direction X, and multiple rows of pixel circuits PL1 are arranged along the first direction Y. The first direction Y and the second direction X are both parallel to the plane where the display panel is located, and the second direction X intersects the first direction Y. Therefore, the shift register circuit VSR can be arranged in the same row as the row of pixel circuits PL1, that is, the shift register circuit VSR can be located in the circuit area P1 of the row of pixel unit 220 along with the row of pixel circuits PL1.

[0116] Figure 7 and Figure 8 This application provides two schematic diagrams illustrating the arrangement of a row of pixel units 220 in display panels, as shown in the embodiments of this application. Figure 7 and Figure 8 As shown, optionally, in some embodiments of this application, when the shift register circuit VSR is arranged in the same row as the row pixel circuit PL1, the shift register circuit VSR may be located on at least one side of the row pixel circuit PL1 along the second direction X.

[0117] It should be noted that the shift register circuit VSR includes a scanning circuit SCAN and / or an illumination control circuit EMIT. Optional, such as Figure 7As shown, the scanning circuit SCAN can be located on one side of the pixel circuit PL1 in a row along the second direction X, in which case the scanning circuit SCAN drives the pixel circuit PL1 in the same row on one side only; similarly, the light emission control circuit EMIT can be located on one side of the pixel circuit PL1 in a row along the second direction X, in which case the light emission control circuit EMIT drives the pixel circuit PL1 in the same row on one side only. Another option is... Figure 8 As shown, the scanning circuit SCAN can be located on both sides of the pixel circuit PL1 in a row along the second direction X, so the scanning circuit SCAN drives the pixel circuit PL1 in the same row on both sides; similarly, the light emission control circuit EMIT can be located on both sides of the pixel circuit PL1 in a row along the second direction X, so the light emission control circuit EMIT drives the pixel circuit PL1 in the same row on both sides.

[0118] Figure 9 This illustration shows a schematic diagram of the arrangement of a row of pixel units 220 in a display panel according to another embodiment of this application. Figure 9 As shown, alternatively, in some embodiments of this application, when the shift register circuit VSR is arranged in the same row as the row pixel circuit PL1, the shift register circuit VSR can also be located between two pixel circuits PL1 in the row pixel circuit PL1. That is, the two opposite sides of the row pixel unit 220 along the second direction X are pixel circuits PL1, and the shift register circuit VSR is located inside the row pixel unit 220. With this configuration, the shift register circuit VSR is relatively far from the bezel area of ​​the display panel. Therefore, when the bezel area of ​​the display panel is affected by moisture, the path for moisture intrusion into the shift register circuit VSR is relatively long, making it less likely to affect the shift register circuit VSR. Although the row pixel unit 220 The outermost pixel circuit PL1 along the second direction X may also be affected by moisture intrusion. However, the pixel circuit is an analog circuit, while the shift register circuit has 0 / 1 control logic. That is, the pixel circuit is less susceptible to moisture intrusion than the shift register circuit. Furthermore, if the cascaded shift register circuit is affected by moisture intrusion, it will affect the display of the entire display panel. However, if one or a column of pixel circuits at the edge of the display panel is affected by moisture intrusion, it will only affect the local brightness of the display panel. Therefore, by embedding the shift register circuit VSR inside the row of pixel units 220, so that the outermost pixel circuit PL1 of the row of pixel units 220 along the second direction X, the display panel can be made less susceptible to moisture intrusion.

[0119] Based on the aforementioned information, combined with Figures 3-6As shown, both the first display area AA1 and the second display area AA2 of the display panel include pixel units 220 and light-emitting element groups 210. The pixel units 220 and light-emitting element groups 210 are arranged in an array along the first direction Y and the second direction X. The pixel units 220 and the light-emitting element groups 210 are correspondingly arranged. The arrangement period length of the pixel units 220 along a direction parallel to the plane of the display panel is equal to the arrangement period length of the light-emitting element groups 210 along the same direction. By selecting the division area of ​​the pixel units 220, the pixel units 220 in the first display area AA1 and the second display area AA2 can be arranged in a way that allows for a more efficient and coordinated arrangement of the pixel units 220 in the first display area AA1 and the light-emitting element groups 210. Each pixel unit 220 in AA2 includes a transparent area 221 and a non-transparent area 222. The transparent area 221 of the pixel unit 220 in the first display area AA1 includes a first transparent area 10, and the transparent area 221 of the pixel unit 220 in the second display area AA2 includes a second transparent area 20. Furthermore, the non-transparent areas 222 of the pixel unit 220 in the first display area AA1 and the pixel unit 220 in the second display area AA2 both include a circuit area P1 for setting up a circuit structure and a trace area P2 for setting up metal traces. Therefore, optionally, in some embodiments of this application, combined with... Figures 3-6 As shown, the relative positions of the transparent areas 221 and the opaque areas 222 of the pixel unit 220 in the first display area AA1 and the second display area AA2 can be set to be the same. That is, the relative positional relationship of the transparent areas 221 and the opaque areas 222 of the pixel unit 220 in the first display area AA1 is the same as that of the pixel unit 220 in the second display area AA2.

[0120] It is understandable that because the first display area AA1 is equipped with a shift register circuit VSR, the space occupied by the shift register circuit VSR and the pixel circuit PL1 in the first display area AA1 is usually compressed. In order to transmit signals to the densely arranged shift register circuit VSR and pixel circuit PL1 in the first display area AA1, the metal traces in the first display area AA1 need to be densely arranged, and the proportion of transparent areas in the first display area AA1 needs to be reduced. For example, only a few small transparent areas can be set in the first display area AA1, resulting in obvious metal lines that are visible to the naked eye. However, in this application, the relative positions of the transparent areas 221 and the non-transparent areas 222 of the pixel unit 220 in the first display area AA1 and the second display area AA2 are the same. That is, multiple small transparent areas in the first display area AA1 can be merged into a larger transparent area, and the metal traces extending along the first direction Y are set at the intervals of the merged larger transparent area, thereby reducing the visual difference between the first display area AA1 and the second display area AA2, which can further improve the uniformity of the transmittance and reflectance of the display panel, and thus further improve the display effect.

[0121] Further optional, combined Figures 3-6 As shown, in the first display area AA1 and the second display area AA2, the patterns formed by the transparent areas 221 and the non-transparent areas 221 of the pixel units 220 are the same. That is, not only are the relative positions of the transparent areas 221 and the non-transparent areas 222 of the pixel units 220 in the first display area AA1 the same as those in the second display area AA2, but also the areas of the transparent areas 221 and the non-transparent areas 222 of the pixel units 220 in the first display area AA1 and the second display area AA2 are the same. This further reduces the visual difference between the first display area AA1 and the second display area AA2, further improves the uniformity of the transmittance and reflectance of the display panel, and further enhances the display effect.

[0122] Combination Figures 3-6 As shown, the display panel includes a light-shielding layer BM, which covers the non-transparent area 222 of the pixel unit 220 and exposes the transparent area 221 and the light-emitting element group 210 of the pixel unit 220. Specifically, the first opening K1 in the light-shielding layer BM exposes the transparent area 221 of the pixel unit 220, and the second opening K2 in the light-shielding layer BM exposes the light-emitting element 201 in the light-emitting element group 210. That is, the transparent area 221 of the pixel unit 220 corresponds to the first opening K1 of the light-shielding layer BM, and the non-transparent area 222 of the pixel unit 220 is correspondingly provided with the light-shielding layer BM. In this way, the light-shielding layer BM can be divided into multiple light-shielding units BM0, that is, the light-shielding layer BM includes multiple light-shielding units BM0. The light-shielding units BM0 and the pixel unit 220 are correspondingly provided. The light-shielding units BM0 are also arranged in an array along the first direction Y and the second direction X. The light-shielding unit BM0 has a first opening K1, which exposes the transparent area 221 of the pixel unit 220.

[0123] Accordingly, considering that the non-transparent area 222 of the pixel unit 220 includes a circuit area P1 and a wiring area P2, the wiring area P2 extends along the first direction Y, the circuit area P1 extends along the second direction X, and the circuit area P1 and the wiring area P2 overlap, the light-shielding unit BM includes an overlapping first light-shielding area BM1 and a second light-shielding area BM2. The first light-shielding area BM1 covers the circuit area P1, and the second light-shielding area BM2 covers the wiring area P2, so that the light-shielding unit BM can cover the non-transparent area 222 of the pixel unit 220.

[0124] Therefore, it can be understood that, without considering the second opening K2 of the exposed light-emitting element 201 in the light-shielding layer BM, the pattern of the light-shielding unit BM0 in the light-shielding layer BM can be regarded as the pattern composed of the transparent area 221 and the non-transparent area 221 of the pixel unit 220. Then, when the patterns composed of the transparent area 221 and the non-transparent area 221 of the pixel unit 220 are the same in the first display area AA1 and the second display area AA2, that is, the pattern of the light-shielding unit BM0 in the first display area AA1 is the same as the pattern of the light-shielding unit BM0 in the second display area AA2. At this time, the arrangement period length of the pixel unit 220 along the first direction Y is also equal to the arrangement period length of the first opening K1 in the light-shielding layer BM along the first direction Y, and the arrangement period length of the pixel unit 220 along the second direction X is equal to the arrangement period length of the first opening K1 in the light-shielding layer BM along the second direction X.

[0125] It is also understandable that even if the circuit density of the portion of a row of pixel units 220 located in the first display area AA1 (including the shift register circuit VSR and the densely arranged pixel circuit group 110) is different from that of the portion located in the second display area AA2 (including the sparsely arranged pixel circuit group 110 or the pixel circuit group 110 and the redundant pixel circuit group 120 arranged alternately), and the number and spacing of the traces extending along the first direction Y in the trace area P2 of the first display area AA1 and the second display area AA2 are different, because the light-shielding units BM0 are arranged in an array along the first direction Y and the second direction X, and the pattern of the light-shielding units BM0 in the first display area AA1 and the light-shielding units BM0 in the second display area AA2 is the same, the visual difference between the first display area AA1 and the second display area AA2 can be reduced or even eliminated, thereby improving the uniformity of the transmittance and reflectance of the display panel and thus improving the display effect.

[0126] It should be noted that, in order to ensure that the relative positions of the transparent areas 221 and the non-transparent areas 222 of the pixel unit 220 are the same in the first display area AA1 and the second display area AA2, and to further ensure that the patterns composed of the transparent areas 221 and the non-transparent areas 221 of the pixel unit 220 are the same in the first display area AA1 and the second display area AA2, the size of a set of pixel circuit groups 110 is appropriately compressed, and the width of the wiring area P2 between two adjacent transparent areas 221 is appropriately widened. This effectively sacrifices the proportion of the transparent area 221 in the second display area AA2, thereby making the pixel unit 220 more visible in the display area. The entire display area of ​​the display panel can be arranged in the same pattern along the first direction Y and the second direction X, further reducing or even eliminating the visual difference between the first display area AA1 and the second display area AA2, further improving the uniformity of the transmittance and reflectance of the display panel, and thus further improving the display effect; and, within the first display area AA1 of the display panel, the densely arranged shift register circuit VSR and pixel circuit group 110 can be reasonably accommodated, and the metal traces that transmit signals to the shift register circuit VSR and pixel circuit group 110 in the first display area AA1 can also be reasonably accommodated within the trace area P2 in the first display area AA1.

[0127] Combination Figures 3-6 As shown, multiple pixel units 220 are arranged in a row along the second direction X. The circuit area P1 of each pixel unit 220 in a row is arranged along the second direction X. The multiple rows of pixel units 220 are arranged along the first direction Y. That is, based on the array arrangement of pixel units 220 along the first direction Y and the second direction X, and the circuit area P1 of each pixel unit 220 in a row is arranged along the second direction X, then the transparent area 221 of each pixel unit 220 in a row can also be arranged along the second direction X. The area between the two transparent areas 221 is the wiring area P2. Optionally, along the direction perpendicular to the plane of the display panel, the circuit area P1 in the pixel unit 220 overlaps with the corresponding light-emitting element group 210. With this configuration, the connection between the light-emitting element 201 in the light-emitting element group 210 and the pixel circuit PL1 located in the circuit area P1 of the pixel unit 220 can still be located in the non-transparent area 222 of the pixel unit 220, and not in the transparent area 221 of the pixel unit 220, so as not to lose the transmittance of the transparent area 221 of the pixel unit 220.

[0128] For example, combining Figures 3-6 As shown, some pixel units 220 in the first display area AA1 (such as...) Figures 3-6 The circuit region P1 of the first pixel unit on the left side along the second direction X includes a shift register circuit VSR, and other pixel units 220 (such as...) Figures 3-6The circuit area P1 of the second pixel unit (located to the left of the second pixel unit along the second direction X) includes two sets of pixel circuit groups 110. Thus, in the first display area AA1, along the direction perpendicular to the plane of the display panel, in the pixel unit 220 including the shift register circuit VSR, the shift register circuit VSR overlaps with the corresponding light-emitting element group 210. In the pixel unit 220 including the two sets of pixel circuit groups 110, the two sets of pixel circuit groups 110 overlap with the corresponding light-emitting element group 210. The circuit area P1 of the pixel unit 220 in the second display area AA2 may include only one set of pixel circuit groups 110 (e.g., ...). Figures 3-4 As shown), in the second display area AA2, along the direction perpendicular to the plane of the display panel, a group of pixel circuits 110 in each pixel unit 220 overlaps with the corresponding light-emitting element group 210; the circuit area P1 of the pixel unit 220 in the second display area AA2 may also include a group of pixel circuits 110 and a group of redundant pixel circuits 120 (as shown). Figure 6 As shown), in the second display area AA2, along the direction perpendicular to the plane where the display panel is located, a group of pixel circuits 110 and a group of redundant pixel circuits 120 in each pixel unit 220 overlap with the corresponding light-emitting element group 210.

[0129] Regarding the arrangement of the trace area P2 and the transparent area 221 in the non-transparent area 222 of pixel unit 220, it is optional, such as... Figures 7-10 As shown, Figure 10 This illustration shows a schematic diagram of the arrangement of a row of pixel units 220 in a display panel according to another embodiment of this application. It can be seen that in the pixel unit 220, the trace area P2 of the non-transparent area 222 can be located on one side of the transparent area 221 along the second direction X; for example, as... Figures 7-9 As shown, in pixel unit 220, the trace area P2 is located to the left of the transparent area 221 along the second direction X; for example, as Figure 10 As shown, in pixel unit 220, the trace area P2 can also be located on the right side of the transparent area 221 along the second direction X.

[0130] It is understandable that, such as Figures 7-10As shown, the routing area P2 in pixel unit 220 is located on one side of the transparent area 221 along the second direction X. The routing area P2 includes a trace extending along the first direction Y. Therefore, the trace in the routing area P2 of a pixel unit 220 can be electrically connected only to the circuit structure (such as a shift register circuit VSR or pixel circuit PL) set in the circuit area P1 of that pixel unit 220. In this case, the circuit structures (such as shift register circuit VSR or pixel circuit PL) set in the circuit area P1 of each pixel unit 220 are all connected from the side of the second direction X to the trace extending along the first direction Y. However, in practical applications, the trace in the routing area P2 of a pixel unit 220 may not only be electrically connected to the circuit structure set in the circuit area P1 of that pixel unit 220, but may also be electrically connected to the circuit structure set in the circuit area P1 of adjacent pixel units 220.

[0131] For example, combining Figures 3-4 As shown, some pixel units 220 in the first display area AA1 (such as...) Figures 3-4 The circuit region P1 of the first pixel unit on the left side along the second direction X includes a shift register circuit VSR, and other pixel units 220 (such as...) Figures 3-4 The circuit area P1 of the second pixel unit (located on the left side along the second direction X) includes two sets of pixel circuit groups 110, while the circuit area P1 of the pixel unit 220 in the second display area AA2 may only include one set of pixel circuit groups 110. It is understood that in the second display area AA2, each set of pixel circuit groups 110 in each pixel unit 220 may only be electrically connected to the traces in its trace area P2 along the second direction X. However, in the first display area AA1, because the number of traces required for the shift register circuit VSR and the number of traces required for the two sets of pixel circuit groups 110 are relatively large, therefore, the bit... The traces connected to the shift register circuit VSR within a pixel unit 220 may not only be located in the trace area P2 on one side along the second direction X, but may also be located in the trace areas P2 on opposite sides along the second direction X, i.e., within the trace areas P2 of two pixel units 220. Similarly, the traces connected to the two sets of pixel circuit groups 110 within a pixel unit 220 may not only be located in the trace area P2 on one side along the second direction X, but may also be located in the trace areas P2 on opposite sides along the second direction X, i.e., within the trace areas P2 of two pixel units 220. Of course, if the width of the trace area P2 within the pixel unit 220 along the second direction X is sufficient, the traces in the trace area P2 of each pixel unit 220 may only be electrically connected to the circuit structure in the circuit area P1 of its own pixel unit.

[0132] Another option, such as Figure 11 As shown, Figure 11The illustration shows a schematic diagram of the arrangement of a row of pixel units 220 in a display panel according to another embodiment of this application. It can be seen that in pixel units 220, the trace area P2 of the non-transparent area 222 can also be located on both sides of the transparent area 221 along the second direction X. In this case, the trace in the trace area P2 of a pixel unit 220 can be electrically connected only to the circuit structure (such as the shift register circuit VSR or the pixel circuit PL) provided in the circuit area P1 of the pixel unit 220. Then, the circuit structure (such as the shift register circuit VSR or the pixel circuit PL) provided in the circuit area P1 of the pixel unit 220 can be connected from both sides of the second direction X to the traces extending along the first direction Y. This makes it more convenient for the circuit structure provided in the circuit area P1 of the pixel unit 220 to connect to the traces extending along the first direction Y.

[0133] For example, refer to Figure 6 As shown, some pixel units 220 in the first display area AA1 (such as...) Figure 6 The circuit region P1 of the first pixel unit on the left side along the second direction X includes a shift register circuit VSR, and other pixel units 220 (such as...) Figure 6 The circuit area P1 of the second pixel unit (located on the left side along the second direction X) in the first display area AA1 includes two sets of pixel circuit groups 110. The circuit area P1 of the pixel unit 220 in the second display area AA2 may include a set of pixel circuit groups 110 and a set of redundant pixel circuit groups 120. In the first display area AA1, the traces connected to the shift register circuit VSR located in a pixel unit 220 can be respectively set in the trace areas P2 on both sides opposite to it along the second direction X. The traces connected to the two sets of pixel circuit groups 110 located in a pixel unit 220 can also be respectively set in the trace areas P2 on both sides opposite to it along the second direction X. In a pixel unit 220 of the second display area AA2, the traces connected to a set of pixel circuit groups 110 can be set in the trace area P2 on one side along the second direction X, and the traces connected to a set of redundant pixel circuit groups 120 can be set in the trace area P2 on the other side along the second direction X.

[0134] It is understandable that if the routing area P2 in pixel unit 220 is located on opposite sides of the transparent area 221 along the second direction X, then the routing areas P2 of two adjacent pixel units 220 along the second direction X can be merged into a relatively wide routing area along the second direction X. This is similar to the case where the routing area P2 in pixel unit 220 is located on one side of the transparent area 221 along the second direction X. That is, the routing in the routing area P2 of a pixel unit 220 can be electrically connected only to the circuit structure (such as the shift register circuit VSR or pixel circuit PL) set in the circuit area P1 of the pixel unit 220. Alternatively, the routing in the routing area P2 of a pixel unit 220 can also be electrically connected not only to the circuit structure set in the circuit area P1 of the pixel unit 220, but also to the circuit structure set in the circuit area P1 of the adjacent pixel unit 220.

[0135] Another option, such as Figure 12 As shown, Figure 12 This illustration shows a schematic diagram of the arrangement of a row of pixel units 220 in a display panel according to another embodiment of this application. It can be seen that in pixel units 220, the trace area P2 of the non-transparent area 222 can also be located at the middle position of the transparent area 221 along the second direction X, that is, the transparent area 221 is located on opposite sides of the trace area P2 along the second direction X. In this case, the traces in the trace area P2 of a pixel unit 220 can be electrically connected only to the circuit structure (such as the shift register circuit VSR or pixel circuit PL) in the circuit area P1 of the pixel unit 220. Furthermore, since the traces in the trace area P2 of a pixel unit 220 are connected to the circuit structure from the middle position of the circuit area P1 of the pixel unit 220, it is also relatively convenient for the circuit structure provided in the circuit area P1 of the pixel unit 220 to connect to the traces extending along the first direction Y. In addition, since the trace area P2 in the pixel unit 220 is located in the middle of the transparent area 221 along the second direction X, the transparent areas 221 of two adjacent pixel units 220 can be connected to form a relatively large transparent area. Therefore, this will not affect the proportion of the transparent area 221 in the pixel unit 220.

[0136] It is understandable that regardless of whether the trace area P2 in pixel unit 220 is located on one side of the transparent area 221 along the second direction X, on opposite sides along the second direction X, or in the middle along the second direction X, for a row of pixel units 220, the circuit areas P1 of each pixel unit 220 in the row of pixel units 220 are arranged along the second direction X, the transparent areas 221 in the row of pixel units 220 are arranged along the second direction X, and the transparent areas 221 and trace areas P2 in the row of pixel units 220 are arranged alternately along the second direction X. In other words, a row of pixel units 220... The area between two adjacent transparent areas 221 along the second direction X in row 20 is the wiring area P2. Thus, according to actual needs, the pixel circuit PL1 and the shift register circuit VSR can be set in the circuit area P1 of a row of pixel units 220. The wiring area P2 of a row of pixel units 220 can be set according to the arrangement of the circuit structure in the circuit area P1, so as to facilitate electrical connection with the circuit structure in the circuit area P1. At the same time, the transparent areas 221 of a row of pixel units 220 are arranged periodically along the second direction X, which can improve the uniformity of the transmittance and reflectance of the display panel.

[0137] Another option, such as Figure 13 As shown, Figure 13 A schematic diagram of the layout structure of a pixel unit 220 located in the driving circuit layer 100 is shown. It can be seen that in the pixel unit 200, the circuit area P1 of the non-transparent area 222 includes a first sub-circuit area P11 and a second sub-circuit area P12 arranged along the second direction X. The trace area P2 of the non-transparent area 222 includes a first sub-trace area P21 and a second sub-trace area P22 arranged at intervals along the second direction X. The first sub-circuit area P11 and the first sub-trace area P21 overlap, and the second sub-circuit area P12 and the second sub-trace area P22 overlap. That is, the circuit structure set in the first sub-circuit area P11 is electrically connected to the trace set in the first sub-trace area P21, and the circuit structure set in the second sub-circuit area P12 is electrically connected to the trace set in the second sub-trace area P22.

[0138] For example, combining Figure 6 As shown, some pixel units 220 in the first display area AA1 (such as...) Figure 6 The circuit region P1 of the first pixel unit on the left side along the second direction X includes a shift register circuit VSR, and other pixel units 220 (such as...) Figure 6The circuit area P1 of the second pixel unit (located to the left of the second pixel unit along the second direction X) includes two sets of pixel circuit groups 110. The circuit area P1 of the pixel unit 220 in the second display area AA2 may include one set of pixel circuit groups 110 and one set of redundant pixel circuit groups 120. In the first display area AA1, the shift register circuit VSR located in a pixel unit 220 can be divided into two parts and electrically connected to the traces set in the first sub-trace area P21 and the second sub-trace area P22 of the pixel unit 220, respectively. Of the two sets of pixel circuit groups 110 located in a pixel unit 220, one set of pixel circuit groups 110 is electrically connected to the traces set in the first sub-trace area P21 of the pixel unit 220, and the other set of pixel circuit groups 110 is connected to the traces set in the second sub-trace area P22 of the pixel unit 220. Electrical connection; In the second display area AA2, within a pixel unit 220, a group of pixel circuit groups 110 are electrically connected to the traces set in the first sub-trace area P21 within the pixel unit 220, and a group of redundant pixel circuit groups 120 are electrically connected to the traces set in the second sub-trace area P22 within the pixel unit 220; With this configuration, whether it is the two groups of pixel circuit groups 110 within a pixel unit 220 in the first display area AA1, or the group of pixel circuit groups 110 within a pixel unit 220 in the second display area AA2, they are all connected to the traces extending along the first direction Y from the same side of the second direction X. This ensures that the data signal lines electrically connected to the pixel circuits PL1 electrically connected to the same color light-emitting elements in each pixel circuit group 110 have the same resistance and capacitance characteristics, which can further improve the display uniformity of the display panel.

[0139] The above lists several arrangements of the trace area P2 and the transparent area 221 in the non-transparent area 221 of pixel unit 220. It can be understood that, combined with Figure 3 , Figure 5 and Figure 14 As shown, Figure 14 The illustration shows a schematic diagram of the arrangement of a row of light-shielding units BM0 in a display panel according to an embodiment of this application. It can be seen that the circuit area P1 in the row of pixel units 220 is arranged along the second direction X, and the wiring area P2 and the transparent area 211 in the row of pixel units 220 are arranged alternately and periodically along the second direction. Correspondingly, in the light-shielding layer BM, the first light-shielding area BM1 covering the circuit area P1 in the row of light-shielding units BM0 is arranged along the second direction X, and the second light-shielding area BM2 covering the wiring area P2 and the first opening K1 of the exposed transparent area 211 in the row of light-shielding units BM0 are arranged alternately and periodically along the second direction X.

[0140] Combination Figure 3 , Figure 5 and Figure 14As shown, in order to set the pattern composed of the transparent area 221 and the non-transparent area 221 of the pixel unit 220 in the first display area AA1 and the second display area AA2 to be the same, the width H2 of the second light-blocking area BM2 between two adjacent transparent areas 221 along the second direction X in the second display area AA can be set to be equal to the width H1 of the second light-blocking area BM2 between two adjacent transparent areas 221 along the second direction X in the first display area AA1. That is, the width H2 of the trace area P2 between two adjacent transparent areas 221 along the second direction X in the second display area AA is equal to the width H1 of the trace area P2 between two adjacent transparent areas 221 along the second direction X in the first display area AA1.

[0141] However, due to the large number of traces extending along the first direction Y that need to be electrically connected to the shift register circuit VSR and the densely arranged pixel circuit group 110 in the first display area AA1, for example, some pixel units 220 in the first display area AA1 (such as...) Figure 3 , Figure 5 and Figure 14 The circuit area P1 of the first pixel unit (located to the left of the second direction X) includes a shift register circuit VSR. The shift register circuit VSR needs to be electrically connected to the trigger signal line STV, the first level signal line CK, the first level signal line VGH, the second level signal line XCK, the second level signal line VGL, and the output signal line Out, which extend along the first direction Y. Figure 3 , Figure 5 and Figure 14 The circuit area P1 of the second pixel unit (located to the left of the second pixel unit along the second direction X) includes two sets of pixel circuit groups 110. The two sets of pixel circuit groups 110 need to be electrically connected, for example, six data signal lines data extending along the first direction Y. However, the circuit area P1 of the pixel unit 220 in the second display area AA2 may only include one set of pixel circuit groups 110. The set of pixel circuit groups 110 only needs to be electrically connected, for example, three data signal lines data extending along the first direction Y. Therefore, the arrangement density of the traces extending along the first direction Y in the trace area P2 of the second display area AA2 is less than the arrangement density of the traces extending along the first direction Y in the trace area P2 of the first display area AA1. That is, the arrangement of the traces extending along the first direction Y in the trace area P2 of the second display area AA2 is relatively sparse, while the arrangement of the traces extending along the first direction Y in the trace area P2 of the first display area AA1 is relatively dense.

[0142] As previously known, in order to ensure that the patterns composed of the transparent areas 221 and the non-transparent areas 221 of the pixel units 220 are identical in the first display area AA1 and the second display area AA2, this application actually appropriately compresses the size of a set of pixel circuit groups 110 and appropriately widens the width of the trace area P2 between two adjacent transparent areas 221. It is understood that, in conjunction with... Figure 3 , Figure 5 and Figure 14 As shown, apart from the one routing area P2 adjacent to the first display area AA1 and the second display area AA2, the other routing areas P2 in the second display area AA2 only need to be provided with a set of signal lines (such as three data signal lines) electrically connected to the pixel circuit group 110 extending along the first direction Y. The required width of the routing area P2 along the second direction X can be relatively narrow. However, the routing area P2 in the first display area AA1 needs to be provided with a larger number of signal lines extending along the first direction Y, and the required width of the routing area P2 along the second direction X is relatively wider. Therefore, this application appropriately widens the width of the routing area P2 in the second display area AA2 along the second direction X, so that the width H2 of the routing area P2 in the second display area AA2 along the second direction X is equal to that of the first display area AA1. The width H1 of the trace area P2 in AA1 along the second direction X is equal to the width H2 of the second light-shielding area BM2 in the second display area AA2 along the second direction X. This makes the pattern composed of the transparent area 221 and the non-transparent area 221 of the pixel unit 220 in the first display area AA1 and the second display area AA2 the same, reducing or even eliminating the visual difference between the first display area AA1 and the second display area AA2, improving the uniformity of the transmittance and reflectance of the display panel, and thus improving the display effect. At the same time, it also makes the arrangement density of the traces in the trace area P2 of the second display area AA2 less than the arrangement density of the traces in the trace area P2 of the first display area AA1.

[0143] It should be noted that the routing density in the routing area P2 of the second display area AA2 is less than that in the routing area P2 of the first display area AA1. Specifically, when the width of each routing area P2 along the second direction X is the same, the number of routing lines in the routing area P2 of the second display area AA2 is less than that in the routing area P2 of the first display area AA1. For example, when the width of each routing area P2 along the second direction X is the same, the routing area P2 of the second display area AA2 only needs to provide the three data signal lines required for electrical connection of a set of pixel circuit group 110, while some routing areas P2 of the second display area AA1 (such as...) Figure 3 , Figure 5 and Figure 14The first trace area on the left side along the second direction X) sets up the four signal lines required for the shift register circuit VSR: trigger signal line STV, first level signal line CK, first level signal line VGH, and second level signal line XCK. Other trace areas P2 in the second display area AA1 (such as...) Figure 3 , Figure 5 and Figure 14 The second trace area on the left side of the second direction X is set up with the second level signal line VGL, the output signal line Out, and the three data signal lines data required for the electrical connection of the shift register circuit VSR, as well as a set of pixel circuit group 110. There are a total of five signal lines. Even so, some circuit structures of the first display area AA1 (such as...) Figure 3 , Figure 5 and Figure 14 The traces (e.g., three data signal lines) required for electrical connections of the second pixel unit 220 on the left side of the second direction X along the second direction X still need to be connected via the adjacent trace area P2.

[0144] The routing density in the routing area P2 of the second display area AA2 is less than that in the routing area P2 of the first display area AA1. Specifically, when the width of each routing area P2 along the second direction X is the same, the spacing between two adjacent routing lines in the routing area P2 of the second display area AA2 is greater than the spacing between two adjacent routing lines in the routing area P2 of the first display area AA1. It can be understood that when the width of each routing area P2 along the second direction X is the same, if the number of routing lines in the routing area P2 of the second display area AA2 is less than the number of routing lines in the routing area P2 of the first display area AA1, then the spacing between two adjacent routing lines in the routing area P2 of the second display area AA2 can be greater than the spacing between two adjacent routing lines in the routing area P2 of the first display area AA1.

[0145] The routing density in the routing area P2 of the second display area AA2 is generally less than that in the routing area P2 of the first display area AA1. Specifically, when the width of each routing area P2 along the second direction X is the same, the distance between the outermost routing line in the routing area P2 of the second display area AA2 along the second direction X and the boundary of the second light-shielding area BM2 is greater than the distance between the outermost routing line in the routing area P2 of the first display area AA1 along the second direction X and the boundary of the second light-shielding area BM2. It can be understood that, when the width of each routing area P2 along the second direction X is the same, the number of routing lines in the routing area P2 of the second display area AA2 is less than the number of routing lines in the routing area P2 of the first display area AA1. Therefore, the distance between the outermost routing line in the routing area P2 of the second display area AA2 along the second direction X and the boundary of the second light-shielding area BM2 can be greater than the distance between the outermost routing line in the routing area P2 of the first display area AA1 along the second direction X and the boundary of the second light-shielding area BM2.

[0146] It should also be noted that, in combination Figure 3 , Figure 5 and Figure 14 As shown, although the wiring arrangement in the wiring area P2 adjacent to the first display area AA1 is also relatively dense, this is because some circuit structures in the first display area AA1 (such as...) Figure 3 , Figure 5 and Figure 14 The traces (e.g., three data signal lines) required for the electrical connection of a group of pixel circuits 110 in the second pixel unit 220 on the left side of the second direction X occupy part of the space of this trace area P2. Therefore, the trace settings in this trace area P2 cannot represent the trace settings in the trace area P2 of the second display area AA2. The trace settings in other trace areas P2 of the second display area AA2 can be represented by only setting the traces (e.g., three data signal lines) required for the electrical connection of a group of pixel circuits 110 in one pixel unit 110.

[0147] Regarding the arrangement of the circuit area P1 and the transparent area 221 in the non-transparent area 221 of pixel unit 220, it is optional, such as... Figures 7-12 As shown, in pixel unit 220, the circuit region P1 of the non-transparent region 222 can be located on one side of the transparent region 211 along the first direction Y; for example, as Figures 7-12 As shown, in pixel unit 220, circuit area P1 can be located above transparent area 211 along the first direction Y; it can be understood that in pixel unit 220, circuit area P1 can also be located below transparent area 211 along the first direction Y.

[0148] Another option, such as Figures 15-17 As shown, Figures 15-17 The diagram shows the arrangement of a row of pixel units 220 in three other display panels provided in the embodiments of this application. It can be seen that in the pixel unit 220, the circuit area P1 of the non-transparent area 222 can also be located in the middle position of the transparent area 211 along the first direction Y, that is, the transparent area 211 is located on both sides of the circuit area P1 along the first direction Y.

[0149] It is understandable that, such as Figures 15-17 As shown, in pixel unit 220, the arrangement of the circuit area P1 of the non-transparent area 221 and the transparent area 221 can be designed by combining the arrangement of the wiring area P2 of the non-transparent area 221 and the transparent area 221. Optionally, as... Figure 15 and Figure 16 As shown, in pixel unit 220, the wiring area P2 is located on one side of the transparent area 221 along the second direction X, and the circuit area P1 is located in the middle of the transparent area 221 along the first direction Y. Alternatively, as... Figure 17 As shown, in pixel unit 220, the trace area P2 is located in the middle of the transparent area 221 along the second direction X, and the circuit area P1 is located in the middle of the transparent area 221 along the first direction Y. At this time, it can be imagined that after the pixel units 220 in the display panel are arranged in an array along the first direction Y and the second direction X, there will be no whole row of circuit structure along the edge of the display panel along the first direction Y, and there will be no whole trace along the first direction Y along the edge of the display panel along the second direction X, thereby significantly reducing the risk of cutting loss at the edge of the display panel.

[0150] Regarding the arrangement of the circuit structure within the circuit region P1 of the pixel unit 220, considering that multiple pixel units 220 are arranged in a row along the second direction X, and the circuit region P1 of each pixel unit 220 in a row is arranged along the second direction X, while the multiple rows of pixel units 220 are arranged along the first direction Y, optionally, as follows: Figures 3-4 as well as Figure 6 As shown, the shift register circuit VSR and pixel circuit PL1 in the circuit area P1 of a row of pixel units 220 can be arranged along the second direction X; this arrangement facilitates the arrangement of the shift register circuit VSR and pixel circuit PL1 arranged in the same row.

[0151] Optional, combined Figure 5 As shown, the light-emitting element group 210 corresponding to the pixel unit 110 in the first display area AA1, which includes the shift register circuit VSR, may need to be connected by a connecting line R1 to the pixel circuit group 110 in the adjacent pixel unit 110.

[0152] Specifically, in combination Figures 3-5 as well as Figure 6As shown, in the second display area AA2, the circuit area P1 of the pixel unit 220 includes at least a pixel circuit group 110. The circuit area P1 of the pixel unit 220 in the second display area AA2 may include only one pixel circuit group 110, or it may include one pixel circuit group 110 and a redundant pixel circuit group 120. The pixel circuit group 110 is electrically connected to the corresponding light-emitting element group 210. The pixel unit 220 of the first display area AA1 includes a first pixel unit 220-1 and a second pixel unit 220-2. The first pixel unit 220-1 includes a shift register circuit VSR, and the second pixel unit 220-2 includes two groups of pixel circuit groups 110. In the second pixel unit 220-2, one group of pixel circuit groups 110 is electrically connected to the corresponding light-emitting element group 210, and the other group of pixel circuit groups 110 is electrically connected to the light-emitting element group 210 corresponding to the first pixel unit 220-1 through a connecting line R1.

[0153] Combination Figure 2 As shown, the display panel includes a substrate sub and a first metal layer (i.e., metal layer MMG), a second metal layer (i.e., metal layer M2), a third metal layer (i.e., metal layer M3), and a fourth metal layer (i.e., metal layer RE) stacked on one side of the substrate sub in a direction away from the substrate. Optionally, the third metal layer (i.e., metal layer M3) includes a first power supply voltage line PVDD, and the fourth metal layer (i.e., metal layer RE) includes a second power supply voltage line PVEE. The first power supply voltage line PVDD is used to provide a first power supply voltage, and the second power supply voltage line PVEE is used to provide a second power supply voltage. The first power supply voltage line PVDD is electrically connected to the pixel circuit group 110. Then, the second power supply voltage line PVEE is electrically connected to the light-emitting element group 210. At this time, the connecting line R1 can be located in the first metal layer (i.e., metal layer MG). That is, the light-emitting element 201 in the light-emitting element group 210 corresponding to the first pixel unit 220-1 is electrically connected to the pixel circuit PL1 of a group of pixel circuits 110 in the second pixel unit 220-2 through the connecting line R1 located in the first metal layer (i.e., metal layer MG). The pixel circuit PL1 is electrically connected to the first power supply voltage line PVDD located in the third metal layer (i.e., metal layer M3). The light-emitting element 201 is also electrically connected to the second power supply voltage line PVEE located in the fourth metal layer (i.e., metal layer RE).

[0154] Alternatively, the second metal layer (i.e., metal layer M2) includes a first power supply voltage line PVDD, and the fourth metal layer (i.e., metal layer RE) includes a second power supply voltage line PVEE. The first power supply voltage line PVDD is used to provide a first power supply voltage, and the second power supply voltage line PVEE is used to provide a second power supply voltage. The first power supply voltage line PVDD is electrically connected to the pixel circuit group 110, and the second power supply voltage line PVEE is electrically connected to the light-emitting element group 210. In this case, the connecting line R1 can also be located in the third metal layer (i.e., metal layer M3). That is, the light-emitting element 201 in the light-emitting element group 210 corresponding to the first pixel unit 220-1 is electrically connected to the pixel circuit PL1 of the pixel circuit group 110 in the second pixel unit 220-2 through the connecting line R1 located in the third metal layer (i.e., metal layer M3). The pixel circuit PL1 is electrically connected to the first power supply voltage line PVDD located in the second metal layer (i.e., metal layer M2), and the light-emitting element 201 is also electrically connected to the second power supply voltage line PVEE located in the fourth metal layer (i.e., metal layer RE).

[0155] Understandably, it is desirable for the metal layer on which the first power voltage line PVDD and the second power voltage line PVEE are located to be relatively thick, so that the resistance of the first power voltage line PVDD and the second power voltage line PVEE is relatively small, which helps to reduce the voltage drop of the first power voltage line PVDD and the second power voltage line PVEE and improve the display uniformity of the display panel. The above-mentioned placement of the connecting line R1 on the first metal layer (i.e., metal layer MG) or the third metal layer (i.e., metal layer M3), and different from the metal layer on which the first power voltage line PVDD and the second power voltage line PVEE are located, can avoid the connection line R1 being too thin when placed on the metal layer on which the first power voltage line PVDD and the second power voltage line PVEE are located, which would increase the resistance of the first power voltage line PVDD and the second power voltage line PVEE, and thus increase the voltage drop of the first power voltage line PVDD and the second power voltage line PVEE.

[0156] Furthermore, when the connecting line R1 is placed on the third metal layer (i.e., metal layer M3), the second metal layer (i.e., metal layer M2) includes the first power supply voltage line PVDD, and the fourth metal layer (i.e., metal layer RE) includes the second power supply voltage line PVEE. In this way, the second metal layer (i.e., metal layer M2) and the fourth metal layer (i.e., metal layer RE) sandwich the connecting line R1 located on the third metal layer (i.e., metal layer M3) from above and below, which can prevent the connecting line R1 from crossing other thin film transistors and causing accidental signal coupling that would affect the display effect.

[0157] The above only lists cases where the connecting line R1 is located in the first metal layer (i.e., metal layer MG) or the third metal layer (i.e., metal layer M3). However, this application does not limit which metal layer the connecting line R1 is specifically located in. Alternatively, the connecting line R1 can also be located in the fourth metal layer (i.e., metal layer RE), for example... Figure 5 As shown.

[0158] Combination Figures 3-5 as well as Figure 6 As shown, in the first display area AA1, the light-emitting element group 210 corresponding to the first pixel unit 220-1 is far from a group of pixel circuits 110 located in the adjacent second pixel unit 220-2, so the aforementioned connecting line R1 is required for electrical connection. It is understood that in the first display area AA1, the light-emitting element group 210 corresponding to the second pixel unit 220-2 and its other group of pixel circuits 110 may not completely overlap in the direction perpendicular to the plane of the display panel, so connecting line R2 is also required for electrical connection. That is, the light-emitting element group 210 corresponding to the second pixel unit 220-2 also needs to be electrically connected to its own group of pixel circuits 110 via connecting line R2. In this case, if connecting line R1 and connecting line R2 are located on the same metal layer, for example, ... Figure 5 As shown, both connecting lines R1 and R2 are located in the fourth metal layer (i.e., metal layer RE). Therefore, the positions of connecting lines R1 and R2 must be set to avoid mutual interference between them, thereby avoiding affecting the display of the light-emitting element group 210 corresponding to the first pixel unit 220-1 and the light-emitting element group 210 corresponding to the second pixel unit 220-2. Alternatively, as... Figure 18 As shown, Figure 18 This illustration shows a schematic diagram of the layout structure of the fourth metal layer (i.e., metal layer RE) and the first metal layer (i.e., metal layer MG) of the first pixel unit 220-1 and the second pixel unit 220-2 in the first display area AA1 of a display panel provided in this application embodiment. Connecting line R1 is located in the first metal layer (i.e., metal layer MG), and connecting line R2 is located in the fourth metal layer (i.e., metal layer RE). By placing connecting lines R1 and R2 in different metal layers, mutual interference between connecting lines R1 and R2 can be avoided, and the position of connecting line R1 can be conveniently set. Figure 18 The light-emitting element 201 is represented by the connection position of the light-emitting element 201 in the fourth metal layer RE.

[0159] It is also understandable that, in combination Figure 2 and Figure 5As shown, in the second display area AA2, the light-emitting element group 210 corresponding to pixel unit 220 and its own pixel circuit group 110 may not completely overlap in the direction perpendicular to the plane of the display panel. Therefore, a connecting line R3 is also needed for electrical connection. That is, the light-emitting element group 210 corresponding to pixel unit 220 in the second display area AA2 also needs to be electrically connected to its own pixel circuit group 110 through the connecting line R3. Furthermore, since the light-emitting element group 210 corresponding to pixel unit 220 in the second display area AA2 and the light-emitting element group 210 corresponding to the second pixel unit 220-2 in the first display area AA1 are both electrically connected to their own pixel circuit group 110 through connecting lines, the connecting lines R2 and R3 are relatively short, and the connecting lines R2 and R3 can be located on the same metal layer, for example, as shown in the figure. Figure 5 As shown, both connecting lines R2 and R3 are located in the fourth metal layer (i.e., metal layer RE). Connecting lines R2 and R4 can be located in a different layer than connecting line R1. For example, connecting lines R2 and R3 can both be located in the fourth metal layer (i.e., metal layer RE), while connecting line R1 is located in the first metal layer (i.e., metal layer MG). This avoids mutual interference between connecting lines R1 and R2, and between connecting lines R1 and R3, and also facilitates the placement of connecting line R1.

[0160] Of course, if the light-emitting element group 210 corresponding to the pixel unit 220 in the second display area AA2 and the light-emitting element 201 in the light-emitting element group 210 corresponding to the second pixel unit 220-2 in the first display area AA1 overlap with the electrically connected pixel circuit PL1 in a direction perpendicular to the plane of the display panel, they can be directly electrically connected without setting a connecting line.

[0161] Based on the arrangement of the shift register circuit VSR and pixel circuit PL1 in the circuit area P1 of a row of pixel units 110 along the second direction X, another optional feature is... Figure 19 As shown, Figure 19The illustration shows a schematic diagram of the arrangement of a row of pixel units 220 in a display panel according to another embodiment of this application. It can be seen that in the second display area AA2, the circuit area P1 of the pixel unit 220 includes at least a pixel circuit group 110. The circuit area P1 of the pixel unit 220 in the second display area AA2 may include only one set of pixel circuit groups 110, or it may include one set of pixel circuit groups 110 and a set of redundant pixel circuit groups 120. The pixel circuit group 110 is electrically connected to the corresponding light-emitting element group 210. The pixel unit 220 in the first display area AA1 includes a third pixel unit 220-3. The circuit area P1 of the third pixel unit 220-3 includes not only a portion of the shift register circuit VSR, but also the pixel circuit group 110. Furthermore, the shift register circuit VSR is distributed in the circuit areas P1 of two adjacent third pixel units 220-3 along the second direction X. It is understood that the pixel unit 220 (i.e. the third pixel unit 220-3) in the first display area AA1 includes a portion of the shift register circuit VSR arranged along the second direction X and a set of pixel circuit groups 110. The shift register circuit VSR of two adjacent third pixel units 220-3 along the second direction X constitutes the shift register circuit VSR. In this way, each pixel unit 220 (i.e. the third pixel unit 220-3) in the first display area AA1 is provided with a set of pixel circuit groups 11. Then, the light-emitting element group 210 corresponding to the pixel unit 220 (i.e. the third pixel unit 220-3) in the first display area AA1 can be directly electrically connected to its own pixel circuit group 11, and there is no need to set up a connecting line R1.

[0162] Regarding the arrangement of the circuit structure within the circuit region P1 of the pixel unit 220, considering that multiple pixel units 220 are arranged in a row along the second direction X, and the circuit region P1 of each pixel unit 220 in a row is arranged along the second direction X, and the multiple rows of pixel units 220 are arranged along the first direction Y, another option is, as follows: Figure 20 As shown, Figure 20 The illustration shows a schematic diagram of the arrangement of a row of pixel units 220 in a display panel according to another embodiment of this application. It can be seen that in the first display area AA1, the circuit area P1 of the pixel unit 110 can also be set to include a third sub-circuit area P13 and a fourth sub-circuit area P14 arranged along the first direction Y. Thus, circuit structures can be set in the two sub-circuit areas arranged along the first direction Y respectively. Furthermore, the wiring area P2 of the pixel unit 220 overlaps with the third sub-circuit area P113, and the wiring area of ​​the pixel unit 220 overlaps with the fourth sub-circuit area P14. That is, part of the wiring set in the wiring area P2 of the pixel unit 220 is electrically connected to the circuit structure in the third sub-circuit area P13, and the other part of the wiring is electrically connected to the circuit structure in the fourth sub-circuit area P14.

[0163] In this case, options include, Figure 20 As shown, in the second display area AA2, the circuit area P1 of the pixel unit 220 includes at least a pixel circuit group 110. The circuit area P1 of the pixel unit 220 in the second display area AA2 may include only one pixel circuit group 110, or it may include one pixel circuit group 110 and a redundant pixel circuit group 120. The pixel circuit group 110 is electrically connected to the corresponding light-emitting element group 210. The pixel unit 220 of the first display area AA1 includes a third pixel unit 220-3. The circuit area P1 of the third pixel unit 220-3 includes a portion of the shift register circuit VSR and a pixel circuit group 110. In the third pixel unit 220-3, a portion of the shift register circuit VSR and the pixel circuit group 110 are arranged along the first direction Y. Furthermore, the shift register circuit VSR is distributed in the circuit areas P1 of at least two adjacent third pixel units 220-3 along the second direction X. It is understood that the pixel unit 220 (i.e. the third pixel unit 220-3) in the first display area AA1 includes a portion of the shift register circuit VSR arranged along the first direction Y and a set of pixel circuit groups 110. The shift register circuit VSRs of two or more adjacent third pixel units 220-3 along the second direction X constitute the shift register circuit VSR. In this way, each pixel unit 220 (i.e. the third pixel unit 220-3) in the first display area AA1 is provided with a set of pixel circuit groups 11. Then, the light-emitting element group 210 corresponding to the pixel unit 220 (i.e. the third pixel unit 220-3) in the first display area AA1 can be directly electrically connected to its own pixel circuit group 11, and there is no need to set up a connecting line R1.

[0164] Furthermore, to maintain consistency in the pattern composed of transparent areas 221 and non-transparent areas 222 within pixel units 220 in the first display area AA1 and the second display area AA2, the position and size of the circuit area P1 of pixel unit 220 in the second display area AA2 are the same as those of the circuit area P1 of pixel unit 110 in the first display area AA1. The circuit area P1 of pixel unit 110 in the second display area AA2 can contain only one set of pixel circuit groups 110, or it can contain one set of pixel circuit groups 110 and one set of redundant pixel circuit groups 120. The set of pixel circuit groups 110 can be located in one of the third sub-circuit area P13 and the fourth sub-circuit area P14, and the set of redundant pixel circuit groups 120 can be located in the other of the third sub-circuit area P13 and the fourth sub-circuit area P14. However, this arrangement may increase the width of the circuit area P1 in pixel unit 220 (i.e., the third pixel unit 220-3) in the first display area AA1 along the first direction Y, potentially sacrificing the proportion of the transparent area 221.

[0165] Figure 21This illustration shows a schematic diagram of the arrangement of a row of pixel units 220 in a display panel according to another embodiment of this application. Figure 21 As shown, in another optional embodiment of this application, both the first display area AA1 and the second display area AA2 include pixel units 220 and light-emitting element groups 210. Unlike the aforementioned embodiments, the pixel unit 220 includes two sub-pixel units 220A arranged along the second direction X. The sub-pixel units 220A and the light-emitting element groups 210 are correspondingly arranged. The arrangement period length of the sub-pixel units 220A along a direction parallel to the plane of the display panel is equal to the arrangement period length of the light-emitting element groups 210 along the same direction. It can be understood that in the display area of ​​the display panel, the light-emitting element groups 210 are arranged in an array along the first direction Y and the second direction X. Therefore, with the arrangement period length W1 of the light-emitting element groups 210 along the first direction Y... 1. The arrangement period length W12 along the second direction X is the side length. Pixel units 220 arranged along the first direction Y and the second direction X can be divided within the display area of ​​the display panel. Each pixel unit 220 includes two sub-pixel units 220A arranged along the second direction X. The arrangement period length W21 of the sub-pixel unit 220A along the first direction Y is equal to the arrangement period length W11 of the light-emitting element group 210 along the first direction Y. The arrangement period length W22 of the sub-pixel unit 220A along the second direction X is equal to the arrangement period length W12 of the light-emitting element group 210 along the second direction X. Optionally, if W11=W12=W21=W22, then the shape of the sub-pixel unit 220A is square, and the pixel unit 220 is rectangular.

[0166] like Figure 21 As shown, the sub-pixel unit 220A includes a transparent area 221 and a non-transparent area 222; in the first display area AA1, the transparent area 221 of the sub-pixel unit 220A may include a first transparent area 10; in the second display area AA2, the transparent area 221 of the sub-pixel unit 220A may include a second transparent area 20; and in the first display area AA1 and the second display area AA2, the non-transparent area 222 of the sub-pixel unit 220A includes a circuit area P1 and a wiring area P2. The circuit area P1 is used to set a circuit structure, such as a shift register circuit and / or a pixel circuit, and the wiring area P2 is used to set a metal wiring; wherein, the wiring area P2 extends along the first direction Y, and the circuit area P1 extends along the second direction X. Because the metal wiring of the wiring area P2 is electrically connected to the circuit structure of the circuit area P1, the circuit area P1 and the wiring area P2 overlap.

[0167] like Figure 21As shown, multiple pixel units 220 are arranged in a column along the first direction Y. The trace area P2 of each pixel unit 220 in the column is arranged along the first direction Y. The multiple columns of pixel units 220 are arranged along the second direction X. It can be understood that since each pixel unit 220 includes two sub-pixel units 220A arranged along the second direction X, a column of pixel units 220 includes two columns of sub-pixel units 220A. In a column of pixel units 220, the trace area P2 of each column of sub-pixel units 220A is arranged along the first direction Y.

[0168] like Figure 21 As shown, in the two columns of sub-pixel units 220A of a column of pixel units 220, the trace area P2 of one column of sub-pixel units 220A is arranged adjacent to the trace area P2 of the other column of sub-pixel units 220A; that is, the trace area P2 and the transparent area 221 of the two sub-pixel units 220A arranged along the second direction X in a pixel unit 220 are mirror-symmetrically arranged along the first direction Y.

[0169] And, as Figure 21 As shown, in the first display area AA1 and the second display area AA2, the relative positions of the transparent area 221 and the non-transparent area 222 of the pixel unit 220 are the same. That is, the relative positions of the transparent area 221 and the non-transparent area 222 of the two sub-pixel units 220A of the pixel unit 220 in the first display area AA1 are the same as the relative positions of the transparent area 221 and the non-transparent area 222 of the two sub-pixel units 220A of the pixel unit 220 in the second display area AA2.

[0170] With this configuration, for two sub-pixel units 220A arranged along the second direction X within a pixel unit 220, the routing areas P2 of these two sub-pixel units 220A can be merged into one routing area, that is, these two sub-pixel units 220A can share one routing area, thereby saving the space that needs to be reserved between the routing extending along the first direction Y and the boundary of the transparent area 221 within the routing area, and improving space utilization; for two adjacent pixel units 220 along the second direction X, the transparent area 221 of the sub-pixel unit 220A of one pixel unit 220 that is close to the other pixel unit 220 can be merged into a larger transparent area, reducing the influence of the non-transparent area.

[0171] At the same time, in the first display area AA1 and the second display area AA2, the relative positions of the transparent area 221 and the non-transparent area 222 of the pixel unit 220 are the same, which can reduce the visual difference between the first display area AA1 and the second display area AA2, further improve the uniformity of the transmittance and reflectance of the display panel, and thus further improve the display effect.

[0172] It is understood that, in the foregoing embodiments, as Figures 3-20As shown, in all cases, pixel unit 220 includes a sub-pixel unit 220A, and the relative positions of the transparent area 221 and the non-transparent area 222 of pixel unit 220 (i.e., sub-pixel unit 220A) in the first display area AA1 and the second display area AA2 are the same. However, in this embodiment, as... Figure 21 As shown, pixel unit 220 includes two sub-pixel units 220A arranged along the second direction X. The trace areas P2 of the two sub-pixel units 220A are arranged adjacent to each other. The trace areas P2 and transparent areas 221 of the two sub-pixel units 220A are mirror-symmetrical along the first direction Y. The relative positions of the transparent areas 221 and the non-transparent areas 222 of the pixel units 220 (i.e., the two sub-pixel units 220A) in the first display area AA1 and the second display area AA2 are the same.

[0173] In this embodiment, the circuit regions P1 of each sub-pixel unit 220A in a row of pixel units 220 are arranged along the second direction Y. The relative position settings of the circuit regions P1 and the transparent region 221 of the row of pixel units 220, as well as the settings of the circuit structure within the circuit regions P1 of the row of pixel units 220, can all refer to the aforementioned embodiments, and will not be repeated here.

[0174] For the configuration of different pixel circuits PL1 within a pixel circuit group 110, such as Figure 22 and Figure 23 As shown, Figure 22 and Figure 23 This paper illustrates the structure of two pixel units 220 within the first display area AA1 of two display panels provided in the embodiments of this application. Each pixel unit 220 includes a sub-pixel unit 220A. The circuit area P1 of the pixel unit 220 (i.e., the first pixel unit 220-1) on the left side along the second direction X includes a shift register circuit VSR. The circuit area P1 of the pixel unit 220 (i.e., the second pixel unit 220-2) on the right side along the second direction X includes two sets of pixel circuit groups 110. It can be seen that the pixel units 220 are correspondingly arranged with the light-emitting element groups 210, and each set of light-emitting element groups 210 is electrically connected to one set of pixel circuit groups 110. The light-emitting element group 210 includes a first light-emitting element... The pixel circuit group 110 includes a first pixel circuit 111 and a second pixel circuit 112, with the first pixel circuit 111 electrically connected to the first light-emitting element 211 and the second pixel circuit 112 electrically connected to the second light-emitting element 212. Considering that the driving currents of the first light-emitting element 211 and the second light-emitting element 212 may be different, and that the larger the area of ​​the orthographic projection of the pixel circuit on the plane of the display panel, the larger the output current and the larger the driving current for the corresponding light-emitting element, it is optional that the area of ​​the orthographic projection of the first pixel circuit 111 on the plane of the display panel and the area of ​​the orthographic projection of the second pixel circuit 112 on the plane of the display panel are different.

[0175] Considering that the first pixel circuit 111 and the second pixel circuit 112 are arranged along the second direction X, it is possible that the area of ​​the orthographic projection of the first pixel circuit 111 onto the plane of the display panel and the area of ​​the orthographic projection of the second pixel circuit 112 onto the plane of the display panel are different. Specifically, the width of the first pixel circuit 111 along the second direction X and the width of the second pixel circuit 112 along the second direction X are different. The first direction Y and the second direction X are both parallel to the plane of the display panel, and the second direction X intersects the first direction Y.

[0176] In practical applications, such as Figure 22 and Figure 23 As shown, the light-emitting element group 210 typically includes a red light-emitting element R, a green light-emitting element G, and a blue light-emitting element B. Because the driving current required for the red light-emitting element R is greater than that required for the green light-emitting element G, and the driving current required for the green light-emitting element G is greater than that required for the blue light-emitting element B, optionally, as... Figure 22 As shown, the first light-emitting element 211 can be a red light-emitting element R, and the second light-emitting element 212 can be a green light-emitting element B or a blue light-emitting element G; or another optional element, such as... Figure 23 As shown, the first light-emitting element 211 can be a green light-emitting element B, and the second light-emitting element 212 can be a blue light-emitting element G. Alternatively, the areas of the pixel circuits electrically connected to the red light-emitting element R, the green light-emitting element G, and the blue light-emitting element B in the orthographic projection onto the plane of the display panel are all different. Of course, the areas of the pixel circuits electrically connected to the red light-emitting element R, the green light-emitting element G, and the blue light-emitting element B in the orthographic projection onto the plane of the display panel can also be the same.

[0177] Accordingly, embodiments of this application also provide a display device, such as... Figure 24 As shown, the display device 400 includes the display panel 300 provided in any of the above embodiments. Since the display panel 300 has been described in detail in the foregoing embodiments, it will not be described again here.

[0178] The display device 400 can be any electronic device with display capabilities, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television.

[0179] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0180] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, It includes a first display area and a second display area, wherein the first display area includes at least a shift register circuit and the second display area includes at least a pixel circuit; The first display area includes a first transparent area, and at least a portion of the first transparent area overlaps with the shift register circuit along a first direction; the second display area includes a second transparent area, and the second transparent area overlaps with the pixel circuit along the first direction, wherein the first direction is parallel to the plane of the display panel. The area of ​​the first transparent region is S1, and the area of ​​the second transparent region is S2. .

2. The display panel according to claim 1, characterized in that, Along the second direction, the width of the first transparent area is L1, and the width of the second transparent area is L2. The second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction.

3. The display panel according to claim 1, characterized in that, Multiple pixel circuits are arranged in a row along a second direction, and multiple rows of pixel circuits are arranged along a first direction. The second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction. The maximum dimension of the shift register circuit along the second direction is greater than the maximum dimension of the shift register circuit along the first direction.

4. The display panel according to claim 1, characterized in that, The first display area also includes pixel circuits, and along the first direction, a portion of the first transparent area overlaps with the pixel circuits; The shift register circuit, the pixel circuit in the first display area, and the pixel circuit in the second display area are arranged along a second direction, which is parallel to the plane where the display panel is located and intersects with the first direction. The pixel circuit arrangement density in the first display area is greater than that in the second display area.

5. The display panel according to claim 1, characterized in that, The first display area also includes pixel circuits, and along the first direction, a portion of the first transparent area overlaps with the pixel circuits; The second display area further includes a redundant pixel circuit. The shift register circuit, the pixel circuit in the first display area, and the pixel circuit and the redundant pixel circuit in the second display area are arranged along the second direction, which is parallel to the plane of the display panel and intersects the first direction.

6. The display panel according to claim 5, characterized in that, The pixel circuit arrangement density in the first display area is the same as the pixel circuit and the redundant pixel circuit arrangement density in the second display area.

7. The display panel according to claim 1, characterized in that, Multiple pixel circuits are arranged in a row along a second direction, and multiple rows of pixel circuits are arranged along a first direction. The second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction. The shift register circuit is located on at least one side of a row of pixel circuits along the second direction; Alternatively, the shift register circuit may be located between two pixel circuits in a row of pixel circuits.

8. The display panel according to claim 1, characterized in that, Both the first display area and the second display area include pixel units and light-emitting element groups. The pixel units and the light-emitting element groups are arranged correspondingly. The arrangement period length of the pixel units along a direction parallel to the plane of the display panel is equal to the arrangement period length of the light-emitting element groups along the same direction. The pixel unit includes a transparent area and a non-transparent area; in the first display area, the transparent area of ​​the pixel unit includes the first transparent area; in the second display area, the transparent area of ​​the pixel unit includes the second transparent area; In the first display area and the second display area, the relative positions of the transparent area and the non-transparent area of ​​the pixel unit are the same.

9. The display panel according to claim 8, characterized in that, In both the first and second display areas, the transparent and non-transparent areas of the pixel units form the same pattern.

10. The display panel according to claim 8, characterized in that, The non-transparent area of ​​the pixel unit includes a circuit area and a trace area. The trace area extends along the first direction, and the circuit area extends along the second direction. The circuit area and the trace area overlap. The second direction is parallel to the plane of the display panel and intersects with the first direction.

11. The display panel according to claim 10, characterized in that, Multiple pixel units are arranged in a row along the second direction, the circuit area of ​​each pixel unit in a row is arranged along the second direction, and multiple rows of pixel units are arranged along the first direction; Along a direction perpendicular to the plane of the display panel, the circuit area in the pixel unit overlaps with the corresponding light-emitting element group.

12. The display panel according to claim 10, characterized in that, In the pixel unit, the trace area is located on one side of the transparent area along the second direction; Alternatively, in the pixel unit, the trace area is located on opposite sides of the transparent area along the second direction; Alternatively, in the pixel unit, the transparent area is located on opposite sides of the trace area along the second direction.

13. The display panel according to claim 10, characterized in that, The circuit area includes a first sub-circuit area and a second sub-circuit area arranged along the second direction, and the routing area includes a first sub-routing area and a second sub-routing area arranged at intervals along the second direction. The first sub-circuit area and the first sub-routing area overlap, and the second sub-circuit area and the second sub-routing area overlap.

14. The display panel according to claim 10, characterized in that, In the pixel unit, the circuit area is located on one side of the transparent area along the first direction; Alternatively, in the pixel unit, the transparent area is located on opposite sides of the circuit area along the first direction.

15. The display panel according to claim 10, characterized in that, In the first display area, the circuit area includes a third sub-circuit area and a fourth sub-circuit area arranged along the first direction. The wiring area overlaps with the third sub-circuit area and the wiring area overlaps with the fourth sub-circuit area.

16. The display panel according to claim 10, characterized in that, In the second display area, the circuit area of ​​the pixel unit includes at least a pixel circuit group, and the pixel circuit group is electrically connected to the corresponding light-emitting element group; The pixel unit of the first display area includes a first pixel unit and a second pixel unit. The circuit area of ​​the first pixel unit includes the shift register circuit, and the circuit area of ​​the second pixel unit includes two sets of pixel circuit groups. In the second pixel unit, one group of pixel circuits is electrically connected to the corresponding light-emitting element group, and another group of pixel circuits is electrically connected to the light-emitting element group corresponding to the first pixel unit through a connecting line.

17. The display panel according to claim 16, characterized in that, The display panel includes a substrate and a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked on one side of the substrate in a direction away from the substrate; The third metal layer includes a first power supply voltage line, and the fourth metal layer includes a second power supply voltage line. The first power supply voltage line is electrically connected to the pixel circuit group, and the second power supply voltage line is electrically connected to the light-emitting element group. The connection line is located in the first metal layer. Alternatively, the second metal layer includes a first power supply voltage line, the fourth metal layer includes a second power supply voltage line, the first power supply voltage line is electrically connected to the pixel circuit group, and the second power supply voltage line is electrically connected to the light-emitting element group; the connection line is located in the third metal layer.

18. The display panel according to claim 10, characterized in that, In the second display area, the circuit area of ​​the pixel unit includes at least a pixel circuit group, and the pixel circuit group is electrically connected to the corresponding light-emitting element group; The pixel unit of the first display area includes a third pixel unit, and the circuit area of ​​the third pixel unit includes not only part of the shift register circuit, but also the pixel circuit group; the shift register circuit is distributed in the circuit areas of at least two adjacent third pixel units along the second direction.

19. The display panel according to claim 18, characterized in that, Within the third pixel unit, a portion of the shift register circuit and the pixel circuit group are arranged along the first direction.

20. The display panel according to claim 1, characterized in that, Both the first display area and the second display area include pixel units and light-emitting element groups. The pixel unit includes two sub-pixel units arranged along a second direction. The second direction is parallel to the plane where the display panel is located and intersects with the first direction. The sub-pixel units and the light-emitting element groups are arranged correspondingly. The arrangement period length of the sub-pixel units along a direction parallel to the plane where the display panel is located is equal to the arrangement period length of the light-emitting element groups along the same direction. The sub-pixel unit includes a transparent area and a non-transparent area; in the first display area, the transparent area of ​​the sub-pixel unit includes the first transparent area; in the second display area, the transparent area of ​​the sub-pixel unit includes the second transparent area; the non-transparent area of ​​the sub-pixel unit includes a circuit area and a wiring area, the wiring area extends along the first direction, the circuit area extends along the second direction, and the circuit area and the wiring area overlap. Multiple pixel units are arranged in a column along the first direction, and the trace areas of each pixel unit in a column are arranged along the first direction. Multiple columns of pixel units are arranged along the second direction. In the two columns of sub-pixel units of a column of pixel units, the trace areas of one column of sub-pixel units are adjacent to the trace areas of the other column of sub-pixel units. In the first display area and the second display area, the relative positions of the transparent area and the non-transparent area of ​​the pixel unit are the same.

21. The display panel according to claim 8, characterized in that, A group of light-emitting elements is electrically connected to a group of pixel circuits. The group of light-emitting elements includes a first light-emitting element and a second light-emitting element. The group of pixel circuits includes a first pixel circuit and a second pixel circuit. The first pixel circuit is electrically connected to the first light-emitting element, and the second pixel circuit is electrically connected to the second light-emitting element. The area of ​​the first pixel circuit projected onto the plane of the display panel is different from the area of ​​the second pixel circuit projected onto the plane of the display panel.

22. The display panel according to claim 21, characterized in that, The first pixel circuit and the second pixel circuit are arranged along a second direction. The width of the first pixel circuit along the second direction and the width of the second pixel circuit along the second direction are different. The second direction is parallel to the plane where the display panel is located, and the second direction intersects the first direction.

23. The display panel according to claim 22, characterized in that, The first light-emitting element is a red light-emitting element, and the second light-emitting element is a green light-emitting element or a blue light-emitting element; Alternatively, the first light-emitting element may be a green light-emitting element, and the second light-emitting element may be a blue light-emitting element.

24. The display panel according to claim 8, characterized in that, The display panel includes a light-shielding layer that covers the non-transparent area of ​​the pixel unit and exposes the transparent area of ​​the pixel unit and the light-emitting element group.

25. The display panel according to claim 24, characterized in that, The light-shielding layer includes multiple light-shielding units, and the light-shielding units and the pixel units are correspondingly arranged; The light-shielding unit has a first opening that exposes the transparent area of ​​the pixel unit.

26. The display panel according to claim 25, characterized in that, The non-transparent area of ​​the pixel unit includes a circuit area and a trace area. The trace area extends along the first direction, and the circuit area extends along the second direction. The circuit area and the trace area overlap. The second direction is parallel to the plane of the display panel and intersects with the first direction. The light-shielding unit includes an overlapping first light-shielding area and a second light-shielding area, the first light-shielding area covering the circuit area and the second light-shielding area covering the wiring area.

27. The display panel according to claim 26, characterized in that, The wiring area includes wiring extending along the first direction. The wiring density in the wiring area of ​​the second display area is less than the wiring density in the wiring area of ​​the first display area. The width of the second light-shielding area of ​​the second display area along the second direction is equal to the width of the second light-shielding area of ​​the first display area along the second direction.

28. A display device, characterized in that, Includes the display panel as described in any one of claims 1-27.

Images