Duty ratio detection device and random access memory

Abstract

The invention provides a duty ratio detection device and a random access memory. The duty ratio detection device comprises a duty ratio detection module which is configured to receive a calibration clock signal in a calibration execution process and execute duty ratio detection on the calibration clock signal to obtain a duty ratio detection result; the adjustment control module is connected with the duty ratio detection module, the adjustment control module is configured to generate a corresponding target adjustment code based on a duty ratio detection result in the calibration execution process, and the duty ratio detection module adjusts a response threshold value based on the target adjustment code so as to eliminate the deviation between the response threshold value and a target response threshold value; and the duty ratio detection module performs duty ratio detection on the input clock signal based on the target response threshold value in the normal detection execution process. According to the scheme, the duty ratio detection module can respond when the duty ratio of the input clock signal is equal to the target response threshold value, that is, the response threshold value of the duty ratio detection module is adjusted to the target response threshold value, so that the detection deviation of the duty ratio detection device is reduced.

Description

Technical Field

[0001] The disclosed embodiments of this application relate to the field of storage technology, and more specifically, to a duty cycle detection device and a random access memory. Background Technology

[0002] Double Data Rate (DDR) Synchronous Random Access Memory (SDRAM) is the mainstream random access memory and a typical semiconductor memory. DDR-type memory is designed to synchronously input or output data on both the rising and falling edges of the clock signal. Therefore, the duty cycle of the clock signal needs to be precisely maintained at 50%. For this purpose, chips typically employ duty cycle adjustment circuits to adjust the duty cycle of the clock signal. These duty cycle adjustment circuits include duty cycle detectors to detect the duty cycle of the clock signal output by the circuit.

[0003] However, if the duty cycle detector itself is biased, the duty cycle of the clock signal output by the duty cycle adjustment circuit cannot be accurately maintained at 50%.

[0004] Therefore, how to reduce the detection bias of the duty cycle detector has become an urgent problem to be solved. Summary of the Invention

[0005] According to embodiments of this application, the present invention proposes a duty cycle detection device and a random access memory to reduce the detection deviation of the duty cycle detector.

[0006] According to one aspect of this application, a duty cycle detection device is disclosed, comprising: a duty cycle detection module and an adjustment control module. The duty cycle detection module is configured to receive a calibration clock signal during calibration and perform duty cycle detection on the calibration clock signal to obtain a duty cycle detection result. The adjustment control module is connected to the duty cycle detection module and is configured to generate a corresponding target adjustment code based on the duty cycle detection result during calibration. The duty cycle detection module adjusts its response threshold based on the target adjustment code to eliminate the deviation between the response threshold and the target response threshold, so that the duty cycle detection module performs duty cycle detection on the input clock signal based on the target response threshold during normal detection.

[0007] According to a second aspect of this application, a random access memory is disclosed, including the duty cycle detection device described in the first aspect.

[0008] The above scheme adjusts the response threshold of the duty cycle detection module by generating a corresponding target adjustment code based on the duty cycle detection result of the duty cycle detection module. This enables the duty cycle detection module to respond when the duty cycle of the input clock signal is equal to the target response threshold, thus adjusting the response threshold of the duty cycle detection module to the target response threshold and reducing the detection deviation of the duty cycle detection device. Attached Figure Description

[0009] The present application will be further described below with reference to the accompanying drawings and embodiments. In the drawings: Figure 1 This is a schematic diagram of the frame of a duty cycle detection device in one embodiment of this application; Figure 2 This is a schematic diagram of the framework of a duty cycle adjustment circuit; Figure 3 This is a schematic diagram of the frame of a duty cycle detection device in another embodiment of this application; Figure 4 This is a schematic diagram of the frame of the duty cycle detection device in another embodiment of this application; Figure 5 This is a schematic diagram of the frame of the duty cycle detection device in another embodiment of this application; Figure 6 This is a schematic diagram of the frame of the duty cycle detection device in yet another embodiment of this application; Figure 7 This is a schematic diagram of the frame of the duty cycle detection device in yet another embodiment of this application; Figure 8 This is a schematic diagram of the signal timing in a duty cycle detection device according to an embodiment of this application; Figure 9 This is a schematic diagram of the frame of the duty cycle detection device in yet another embodiment of this application; Figure 10 This is a schematic diagram of the frame of the duty cycle detection device in yet another embodiment of this application; Figure 11 This is a schematic diagram of the adjustment code processing unit in one embodiment of this application; Figure 12 This is a schematic diagram of the frame of the duty cycle detection device in yet another embodiment of this application; Figure 13 This is a schematic diagram of the frame of the duty cycle detection device in yet another embodiment of this application; Figure 14 This is a schematic diagram of the signal timing in a duty cycle detection device according to another embodiment of this application; Figure 15 This is a schematic diagram of the framework of a random access memory in one embodiment of this application. Detailed Implementation

[0010] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0011] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0012] It should be understood that the term "and / or" used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0013] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0014] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0015] Please refer to Figure 1 , Figure 1This is a schematic diagram of the framework of a duty cycle detection device 100 according to an embodiment of this application. The duty cycle detection device 100 includes a duty cycle detection module 120 and an adjustment control module 110. The duty cycle detection module 120 is configured to receive a calibration clock signal during calibration and perform duty cycle detection on the calibration clock signal to obtain a duty cycle detection result. The adjustment control module 110 is connected to the duty cycle detection module 120. The adjustment control module 110 is configured to generate a corresponding target adjustment code based on the duty cycle detection result during calibration. The duty cycle detection module 120 adjusts its response threshold based on the target adjustment code to eliminate the deviation between the response threshold and the target response threshold, so that the duty cycle detection module 120 performs duty cycle detection on the input clock signal based on the target response threshold during normal detection.

[0016] The above scheme adjusts the response threshold of the duty cycle detection module 120 by generating a corresponding target adjustment code based on the duty cycle detection result of the duty cycle detection module 120. This enables the duty cycle detection module 120 to respond when the duty cycle of the input clock signal is equal to the target response threshold, thereby adjusting the response threshold of the duty cycle detection module 120 to the target response threshold and reducing the detection deviation of the duty cycle detection device 100.

[0017] It can be understood that the "calibration process" refers to the process of calibrating the response threshold of the duty cycle detection module 120 to adjust it to the target response threshold.

[0018] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the framework of a duty cycle adjustment device 200; the duty cycle adjustment link 210 receives the initial clock signal CLKIN and adjusts the initial clock signal CLKIN to generate an output clock signal CLKOUT; the duty cycle detection device 100 is coupled to the duty cycle adjustment link 210 to generate a corresponding duty cycle detection result based on the detected duty cycle of the output clock signal CLKOUT; the state machine 220 is coupled to the duty cycle detection device 100 to generate a corresponding control code based on the duty cycle detection result. <n:1>Duty cycle adjustment link 210 is based on control code. <n:1>Adjust the duty cycle of the output clock signal CLKOUT. It can be understood that the output clock signal CLKOUT of the duty cycle adjustment link 210 is output to the duty cycle detection device 100 as... Figure 1 The duty cycle detection device 100 receives the input clock signal, thereby enabling it to detect the duty cycle of the input clock signal.

[0019] In some embodiments, the duty cycle detection result generated by the duty cycle detection device 100 may include logic levels. For example, a logic level "1" indicates that the duty cycle of the output clock signal CLKOUT is greater than 50%, and a logic level "0" indicates that the duty cycle of the output clock signal CLKOUT is less than 50%.

[0020] In some embodiments, state machine 220 generates a corresponding control code based on the duty cycle detection result. <n:1>The duty cycle of the output clock signal CLKOUT can be adjusted in the duty cycle adjustment link 210. For example, when the state machine 220 receives a logic level "1", it generates a control code. <n:1>Used to reduce the duty cycle of the initial clock signal CLKIN in the duty cycle adjustment link 210, the control code generated when the state machine 220 receives the logic level "0" is... <n:1>This is used to increase the duty cycle of the initial clock signal CLKIN in the duty cycle adjustment link 210. The duty cycle continues until the duty cycle detection result alternates (or jitters) between "1" and "0", indicating that the duty cycle of the output clock signal CLKOUT is close to or equal to 50%, then the corresponding control code is locked. <n:1>.

[0021] In the above embodiment, the duty cycle detection device 100 in the duty cycle adjustment device 200 can detect the duty cycle of the output clock signal CLKOUT. The state machine 220 generates a corresponding control code based on the duty cycle detection result, causing the duty cycle adjustment link 210 to adjust the duty cycle of the initial clock signal CLKIN. Thus, when the duty cycle of the output clock signal CLKOUT is not 50%, the duty cycle of the initial clock signal CLKIN is adjusted through the duty cycle adjustment link 210 to make the duty cycle of the output clock signal CLKOUT as close to 50% as possible. That is to say, if the detection result of the duty cycle detection device 100 itself has an error, for example, when the duty cycle of the output clock signal CLKOUT is 55%, but a duty cycle detection result of 50% for the input clock signal CLKOUT is generated, the duty cycle of the final output clock signal CLKOUT will deviate from 50%.

[0022] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the duty cycle detection device 300 in another embodiment of this application; in some embodiments, the duty cycle detection device 300 includes a selection module 320 and a duty cycle detection module 310. The selection module 320 selectively sends an input clock signal or a calibration clock signal to the duty cycle detection module 310, and in this embodiment, the duty cycle of the calibration clock signal is 50%. When adjusting the response threshold of the duty cycle detection module 310, the selection module 320 sends a calibration clock signal to the duty cycle detection module 310. The duty cycle detection module 310 performs duty cycle detection on the calibration clock signal and obtains the duty cycle detection result. To obtain the duty cycle detection result, it is necessary to probe the corresponding pin of the duty cycle detection module 310. Based on the duty cycle detection result, a detector adjustment code (DCD code) is input to the duty cycle detection module 310. This process continues until the duty cycle detection result of the duty cycle detection module 310 flips. At this point, the corresponding detector adjustment code (DCD code) is recorded and set to the duty cycle detection module 310 via an electronic fuse. However, in this embodiment, obtaining the duty cycle detection result requires probing the corresponding pin of the duty cycle detection module 310, which is difficult and inefficient in practice.

[0023] Please continue to refer to Figure 1 In some embodiments of this application, the duty cycle detection device 100 adjusts the response threshold of the duty cycle detection module 120 by generating a corresponding target adjustment code based on the duty cycle detection result of the duty cycle detection module 120 through the adjustment control module 110. This enables the duty cycle detection module 120 to respond when the duty cycle of the input clock signal is equal to the target response threshold. In other words, adjusting the response threshold of the duty cycle detection module 120 eliminates the deviation between it and the target response threshold, thereby reducing the detection deviation of the duty cycle detection device 100. Furthermore, by connecting the adjustment control module 110 to the duty cycle detection module 120, the duty cycle detection result can be easily obtained, eliminating the need to manually probe the duty cycle detection result from the corresponding pin of the duty cycle detection module 120. The adjustment control module 110 can automatically obtain the duty cycle detection result and generate a corresponding target adjustment code based on the result, thus reducing operational difficulty and improving efficiency.

[0024] In some embodiments, the duty cycle detection module 120 generates a logic level "1" when the duty cycle of the input clock signal or calibration clock signal is greater than the response threshold, and generates a logic level "0" when the duty cycle of the input clock signal or calibration clock signal is less than the response threshold. In other words, the "response threshold" can be represented by the clock signal duty cycle. When the duty cycle detection module 120 has no error, its response threshold may be exactly Tck*50% (Tck is the period of the input clock signal or calibration clock signal); when the duty cycle detection module 120 has an error, its response threshold may be, for example, Tck*55%, Tck*53%, Tck*45%, etc. Since the desired clock signal duty cycle in the memory is 50%, if the response threshold of the duty cycle detection module 120 deviates from Tck*50%, it may cause the duty cycle of the clock signal output by the duty cycle adjustment link in the memory to also deviate from 50%. Therefore, it is necessary to adjust the response threshold of the duty cycle detection module 120 to the target response threshold (e.g., Tck*50%). In some embodiments, the duty cycle detection module 120 may also generate a logic level "0" when the duty cycle of the input clock signal or calibration clock signal is greater than the response threshold, and generate a logic level "1" when the duty cycle of the input clock signal or calibration clock signal is less than the response threshold. This application does not impose any limitations.

[0025] In some embodiments, the adjustment control module 110 can gradually adjust the detector adjustment code (DCD code) sent to the duty cycle detection module 120 based on the duty cycle detection result of the duty cycle detection module 120, until the duty cycle detection result of the duty cycle detection module 120 meets the preset conditions. Then, the target adjustment code is obtained according to the corresponding detector adjustment code (DCD code), so that the duty cycle detection module 120 adjusts its response threshold to the target response threshold based on the target adjustment code. Thus, the duty cycle detection module 120 performs duty cycle detection on the input clock signal based on the target response threshold during normal detection.

[0026] Please refer to Figure 4 In some embodiments, the calibration clock signal includes a reference clock signal with a duty cycle of 50%.

[0027] In some embodiments, during the calibration process, the duty cycle detection module 120 receives the reference clock signal and performs duty cycle detection on the reference clock signal to obtain a current duty cycle detection result. The adjustment control module 110 generates a corresponding current temporary adjustment code based on the current duty cycle detection result and feeds it back to the duty cycle detection module 120 to adjust the response threshold of the duty cycle detection module 120. The duty cycle detection module 120 then performs duty cycle detection on the reference clock signal again based on the adjusted response threshold to obtain a corresponding adjusted duty cycle detection result, until the adjusted duty cycle detection result meets a preset condition. In response to the adjusted duty cycle detection result meeting the preset condition, the corresponding current temporary adjustment code is set as the target adjustment code, and the corresponding response threshold is set as the target response threshold.

[0028] In some embodiments, when the adjustment control module 110 sends a reference clock signal with a duty cycle of 50% to the duty cycle detection module 120, the duty cycle detection module 120 can perform duty cycle detection on the reference clock signal and adjust the current temporary adjustment code according to the duty cycle detection result. For example, if the duty cycle detection result of the duty cycle detection module 120 indicates that the duty cycle of the reference clock signal is less than 50% (e.g., the duty cycle detection result is "0"), the current temporary adjustment code can be increased, for example, by increasing the temporary adjustment code by a predetermined step size (exemplarily, the predetermined step size can be an integer value such as 1, 2, 3, etc.); until the duty cycle detection result indicates that the duty cycle of the reference clock signal is greater than 50%, the corresponding current temporary adjustment code is set as the target adjustment code. For example, if the duty cycle detection result of the duty cycle detection module 120 indicates that the duty cycle of the reference clock signal is greater than 50% (for example, the duty cycle detection result is "1"), then the current temporary adjustment code can be reduced, for example, by reducing the temporary adjustment code by a predetermined step size (for example, the predetermined step size can be an integer value such as 1, 2, 3, etc.); until the duty cycle detection result indicates that the duty cycle of the reference clock signal is less than 50%, then the corresponding current temporary adjustment code is set as the target adjustment code.

[0029] In some embodiments, when adjusting the current temporary adjustment code based on the duty cycle detection result, the predetermined step size used to adjust the current temporary adjustment code can be a fixed value or a non-fixed value. For example, if the predetermined step size is non-fixed, a larger predetermined step size can be used in the initial stage of adjusting the temporary adjustment code to improve adjustment efficiency; after several adjustments to the temporary adjustment code, a smaller predetermined step size can be used to improve adjustment accuracy. For example, if the duty cycle detection result of the duty cycle detection module 120 indicates that the duty cycle of the reference clock signal is less than 50% (for example, the duty cycle detection result is "0"), the current temporary adjustment code can be increased by a larger predetermined step size (for example, 3, 4, etc.); after three adjustments to the current temporary adjustment code, the current temporary adjustment code can be increased by a smaller predetermined step size (for example, 1, 2, etc.) until the duty cycle detection result indicates that the duty cycle of the reference clock signal is greater than 50%, then the corresponding current temporary adjustment code is set as the target adjustment code. The predetermined step size can be adjusted in more increments. For example, when initially adjusting the current temporary adjustment code, it can be adjusted with the largest predetermined step size (e.g., 5, 6, etc.). After three adjustments, the current temporary adjustment code can be increased with smaller predetermined step sizes (e.g., 3, 4, etc.). After six adjustments, the current temporary adjustment code can be increased with the smallest predetermined step size (e.g., 1, 2, etc.). In this embodiment, adjusting the current temporary adjustment code with a non-fixed predetermined step size is beneficial for balancing adjustment accuracy and efficiency.

[0030] In some embodiments, when adjusting the current temporary adjustment code based on the duty cycle detection result, the temporary adjustment code can be adjusted using a counter (not shown), an adder (not shown), a field-programmable gate array (not shown), etc., and the adjustment step size of the counter or adder is a predetermined step size. In some embodiments, when the predetermined step size is not a fixed step size, the value of each accumulation / decrement can be switched by sending a step size adjustment signal to the counter, adder, or field-programmable gate array.

[0031] In some embodiments, please refer to Figure 5 , Figure 5 This is a schematic diagram of the duty cycle detection device 100 in another embodiment of this application; the adjustment control module 110 includes a clock unit 111, a control unit 113, and a counting unit 112; the clock unit 111 is configured to generate a reference clock signal with a duty cycle of 50%; the control unit 113 periodically generates a first counting control signal CTRL after starting the calibration process, and generates a second counting control signal RST based on the duty cycle detection result meeting the preset condition; the counting unit 112 is connected to the control unit 113, and increases or decreases the count value based on the first counting control signal CTRL to generate the current temporary adjustment code, and stops counting or resets the count value based on the second counting control signal RST.

[0032] In some embodiments, clock unit 111 may include an oscillator to generate a reference clock signal. Counting unit 112 may include a flip-flop and a full adder.

[0033] In some embodiments, after the counting unit 112 stops counting based on the second counting control signal, it can retain the last count value and output the count value to the duty cycle detection module 120. In other words, the counting unit 112 outputs the target adjustment code to the duty cycle detection module 120.

[0034] In some embodiments, such as Figure 5 As shown, the clock unit 111 and the control unit 113 are independent units. In other embodiments, the clock unit 111 and the control unit 113 can also be combined. For example, the control unit 113 is a CPU (not shown), which outputs a reference clock signal through one of its output pins. Combining the clock unit 111 and the control unit 113 helps to reduce the circuit size.

[0035] In some embodiments, please refer to Figure 6 The control unit 113 is further configured to generate a lock signal LAT and a target selection signal SEL based on the duty cycle detection result satisfying the preset condition. The adjustment control module 110 also includes a storage unit 114 and a selection unit 115. The storage unit 114 is connected to the counting unit 112 and the control unit 113, and stores the corresponding current temporary adjustment code as the target adjustment code based on the lock signal LAT; the selection unit 115 is connected to the counting unit 112, the storage unit 114 and the duty cycle detection module 120, and in response to receiving the target selection signal SEL, sends the target adjustment code stored in the storage unit 114 to the duty cycle detection module 120.

[0036] In some embodiments, the storage unit 114 may include elements with storage functions such as latches and registers.

[0037] In some embodiments, please refer to Figure 7 The clock unit 111 may further include a multiplexer 1111 (MUX), which receives a reference clock signal and an input clock signal, and is connected to the duty cycle detection module 120 and the control unit 113. The clock unit 111 also includes a clock signal generation device (not shown) for generating a reference clock signal. During normal operation, the multiplexer 1111 outputs the input clock signal to the duty cycle detection module 120. At the start of the calibration process, the control unit 113 sends a clock selection signal clk-mux to the multiplexer 1111. The multiplexer 1111 selects the reference clock signal for output based on the clock selection signal clk-mux, thereby enabling the duty cycle detection module 120 to detect the duty cycle of the reference clock signal.

[0038] In some embodiments, the adjustable range of the detector adjustment code (DCD code) can be pre-configured, meaning the DCD code is adjusted within this adjustable range. Assuming the adjustable range is [-a, a] (where a is an integer value such as 1, 2, or 3), the minimum value of the DCD code is -a (representing a decrease in the response threshold by a picoseconds), and the maximum value is a (representing an increase in the response threshold by a picoseconds). When the DCD code is -a, the response threshold of the duty cycle detection module 120 decreases by a picoseconds (ps); when the DCD code is a, the response threshold of the duty cycle detection module 120 increases by a picoseconds (ps). During calibration, the DCD code can be varied within the adjustable range from minimum to maximum (or from maximum to minimum) in predetermined steps. For example, suppose that before performing the calibration process, the response threshold of the duty cycle detection module 120 is Tck*50%+b, where b is the magnitude of the deviation of the response threshold from the target response threshold (it should be understood that the exact value of b cannot be known in advance during the actual calibration process), and 0 a; During the calibration process, the adjustment control module 110 sends a reference clock signal with a duty cycle of 50% to the duty cycle detection module 120, and first reduces the response threshold of the duty cycle detection module 120 by a picoseconds (at this time, the response threshold of the duty cycle detection module 120 is adjusted to Tck*50%+ba, that is, the current temporary adjustment code is -a). At this time, the duty cycle detection result of the duty cycle detection module 120 indicates that the duty cycle of the reference clock signal is greater than 50% (for example, the duty cycle detection result is "0"). Then, the response threshold of the duty cycle detection module 120 is further adjusted (for example, reduced by a+1 picoseconds, that is, when The temporary adjustment code is -a+1). When the response threshold of the duty cycle detection module 120 is reduced by b picoseconds (i.e., the current temporary adjustment code is -b), the response threshold of the duty cycle detection module 120 is adjusted to Tck*50%, and the duty cycle detection result of the duty cycle detection module 120 is "1". Then, the corresponding current temporary adjustment code is set as the target adjustment code. The duty cycle detection module 120 adjusts its response threshold to the target response threshold based on the target adjustment code, so that the duty cycle detection module 120 performs duty cycle detection on the input clock signal based on the target response threshold during normal detection.

[0039] In some embodiments, please refer to Figure 7 ​The control unit 113 also includes a control clock generator 116 and a controller 1131; the control clock generator 116 is connected to the controller 1131 and the counting unit 112. The controller 1131 generates a clock enable signal OSC-EN at the start of calibration to trigger the control clock generator 116 to generate a counting clock signal trim-clk. Upon receiving the counting clock signal trim-clk, the counting unit 112 increments or decrements the count value by a predetermined step size; for example, it increments the count value by 1 upon receiving the counting clock signal trim-clk.

[0040] The following is combined Figure 7 and Figure 8 The working principle of the duty cycle detection device 100 provided in some embodiments of this application is briefly described as follows: The calibration process is initiated by sending a calibration enable signal EN (e.g., a high-level pulse signal) to the controller 1131. After receiving the calibration enable signal EN, the controller 1131 sends a clock selection signal clk-mux to the multiplexer 1111, thereby causing the multiplexer 1111 to select a reference clock signal with a duty cycle of 50% generated by the clock signal generation device (not shown in the figure) as the input signal for the duty cycle detection module 120. After performing duty cycle detection on the reference clock signal, the duty cycle detection module 120 generates a duty cycle detection result. Furthermore, after receiving the calibration enable signal EN, the controller 1131 starts sending a clock enable signal OSC-EN to the control clock generator 116, thereby controlling the clock generator 116 to start generating a counting clock signal trim-clk, and the period of the counting clock signal trim-clk is greater than the detection period of the duty cycle detection module 120 (generating the time interval between two adjacent duty cycle detection results). The controller 1131 cancels the second counting control signal RST sent to the counting unit 112 (e.g., sets it to a low level), thereby causing the counting unit 112 to start generating adjustment codes triggered by the counting clock signal trim-clk. The controller 1131 also sends a target selection signal SEL (e.g., a high-level signal) to the selection unit 115, causing the selection unit 115 to select the current temporary adjustment code output by the counting unit 112 for output. At the start of the calibration process, the adjustment control module 110 sends the current temporary adjustment code 01 to the duty cycle detection module 120, and performs duty cycle detection on the reference clock signal based on the adjusted response threshold to obtain the duty cycle detection result. This duty cycle detection result is sent to the controller 1131. If the duty cycle detection result is "0" at this time, the counting clock signal trim-clk causes the counting unit 112 to continue generating a new current temporary adjustment code (e.g., 02). Until the duty cycle detection result is "1", the controller 1131 generates a lock signal LAT to cause the storage unit 114 to store the corresponding current temporary adjustment code (e.g., 04) as the target adjustment code, and generates a second count control signal RST to clear the counting unit 112. The controller 1131 generates a target selection signal SEL (e.g., a low-level signal) to cause the selection unit 115 to select the target adjustment code of the storage unit 114 as the detector adjustment code DCD code to adjust the response threshold of the duty cycle detection module 120, so that the duty cycle detection module 120 performs duty cycle detection on the input clock signal based on the target response threshold during normal detection.

[0041] exist Figures 4-8 In a corresponding embodiment, the preset conditions include the duty cycle detection result indicating that the duty cycle of the calibration clock signal is equal to 50%.

[0042] In some embodiments, please refer to Figure 9 The calibration clock signal includes a first calibration clock signal and a second calibration clock signal. During the calibration process, the duty cycle detection module 120 receives either the first calibration clock signal or the second calibration clock signal, and performs duty cycle detection on either signal to obtain a first duty cycle detection result or a second duty cycle detection result. The adjustment control module 110 sends a detector adjustment code (DCD code) to the duty cycle detection module 120. Specifically, the adjustment control module 110 generates a corresponding current first temporary adjustment code or a current second temporary adjustment code based on the first duty cycle detection result or the second duty cycle detection result to adjust the response threshold of the duty cycle detection module 120. The duty cycle detection module 120 performs duty cycle detection on the first calibration clock signal or the second calibration clock signal again based on the adjusted response threshold to obtain the corresponding adjusted first duty cycle detection result or second duty cycle detection result, until the adjusted first duty cycle detection result or second duty cycle detection result meets a preset condition. In response to the adjusted first duty cycle detection result meeting the preset condition, the corresponding current first temporary adjustment code is set as a first target adjustment code. In response to the adjusted second duty cycle detection result meeting the preset condition, the corresponding current second temporary adjustment code is set as a second target adjustment code. The target adjustment code is obtained based on the first target adjustment code and the second target adjustment code. The target adjustment code is used to adjust the response threshold of the duty cycle detection module 120 to obtain the target response threshold.

[0043] In some embodiments, the second calibration clock signal is the inverted signal of the first calibration clock signal. For example, if the duty cycle of the first calibration clock signal is 55% (e.g., the high-level pulse width of the first calibration clock signal is 55 picoseconds and the low-level pulse width is 45 picoseconds), then the duty cycle of the second calibration clock signal is 45% (e.g., the low-level pulse width of the second calibration clock signal is 55 picoseconds and the high-level pulse width is 45 picoseconds).

[0044] In some embodiments, the adjustment control module 110 obtains the target adjustment code based on the first target adjustment code and the second target adjustment code by: averaging the first target adjustment code and the second target adjustment code to obtain the target adjustment code. Referring to the foregoing embodiments, assuming the adjustment range of the response threshold of the duty cycle detection module 120 is [-a, a], and the response threshold of the duty cycle detection module 120 before adjustment is Tck*50%+b picoseconds (Tck is the period of the input clock signal, the first calibration clock signal, or the second calibration clock signal); when the input duty cycle is not equal to 50% of the first calibration clock signal, for example, the high level width is tH picoseconds and the low level width is tL picoseconds, assuming the duty cycle detection module 120's duty cycle detection result for the first calibration clock signal is "1", then when When the response threshold changes by tH-Tck*50%-b picoseconds, the duty cycle detection result flips (i.e., becomes "0"). When the high-level width of the input first calibration clock signal is tL picoseconds and the low-level width is tH picoseconds, the duty cycle detection result will flip (e.g., change from "1" to "0") when the response threshold changes by tL-Tck*50%-b picoseconds. The required adjustment amount for the response threshold can be obtained as [(tH-Tck*50%-b)+(tL-Tck*50%-b)] / 2=-b picoseconds, thus obtaining the target adjustment code. For example, assuming the response threshold before adjustment is 505 picoseconds, and the duty cycle of the first calibration clock signal is 52% (e.g., the high-level pulse width of the first calibration clock signal is 520 picoseconds and the low-level pulse width is 480 picoseconds), and the duty cycle of the second calibration clock signal is 48% (e.g., the low-level pulse width of the second calibration clock signal is 480 picoseconds and the high-level pulse width is 520 picoseconds), then the first target adjustment code is 15 (that is, the response threshold is increased by 15 picoseconds), and the second target adjustment code is -25 (that is, the response threshold is decreased by 25 picoseconds). Then the target adjustment code is (15-25) / 2, which gives a target adjustment code of -5. In other words, the response threshold is decreased by 5 picoseconds to obtain the target response threshold.

[0045] In this embodiment, by sending a first calibration clock signal and a second calibration clock signal to the duty cycle detection module 120 respectively, and adjusting the current first temporary adjustment code and the current second temporary adjustment code based on the first and second duty cycle detection results, and when the first and second duty cycle detection results meet preset conditions, the corresponding current first temporary adjustment code and the current second temporary adjustment code are set as the first target adjustment code and the second target adjustment code respectively, and the target adjustment code is obtained based on the first target adjustment code and the second target adjustment code. Therefore, the duty cycle of the first calibration clock signal and the second calibration clock signal does not have to be 50%, that is, the adjustment control module 110 does not need to precisely generate a calibration clock signal with a duty cycle of 50%, thereby reducing the accuracy requirements of the clock signal generated by the adjustment control module 110 and helping to reduce circuit costs. Furthermore, since the target threshold can be obtained by adjusting the response threshold of the duty cycle detection module 120 without precisely generating a calibration clock signal with a duty cycle of 50%, it is beneficial to improve the accuracy of the target threshold adjustment.

[0046] In some embodiments, please refer to Figure 10 The adjustment control module 110 includes a clock unit 111, a control unit 113, a counting unit 112, and an adjustment code processing unit 117. The clock unit 111 is configured to generate the input clock signal, the first calibration clock signal, and the second calibration clock signal. The control unit 113 periodically generates a first counting control signal CTRL after starting the calibration process, and generates a second counting control signal RST and a lock signal LAT based on the duty cycle detection result meeting the preset condition. The counting unit 112 is connected to the control unit 113, and based on the first counting control signal CTRL, increases the count value from the minimum value with a first adjustment step or decreases the count value from the maximum value with a second adjustment step to obtain the current first count value or the current second count value, and resets the count value based on the second counting control signal RST. The adjustment code processing unit 117 is connected to the counting unit 112 and the control unit 113. It outputs the current first temporary adjustment code based on the current first count value and the current second temporary adjustment code based on the current second count value. It locks the current first temporary adjustment code as the first target adjustment code and the current second temporary adjustment code as the second target adjustment code based on the locking signal LAT. It also calculates the average of the first target adjustment code and the second target adjustment code to obtain the target adjustment code.

[0047] In some embodiments, the first adjustment step size and the second adjustment step size are fixed values. The counting unit 112 may include a counter (not shown), an adder (not shown), a field-programmable gate array (not shown), or an integrated circuit with counting functionality.

[0048] exist Figure 10 In the illustrated embodiment, the control unit 113 and the clock unit 111 are independent units. In other embodiments, the control unit 113 and the clock unit 111 can also be combined, with the control unit 113 sending a first calibration clock signal and a second calibration clock signal to the duty cycle detection module 120. In some embodiments, the adjustment code processing unit 117 includes a multiplication circuit 1171, a first storage unit 1172, a second storage unit 1173, and an addition circuit 1174. The multiplication circuit 1171 is connected to the counting unit 112, multiplying the current first count value by 2 to obtain the current first temporary adjustment code; multiplying the current second count value by 2 to obtain the current second temporary adjustment code; the first storage unit 1172 is connected to the control unit 113 and the counting unit 112, storing the current first count value based on the lock signal LAT; the second storage unit 1173 is connected to the control unit 113 and the counting unit 112, storing the current second value based on the lock signal LAT; the addition circuit 1174 is connected to the first storage unit 1172 and the second storage unit 1173, adding the current first count value and the current second count value to obtain the target adjustment code.

[0049] In some embodiments, the multiplication circuit 1171 includes a left-shift multiplication circuit 1171 connected to the counting unit 112, which multiplies the current first count value by 2 to obtain the current first temporary adjustment code; and multiplies the current second count value by 2 to obtain the current second temporary adjustment code.

[0050] In some embodiments, the first storage unit 1172 and the second storage unit 1173 include latches, registers, or elements with storage functions.

[0051] like Figure 11 As shown, in the adjustment code processing unit 117, the current first count value or the current second count value output by the counting unit 112 is multiplied by 2 by the multiplication circuit 1171 to obtain the current first / second temporary adjustment code, which is then sent to the duty cycle detection module 120 so that the duty cycle detection module 120 adjusts the response threshold based on the current first / second temporary adjustment code. The counting unit 112 also sends the current first count value or the current second count value to the first storage unit 1172 or the second storage unit 1173 respectively. If the duty cycle detection result does not flip, the control unit... Yuan 113 triggers the counting unit 112 to generate a new current first count value or a current second count value, and the counting unit 112 sends the new current first count value or current second count value to the first storage unit 1172 or the second storage unit 1173 respectively; until the duty cycle detection result of the duty cycle detection module 120 flips, the first storage unit 1172 saves the corresponding current first count value, the second storage unit 1173 saves the corresponding current second count value, and the target adjustment code is obtained by adding the current first count value and the current second count value.

[0052] In some embodiments, after the duty cycle detection result of the duty cycle detection module 120 flips, the control unit 113 can send a calibration end signal (not shown) to the duty cycle detection module 120. Based on the calibration end signal, the duty cycle detection module 120 only receives the target adjustment code provided by the adder circuit 1174. In some embodiments, the multiplier circuit 1171 can be connected to the duty cycle detection module 120 through a switching unit (not shown). After the duty cycle detection result of the duty cycle detection module 120 flips, the control unit 113 can send a calibration end signal to the switching unit to control the switching unit to open, so that the duty cycle detection module 120 only receives the target adjustment code provided by the adder circuit 1174. The switching unit may include a BJT, a MOSFET, or an integrated circuit with switching function.

[0053] In some embodiments, please refer to Figure 12 The adjustment control module 110 further includes a selection unit 115 connected to the adder circuit 1174, the multiplier circuit 1171, the control unit 113, and the duty cycle detection module 120. The control unit 113 is configured to, in response to a first detection result from the duty cycle detection module 120 satisfying a preset condition, send a lock signal to the first storage unit 1172 to store the current first count value; in response to a second detection result from the duty cycle detection module 120 satisfying the preset condition, send a lock signal to the second storage unit 1173 to store the current second count value; and, in response to sending a lock signal to the second storage unit 1173, send a second counting control signal to the counting unit 112. The control unit 113 is also configured to generate a target selection signal SEL when the duty cycle detection result meets a preset condition. After receiving the target selection signal SEL, the selection unit 115 selectively outputs the current first temporary adjustment code / current second temporary adjustment code output by the multiplication circuit 1171 to the duty cycle detection module 120, or outputs the target adjustment code output by the addition circuit 1174 to the duty cycle detection module 120. For example, when the target selection signal SEL is low, the current first temporary adjustment code / current second temporary adjustment code output by the multiplication circuit 1171 is output to the duty cycle detection module 120; when the target selection signal SEL is high, the target adjustment code output by the addition circuit 1174 is output to the duty cycle detection module 120.

[0054] In some embodiments, the selection module 320 is a multiplexer 1111. In some embodiments, the selection module 320 may include components capable of switching functions such as BJTs and MOSFETs. For example, the selection module 320 may include two MOSFETs, which respectively connect the multiplication circuit 1171 and the addition circuit 1174 to the duty cycle detection module 120, and are turned on and off respectively under the excitation of the target selection signal SEL so that the multiplication circuit 1171 or the addition circuit 1174 is turned on to the duty cycle detection module 120.

[0055] In some embodiments, please refer to Figure 13 The control unit 113 further includes a controller 1131 and a control clock generator 116; the controller 1131 is configured to generate a clock enable signal at the start of the calibration process; the control clock generator 116 is coupled to the controller 1131 and the counting unit 112, and the control clock generator 116 is configured to periodically generate a counting clock signal based on the clock enable signal, so that the counting unit increases the count value by a first adjustment step or decreases the count value by a second adjustment step from a minimum value based on the counting clock signal to obtain the current first count value or the current second count value. For details, please refer to the description of the control clock generator 116 in the foregoing embodiments, which will not be repeated here.

[0056] exist Figures 9-14 In a corresponding embodiment, the preset conditions include either the duty cycle detection result indicating that the duty cycle of the calibration clock signal is greater than 50%, or the duty cycle detection result indicating that the duty cycle of the calibration clock signal is less than 50%.

[0057] The following is combined Figure 13 and Figure 14 The working principle of the duty cycle detection device 100 in some embodiments of this application is explained as follows: The calibration process is initiated by sending a calibration enable signal EN (e.g., a high-level pulse signal) to the control unit 113. After receiving the calibration enable signal EN, the control unit 113 sends a first calibration clock signal (in...) to the duty cycle detection module 120. Figure 15 In this circuit, the low-level portion of the calibration clock signal (indicating the sending of a first calibration clock signal to the duty cycle detection module 120) serves as the input signal to the duty cycle detection module 120. After performing duty cycle detection on the first calibration clock signal, the duty cycle detection module 120 generates a duty cycle detection result. Furthermore, after the control unit 113 receives the calibration enable signal EN, it begins sending a clock enable signal OSC-EN (e.g., a high-level electrical signal) to the control clock generator 116, thereby controlling the clock generator 116 to begin generating a counting clock signal trim-clk. The period of the counting clock signal trim-clk is greater than the detection period of the duty cycle detection module 120 (the time interval between two adjacent duty cycle detection results). Control unit 113 cancels the second counting control signal RST sent to counting unit 112 (e.g., sets it to low level), thereby causing counting unit 112 to start generating the current first count value under the trigger of counting clock signal trim-clk, and control unit 113 sends target selection signal SEL (e.g., high level signal) to selection unit 115 so that selection unit 115 selects the current first temporary adjustment code output by multiplication circuit 1171 for output. When the calibration process begins, the duty cycle detection module 120 detects the duty cycle of the first calibration clock signal and generates a duty cycle detection result. In response to the duty cycle detection result not flipping (e.g., "0"), the counting unit 112 updates the current first count value under the trigger of the high-level pulse of the counting clock signal trim-clk, thereby sending the current first count value 01 to the multiplication circuit 1171 to obtain the current first temporary adjustment code 02. The multiplication circuit 1171 then sends the first temporary adjustment code to the duty cycle detection module 120. The duty cycle detection module 120 adjusts the response threshold based on the first temporary adjustment code and performs duty cycle detection on the first calibration clock signal based on the adjusted response threshold to obtain the duty cycle detection result. The duty cycle detection result is then sent to the control unit 113. If the duty cycle detection result is still "0" at this time, the counting unit 112 continues to generate a new current temporary adjustment code (e.g., 02). Until the duty cycle detection result is "1", the control unit 113 generates a first lock signal LAT-1 to cause the storage unit 114 to store the corresponding current first count value (e.g., 04), and generates a second count control signal RST to clear the counting unit 112. Next, the control unit 113 sends a second calibration clock signal (in...) to the duty cycle detection module 120. Figure 15 In this circuit, the high-level portion of the calibration clock signal (representing the sending of a second calibration clock signal to the duty cycle detection module 120) serves as the input signal to the duty cycle detection module 120. The duty cycle detection module 120 performs duty cycle detection on the second calibration clock signal and generates a duty cycle detection result. In response to the duty cycle detection result not flipping (e.g., "1"), the counting unit 112, triggered by the high-level pulse of the counting clock signal trim-clk, updates the current second count value, thereby sending the current second count value 01 to the multiplication circuit 1171 to obtain the current second temporary adjustment code 02. The multiplication circuit 1171 then sends the second temporary adjustment code to the duty cycle detection module 120. The duty cycle detection module 120 adjusts the response threshold based on the second temporary adjustment code and performs duty cycle detection on the second calibration clock signal based on the adjusted response threshold to obtain the duty cycle detection result, which is then sent to the control unit 113. If the duty cycle detection result is still "1" at this time, the counting unit 112 continues to generate a new current temporary adjustment code (e.g., 02). Until the duty cycle detection result is "0", the control unit 113 generates a second lock signal LAT-2 to cause the storage unit 114 to store the corresponding current second count value (e.g., 03) and generates a second count control signal RST to clear the counting unit 112. After the first storage unit 1172 and the second storage unit 1173 have both been saved, the saved data is sent to the adder circuit 1174. The adder circuit 1174 adds the data stored in the first storage unit 1172 and the second storage unit 1173, and the control unit 113 sets the target selection signal to a low level, so that the selection unit 115 sends the output value of the adder (e.g., 07) to the duty cycle detection module 120. The duty cycle detection module 120 selects the input clock signal again as the input signal, so that the duty cycle detection module 120 performs duty cycle detection on the input clock signal based on the target response threshold during the normal detection process.

[0058] In some embodiments, the duty cycle detection device 100 provided in this application can be applied to, for example... Figure 2 The duty cycle adjustment device 200 is shown. Each time the duty cycle adjustment device 200 is powered on, it can perform a calibration process on the duty cycle detection device 100. For example, it can generate a calibration enable signal EN to the control unit 113 to perform the calibration process, thereby obtaining a target adjustment code to calibrate the response threshold of the duty cycle detection module 120 to a target response threshold. In some embodiments, after performing the calibration process, the obtained target adjustment code can also be read from the adjustment control module 110 and burned into an electronic fuse.

[0059] A second aspect of this application also provides a random access memory 1600, please refer to... Figure 15 The random access memory 1600 includes the duty cycle detection device 100 in any of the above embodiments.

[0060] Random access memory 1600 can be random access memory DRAM, static random access memory SRAM, or pseudo static random access memory (PSRAM), and there is no restriction here.

[0061] In some embodiments, the random access memory further includes a state machine and a duty cycle adjustment link, wherein the duty cycle adjustment link receives an initial clock signal and adjusts the duty cycle of the initial clock signal according to the control code output by the state machine to generate an output clock signal, wherein the duty cycle detection device performs duty cycle detection on the output clock signal based on a target response threshold during normal detection, and flips the duty cycle detection result when the duty cycle of the output clock signal meets a preset condition, and the state machine adjusts the control code according to the flipped duty cycle detection result so that the duty cycle adjustment link adjusts the duty cycle of the initial clock signal based on the control code.

[0062] In some embodiments, the regulation control module performs a calibration process to obtain the target regulation code after the random access memory is powered on; or, the regulation control module performs a calibration process to obtain the target regulation code during the random access memory's pre-shipment testing, wherein the target regulation code is read from the regulation control module and burned into the electronic fuse of the random access memory.

[0063] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims.

Claims

1. A duty cycle detection device, characterized in that, include: The duty cycle detection module is configured to receive a calibration clock signal during the calibration process and perform duty cycle detection on the calibration clock signal to obtain a duty cycle detection result; An adjustment control module is connected to the duty cycle detection module. The adjustment control module is configured to generate a corresponding target adjustment code based on the duty cycle detection result during the calibration process. The duty cycle detection module adjusts its response threshold based on the target adjustment code to eliminate the deviation between the response threshold and the target response threshold, so that the duty cycle detection module performs duty cycle detection on the input clock signal based on the target response threshold during normal detection.

2. The duty cycle detection device according to claim 1, characterized in that, The calibration clock signal includes a reference clock signal, the duty cycle of which is 50%. During the calibration process, the duty cycle detection module receives the reference clock signal and performs duty cycle detection on the reference clock signal to obtain the current duty cycle detection result; The adjustment control module generates a corresponding current temporary adjustment code based on the current duty cycle detection result and feeds it back to the duty cycle detection module to adjust the response threshold of the duty cycle detection module. The duty cycle detection module performs duty cycle detection on the reference clock signal again based on the adjusted response threshold to obtain the corresponding adjusted duty cycle detection result, until the adjusted duty cycle detection result meets the preset conditions. In response to the adjusted duty cycle detection result satisfying the preset conditions, the corresponding current temporary adjustment code is set as the target adjustment code, and the corresponding response threshold is set as the target response threshold.

3. The duty cycle detection device according to claim 2, characterized in that, The adjustment and control module includes: A clock unit is configured to generate the reference clock signal; The control unit periodically generates a first counting control signal after starting the calibration process, and generates a second counting control signal based on the duty cycle detection result satisfying the preset condition; A counting unit, connected to the control unit, increases or decreases the count value based on the first counting control signal to generate the current temporary adjustment code, and stops counting based on the second counting control signal.

4. The duty cycle detection device according to claim 3, characterized in that, The control unit is also configured to generate a locking signal and a target selection signal based on the duty cycle detection result meeting the preset conditions; The adjustment and control module further includes: A storage unit, connected to the counting unit and the control unit, stores the corresponding current temporary adjustment code as the target adjustment code based on the locking signal; The selection unit is connected to the counting unit, the storage unit, and the duty cycle detection module. In response to receiving the target selection signal, it sends the target adjustment code stored in the storage unit to the duty cycle detection module.

5. The duty cycle detection device according to claim 4, characterized in that, The control unit includes: The controller is configured to generate a clock enable signal at the start of the calibration process; A control clock generator, coupled to the controller and the counting unit, is configured to periodically generate a counting clock signal based on the clock enable signal, so that the counting unit increases or decreases the count value based on the counting clock signal to generate the current temporary adjustment code.

6. The duty cycle detection device according to claim 1, characterized in that, The calibration clock signal includes a first calibration clock signal and a second calibration clock signal; During the calibration process, the duty cycle detection module receives the first calibration clock signal or the second calibration clock signal respectively, and performs duty cycle detection on the first calibration clock signal or the second calibration clock signal respectively to obtain a first duty cycle detection result or a second duty cycle detection result; The adjustment control module generates a corresponding current first temporary adjustment code or a current second temporary adjustment code based on the first duty cycle detection result or the second duty cycle detection result to adjust the response threshold of the duty cycle detection module. The duty cycle detection module performs duty cycle detection on the first calibration clock signal or the second calibration clock signal again based on the adjusted response threshold to obtain the corresponding adjusted first duty cycle detection result or second duty cycle detection result, until the adjusted first duty cycle detection result or second duty cycle detection result meets the preset conditions. In response to the adjusted first duty cycle detection result meeting the preset condition, the corresponding current first temporary adjustment code is set as the first target adjustment code; In response to the adjusted second duty cycle detection result satisfying the preset condition, the corresponding current second temporary adjustment code is set as the second target adjustment code. The target adjustment code is obtained based on the first target adjustment code and the second target adjustment code. The response threshold of the duty cycle detection module is adjusted using the target adjustment code to obtain the target response threshold.

7. The duty cycle detection device according to claim 6, characterized in that, The second calibration clock signal is the inverted signal of the first calibration clock signal; The adjustment control module obtains the target adjustment code based on the first target adjustment code and the second target adjustment code by: The average of the first target adjustment code and the second target adjustment code is calculated to obtain the target adjustment code.

8. The duty cycle detection device according to claim 7, characterized in that, The adjustment and control module includes: A clock unit is configured to generate the first calibration clock signal and the second calibration clock signal; The control unit periodically generates a first counting control signal after starting the calibration process, and generates a second counting control signal and a lock signal based on the first duty cycle detection result or the second duty cycle detection result satisfying the preset condition; A counting unit, connected to the control unit, increases the count value by a first adjustment step size starting from the minimum value or decreases the count value by a second adjustment step size starting from the maximum value based on the first counting control signal to obtain the current first count value or the current second count value, and resets the count value based on the second counting control signal; An adjustment code processing unit, connected to the counting unit and the control unit, outputs a current first temporary adjustment code based on the current first count value and a current second temporary adjustment code based on the current second count value. Based on the locking signal, it locks the current first temporary adjustment code as the first target adjustment code and the current second temporary adjustment code as the second target adjustment code. It then calculates the average of the first target adjustment code and the second target adjustment code to obtain the target adjustment code.

9. The duty cycle detection device according to claim 8, characterized in that, The adjustment code processing unit includes: A first storage unit is connected to the control unit and the counting unit, and stores the current first count value based on the locking signal; The second storage unit is connected to the control unit and the counting unit, and stores the current second value based on the locking signal; The control unit is configured to, in response to the first detection result of the duty cycle detection module satisfying the preset condition, send a lock signal to the first storage unit to store the current first count value; in response to the second detection result of the duty cycle detection module satisfying the preset condition, send a lock signal to the second storage unit to store the current second count value; and in response to sending the lock signal to the second storage unit, send a second counting control signal to the counting unit.

10. The duty cycle detection device according to claim 8, characterized in that, The control unit includes: The controller is configured to generate a clock enable signal at the start of the calibration process; A control clock generator, coupled to the controller and the counting unit, is configured to periodically generate a counting clock signal based on the clock enable signal, so that the counting unit increases the count value by a first trimming step or decreases the count value by a second trimming step from a minimum value based on the counting clock signal to obtain the current first count value or the current second count value.

11. The duty cycle detection device according to claim 8, characterized in that, The adjustment code processing unit includes: A multiplication circuit, connected to the counting unit, multiplies the current first count value by 2 to obtain the current first temporary adjustment code; and multiplies the current second count value by 2 to obtain the current second temporary adjustment code. A first storage unit is connected to the control unit and the counting unit, and stores the current first count value based on the locking signal; The second storage unit is connected to the control unit and the counting unit, and stores the current second value based on the locking signal; An addition circuit, connected to the first storage unit and the second storage unit, adds the current first count value and the current second count value to obtain the target adjustment code.

12. The duty cycle detection device according to any one of claims 2 to 5, characterized in that, The preset conditions include: the duty cycle detection result indicates that the duty cycle of the calibration clock signal is equal to 50%.

13. The duty cycle detection device according to any one of claims 6 to 11, characterized in that, The preset conditions include: The duty cycle detection result indicates that the duty cycle of the calibration clock signal is greater than 50%, or the duty cycle detection result indicates that the duty cycle of the calibration clock signal is less than 50%.

14. A random access memory, characterized in that, The duty cycle detection device includes any one of claims 1 to 13.

15. The random access memory as claimed in claim 14, characterized in that, The random access memory further includes a state machine and a duty cycle adjustment link, wherein the duty cycle adjustment link receives an initial clock signal and adjusts the duty cycle of the initial clock signal according to the control code output by the state machine to generate an output clock signal. The duty cycle detection device performs duty cycle detection on the output clock signal based on a target response threshold during normal detection, and flips the duty cycle detection result when the duty cycle of the output clock signal meets a preset condition. The state machine adjusts the control code according to the flipped duty cycle detection result so that the duty cycle adjustment link adjusts the duty cycle of the initial clock signal based on the control code.

16. The random access memory as claimed in claim 14, characterized in that, The adjustment control module executes the calibration process after the random access memory is powered on to obtain the target adjustment code; or... The adjustment control module performs the calibration process during the pre-shipment testing of the random access memory to obtain the target adjustment code, wherein the target adjustment code is read from the adjustment control module and burned into the electronic fuse of the random access memory.

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