Data serialization sampling circuit and method
By setting a delay module in the serialized sampling circuit to delay the sampling clock and parallel data, the problems of data loss and bit error in traditional serialization circuits under high-speed application scenarios are solved, and accurate data conversion is achieved.
Patent Information
- Application Number
- CN202510780273.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-31
AI Technical Summary
Traditional serialization circuits cause parallel data loss and bit errors when sampling parallel data in high-speed applications.
By setting a delay module, the received sampling clock signal and the first serialization clock signal are delayed, and the received parallel data is also delayed, increasing the margin for data sampling and enabling the serialization circuit to accurately convert data into serial data in high-speed application scenarios.
This effectively increases the margin for data sampling, ensuring that parallel data can be accurately converted into serial data in high-speed application scenarios, thus avoiding data loss and bit errors.
Smart Images
Figure CN120880459A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of FPGA technology, specifically relating to a data serialization sampling circuit and method. Background Technology
[0002] To meet the operational requirements of an FPGA, the transmitter of a serializer needs to convert received parallel data into serial data. Since it must support multiple data rates and bit widths, the serialization circuit must ensure accurate serialization results under different configurations. Common serialization circuits include full-rate and half-rate structures, but regardless of the structure, they all require sampling of the input parallel data before serialization processing via a multiplexer.
[0003] Parallel data is generated by the digital module. To reduce the impact of latency in the digital transmission path, the conventional practice is to synchronize the parallel data using a parallel clock before it enters the serialization circuit. Ideally, the edges of the synchronization clock and the sampling clock should be aligned. However, the parallel clock is generated by frequency division of a high-frequency clock. When used as the clock for synchronization data, it experiences a long path delay, causing the edges of the synchronization clock and the sampling clock to become misaligned. This misalignment leads to the simultaneous capture of portions of data from the previous cycle and the current cycle within the sampling window, resulting in a reduction in the effective data width. In high-speed applications, this reduced data width affects the setup time. When the setup time is insufficient, the trigger may fail to correctly identify the sampled signal, leading to data loss and bit errors.
[0004] Therefore, how to solve the problem of parallel data loss and bit errors caused by traditional serialization circuits when sampling parallel data in high-speed application scenarios is an urgent technical problem to be solved. Summary of the Invention
[0005] To address the problem that traditional serialization circuits cause parallel data loss and bit errors when sampling parallel data in high-speed applications, this invention provides a data serialization sampling circuit and method.
[0006] In a first aspect, the present invention provides a data serialization sampling circuit, the circuit comprising: a clock division module, a parallel data transmission module, a delay module, a data sampling module, and a serialization processing module;
[0007] The parallel data transmission module is used to receive the parallel clock signal generated by the clock division module, and send the generated parallel data to the delay module according to the received parallel clock signal;
[0008] The delay module is used to receive the sampling clock signal and the first serialized clock signal generated by the clock division module, delay the received sampling clock signal and the first serialized clock signal, and send the delayed sampling clock signal and the delayed first serialized clock signal to the data sampling module and the serialization processing module respectively.
[0009] The delay module is also used to receive parallel data sent by the parallel data sending module, delay the received parallel data, and send the delayed parallel data to the data sampling module.
[0010] The data sampling module is used to receive the delayed sampling clock signal and the delayed parallel data, to synchronously sample the delayed parallel data according to the delayed sampling clock signal, and to send the sampled data to the serialization processing module.
[0011] The serialization processing module is used to receive the delayed first serialization clock signal, convert the sampled parallel data into serial data according to the received delayed first serialization clock signal, and output the serial data.
[0012] Preferably, the parallel data transmission module includes a parallel clock signal control unit and a parallel data transmission unit;
[0013] The parallel clock signal control unit is used to control the synchronous transmission of the parallel data based on the parallel clock signal;
[0014] The parallel data transmission unit is used to transmit parallel data to the delay module based on the parallel clock signal.
[0015] Preferably, the delay module includes a parallel clock processing unit and a data delay unit;
[0016] The parallel clock processing unit is used to receive the parallel clock signal generated by the clock division module, reverse the parallel clock signal, and send the reversed parallel clock signal to the D flip-flop of the data delay unit.
[0017] The D flip-flop of the data delay unit delays the parallel data sent by the parallel data sending unit and sends the delayed parallel data to the data sampling module.
[0018] Preferably, the data sampling module includes a sampling clock control unit and a data sampling unit;
[0019] The sampling clock control unit is used to receive the delayed sampling clock signal and perform phase calibration on the delayed sampling clock signal;
[0020] The data sampling unit is used to synchronously sample delayed parallel data based on the phase-calibrated sampling clock signal, and send the sampled data to the serialization processing module.
[0021] Preferably, the circuit further includes a delay selection module;
[0022] The delay selection module is used to select the delayed parallel data and send the selected parallel data to the data sampling module.
[0023] Preferably, the delay selection module includes a bit width selection signal unit and a data selector unit;
[0024] The bit width selection signal unit is used to generate a bit width selection signal;
[0025] The data selector unit is used to select the target bit width data in the delayed parallel data according to the bit width selection signal, and send the selected target bit width data to the data sampling module.
[0026] Secondly, the present invention also provides a data serialization sampling method, comprising:
[0027] The parallel data transmission module receives the parallel clock signal generated by the clock divider module, and sends the generated parallel data to the delay module according to the received parallel clock signal;
[0028] The delay module receives the sampling clock signal and the first serialized clock signal generated by the clock division module, performs delay processing on the received sampling clock signal and the first serialized clock signal, and sends the delayed sampling clock signal and the delayed first serialized clock signal to the data sampling module and the serialization processing module respectively.
[0029] The delay module also delays the received parallel data and sends the delayed parallel data to the data sampling module.
[0030] The data sampling module synchronously samples the delayed parallel data according to the received delayed sampling clock signal, and sends the sampled data to the serialization processing module.
[0031] The serialization processing module converts the sampled parallel data into serial data based on the received delayed first serialization clock signal, and outputs the serial data.
[0032] Preferably, the delay module further delays the received parallel data and sends the delayed parallel data to the data sampling module, including:
[0033] The parallel clock processing unit receives the parallel clock signal generated by the clock divider module, reverses the parallel clock signal, and sends the reversed parallel clock signal to the D flip-flop of the data delay unit.
[0034] The parallel data sent by the parallel data sending unit is delayed by the D flip-flop of the data delay unit, and the delayed parallel data is sent to the data sampling module.
[0035] Preferably, the data sampling module synchronously samples the delayed parallel data according to the received delayed sampling clock signal, and sends the sampled data to the serialization processing module, including:
[0036] The sampling clock control unit receives the delayed sampling clock signal and performs phase calibration on the delayed sampling clock signal;
[0037] The data sampling unit synchronously samples the delayed parallel data based on the phase-calibrated sampling clock signal and sends the sampled data to the serialization processing module.
[0038] Preferably, the serialization processing module converts the sampled parallel data into serial data based on the received delayed first serialization clock signal, and outputs the serial data. The method further includes:
[0039] The bit width selection signal is obtained through the delay selection module. The target bit width data in the delayed parallel data is selected according to the bit width selection signal, and the selected target bit width data is sent to the data sampling module.
[0040] Compared with the prior art, the data serialization sampling circuit and method provided by the present invention, by setting a delay module, delays the received sampling clock signal and the first serialization clock signal, and delays the received parallel data, effectively increasing the data sampling margin, so that the serialization circuit can accurately convert parallel data into serial data in high-speed application scenarios. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and not all embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of the present invention.
[0042] Figure 1 A schematic diagram of the framework of a data serialization sampling circuit provided in an embodiment of the present invention;
[0043] Figure 2 A timing diagram of a data serialization sampling circuit provided in an embodiment of the present invention;
[0044] Figure 3 This is a schematic diagram of the internal structure of a data serialization sampling circuit provided in an embodiment of the present invention;
[0045] Figure 4 This is a flowchart illustrating a data serialization sampling method provided in an embodiment of the present invention.
[0046] Among them, 10 is the clock divider module, 20 is the parallel data transmission module, 30 is the delay module, 40 is the serialization processing module, 50 is the serialization processing module, and 60 is the delay selection module. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0048] To provide a more detailed and complete description of the present invention, illustrative descriptions of its implementation methods and specific embodiments are provided below; however, these are not the only forms of implementing or utilizing the specific embodiments of the present invention. The implementation methods cover features of multiple specific embodiments, as well as the methods, steps, and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and sequence of steps. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.
[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.
[0050] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustrating and explaining the present invention and are not intended to limit the present invention. Furthermore, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.
[0051] To address the problem of parallel data loss and bit errors caused by traditional serialization circuits when sampling parallel data in high-speed applications, this invention provides a data serialization sampling circuit. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of a data serialization sampling circuit according to an embodiment of the present invention. The circuit includes: a clock division module 10, a parallel data transmission module 20, a delay module 30, a data sampling module 40, and a serialization processing module 50. The parallel data transmission module 20 is used to receive the parallel clock signal generated by the clock division module 10, and send the generated parallel data to the delay module 30 according to the received parallel clock signal. The delay module 30 is used to receive the sampling clock signal and the first serialization clock signal generated by the clock division module 10, delay the received sampling clock signal and the first serialization clock signal, and send the delayed sampling clock signal and the delayed first serialization clock signal respectively. The data is sent to the data sampling module 40 and the serialization processing module 50. The delay module 30 is also used to receive parallel data sent by the parallel data sending module 20, delay the received parallel data, and send the delayed parallel data to the data sampling module 40. The data sampling module 40 is used to receive the delayed sampling clock signal and the delayed parallel data, synchronously sample the delayed parallel data according to the delayed sampling clock signal, and send the sampled data to the serialization processing module 50. The serialization processing module 50 is used to receive the delayed first serialization clock signal, convert the sampled parallel data into serial data according to the received delayed first serialization clock signal, and output the serial data. It should be noted that the clock frequency division module 10 contains a high-speed clock signal, which can divide the frequency to generate a parallel clock signal, a sampling clock signal, and a serialization clock signal. Each clock signal can be a clock signal of different frequencies. For example, the parallel clock signal is a 40% division of the high-speed clock signal, and the sampling clock signal is a 4% division of the high-speed clock signal.
[0052] Specifically, in the embodiments of the present invention, please refer to Figure 2 , Figure 2 This is a timing diagram of a data serialization sampling circuit provided in an embodiment of the present invention. The parallel data transmission module 20 is connected to the clock divider module 10 and the delay module 30, respectively. It receives the parallel clock signal generated by the clock divider module 10, which provides a synchronous reference clock. The generated parallel data is synchronously transmitted to the delay module 30, ensuring that the parallel data maintains phase consistency after long-distance transmission. The delay module 30 receives the sampling clock signal and the first serialization clock signal generated by the clock divider module 10. Internally, the delay module 30 delays the sampling clock signal and the first serialization clock signal by a high-speed cycle, ensuring that the edge of the sampling clock signal precisely avoids the data transition region. The first serialization clock signal is synchronously delayed with the sampling clock signal, ensuring that serialization switching is triggered only after sampling is completed. Furthermore, the received parallel data is also delayed, with the data path using a reverse parallel clock signal delayed by b cycles, forming a fixed phase difference with the delayed sampling clock. The data sampling module 40 is connected to the delay module 30 and the serialization processing module 50, respectively. It synchronously samples the delayed parallel data according to the delayed sampling clock signal and sends the sampled data to the serialization processing module 50. The serialization processing module 40 receives the delayed first serialization clock signal and the second serialization clock signal generated by the clock division module. The first serialization clock signal is a low-speed serialization clock, and the second serialization clock signal is a high-speed serialization clock. The serialization processing module 50 converts the sampled parallel data into serial data based on the received delayed first serialization clock signal and outputs the serial data. For example, in this embodiment of the invention, the parallel clock signal is a 40% division of a high-speed clock. Please refer to [reference needed]. Figure 2 The parallel data transmission module 20 stores parallel data to be serialized. DATA<9:0> contains 10 sets of parallel data. The sampling clock signal and the first serialization clock signal can be delayed by 4 high-speed cycles relative to the parallel clock. The parallel data can be delayed by half a high-speed cycle. So, the original parallel data can be sampled in the first step of sampling parallel data. The sampling clock signal is delayed by 4 high-speed cycles relative to the parallel clock signal. So, the edge of the sampling clock signal precisely avoids the data transition area. In the last step of sampling parallel data, the delayed parallel data can be sampled. The parallel data is delayed by half a parallel cycle, that is, 20 high-speed clock cycles. Therefore, there is still a margin of 16 high-speed clock cycles after the last step of using parallel data.
[0053] As one implementation method, please refer to Figure 3 , Figure 3This is a schematic diagram of the internal structure of a data serialization sampling circuit provided in an embodiment of the present invention. The parallel data transmission module 20 includes a parallel clock signal control unit and a parallel data transmission unit. The parallel clock signal control unit is used to control the synchronous transmission of the parallel data based on the parallel clock signal. The parallel data transmission unit is used to send the parallel data to the delay module 30 based on the parallel clock signal. Specifically, in this embodiment of the present invention, the parallel clock signal is generated by dividing the high-speed clock signal of the clock divider module 10. The parallel clock signal control unit in the parallel data transmission module 20 controls the synchronous transmission of the parallel data based on the parallel clock signal, ensuring synchronous data transmission and avoiding data errors or loss due to clock signal asynchrony. In addition, the parallel data transmission unit in the parallel data transmission module 20 synchronously sends the parallel data to the delay module 30 based on the parallel clock signal. For example, Figure 3 DATA1 and DATA2 are two sets of parallel data, and CLK_PARA is a parallel clock signal. The parallel clock signal CLK_PARA controls the two sets of parallel data DATA1 and DATA2 to be sent synchronously to the delay module 30.
[0054] In one implementation, the delay module 30 includes a parallel clock processing unit and a data delay unit. The parallel clock processing unit receives the parallel clock signal generated by the clock divider module 10, reverses the parallel clock signal, and sends the reversed parallel clock signal to the D flip-flop of the data delay unit. The D flip-flop of the data delay unit delays the parallel data sent by the parallel data sending unit and sends the delayed parallel data to the data sampling module 40. Specifically, in this embodiment, the parallel clock processing unit in the delay module 30 can receive and process the parallel clock signal from the clock divider module 10, reverse the parallel clock signal, and flexibly adjust the phase of the clock signal. The D flip-flop of the data delay unit is responsible for delaying the parallel data. Through the characteristics of the D flip-flop, precise delay of the parallel data can be achieved. For example, please refer to... Figure 3 DEF represents the D flip-flop of the data delay unit. The parallel clock processing unit reverses the two sets of parallel clock signals CLK_PARA and sends the reversed parallel clock signal CLK_PARA to the D flip-flop of the data delay unit. In addition, after the two sets of parallel data are input to the delay module 30, the D flip-flop of the data delay unit delays the parallel data sent by the parallel data sending unit.
[0055] As one implementation method, please refer to Figure 3The delay module 30 further includes a clock delay unit, wherein CLK_SAMP_P represents a positive sampling clock signal, CLK_DIV4 represents a delayed clock signal, CLK_SAMP_N represents a negative sampling clock signal, CLK_P_DELAY represents a delayed positive sampling clock signal, CLK_N_DELAY represents a delayed negative sampling clock signal, LOW_CLK_MUX represents a first serialized clock signal, and LOW_CLK_MUX_DELAY represents a delayed first serialized clock signal. In this embodiment of the invention, the clock delay unit in the delay module 30 delays the positive sampling clock signal CLK_SAMP_P and the negative sampling clock signal CLK_SAMP_N respectively using the delayed clock signal CLK_DIV4 to obtain the delayed positive sampling clock signal CLK_P_DELAY and the negative sampling clock signal CLK_N_DELAY. The first serialized clock signal LOW_CLK_MUX is delayed using the delayed clock signal CLK_DIV4 to obtain the delayed first serialized clock signal LOW_CLK_MUX_DELAY.
[0056] In one implementation, the data sampling module 40 includes a sampling clock control unit and a data sampling unit. The sampling clock control unit receives a delayed sampling clock signal and performs phase calibration on the delayed sampling clock signal. The data sampling unit synchronously samples the delayed parallel data based on the phase-calibrated sampling clock signal and sends the sampled data to the serialization processing module 50. Specifically, in this embodiment of the invention, the sampling clock control unit enables the data sampling module 40 to receive the delayed sampling clock signal and perform phase calibration, ensuring the accuracy of the sampling clock signal. By using the phase-calibrated sampling clock signal, the data sampling unit can synchronously sample the delayed parallel data based on this signal, ensuring that multiple data bits are correctly acquired at the same time, thus improving the overall efficiency and accuracy of data acquisition. For an example, please refer to [reference needed]. Figure 3 CLK_P_DELAY represents the delayed positive sampling clock signal, and CLK_N_DELAY represents the delayed negative sampling clock signal. The delayed positive sampling clock signal CLK_P_DELAY and the delayed negative sampling clock signal CLK_N_DELAY can sample the delayed parallel data and send the sampled data to the serialization processing module 50.
[0057] As one implementation method, please refer to Figure 1The circuit further includes a delay selection module 60; the delay selection module 60 is used to select the delayed parallel data and send the selected parallel data to the data sampling module 40. Specifically, in this embodiment of the invention, the delay selection module 60 can effectively filter out the required parallel data for further processing, filter out irrelevant or redundant parallel data, and effectively improve the accuracy of subsequent data sampling.
[0058] In one implementation, the delay selection module 60 includes a bit-width selection signal unit and a data selector unit. The bit-width selection signal unit generates a bit-width selection signal. The data selector unit selects a target bit-width data from the delayed parallel data according to the bit-width selection signal and sends the selected target bit-width data to the data sampling module 40. Specifically, in this embodiment of the invention, by selecting specific bit-width data, the data sampling module 40 only needs to process data that meets the requirements, avoiding data sampling errors caused by data mismatch. For example, please refer to... Figure 3 BIT_SEL represents the bit width selection signal. The delay module 30 inputs the delayed parallel data into the bit width selection signal unit, selects the delayed parallel data according to the bit width selection signal, uses the selected delayed parallel data as the target bit width data, and sends the selected target bit width data to the data sampling module 40.
[0059] Based on the above-described data serialization sampling circuit, this invention also provides a data serialization sampling method, please refer to... Figure 4 , Figure 4 The flowchart of a data serialization sampling method provided by an embodiment of the present invention includes: S101, a parallel data transmission module receives a parallel clock signal generated by a clock division module, and sends the generated parallel data to a delay module according to the received parallel clock signal; S102, the delay module receives a sampling clock signal and a first serialization clock signal generated by the clock division module, performs delay processing on the received sampling clock signal and the first serialization clock signal, and sends the delayed sampling clock signal and the delayed first serialization clock signal to a data sampling module and a serialization processing module respectively; S103, the delay module also performs delay processing on the received parallel data, and sends the delayed parallel data to the data sampling module; S104, the data sampling module synchronously samples the delayed parallel data according to the received delayed sampling clock signal, and sends the sampled data to the serialization processing module;
[0060] S105. The serialization processing module converts the sampled parallel data into serial data according to the received delayed first serialization clock signal and outputs the serial data. Specifically, in this embodiment of the invention, the received sampling clock signal and the first serialization clock signal are delayed in the delay module, and the received parallel data is also delayed, which effectively increases the margin of data sampling, so that the serialization circuit can accurately convert parallel data into serial data in high-speed application scenarios.
[0061] In one implementation, the delay module further delays the received parallel data and sends the delayed parallel data to the data sampling module. This includes: a parallel clock processing unit receiving a parallel clock signal generated by a clock divider module, reversing the parallel clock signal, and sending the reversed parallel clock signal to the D flip-flop of the data delay unit; and delaying the parallel data sent by the parallel data sending unit through the D flip-flop of the data delay unit, and then sending the delayed parallel data to the data sampling module. Specifically, in this embodiment, the parallel clock processing unit in the delay module can receive and process the parallel clock signal from the clock divider module. By reversing the parallel clock signal, the phase of the clock signal can be flexibly adjusted to adapt to different data transmission requirements. The D flip-flop of the data delay unit is responsible for delaying the parallel data, enabling precise delay of the parallel data.
[0062] In one implementation, the data sampling module synchronously samples the delayed parallel data based on the received delayed sampling clock signal and sends the sampled data to the serialization processing module. This includes: a sampling clock control unit receiving the delayed sampling clock signal and performing phase calibration on the delayed sampling clock signal; and a data sampling unit synchronously sampling the delayed parallel data based on the phase-calibrated sampling clock signal and sending the sampled data to the serialization processing module. Specifically, in this embodiment of the invention, the sampling clock control unit enables the data sampling module to receive the delayed sampling clock signal and perform phase calibration, ensuring the accuracy of the sampling clock signal. By using the phase-calibrated sampling clock signal, the data sampling unit can synchronously sample the delayed parallel data based on this signal, ensuring that multiple data bits are correctly acquired at the same time, thus improving the overall efficiency and accuracy of data acquisition.
[0063] In one implementation, the serialization processing module converts the sampled parallel data into serial data based on the received delayed first serialization clock signal, and outputs the serial data. The method further includes: obtaining a bit-width selection signal through a delay selection module, selecting target bit-width data from the delayed parallel data according to the bit-width selection signal, and sending the selected target bit-width data to the data sampling module. Specifically, in this embodiment of the invention, the delay selection module can effectively filter out the required parallel data for further processing, filtering out irrelevant or redundant parallel data, effectively improving the accuracy of subsequent data sampling.
[0064] The data serialization sampling method provided in this embodiment of the invention can execute the technical solution of the data serialization sampling circuit in any of the above embodiments. Its implementation principle and beneficial effects are similar to those of the data serialization sampling circuit. Please refer to the implementation principle and beneficial effects of the data serialization sampling circuit. It will not be repeated here.
[0065] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.
[0066] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0067] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A data serialization sampling circuit, characterized in that, The circuit includes: a clock division module, a parallel data transmission module, a delay module, a data sampling module, and a serialization processing module; The parallel data transmission module is used to receive the parallel clock signal generated by the clock division module, and send the generated parallel data to the delay module according to the received parallel clock signal; The delay module is used to receive the sampling clock signal and the first serialized clock signal generated by the clock division module, delay the received sampling clock signal and the first serialized clock signal, and send the delayed sampling clock signal and the delayed first serialized clock signal to the data sampling module and the serialization processing module respectively. The delay module is also used to receive parallel data sent by the parallel data sending module, delay the received parallel data, and send the delayed parallel data to the data sampling module. The data sampling module is used to receive the delayed sampling clock signal and the delayed parallel data, to synchronously sample the delayed parallel data according to the delayed sampling clock signal, and to send the sampled data to the serialization processing module. The serialization processing module is used to receive the delayed first serialization clock signal, convert the sampled parallel data into serial data according to the received delayed first serialization clock signal, and output the serial data.
2. The data serialization sampling circuit according to claim 1, characterized in that, The parallel data transmission module includes a parallel clock signal control unit and a parallel data transmission unit; The parallel clock signal control unit is used to control the synchronous transmission of the parallel data based on the parallel clock signal; The parallel data transmission unit is used to transmit parallel data to the delay module based on the parallel clock signal.
3. The data serialization sampling circuit according to claim 2, characterized in that, The delay module includes a parallel clock processing unit and a data delay unit; The parallel clock processing unit is used to receive the parallel clock signal generated by the clock division module, reverse the parallel clock signal, and send the reversed parallel clock signal to the D flip-flop of the data delay unit. The D flip-flop of the data delay unit delays the parallel data sent by the parallel data sending unit and sends the delayed parallel data to the data sampling module.
4. The data serialization sampling circuit according to claim 3, characterized in that, The data sampling module includes a sampling clock control unit and a data sampling unit; The sampling clock control unit is used to receive the delayed sampling clock signal and perform phase calibration on the delayed sampling clock signal; The data sampling unit is used to synchronously sample delayed parallel data based on the phase-calibrated sampling clock signal, and send the sampled data to the serialization processing module.
5. The data serialization sampling circuit according to claim 1, characterized in that, The circuit also includes a delay selection module; The delay selection module is used to select the delayed parallel data and send the selected parallel data to the data sampling module.
6. The data serialization sampling circuit according to claim 1, characterized in that, The delay selection module includes a bit width selection signal unit and a data selector unit; The bit width selection signal unit is used to generate a bit width selection signal; The data selector unit is used to select the target bit width data in the delayed parallel data according to the bit width selection signal, and send the selected target bit width data to the data sampling module.
7. A data serialization sampling method, characterized in that, include: The parallel data transmission module receives the parallel clock signal generated by the clock divider module, and sends the generated parallel data to the delay module according to the received parallel clock signal; The delay module receives the sampling clock signal and the first serialized clock signal generated by the clock division module, performs delay processing on the received sampling clock signal and the first serialized clock signal, and sends the delayed sampling clock signal and the delayed first serialized clock signal to the data sampling module and the serialization processing module respectively. The delay module also delays the received parallel data and sends the delayed parallel data to the data sampling module. The data sampling module synchronously samples the delayed parallel data according to the received delayed sampling clock signal, and sends the sampled data to the serialization processing module. The serialization processing module converts the sampled parallel data into serial data based on the received delayed first serialization clock signal, and outputs the serial data.
8. The data serialization sampling method according to claim 7, characterized in that, The delay module also delays the received parallel data and sends the delayed parallel data to the data sampling module, including: The parallel clock processing unit receives the parallel clock signal generated by the clock divider module, reverses the parallel clock signal, and sends the reversed parallel clock signal to the D flip-flop of the data delay unit. The parallel data sent by the parallel data sending unit is delayed by the D flip-flop of the data delay unit, and the delayed parallel data is sent to the data sampling module.
9. The data serialization sampling method according to claim 7, characterized in that, The data sampling module synchronously samples the delayed parallel data based on the received delayed sampling clock signal, and sends the sampled data to the serialization processing module, including: The sampling clock control unit receives the delayed sampling clock signal and performs phase calibration on the delayed sampling clock signal; The data sampling unit synchronously samples the delayed parallel data based on the phase-calibrated sampling clock signal and sends the sampled data to the serialization processing module.
10. The data serialization sampling method according to claim 7, characterized in that, The serialization processing module converts the sampled parallel data into serial data based on the received delayed first serialization clock signal, and outputs the serial data. The method further includes: The bit width selection signal is obtained through the delay selection module. The target bit width data in the delayed parallel data is selected according to the bit width selection signal, and the selected target bit width data is sent to the data sampling module.